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atl2.c
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linux-6.19.14/drivers/net/ethernet/atheros/atlx/atl2.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. 4 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> 5 * 6 * Derived from Intel e1000 driver 7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 8 */ 9 10#include <linux/atomic.h> 11#include <linux/crc32.h> 12#include <linux/dma-mapping.h> 13#include <linux/etherdevice.h> 14#include <linux/ethtool.h> 15#include <linux/hardirq.h> 16#include <linux/if_vlan.h> 17#include <linux/in.h> 18#include <linux/interrupt.h> 19#include <linux/ip.h> 20#include <linux/irqflags.h> 21#include <linux/irqreturn.h> 22#include <linux/mii.h> 23#include <linux/net.h> 24#include <linux/netdevice.h> 25#include <linux/pci.h> 26#include <linux/pci_ids.h> 27#include <linux/pm.h> 28#include <linux/skbuff.h> 29#include <linux/slab.h> 30#include <linux/spinlock.h> 31#include <linux/string.h> 32#include <linux/tcp.h> 33#include <linux/timer.h> 34#include <linux/types.h> 35#include <linux/workqueue.h> 36 37#include "atl2.h" 38 39static const char atl2_driver_name[] = "atl2"; 40static const struct ethtool_ops atl2_ethtool_ops; 41 42MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); 43MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); 44MODULE_LICENSE("GPL"); 45 46/* 47 * atl2_pci_tbl - PCI Device ID Table 48 */ 49static const struct pci_device_id atl2_pci_tbl[] = { 50 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, 51 /* required last entry */ 52 {0,} 53}; 54MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); 55 56static void atl2_check_options(struct atl2_adapter *adapter); 57 58/** 59 * atl2_sw_init - Initialize general software structures (struct atl2_adapter) 60 * @adapter: board private structure to initialize 61 * 62 * atl2_sw_init initializes the Adapter private data structure. 63 * Fields are initialized based on PCI device information and 64 * OS network device settings (MTU size). 65 */ 66static int atl2_sw_init(struct atl2_adapter *adapter) 67{ 68 struct atl2_hw *hw = &adapter->hw; 69 struct pci_dev *pdev = adapter->pdev; 70 71 /* PCI config space info */ 72 hw->vendor_id = pdev->vendor; 73 hw->device_id = pdev->device; 74 hw->subsystem_vendor_id = pdev->subsystem_vendor; 75 hw->subsystem_id = pdev->subsystem_device; 76 hw->revision_id = pdev->revision; 77 78 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 79 80 adapter->wol = 0; 81 adapter->ict = 50000; /* ~100ms */ 82 adapter->link_speed = SPEED_0; /* hardware init */ 83 adapter->link_duplex = FULL_DUPLEX; 84 85 hw->phy_configured = false; 86 hw->preamble_len = 7; 87 hw->ipgt = 0x60; 88 hw->min_ifg = 0x50; 89 hw->ipgr1 = 0x40; 90 hw->ipgr2 = 0x60; 91 hw->retry_buf = 2; 92 hw->max_retry = 0xf; 93 hw->lcol = 0x37; 94 hw->jam_ipg = 7; 95 hw->fc_rxd_hi = 0; 96 hw->fc_rxd_lo = 0; 97 hw->max_frame_size = adapter->netdev->mtu; 98 99 spin_lock_init(&adapter->stats_lock); 100 101 set_bit(__ATL2_DOWN, &adapter->flags); 102 103 return 0; 104} 105 106/** 107 * atl2_set_multi - Multicast and Promiscuous mode set 108 * @netdev: network interface device structure 109 * 110 * The set_multi entry point is called whenever the multicast address 111 * list or the network interface flags are updated. This routine is 112 * responsible for configuring the hardware for proper multicast, 113 * promiscuous mode, and all-multi behavior. 114 */ 115static void atl2_set_multi(struct net_device *netdev) 116{ 117 struct atl2_adapter *adapter = netdev_priv(netdev); 118 struct atl2_hw *hw = &adapter->hw; 119 struct netdev_hw_addr *ha; 120 u32 rctl; 121 u32 hash_value; 122 123 /* Check for Promiscuous and All Multicast modes */ 124 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); 125 126 if (netdev->flags & IFF_PROMISC) { 127 rctl |= MAC_CTRL_PROMIS_EN; 128 } else if (netdev->flags & IFF_ALLMULTI) { 129 rctl |= MAC_CTRL_MC_ALL_EN; 130 rctl &= ~MAC_CTRL_PROMIS_EN; 131 } else 132 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); 133 134 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); 135 136 /* clear the old settings from the multicast hash table */ 137 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 138 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 139 140 /* comoute mc addresses' hash value ,and put it into hash table */ 141 netdev_for_each_mc_addr(ha, netdev) { 142 hash_value = atl2_hash_mc_addr(hw, ha->addr); 143 atl2_hash_set(hw, hash_value); 144 } 145} 146 147static void init_ring_ptrs(struct atl2_adapter *adapter) 148{ 149 /* Read / Write Ptr Initialize: */ 150 adapter->txd_write_ptr = 0; 151 atomic_set(&adapter->txd_read_ptr, 0); 152 153 adapter->rxd_read_ptr = 0; 154 adapter->rxd_write_ptr = 0; 155 156 atomic_set(&adapter->txs_write_ptr, 0); 157 adapter->txs_next_clear = 0; 158} 159 160/** 161 * atl2_configure - Configure Transmit&Receive Unit after Reset 162 * @adapter: board private structure 163 * 164 * Configure the Tx /Rx unit of the MAC after a reset. 165 */ 166static int atl2_configure(struct atl2_adapter *adapter) 167{ 168 struct atl2_hw *hw = &adapter->hw; 169 u32 value; 170 171 /* clear interrupt status */ 172 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); 173 174 /* set MAC Address */ 175 value = (((u32)hw->mac_addr[2]) << 24) | 176 (((u32)hw->mac_addr[3]) << 16) | 177 (((u32)hw->mac_addr[4]) << 8) | 178 (((u32)hw->mac_addr[5])); 179 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); 180 value = (((u32)hw->mac_addr[0]) << 8) | 181 (((u32)hw->mac_addr[1])); 182 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); 183 184 /* HI base address */ 185 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 186 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); 187 188 /* LO base address */ 189 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, 190 (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); 191 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, 192 (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); 193 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, 194 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); 195 196 /* element count */ 197 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); 198 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); 199 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); 200 201 /* config Internal SRAM */ 202/* 203 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); 204 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); 205*/ 206 207 /* config IPG/IFG */ 208 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << 209 MAC_IPG_IFG_IPGT_SHIFT) | 210 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << 211 MAC_IPG_IFG_MIFG_SHIFT) | 212 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << 213 MAC_IPG_IFG_IPGR1_SHIFT)| 214 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << 215 MAC_IPG_IFG_IPGR2_SHIFT); 216 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); 217 218 /* config Half-Duplex Control */ 219 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 220 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << 221 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 222 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 223 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 224 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << 225 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 226 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); 227 228 /* set Interrupt Moderator Timer */ 229 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); 230 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); 231 232 /* set Interrupt Clear Timer */ 233 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); 234 235 /* set MTU */ 236 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + 237 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 238 239 /* 1590 */ 240 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); 241 242 /* flow control */ 243 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); 244 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); 245 246 /* Init mailbox */ 247 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); 248 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); 249 250 /* enable DMA read/write */ 251 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); 252 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); 253 254 value = ATL2_READ_REG(&adapter->hw, REG_ISR); 255 if ((value & ISR_PHY_LINKDOWN) != 0) 256 value = 1; /* config failed */ 257 else 258 value = 0; 259 260 /* clear all interrupt status */ 261 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); 262 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 263 return value; 264} 265 266/** 267 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources 268 * @adapter: board private structure 269 * 270 * Return 0 on success, negative on failure 271 */ 272static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) 273{ 274 struct pci_dev *pdev = adapter->pdev; 275 int size; 276 u8 offset = 0; 277 278 /* real ring DMA buffer */ 279 adapter->ring_size = size = 280 adapter->txd_ring_size * 1 + 7 + /* dword align */ 281 adapter->txs_ring_size * 4 + 7 + /* dword align */ 282 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ 283 284 adapter->ring_vir_addr = dma_alloc_coherent(&pdev->dev, size, 285 &adapter->ring_dma, GFP_KERNEL); 286 if (!adapter->ring_vir_addr) 287 return -ENOMEM; 288 289 /* Init TXD Ring */ 290 adapter->txd_dma = adapter->ring_dma ; 291 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; 292 adapter->txd_dma += offset; 293 adapter->txd_ring = adapter->ring_vir_addr + offset; 294 295 /* Init TXS Ring */ 296 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; 297 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; 298 adapter->txs_dma += offset; 299 adapter->txs_ring = (struct tx_pkt_status *) 300 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); 301 302 /* Init RXD Ring */ 303 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; 304 offset = (adapter->rxd_dma & 127) ? 305 (128 - (adapter->rxd_dma & 127)) : 0; 306 if (offset > 7) 307 offset -= 8; 308 else 309 offset += (128 - 8); 310 311 adapter->rxd_dma += offset; 312 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + 313 (adapter->txs_ring_size * 4 + offset)); 314 315/* 316 * Read / Write Ptr Initialize: 317 * init_ring_ptrs(adapter); 318 */ 319 return 0; 320} 321 322/** 323 * atl2_irq_enable - Enable default interrupt generation settings 324 * @adapter: board private structure 325 */ 326static inline void atl2_irq_enable(struct atl2_adapter *adapter) 327{ 328 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 329 ATL2_WRITE_FLUSH(&adapter->hw); 330} 331 332/** 333 * atl2_irq_disable - Mask off interrupt generation on the NIC 334 * @adapter: board private structure 335 */ 336static inline void atl2_irq_disable(struct atl2_adapter *adapter) 337{ 338 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); 339 ATL2_WRITE_FLUSH(&adapter->hw); 340 synchronize_irq(adapter->pdev->irq); 341} 342 343static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) 344{ 345 if (features & NETIF_F_HW_VLAN_CTAG_RX) { 346 /* enable VLAN tag insert/strip */ 347 *ctrl |= MAC_CTRL_RMV_VLAN; 348 } else { 349 /* disable VLAN tag insert/strip */ 350 *ctrl &= ~MAC_CTRL_RMV_VLAN; 351 } 352} 353 354static void atl2_vlan_mode(struct net_device *netdev, 355 netdev_features_t features) 356{ 357 struct atl2_adapter *adapter = netdev_priv(netdev); 358 u32 ctrl; 359 360 atl2_irq_disable(adapter); 361 362 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); 363 __atl2_vlan_mode(features, &ctrl); 364 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); 365 366 atl2_irq_enable(adapter); 367} 368 369static void atl2_restore_vlan(struct atl2_adapter *adapter) 370{ 371 atl2_vlan_mode(adapter->netdev, adapter->netdev->features); 372} 373 374static netdev_features_t atl2_fix_features(struct net_device *netdev, 375 netdev_features_t features) 376{ 377 /* 378 * Since there is no support for separate rx/tx vlan accel 379 * enable/disable make sure tx flag is always in same state as rx. 380 */ 381 if (features & NETIF_F_HW_VLAN_CTAG_RX) 382 features |= NETIF_F_HW_VLAN_CTAG_TX; 383 else 384 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 385 386 return features; 387} 388 389static int atl2_set_features(struct net_device *netdev, 390 netdev_features_t features) 391{ 392 netdev_features_t changed = netdev->features ^ features; 393 394 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 395 atl2_vlan_mode(netdev, features); 396 397 return 0; 398} 399 400static void atl2_intr_rx(struct atl2_adapter *adapter) 401{ 402 struct net_device *netdev = adapter->netdev; 403 struct rx_desc *rxd; 404 struct sk_buff *skb; 405 406 do { 407 rxd = adapter->rxd_ring+adapter->rxd_write_ptr; 408 if (!rxd->status.update) 409 break; /* end of tx */ 410 411 /* clear this flag at once */ 412 rxd->status.update = 0; 413 414 if (rxd->status.ok && rxd->status.pkt_size >= 60) { 415 int rx_size = (int)(rxd->status.pkt_size - 4); 416 /* alloc new buffer */ 417 skb = netdev_alloc_skb_ip_align(netdev, rx_size); 418 if (NULL == skb) { 419 /* 420 * Check that some rx space is free. If not, 421 * free one and mark stats->rx_dropped++. 422 */ 423 netdev->stats.rx_dropped++; 424 break; 425 } 426 memcpy(skb->data, rxd->packet, rx_size); 427 skb_put(skb, rx_size); 428 skb->protocol = eth_type_trans(skb, netdev); 429 if (rxd->status.vlan) { 430 u16 vlan_tag = (rxd->status.vtag>>4) | 431 ((rxd->status.vtag&7) << 13) | 432 ((rxd->status.vtag&8) << 9); 433 434 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 435 } 436 netif_rx(skb); 437 netdev->stats.rx_bytes += rx_size; 438 netdev->stats.rx_packets++; 439 } else { 440 netdev->stats.rx_errors++; 441 442 if (rxd->status.ok && rxd->status.pkt_size <= 60) 443 netdev->stats.rx_length_errors++; 444 if (rxd->status.mcast) 445 netdev->stats.multicast++; 446 if (rxd->status.crc) 447 netdev->stats.rx_crc_errors++; 448 if (rxd->status.align) 449 netdev->stats.rx_frame_errors++; 450 } 451 452 /* advance write ptr */ 453 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) 454 adapter->rxd_write_ptr = 0; 455 } while (1); 456 457 /* update mailbox? */ 458 adapter->rxd_read_ptr = adapter->rxd_write_ptr; 459 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); 460} 461 462static void atl2_intr_tx(struct atl2_adapter *adapter) 463{ 464 struct net_device *netdev = adapter->netdev; 465 u32 txd_read_ptr; 466 u32 txs_write_ptr; 467 struct tx_pkt_status *txs; 468 struct tx_pkt_header *txph; 469 int free_hole = 0; 470 471 do { 472 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 473 txs = adapter->txs_ring + txs_write_ptr; 474 if (!txs->update) 475 break; /* tx stop here */ 476 477 free_hole = 1; 478 txs->update = 0; 479 480 if (++txs_write_ptr == adapter->txs_ring_size) 481 txs_write_ptr = 0; 482 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); 483 484 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); 485 txph = (struct tx_pkt_header *) 486 (((u8 *)adapter->txd_ring) + txd_read_ptr); 487 488 if (txph->pkt_size != txs->pkt_size) { 489 struct tx_pkt_status *old_txs = txs; 490 printk(KERN_WARNING 491 "%s: txs packet size not consistent with txd" 492 " txd_:0x%08x, txs_:0x%08x!\n", 493 adapter->netdev->name, 494 *(u32 *)txph, *(u32 *)txs); 495 printk(KERN_WARNING 496 "txd read ptr: 0x%x\n", 497 txd_read_ptr); 498 txs = adapter->txs_ring + txs_write_ptr; 499 printk(KERN_WARNING 500 "txs-behind:0x%08x\n", 501 *(u32 *)txs); 502 if (txs_write_ptr < 2) { 503 txs = adapter->txs_ring + 504 (adapter->txs_ring_size + 505 txs_write_ptr - 2); 506 } else { 507 txs = adapter->txs_ring + (txs_write_ptr - 2); 508 } 509 printk(KERN_WARNING 510 "txs-before:0x%08x\n", 511 *(u32 *)txs); 512 txs = old_txs; 513 } 514 515 /* 4for TPH */ 516 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); 517 if (txd_read_ptr >= adapter->txd_ring_size) 518 txd_read_ptr -= adapter->txd_ring_size; 519 520 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); 521 522 /* tx statistics: */ 523 if (txs->ok) { 524 netdev->stats.tx_bytes += txs->pkt_size; 525 netdev->stats.tx_packets++; 526 } 527 else 528 netdev->stats.tx_errors++; 529 530 if (txs->defer) 531 netdev->stats.collisions++; 532 if (txs->abort_col) 533 netdev->stats.tx_aborted_errors++; 534 if (txs->late_col) 535 netdev->stats.tx_window_errors++; 536 if (txs->underrun) 537 netdev->stats.tx_fifo_errors++; 538 } while (1); 539 540 if (free_hole) { 541 if (netif_queue_stopped(adapter->netdev) && 542 netif_carrier_ok(adapter->netdev)) 543 netif_wake_queue(adapter->netdev); 544 } 545} 546 547static void atl2_check_for_link(struct atl2_adapter *adapter) 548{ 549 struct net_device *netdev = adapter->netdev; 550 u16 phy_data = 0; 551 552 spin_lock(&adapter->stats_lock); 553 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 555 spin_unlock(&adapter->stats_lock); 556 557 /* notify upper layer link down ASAP */ 558 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 559 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 560 printk(KERN_INFO "%s: %s NIC Link is Down\n", 561 atl2_driver_name, netdev->name); 562 adapter->link_speed = SPEED_0; 563 netif_carrier_off(netdev); 564 netif_stop_queue(netdev); 565 } 566 } 567 schedule_work(&adapter->link_chg_task); 568} 569 570static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) 571{ 572 u16 phy_data; 573 spin_lock(&adapter->stats_lock); 574 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 575 spin_unlock(&adapter->stats_lock); 576} 577 578/** 579 * atl2_intr - Interrupt Handler 580 * @irq: interrupt number 581 * @data: pointer to a network interface device structure 582 */ 583static irqreturn_t atl2_intr(int irq, void *data) 584{ 585 struct atl2_adapter *adapter = netdev_priv(data); 586 struct atl2_hw *hw = &adapter->hw; 587 u32 status; 588 589 status = ATL2_READ_REG(hw, REG_ISR); 590 if (0 == status) 591 return IRQ_NONE; 592 593 /* link event */ 594 if (status & ISR_PHY) 595 atl2_clear_phy_int(adapter); 596 597 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 598 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 599 600 /* check if PCIE PHY Link down */ 601 if (status & ISR_PHY_LINKDOWN) { 602 if (netif_running(adapter->netdev)) { /* reset MAC */ 603 ATL2_WRITE_REG(hw, REG_ISR, 0); 604 ATL2_WRITE_REG(hw, REG_IMR, 0); 605 ATL2_WRITE_FLUSH(hw); 606 schedule_work(&adapter->reset_task); 607 return IRQ_HANDLED; 608 } 609 } 610 611 /* check if DMA read/write error? */ 612 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 613 ATL2_WRITE_REG(hw, REG_ISR, 0); 614 ATL2_WRITE_REG(hw, REG_IMR, 0); 615 ATL2_WRITE_FLUSH(hw); 616 schedule_work(&adapter->reset_task); 617 return IRQ_HANDLED; 618 } 619 620 /* link event */ 621 if (status & (ISR_PHY | ISR_MANUAL)) { 622 adapter->netdev->stats.tx_carrier_errors++; 623 atl2_check_for_link(adapter); 624 } 625 626 /* transmit event */ 627 if (status & ISR_TX_EVENT) 628 atl2_intr_tx(adapter); 629 630 /* rx exception */ 631 if (status & ISR_RX_EVENT) 632 atl2_intr_rx(adapter); 633 634 /* re-enable Interrupt */ 635 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 636 return IRQ_HANDLED; 637} 638 639static int atl2_request_irq(struct atl2_adapter *adapter) 640{ 641 struct net_device *netdev = adapter->netdev; 642 int flags, err = 0; 643 644 flags = IRQF_SHARED; 645 adapter->have_msi = true; 646 err = pci_enable_msi(adapter->pdev); 647 if (err) 648 adapter->have_msi = false; 649 650 if (adapter->have_msi) 651 flags &= ~IRQF_SHARED; 652 653 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, 654 netdev); 655} 656 657/** 658 * atl2_free_ring_resources - Free Tx / RX descriptor Resources 659 * @adapter: board private structure 660 * 661 * Free all transmit software resources 662 */ 663static void atl2_free_ring_resources(struct atl2_adapter *adapter) 664{ 665 struct pci_dev *pdev = adapter->pdev; 666 dma_free_coherent(&pdev->dev, adapter->ring_size, 667 adapter->ring_vir_addr, adapter->ring_dma); 668} 669 670/** 671 * atl2_open - Called when a network interface is made active 672 * @netdev: network interface device structure 673 * 674 * Returns 0 on success, negative value on failure 675 * 676 * The open entry point is called when a network interface is made 677 * active by the system (IFF_UP). At this point all resources needed 678 * for transmit and receive operations are allocated, the interrupt 679 * handler is registered with the OS, the watchdog timer is started, 680 * and the stack is notified that the interface is ready. 681 */ 682static int atl2_open(struct net_device *netdev) 683{ 684 struct atl2_adapter *adapter = netdev_priv(netdev); 685 int err; 686 u32 val; 687 688 /* disallow open during test */ 689 if (test_bit(__ATL2_TESTING, &adapter->flags)) 690 return -EBUSY; 691 692 /* allocate transmit descriptors */ 693 err = atl2_setup_ring_resources(adapter); 694 if (err) 695 return err; 696 697 err = atl2_init_hw(&adapter->hw); 698 if (err) { 699 err = -EIO; 700 goto err_init_hw; 701 } 702 703 /* hardware has been reset, we need to reload some things */ 704 atl2_set_multi(netdev); 705 init_ring_ptrs(adapter); 706 707 atl2_restore_vlan(adapter); 708 709 if (atl2_configure(adapter)) { 710 err = -EIO; 711 goto err_config; 712 } 713 714 err = atl2_request_irq(adapter); 715 if (err) 716 goto err_req_irq; 717 718 clear_bit(__ATL2_DOWN, &adapter->flags); 719 720 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); 721 722 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 723 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 724 val | MASTER_CTRL_MANUAL_INT); 725 726 atl2_irq_enable(adapter); 727 728 return 0; 729 730err_init_hw: 731err_req_irq: 732err_config: 733 atl2_free_ring_resources(adapter); 734 atl2_reset_hw(&adapter->hw); 735 736 return err; 737} 738 739static void atl2_down(struct atl2_adapter *adapter) 740{ 741 struct net_device *netdev = adapter->netdev; 742 743 /* signal that we're down so the interrupt handler does not 744 * reschedule our watchdog timer */ 745 set_bit(__ATL2_DOWN, &adapter->flags); 746 747 netif_tx_disable(netdev); 748 749 /* reset MAC to disable all RX/TX */ 750 atl2_reset_hw(&adapter->hw); 751 msleep(1); 752 753 atl2_irq_disable(adapter); 754 755 timer_delete_sync(&adapter->watchdog_timer); 756 timer_delete_sync(&adapter->phy_config_timer); 757 clear_bit(0, &adapter->cfg_phy); 758 759 netif_carrier_off(netdev); 760 adapter->link_speed = SPEED_0; 761 adapter->link_duplex = -1; 762} 763 764static void atl2_free_irq(struct atl2_adapter *adapter) 765{ 766 struct net_device *netdev = adapter->netdev; 767 768 free_irq(adapter->pdev->irq, netdev); 769 770#ifdef CONFIG_PCI_MSI 771 if (adapter->have_msi) 772 pci_disable_msi(adapter->pdev); 773#endif 774} 775 776/** 777 * atl2_close - Disables a network interface 778 * @netdev: network interface device structure 779 * 780 * Returns 0, this is not allowed to fail 781 * 782 * The close entry point is called when an interface is de-activated 783 * by the OS. The hardware is still under the drivers control, but 784 * needs to be disabled. A global MAC reset is issued to stop the 785 * hardware, and all transmit and receive resources are freed. 786 */ 787static int atl2_close(struct net_device *netdev) 788{ 789 struct atl2_adapter *adapter = netdev_priv(netdev); 790 791 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 792 793 atl2_down(adapter); 794 atl2_free_irq(adapter); 795 atl2_free_ring_resources(adapter); 796 797 return 0; 798} 799 800static inline int TxsFreeUnit(struct atl2_adapter *adapter) 801{ 802 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 803 804 return (adapter->txs_next_clear >= txs_write_ptr) ? 805 (int) (adapter->txs_ring_size - adapter->txs_next_clear + 806 txs_write_ptr - 1) : 807 (int) (txs_write_ptr - adapter->txs_next_clear - 1); 808} 809 810static inline int TxdFreeBytes(struct atl2_adapter *adapter) 811{ 812 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); 813 814 return (adapter->txd_write_ptr >= txd_read_ptr) ? 815 (int) (adapter->txd_ring_size - adapter->txd_write_ptr + 816 txd_read_ptr - 1) : 817 (int) (txd_read_ptr - adapter->txd_write_ptr - 1); 818} 819 820static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, 821 struct net_device *netdev) 822{ 823 struct atl2_adapter *adapter = netdev_priv(netdev); 824 struct tx_pkt_header *txph; 825 u32 offset, copy_len; 826 int txs_unused; 827 int txbuf_unused; 828 829 if (test_bit(__ATL2_DOWN, &adapter->flags)) { 830 dev_kfree_skb_any(skb); 831 return NETDEV_TX_OK; 832 } 833 834 if (unlikely(skb->len <= 0)) { 835 dev_kfree_skb_any(skb); 836 return NETDEV_TX_OK; 837 } 838 839 txs_unused = TxsFreeUnit(adapter); 840 txbuf_unused = TxdFreeBytes(adapter); 841 842 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || 843 txs_unused < 1) { 844 /* not enough resources */ 845 netif_stop_queue(netdev); 846 return NETDEV_TX_BUSY; 847 } 848 849 offset = adapter->txd_write_ptr; 850 851 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); 852 853 *(u32 *)txph = 0; 854 txph->pkt_size = skb->len; 855 856 offset += 4; 857 if (offset >= adapter->txd_ring_size) 858 offset -= adapter->txd_ring_size; 859 copy_len = adapter->txd_ring_size - offset; 860 if (copy_len >= skb->len) { 861 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); 862 offset += ((u32)(skb->len + 3) & ~3); 863 } else { 864 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); 865 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, 866 skb->len-copy_len); 867 offset = ((u32)(skb->len-copy_len + 3) & ~3); 868 } 869#ifdef NETIF_F_HW_VLAN_CTAG_TX 870 if (skb_vlan_tag_present(skb)) { 871 u16 vlan_tag = skb_vlan_tag_get(skb); 872 vlan_tag = (vlan_tag << 4) | 873 (vlan_tag >> 13) | 874 ((vlan_tag >> 9) & 0x8); 875 txph->ins_vlan = 1; 876 txph->vlan = vlan_tag; 877 } 878#endif 879 if (offset >= adapter->txd_ring_size) 880 offset -= adapter->txd_ring_size; 881 adapter->txd_write_ptr = offset; 882 883 /* clear txs before send */ 884 adapter->txs_ring[adapter->txs_next_clear].update = 0; 885 if (++adapter->txs_next_clear == adapter->txs_ring_size) 886 adapter->txs_next_clear = 0; 887 888 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, 889 (adapter->txd_write_ptr >> 2)); 890 891 dev_consume_skb_any(skb); 892 return NETDEV_TX_OK; 893} 894 895/** 896 * atl2_change_mtu - Change the Maximum Transfer Unit 897 * @netdev: network interface device structure 898 * @new_mtu: new value for maximum frame size 899 * 900 * Returns 0 on success, negative on failure 901 */ 902static int atl2_change_mtu(struct net_device *netdev, int new_mtu) 903{ 904 struct atl2_adapter *adapter = netdev_priv(netdev); 905 struct atl2_hw *hw = &adapter->hw; 906 907 /* set MTU */ 908 WRITE_ONCE(netdev->mtu, new_mtu); 909 hw->max_frame_size = new_mtu; 910 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ETH_HLEN + 911 VLAN_HLEN + ETH_FCS_LEN); 912 913 return 0; 914} 915 916/** 917 * atl2_set_mac - Change the Ethernet Address of the NIC 918 * @netdev: network interface device structure 919 * @p: pointer to an address structure 920 * 921 * Returns 0 on success, negative on failure 922 */ 923static int atl2_set_mac(struct net_device *netdev, void *p) 924{ 925 struct atl2_adapter *adapter = netdev_priv(netdev); 926 struct sockaddr *addr = p; 927 928 if (!is_valid_ether_addr(addr->sa_data)) 929 return -EADDRNOTAVAIL; 930 931 if (netif_running(netdev)) 932 return -EBUSY; 933 934 eth_hw_addr_set(netdev, addr->sa_data); 935 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); 936 937 atl2_set_mac_addr(&adapter->hw); 938 939 return 0; 940} 941 942static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 943{ 944 struct atl2_adapter *adapter = netdev_priv(netdev); 945 struct mii_ioctl_data *data = if_mii(ifr); 946 unsigned long flags; 947 948 switch (cmd) { 949 case SIOCGMIIPHY: 950 data->phy_id = 0; 951 break; 952 case SIOCGMIIREG: 953 spin_lock_irqsave(&adapter->stats_lock, flags); 954 if (atl2_read_phy_reg(&adapter->hw, 955 data->reg_num & 0x1F, &data->val_out)) { 956 spin_unlock_irqrestore(&adapter->stats_lock, flags); 957 return -EIO; 958 } 959 spin_unlock_irqrestore(&adapter->stats_lock, flags); 960 break; 961 case SIOCSMIIREG: 962 if (data->reg_num & ~(0x1F)) 963 return -EFAULT; 964 spin_lock_irqsave(&adapter->stats_lock, flags); 965 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, 966 data->val_in)) { 967 spin_unlock_irqrestore(&adapter->stats_lock, flags); 968 return -EIO; 969 } 970 spin_unlock_irqrestore(&adapter->stats_lock, flags); 971 break; 972 default: 973 return -EOPNOTSUPP; 974 } 975 return 0; 976} 977 978static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 979{ 980 switch (cmd) { 981 case SIOCGMIIPHY: 982 case SIOCGMIIREG: 983 case SIOCSMIIREG: 984 return atl2_mii_ioctl(netdev, ifr, cmd); 985#ifdef ETHTOOL_OPS_COMPAT 986 case SIOCETHTOOL: 987 return ethtool_ioctl(ifr); 988#endif 989 default: 990 return -EOPNOTSUPP; 991 } 992} 993 994/** 995 * atl2_tx_timeout - Respond to a Tx Hang 996 * @netdev: network interface device structure 997 * @txqueue: index of the hanging transmit queue 998 */ 999static void atl2_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1000{ 1001 struct atl2_adapter *adapter = netdev_priv(netdev); 1002 1003 /* Do the reset outside of interrupt context */ 1004 schedule_work(&adapter->reset_task); 1005} 1006 1007/** 1008 * atl2_watchdog - Timer Call-back 1009 * @t: timer list containing a pointer to netdev cast into an unsigned long 1010 */ 1011static void atl2_watchdog(struct timer_list *t) 1012{ 1013 struct atl2_adapter *adapter = timer_container_of(adapter, t, 1014 watchdog_timer); 1015 1016 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1017 u32 drop_rxd, drop_rxs; 1018 unsigned long flags; 1019 1020 spin_lock_irqsave(&adapter->stats_lock, flags); 1021 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); 1022 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); 1023 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1024 1025 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; 1026 1027 /* Reset the timer */ 1028 mod_timer(&adapter->watchdog_timer, 1029 round_jiffies(jiffies + 4 * HZ)); 1030 } 1031} 1032 1033/** 1034 * atl2_phy_config - Timer Call-back 1035 * @t: timer list containing a pointer to netdev cast into an unsigned long 1036 */ 1037static void atl2_phy_config(struct timer_list *t) 1038{ 1039 struct atl2_adapter *adapter = timer_container_of(adapter, t, 1040 phy_config_timer); 1041 struct atl2_hw *hw = &adapter->hw; 1042 unsigned long flags; 1043 1044 spin_lock_irqsave(&adapter->stats_lock, flags); 1045 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1046 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | 1047 MII_CR_RESTART_AUTO_NEG); 1048 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1049 clear_bit(0, &adapter->cfg_phy); 1050} 1051 1052static int atl2_up(struct atl2_adapter *adapter) 1053{ 1054 struct net_device *netdev = adapter->netdev; 1055 int err = 0; 1056 u32 val; 1057 1058 /* hardware has been reset, we need to reload some things */ 1059 1060 err = atl2_init_hw(&adapter->hw); 1061 if (err) { 1062 err = -EIO; 1063 return err; 1064 } 1065 1066 atl2_set_multi(netdev); 1067 init_ring_ptrs(adapter); 1068 1069 atl2_restore_vlan(adapter); 1070 1071 if (atl2_configure(adapter)) { 1072 err = -EIO; 1073 goto err_up; 1074 } 1075 1076 clear_bit(__ATL2_DOWN, &adapter->flags); 1077 1078 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 1079 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | 1080 MASTER_CTRL_MANUAL_INT); 1081 1082 atl2_irq_enable(adapter); 1083 1084err_up: 1085 return err; 1086} 1087 1088static void atl2_reinit_locked(struct atl2_adapter *adapter) 1089{ 1090 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1091 msleep(1); 1092 atl2_down(adapter); 1093 atl2_up(adapter); 1094 clear_bit(__ATL2_RESETTING, &adapter->flags); 1095} 1096 1097static void atl2_reset_task(struct work_struct *work) 1098{ 1099 struct atl2_adapter *adapter; 1100 adapter = container_of(work, struct atl2_adapter, reset_task); 1101 1102 atl2_reinit_locked(adapter); 1103} 1104 1105static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) 1106{ 1107 u32 value; 1108 struct atl2_hw *hw = &adapter->hw; 1109 struct net_device *netdev = adapter->netdev; 1110 1111 /* Config MAC CTRL Register */ 1112 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1113 1114 /* duplex */ 1115 if (FULL_DUPLEX == adapter->link_duplex) 1116 value |= MAC_CTRL_DUPLX; 1117 1118 /* flow control */ 1119 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1120 1121 /* PAD & CRC */ 1122 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1123 1124 /* preamble length */ 1125 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << 1126 MAC_CTRL_PRMLEN_SHIFT); 1127 1128 /* vlan */ 1129 __atl2_vlan_mode(netdev->features, &value); 1130 1131 /* filter mode */ 1132 value |= MAC_CTRL_BC_EN; 1133 if (netdev->flags & IFF_PROMISC) 1134 value |= MAC_CTRL_PROMIS_EN; 1135 else if (netdev->flags & IFF_ALLMULTI) 1136 value |= MAC_CTRL_MC_ALL_EN; 1137 1138 /* half retry buffer */ 1139 value |= (((u32)(adapter->hw.retry_buf & 1140 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1141 1142 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1143} 1144 1145static int atl2_check_link(struct atl2_adapter *adapter) 1146{ 1147 struct atl2_hw *hw = &adapter->hw; 1148 struct net_device *netdev = adapter->netdev; 1149 int ret_val; 1150 u16 speed, duplex, phy_data; 1151 int reconfig = 0; 1152 1153 /* MII_BMSR must read twise */ 1154 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1155 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1156 if (!(phy_data&BMSR_LSTATUS)) { /* link down */ 1157 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 1158 u32 value; 1159 /* disable rx */ 1160 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1161 value &= ~MAC_CTRL_RX_EN; 1162 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1163 adapter->link_speed = SPEED_0; 1164 netif_carrier_off(netdev); 1165 netif_stop_queue(netdev); 1166 } 1167 return 0; 1168 } 1169 1170 /* Link Up */ 1171 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1172 if (ret_val) 1173 return ret_val; 1174 switch (hw->MediaType) { 1175 case MEDIA_TYPE_100M_FULL: 1176 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1177 reconfig = 1; 1178 break; 1179 case MEDIA_TYPE_100M_HALF: 1180 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1181 reconfig = 1; 1182 break; 1183 case MEDIA_TYPE_10M_FULL: 1184 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1185 reconfig = 1; 1186 break; 1187 case MEDIA_TYPE_10M_HALF: 1188 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1189 reconfig = 1; 1190 break; 1191 } 1192 /* link result is our setting */ 1193 if (reconfig == 0) { 1194 if (adapter->link_speed != speed || 1195 adapter->link_duplex != duplex) { 1196 adapter->link_speed = speed; 1197 adapter->link_duplex = duplex; 1198 atl2_setup_mac_ctrl(adapter); 1199 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", 1200 atl2_driver_name, netdev->name, 1201 adapter->link_speed, 1202 adapter->link_duplex == FULL_DUPLEX ? 1203 "Full Duplex" : "Half Duplex"); 1204 } 1205 1206 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 1207 netif_carrier_on(netdev); 1208 netif_wake_queue(netdev); 1209 } 1210 return 0; 1211 } 1212 1213 /* change original link status */ 1214 if (netif_carrier_ok(netdev)) { 1215 u32 value; 1216 /* disable rx */ 1217 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1218 value &= ~MAC_CTRL_RX_EN; 1219 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1220 1221 adapter->link_speed = SPEED_0; 1222 netif_carrier_off(netdev); 1223 netif_stop_queue(netdev); 1224 } 1225 1226 /* auto-neg, insert timer to re-config phy 1227 * (if interval smaller than 5 seconds, something strange) */ 1228 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1229 if (!test_and_set_bit(0, &adapter->cfg_phy)) 1230 mod_timer(&adapter->phy_config_timer, 1231 round_jiffies(jiffies + 5 * HZ)); 1232 } 1233 1234 return 0; 1235} 1236 1237/** 1238 * atl2_link_chg_task - deal with link change event Out of interrupt context 1239 * @work: pointer to work struct with private info 1240 */ 1241static void atl2_link_chg_task(struct work_struct *work) 1242{ 1243 struct atl2_adapter *adapter; 1244 unsigned long flags; 1245 1246 adapter = container_of(work, struct atl2_adapter, link_chg_task); 1247 1248 spin_lock_irqsave(&adapter->stats_lock, flags); 1249 atl2_check_link(adapter); 1250 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1251} 1252 1253static void atl2_setup_pcicmd(struct pci_dev *pdev) 1254{ 1255 u16 cmd; 1256 1257 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1258 1259 if (cmd & PCI_COMMAND_INTX_DISABLE) 1260 cmd &= ~PCI_COMMAND_INTX_DISABLE; 1261 if (cmd & PCI_COMMAND_IO) 1262 cmd &= ~PCI_COMMAND_IO; 1263 if (0 == (cmd & PCI_COMMAND_MEMORY)) 1264 cmd |= PCI_COMMAND_MEMORY; 1265 if (0 == (cmd & PCI_COMMAND_MASTER)) 1266 cmd |= PCI_COMMAND_MASTER; 1267 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1268 1269 /* 1270 * some motherboards BIOS(PXE/EFI) driver may set PME 1271 * while they transfer control to OS (Windows/Linux) 1272 * so we should clear this bit before NIC work normally 1273 */ 1274 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 1275} 1276 1277#ifdef CONFIG_NET_POLL_CONTROLLER 1278static void atl2_poll_controller(struct net_device *netdev) 1279{ 1280 disable_irq(netdev->irq); 1281 atl2_intr(netdev->irq, netdev); 1282 enable_irq(netdev->irq); 1283} 1284#endif 1285 1286 1287static const struct net_device_ops atl2_netdev_ops = { 1288 .ndo_open = atl2_open, 1289 .ndo_stop = atl2_close, 1290 .ndo_start_xmit = atl2_xmit_frame, 1291 .ndo_set_rx_mode = atl2_set_multi, 1292 .ndo_validate_addr = eth_validate_addr, 1293 .ndo_set_mac_address = atl2_set_mac, 1294 .ndo_change_mtu = atl2_change_mtu, 1295 .ndo_fix_features = atl2_fix_features, 1296 .ndo_set_features = atl2_set_features, 1297 .ndo_eth_ioctl = atl2_ioctl, 1298 .ndo_tx_timeout = atl2_tx_timeout, 1299#ifdef CONFIG_NET_POLL_CONTROLLER 1300 .ndo_poll_controller = atl2_poll_controller, 1301#endif 1302}; 1303 1304/** 1305 * atl2_probe - Device Initialization Routine 1306 * @pdev: PCI device information struct 1307 * @ent: entry in atl2_pci_tbl 1308 * 1309 * Returns 0 on success, negative on failure 1310 * 1311 * atl2_probe initializes an adapter identified by a pci_dev structure. 1312 * The OS initialization, configuring of the adapter private structure, 1313 * and a hardware reset occur. 1314 */ 1315static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1316{ 1317 struct net_device *netdev; 1318 struct atl2_adapter *adapter; 1319 static int cards_found = 0; 1320 unsigned long mmio_start; 1321 int mmio_len; 1322 int err; 1323 1324 err = pci_enable_device(pdev); 1325 if (err) 1326 return err; 1327 1328 /* 1329 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA 1330 * until the kernel has the proper infrastructure to support 64-bit DMA 1331 * on these devices. 1332 */ 1333 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) && 1334 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1335 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); 1336 err = -EIO; 1337 goto err_dma; 1338 } 1339 1340 /* Mark all PCI regions associated with PCI device 1341 * pdev as being reserved by owner atl2_driver_name */ 1342 err = pci_request_regions(pdev, atl2_driver_name); 1343 if (err) 1344 goto err_pci_reg; 1345 1346 /* Enables bus-mastering on the device and calls 1347 * pcibios_set_master to do the needed arch specific settings */ 1348 pci_set_master(pdev); 1349 1350 netdev = alloc_etherdev(sizeof(struct atl2_adapter)); 1351 if (!netdev) { 1352 err = -ENOMEM; 1353 goto err_alloc_etherdev; 1354 } 1355 1356 SET_NETDEV_DEV(netdev, &pdev->dev); 1357 1358 pci_set_drvdata(pdev, netdev); 1359 adapter = netdev_priv(netdev); 1360 adapter->netdev = netdev; 1361 adapter->pdev = pdev; 1362 adapter->hw.back = adapter; 1363 1364 mmio_start = pci_resource_start(pdev, 0x0); 1365 mmio_len = pci_resource_len(pdev, 0x0); 1366 1367 adapter->hw.mem_rang = (u32)mmio_len; 1368 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 1369 if (!adapter->hw.hw_addr) { 1370 err = -EIO; 1371 goto err_ioremap; 1372 } 1373 1374 atl2_setup_pcicmd(pdev); 1375 1376 netdev->netdev_ops = &atl2_netdev_ops; 1377 netdev->ethtool_ops = &atl2_ethtool_ops; 1378 netdev->watchdog_timeo = 5 * HZ; 1379 netdev->min_mtu = 40; 1380 netdev->max_mtu = ETH_DATA_LEN + VLAN_HLEN; 1381 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 1382 1383 netdev->mem_start = mmio_start; 1384 netdev->mem_end = mmio_start + mmio_len; 1385 adapter->bd_number = cards_found; 1386 adapter->pci_using_64 = false; 1387 1388 /* setup the private structure */ 1389 err = atl2_sw_init(adapter); 1390 if (err) 1391 goto err_sw_init; 1392 1393 netdev->hw_features = NETIF_F_HW_VLAN_CTAG_RX; 1394 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 1395 1396 /* Init PHY as early as possible due to power saving issue */ 1397 atl2_phy_init(&adapter->hw); 1398 1399 /* reset the controller to 1400 * put the device in a known good starting state */ 1401 1402 if (atl2_reset_hw(&adapter->hw)) { 1403 err = -EIO; 1404 goto err_reset; 1405 } 1406 1407 /* copy the MAC address out of the EEPROM */ 1408 atl2_read_mac_addr(&adapter->hw); 1409 eth_hw_addr_set(netdev, adapter->hw.mac_addr); 1410 if (!is_valid_ether_addr(netdev->dev_addr)) { 1411 err = -EIO; 1412 goto err_eeprom; 1413 } 1414 1415 atl2_check_options(adapter); 1416 1417 timer_setup(&adapter->watchdog_timer, atl2_watchdog, 0); 1418 1419 timer_setup(&adapter->phy_config_timer, atl2_phy_config, 0); 1420 1421 INIT_WORK(&adapter->reset_task, atl2_reset_task); 1422 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); 1423 1424 strcpy(netdev->name, "eth%d"); /* ?? */ 1425 err = register_netdev(netdev); 1426 if (err) 1427 goto err_register; 1428 1429 /* assume we have no link for now */ 1430 netif_carrier_off(netdev); 1431 netif_stop_queue(netdev); 1432 1433 cards_found++; 1434 1435 return 0; 1436 1437err_reset: 1438err_register: 1439err_sw_init: 1440err_eeprom: 1441 iounmap(adapter->hw.hw_addr); 1442err_ioremap: 1443 free_netdev(netdev); 1444err_alloc_etherdev: 1445 pci_release_regions(pdev); 1446err_pci_reg: 1447err_dma: 1448 pci_disable_device(pdev); 1449 return err; 1450} 1451 1452/** 1453 * atl2_remove - Device Removal Routine 1454 * @pdev: PCI device information struct 1455 * 1456 * atl2_remove is called by the PCI subsystem to alert the driver 1457 * that it should release a PCI device. The could be caused by a 1458 * Hot-Plug event, or because the driver is going to be removed from 1459 * memory. 1460 */ 1461/* FIXME: write the original MAC address back in case it was changed from a 1462 * BIOS-set value, as in atl1 -- CHS */ 1463static void atl2_remove(struct pci_dev *pdev) 1464{ 1465 struct net_device *netdev = pci_get_drvdata(pdev); 1466 struct atl2_adapter *adapter = netdev_priv(netdev); 1467 1468 /* flush_scheduled work may reschedule our watchdog task, so 1469 * explicitly disable watchdog tasks from being rescheduled */ 1470 set_bit(__ATL2_DOWN, &adapter->flags); 1471 1472 timer_delete_sync(&adapter->watchdog_timer); 1473 timer_delete_sync(&adapter->phy_config_timer); 1474 cancel_work_sync(&adapter->reset_task); 1475 cancel_work_sync(&adapter->link_chg_task); 1476 1477 unregister_netdev(netdev); 1478 1479 atl2_force_ps(&adapter->hw); 1480 1481 iounmap(adapter->hw.hw_addr); 1482 pci_release_regions(pdev); 1483 1484 free_netdev(netdev); 1485 1486 pci_disable_device(pdev); 1487} 1488 1489static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) 1490{ 1491 struct net_device *netdev = pci_get_drvdata(pdev); 1492 struct atl2_adapter *adapter = netdev_priv(netdev); 1493 struct atl2_hw *hw = &adapter->hw; 1494 u16 speed, duplex; 1495 u32 ctrl = 0; 1496 u32 wufc = adapter->wol; 1497 1498#ifdef CONFIG_PM 1499 int retval = 0; 1500#endif 1501 1502 netif_device_detach(netdev); 1503 1504 if (netif_running(netdev)) { 1505 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 1506 atl2_down(adapter); 1507 } 1508 1509#ifdef CONFIG_PM 1510 retval = pci_save_state(pdev); 1511 if (retval) 1512 return retval; 1513#endif 1514 1515 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1516 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1517 if (ctrl & BMSR_LSTATUS) 1518 wufc &= ~ATLX_WUFC_LNKC; 1519 1520 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { 1521 u32 ret_val; 1522 /* get current link speed & duplex */ 1523 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1524 if (ret_val) { 1525 printk(KERN_DEBUG 1526 "%s: get speed&duplex error while suspend\n", 1527 atl2_driver_name); 1528 goto wol_dis; 1529 } 1530 1531 ctrl = 0; 1532 1533 /* turn on magic packet wol */ 1534 if (wufc & ATLX_WUFC_MAG) 1535 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 1536 1537 /* ignore Link Chg event when Link is up */ 1538 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1539 1540 /* Config MAC CTRL Register */ 1541 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1542 if (FULL_DUPLEX == adapter->link_duplex) 1543 ctrl |= MAC_CTRL_DUPLX; 1544 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1545 ctrl |= (((u32)adapter->hw.preamble_len & 1546 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1547 ctrl |= (((u32)(adapter->hw.retry_buf & 1548 MAC_CTRL_HALF_LEFT_BUF_MASK)) << 1549 MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1550 if (wufc & ATLX_WUFC_MAG) { 1551 /* magic packet maybe Broadcast&multicast&Unicast */ 1552 ctrl |= MAC_CTRL_BC_EN; 1553 } 1554 1555 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); 1556 1557 /* pcie patch */ 1558 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1559 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1560 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1561 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1562 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1563 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1564 1565 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1566 goto suspend_exit; 1567 } 1568 1569 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { 1570 /* link is down, so only LINK CHG WOL event enable */ 1571 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1572 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1573 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); 1574 1575 /* pcie patch */ 1576 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1577 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1578 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1579 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1580 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1581 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1582 1583 hw->phy_configured = false; /* re-init PHY when resume */ 1584 1585 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1586 1587 goto suspend_exit; 1588 } 1589 1590wol_dis: 1591 /* WOL disabled */ 1592 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); 1593 1594 /* pcie patch */ 1595 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1596 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1597 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1598 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1599 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1600 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1601 1602 atl2_force_ps(hw); 1603 hw->phy_configured = false; /* re-init PHY when resume */ 1604 1605 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1606 1607suspend_exit: 1608 if (netif_running(netdev)) 1609 atl2_free_irq(adapter); 1610 1611 pci_disable_device(pdev); 1612 1613 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1614 1615 return 0; 1616} 1617 1618#ifdef CONFIG_PM 1619static int atl2_resume(struct pci_dev *pdev) 1620{ 1621 struct net_device *netdev = pci_get_drvdata(pdev); 1622 struct atl2_adapter *adapter = netdev_priv(netdev); 1623 u32 err; 1624 1625 pci_set_power_state(pdev, PCI_D0); 1626 pci_restore_state(pdev); 1627 1628 err = pci_enable_device(pdev); 1629 if (err) { 1630 printk(KERN_ERR 1631 "atl2: Cannot enable PCI device from suspend\n"); 1632 return err; 1633 } 1634 1635 pci_set_master(pdev); 1636 1637 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ 1638 1639 pci_enable_wake(pdev, PCI_D3hot, 0); 1640 pci_enable_wake(pdev, PCI_D3cold, 0); 1641 1642 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); 1643 1644 if (netif_running(netdev)) { 1645 err = atl2_request_irq(adapter); 1646 if (err) 1647 return err; 1648 } 1649 1650 atl2_reset_hw(&adapter->hw); 1651 1652 if (netif_running(netdev)) 1653 atl2_up(adapter); 1654 1655 netif_device_attach(netdev); 1656 1657 return 0; 1658} 1659#endif 1660 1661static void atl2_shutdown(struct pci_dev *pdev) 1662{ 1663 atl2_suspend(pdev, PMSG_SUSPEND); 1664} 1665 1666static struct pci_driver atl2_driver = { 1667 .name = atl2_driver_name, 1668 .id_table = atl2_pci_tbl, 1669 .probe = atl2_probe, 1670 .remove = atl2_remove, 1671 /* Power Management Hooks */ 1672 .suspend = atl2_suspend, 1673#ifdef CONFIG_PM 1674 .resume = atl2_resume, 1675#endif 1676 .shutdown = atl2_shutdown, 1677}; 1678 1679module_pci_driver(atl2_driver); 1680 1681static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1682{ 1683 struct atl2_adapter *adapter = hw->back; 1684 pci_read_config_word(adapter->pdev, reg, value); 1685} 1686 1687static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1688{ 1689 struct atl2_adapter *adapter = hw->back; 1690 pci_write_config_word(adapter->pdev, reg, *value); 1691} 1692 1693static int atl2_get_link_ksettings(struct net_device *netdev, 1694 struct ethtool_link_ksettings *cmd) 1695{ 1696 struct atl2_adapter *adapter = netdev_priv(netdev); 1697 struct atl2_hw *hw = &adapter->hw; 1698 u32 supported, advertising; 1699 1700 supported = (SUPPORTED_10baseT_Half | 1701 SUPPORTED_10baseT_Full | 1702 SUPPORTED_100baseT_Half | 1703 SUPPORTED_100baseT_Full | 1704 SUPPORTED_Autoneg | 1705 SUPPORTED_TP); 1706 advertising = ADVERTISED_TP; 1707 1708 advertising |= ADVERTISED_Autoneg; 1709 advertising |= hw->autoneg_advertised; 1710 1711 cmd->base.port = PORT_TP; 1712 cmd->base.phy_address = 0; 1713 1714 if (adapter->link_speed != SPEED_0) { 1715 cmd->base.speed = adapter->link_speed; 1716 if (adapter->link_duplex == FULL_DUPLEX) 1717 cmd->base.duplex = DUPLEX_FULL; 1718 else 1719 cmd->base.duplex = DUPLEX_HALF; 1720 } else { 1721 cmd->base.speed = SPEED_UNKNOWN; 1722 cmd->base.duplex = DUPLEX_UNKNOWN; 1723 } 1724 1725 cmd->base.autoneg = AUTONEG_ENABLE; 1726 1727 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1728 supported); 1729 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1730 advertising); 1731 1732 return 0; 1733} 1734 1735static int atl2_set_link_ksettings(struct net_device *netdev, 1736 const struct ethtool_link_ksettings *cmd) 1737{ 1738 struct atl2_adapter *adapter = netdev_priv(netdev); 1739 struct atl2_hw *hw = &adapter->hw; 1740 u32 advertising; 1741 1742 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1743 cmd->link_modes.advertising); 1744 1745 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1746 msleep(1); 1747 1748 if (cmd->base.autoneg == AUTONEG_ENABLE) { 1749#define MY_ADV_MASK (ADVERTISE_10_HALF | \ 1750 ADVERTISE_10_FULL | \ 1751 ADVERTISE_100_HALF| \ 1752 ADVERTISE_100_FULL) 1753 1754 if ((advertising & MY_ADV_MASK) == MY_ADV_MASK) { 1755 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; 1756 hw->autoneg_advertised = MY_ADV_MASK; 1757 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_FULL) { 1758 hw->MediaType = MEDIA_TYPE_100M_FULL; 1759 hw->autoneg_advertised = ADVERTISE_100_FULL; 1760 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_HALF) { 1761 hw->MediaType = MEDIA_TYPE_100M_HALF; 1762 hw->autoneg_advertised = ADVERTISE_100_HALF; 1763 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_FULL) { 1764 hw->MediaType = MEDIA_TYPE_10M_FULL; 1765 hw->autoneg_advertised = ADVERTISE_10_FULL; 1766 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_HALF) { 1767 hw->MediaType = MEDIA_TYPE_10M_HALF; 1768 hw->autoneg_advertised = ADVERTISE_10_HALF; 1769 } else { 1770 clear_bit(__ATL2_RESETTING, &adapter->flags); 1771 return -EINVAL; 1772 } 1773 advertising = hw->autoneg_advertised | 1774 ADVERTISED_TP | ADVERTISED_Autoneg; 1775 } else { 1776 clear_bit(__ATL2_RESETTING, &adapter->flags); 1777 return -EINVAL; 1778 } 1779 1780 /* reset the link */ 1781 if (netif_running(adapter->netdev)) { 1782 atl2_down(adapter); 1783 atl2_up(adapter); 1784 } else 1785 atl2_reset_hw(&adapter->hw); 1786 1787 clear_bit(__ATL2_RESETTING, &adapter->flags); 1788 return 0; 1789} 1790 1791static u32 atl2_get_msglevel(struct net_device *netdev) 1792{ 1793 return 0; 1794} 1795 1796/* 1797 * It's sane for this to be empty, but we might want to take advantage of this. 1798 */ 1799static void atl2_set_msglevel(struct net_device *netdev, u32 data) 1800{ 1801} 1802 1803static int atl2_get_regs_len(struct net_device *netdev) 1804{ 1805#define ATL2_REGS_LEN 42 1806 return sizeof(u32) * ATL2_REGS_LEN; 1807} 1808 1809static void atl2_get_regs(struct net_device *netdev, 1810 struct ethtool_regs *regs, void *p) 1811{ 1812 struct atl2_adapter *adapter = netdev_priv(netdev); 1813 struct atl2_hw *hw = &adapter->hw; 1814 u32 *regs_buff = p; 1815 u16 phy_data; 1816 1817 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); 1818 1819 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 1820 1821 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); 1822 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 1823 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); 1824 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); 1825 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); 1826 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); 1827 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); 1828 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); 1829 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); 1830 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); 1831 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); 1832 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); 1833 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); 1834 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); 1835 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); 1836 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 1837 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); 1838 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); 1839 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); 1840 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); 1841 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); 1842 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); 1843 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); 1844 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); 1845 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); 1846 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); 1847 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); 1848 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); 1849 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); 1850 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); 1851 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); 1852 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); 1853 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); 1854 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); 1855 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); 1856 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); 1857 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); 1858 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); 1859 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); 1860 1861 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); 1862 regs_buff[40] = (u32)phy_data; 1863 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1864 regs_buff[41] = (u32)phy_data; 1865} 1866 1867static int atl2_get_eeprom_len(struct net_device *netdev) 1868{ 1869 struct atl2_adapter *adapter = netdev_priv(netdev); 1870 1871 if (!atl2_check_eeprom_exist(&adapter->hw)) 1872 return 512; 1873 else 1874 return 0; 1875} 1876 1877static int atl2_get_eeprom(struct net_device *netdev, 1878 struct ethtool_eeprom *eeprom, u8 *bytes) 1879{ 1880 struct atl2_adapter *adapter = netdev_priv(netdev); 1881 struct atl2_hw *hw = &adapter->hw; 1882 u32 *eeprom_buff; 1883 int first_dword, last_dword; 1884 int ret_val = 0; 1885 int i; 1886 1887 if (eeprom->len == 0) 1888 return -EINVAL; 1889 1890 if (atl2_check_eeprom_exist(hw)) 1891 return -EINVAL; 1892 1893 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1894 1895 first_dword = eeprom->offset >> 2; 1896 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1897 1898 eeprom_buff = kmalloc_array(last_dword - first_dword + 1, sizeof(u32), 1899 GFP_KERNEL); 1900 if (!eeprom_buff) 1901 return -ENOMEM; 1902 1903 for (i = first_dword; i < last_dword; i++) { 1904 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { 1905 ret_val = -EIO; 1906 goto free; 1907 } 1908 } 1909 1910 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), 1911 eeprom->len); 1912free: 1913 kfree(eeprom_buff); 1914 1915 return ret_val; 1916} 1917 1918static int atl2_set_eeprom(struct net_device *netdev, 1919 struct ethtool_eeprom *eeprom, u8 *bytes) 1920{ 1921 struct atl2_adapter *adapter = netdev_priv(netdev); 1922 struct atl2_hw *hw = &adapter->hw; 1923 u32 *eeprom_buff; 1924 u32 *ptr; 1925 int max_len, first_dword, last_dword, ret_val = 0; 1926 int i; 1927 1928 if (eeprom->len == 0) 1929 return -EOPNOTSUPP; 1930 1931 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1932 return -EFAULT; 1933 1934 max_len = 512; 1935 1936 first_dword = eeprom->offset >> 2; 1937 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1938 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1939 if (!eeprom_buff) 1940 return -ENOMEM; 1941 1942 ptr = eeprom_buff; 1943 1944 if (eeprom->offset & 3) { 1945 /* need read/modify/write of first changed EEPROM word */ 1946 /* only the second byte of the word is being modified */ 1947 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { 1948 ret_val = -EIO; 1949 goto out; 1950 } 1951 ptr++; 1952 } 1953 if (((eeprom->offset + eeprom->len) & 3)) { 1954 /* 1955 * need read/modify/write of last changed EEPROM word 1956 * only the first byte of the word is being modified 1957 */ 1958 if (!atl2_read_eeprom(hw, last_dword * 4, 1959 &(eeprom_buff[last_dword - first_dword]))) { 1960 ret_val = -EIO; 1961 goto out; 1962 } 1963 } 1964 1965 /* Device's eeprom is always little-endian, word addressable */ 1966 memcpy(ptr, bytes, eeprom->len); 1967 1968 for (i = 0; i < last_dword - first_dword + 1; i++) { 1969 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { 1970 ret_val = -EIO; 1971 goto out; 1972 } 1973 } 1974 out: 1975 kfree(eeprom_buff); 1976 return ret_val; 1977} 1978 1979static void atl2_get_drvinfo(struct net_device *netdev, 1980 struct ethtool_drvinfo *drvinfo) 1981{ 1982 struct atl2_adapter *adapter = netdev_priv(netdev); 1983 1984 strscpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); 1985 strscpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); 1986 strscpy(drvinfo->bus_info, pci_name(adapter->pdev), 1987 sizeof(drvinfo->bus_info)); 1988} 1989 1990static void atl2_get_wol(struct net_device *netdev, 1991 struct ethtool_wolinfo *wol) 1992{ 1993 struct atl2_adapter *adapter = netdev_priv(netdev); 1994 1995 wol->supported = WAKE_MAGIC; 1996 wol->wolopts = 0; 1997 1998 if (adapter->wol & ATLX_WUFC_EX) 1999 wol->wolopts |= WAKE_UCAST; 2000 if (adapter->wol & ATLX_WUFC_MC) 2001 wol->wolopts |= WAKE_MCAST; 2002 if (adapter->wol & ATLX_WUFC_BC) 2003 wol->wolopts |= WAKE_BCAST; 2004 if (adapter->wol & ATLX_WUFC_MAG) 2005 wol->wolopts |= WAKE_MAGIC; 2006 if (adapter->wol & ATLX_WUFC_LNKC) 2007 wol->wolopts |= WAKE_PHY; 2008} 2009 2010static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2011{ 2012 struct atl2_adapter *adapter = netdev_priv(netdev); 2013 2014 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2015 return -EOPNOTSUPP; 2016 2017 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) 2018 return -EOPNOTSUPP; 2019 2020 /* these settings will always override what we currently have */ 2021 adapter->wol = 0; 2022 2023 if (wol->wolopts & WAKE_MAGIC) 2024 adapter->wol |= ATLX_WUFC_MAG; 2025 if (wol->wolopts & WAKE_PHY) 2026 adapter->wol |= ATLX_WUFC_LNKC; 2027 2028 return 0; 2029} 2030 2031static int atl2_nway_reset(struct net_device *netdev) 2032{ 2033 struct atl2_adapter *adapter = netdev_priv(netdev); 2034 if (netif_running(netdev)) 2035 atl2_reinit_locked(adapter); 2036 return 0; 2037} 2038 2039static const struct ethtool_ops atl2_ethtool_ops = { 2040 .get_drvinfo = atl2_get_drvinfo, 2041 .get_regs_len = atl2_get_regs_len, 2042 .get_regs = atl2_get_regs, 2043 .get_wol = atl2_get_wol, 2044 .set_wol = atl2_set_wol, 2045 .get_msglevel = atl2_get_msglevel, 2046 .set_msglevel = atl2_set_msglevel, 2047 .nway_reset = atl2_nway_reset, 2048 .get_link = ethtool_op_get_link, 2049 .get_eeprom_len = atl2_get_eeprom_len, 2050 .get_eeprom = atl2_get_eeprom, 2051 .set_eeprom = atl2_set_eeprom, 2052 .get_link_ksettings = atl2_get_link_ksettings, 2053 .set_link_ksettings = atl2_set_link_ksettings, 2054}; 2055 2056#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ 2057 (((a) & 0xff00ff00) >> 8)) 2058#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) 2059#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) 2060 2061/* 2062 * Reset the transmit and receive units; mask and clear all interrupts. 2063 * 2064 * hw - Struct containing variables accessed by shared code 2065 * return : 0 or idle status (if error) 2066 */ 2067static s32 atl2_reset_hw(struct atl2_hw *hw) 2068{ 2069 u32 icr; 2070 u16 pci_cfg_cmd_word; 2071 int i; 2072 2073 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 2074 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2075 if ((pci_cfg_cmd_word & 2076 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != 2077 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { 2078 pci_cfg_cmd_word |= 2079 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); 2080 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2081 } 2082 2083 /* Clear Interrupt mask to stop board from generating 2084 * interrupts & Clear any pending interrupt events 2085 */ 2086 /* FIXME */ 2087 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ 2088 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ 2089 2090 /* Issue Soft Reset to the MAC. This will reset the chip's 2091 * transmit, receive, DMA. It will not effect 2092 * the current PCI configuration. The global reset bit is self- 2093 * clearing, and should clear within a microsecond. 2094 */ 2095 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); 2096 wmb(); 2097 msleep(1); /* delay about 1ms */ 2098 2099 /* Wait at least 10ms for All module to be Idle */ 2100 for (i = 0; i < 10; i++) { 2101 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); 2102 if (!icr) 2103 break; 2104 msleep(1); /* delay 1 ms */ 2105 cpu_relax(); 2106 } 2107 2108 if (icr) 2109 return icr; 2110 2111 return 0; 2112} 2113 2114#define CUSTOM_SPI_CS_SETUP 2 2115#define CUSTOM_SPI_CLK_HI 2 2116#define CUSTOM_SPI_CLK_LO 2 2117#define CUSTOM_SPI_CS_HOLD 2 2118#define CUSTOM_SPI_CS_HI 3 2119 2120static struct atl2_spi_flash_dev flash_table[] = 2121{ 2122/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ 2123{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, 2124{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, 2125{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, 2126}; 2127 2128static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) 2129{ 2130 int i; 2131 u32 value; 2132 2133 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); 2134 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); 2135 2136 value = SPI_FLASH_CTRL_WAIT_READY | 2137 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 2138 SPI_FLASH_CTRL_CS_SETUP_SHIFT | 2139 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << 2140 SPI_FLASH_CTRL_CLK_HI_SHIFT | 2141 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << 2142 SPI_FLASH_CTRL_CLK_LO_SHIFT | 2143 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << 2144 SPI_FLASH_CTRL_CS_HOLD_SHIFT | 2145 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << 2146 SPI_FLASH_CTRL_CS_HI_SHIFT | 2147 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; 2148 2149 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2150 2151 value |= SPI_FLASH_CTRL_START; 2152 2153 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2154 2155 for (i = 0; i < 10; i++) { 2156 msleep(1); 2157 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2158 if (!(value & SPI_FLASH_CTRL_START)) 2159 break; 2160 } 2161 2162 if (value & SPI_FLASH_CTRL_START) 2163 return false; 2164 2165 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); 2166 2167 return true; 2168} 2169 2170/* 2171 * get_permanent_address 2172 * return 0 if get valid mac address, 2173 */ 2174static int get_permanent_address(struct atl2_hw *hw) 2175{ 2176 u32 Addr[2]; 2177 u32 i, Control; 2178 u16 Register; 2179 u8 EthAddr[ETH_ALEN]; 2180 bool KeyValid; 2181 2182 if (is_valid_ether_addr(hw->perm_mac_addr)) 2183 return 0; 2184 2185 Addr[0] = 0; 2186 Addr[1] = 0; 2187 2188 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ 2189 Register = 0; 2190 KeyValid = false; 2191 2192 /* Read out all EEPROM content */ 2193 i = 0; 2194 while (1) { 2195 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { 2196 if (KeyValid) { 2197 if (Register == REG_MAC_STA_ADDR) 2198 Addr[0] = Control; 2199 else if (Register == 2200 (REG_MAC_STA_ADDR + 4)) 2201 Addr[1] = Control; 2202 KeyValid = false; 2203 } else if ((Control & 0xff) == 0x5A) { 2204 KeyValid = true; 2205 Register = (u16) (Control >> 16); 2206 } else { 2207 /* assume data end while encount an invalid KEYWORD */ 2208 break; 2209 } 2210 } else { 2211 break; /* read error */ 2212 } 2213 i += 4; 2214 } 2215 2216 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2217 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2218 2219 if (is_valid_ether_addr(EthAddr)) { 2220 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2221 return 0; 2222 } 2223 return 1; 2224 } 2225 2226 /* see if SPI flash exists? */ 2227 Addr[0] = 0; 2228 Addr[1] = 0; 2229 Register = 0; 2230 KeyValid = false; 2231 i = 0; 2232 while (1) { 2233 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { 2234 if (KeyValid) { 2235 if (Register == REG_MAC_STA_ADDR) 2236 Addr[0] = Control; 2237 else if (Register == (REG_MAC_STA_ADDR + 4)) 2238 Addr[1] = Control; 2239 KeyValid = false; 2240 } else if ((Control & 0xff) == 0x5A) { 2241 KeyValid = true; 2242 Register = (u16) (Control >> 16); 2243 } else { 2244 break; /* data end */ 2245 } 2246 } else { 2247 break; /* read error */ 2248 } 2249 i += 4; 2250 } 2251 2252 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2253 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); 2254 if (is_valid_ether_addr(EthAddr)) { 2255 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2256 return 0; 2257 } 2258 /* maybe MAC-address is from BIOS */ 2259 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 2260 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); 2261 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2262 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2263 2264 if (is_valid_ether_addr(EthAddr)) { 2265 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2266 return 0; 2267 } 2268 2269 return 1; 2270} 2271 2272/* 2273 * Reads the adapter's MAC address from the EEPROM 2274 * 2275 * hw - Struct containing variables accessed by shared code 2276 */ 2277static s32 atl2_read_mac_addr(struct atl2_hw *hw) 2278{ 2279 if (get_permanent_address(hw)) { 2280 /* for test */ 2281 /* FIXME: shouldn't we use eth_random_addr() here? */ 2282 hw->perm_mac_addr[0] = 0x00; 2283 hw->perm_mac_addr[1] = 0x13; 2284 hw->perm_mac_addr[2] = 0x74; 2285 hw->perm_mac_addr[3] = 0x00; 2286 hw->perm_mac_addr[4] = 0x5c; 2287 hw->perm_mac_addr[5] = 0x38; 2288 } 2289 2290 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); 2291 2292 return 0; 2293} 2294 2295/* 2296 * Hashes an address to determine its location in the multicast table 2297 * 2298 * hw - Struct containing variables accessed by shared code 2299 * mc_addr - the multicast address to hash 2300 * 2301 * atl2_hash_mc_addr 2302 * purpose 2303 * set hash value for a multicast address 2304 * hash calcu processing : 2305 * 1. calcu 32bit CRC for multicast address 2306 * 2. reverse crc with MSB to LSB 2307 */ 2308static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) 2309{ 2310 u32 crc32, value; 2311 int i; 2312 2313 value = 0; 2314 crc32 = ether_crc_le(6, mc_addr); 2315 2316 for (i = 0; i < 32; i++) 2317 value |= (((crc32 >> i) & 1) << (31 - i)); 2318 2319 return value; 2320} 2321 2322/* 2323 * Sets the bit in the multicast table corresponding to the hash value. 2324 * 2325 * hw - Struct containing variables accessed by shared code 2326 * hash_value - Multicast address hash value 2327 */ 2328static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) 2329{ 2330 u32 hash_bit, hash_reg; 2331 u32 mta; 2332 2333 /* The HASH Table is a register array of 2 32-bit registers. 2334 * It is treated like an array of 64 bits. We want to set 2335 * bit BitArray[hash_value]. So we figure out what register 2336 * the bit is in, read it, OR in the new bit, then write 2337 * back the new value. The register is determined by the 2338 * upper 7 bits of the hash value and the bit within that 2339 * register are determined by the lower 5 bits of the value. 2340 */ 2341 hash_reg = (hash_value >> 31) & 0x1; 2342 hash_bit = (hash_value >> 26) & 0x1F; 2343 2344 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 2345 2346 mta |= (1 << hash_bit); 2347 2348 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 2349} 2350 2351/* 2352 * atl2_init_pcie - init PCIE module 2353 */ 2354static void atl2_init_pcie(struct atl2_hw *hw) 2355{ 2356 u32 value; 2357 value = LTSSM_TEST_MODE_DEF; 2358 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 2359 2360 value = PCIE_DLL_TX_CTRL1_DEF; 2361 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); 2362} 2363 2364static void atl2_init_flash_opcode(struct atl2_hw *hw) 2365{ 2366 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 2367 hw->flash_vendor = 0; /* ATMEL */ 2368 2369 /* Init OP table */ 2370 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, 2371 flash_table[hw->flash_vendor].cmdPROGRAM); 2372 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, 2373 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); 2374 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, 2375 flash_table[hw->flash_vendor].cmdCHIP_ERASE); 2376 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, 2377 flash_table[hw->flash_vendor].cmdRDID); 2378 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, 2379 flash_table[hw->flash_vendor].cmdWREN); 2380 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, 2381 flash_table[hw->flash_vendor].cmdRDSR); 2382 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, 2383 flash_table[hw->flash_vendor].cmdWRSR); 2384 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, 2385 flash_table[hw->flash_vendor].cmdREAD); 2386} 2387 2388/******************************************************************** 2389* Performs basic configuration of the adapter. 2390* 2391* hw - Struct containing variables accessed by shared code 2392* Assumes that the controller has previously been reset and is in a 2393* post-reset uninitialized state. Initializes multicast table, 2394* and Calls routines to setup link 2395* Leaves the transmit and receive units disabled and uninitialized. 2396********************************************************************/ 2397static s32 atl2_init_hw(struct atl2_hw *hw) 2398{ 2399 u32 ret_val = 0; 2400 2401 atl2_init_pcie(hw); 2402 2403 /* Zero out the Multicast HASH table */ 2404 /* clear the old settings from the multicast hash table */ 2405 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 2406 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 2407 2408 atl2_init_flash_opcode(hw); 2409 2410 ret_val = atl2_phy_init(hw); 2411 2412 return ret_val; 2413} 2414 2415/* 2416 * Detects the current speed and duplex settings of the hardware. 2417 * 2418 * hw - Struct containing variables accessed by shared code 2419 * speed - Speed of the connection 2420 * duplex - Duplex setting of the connection 2421 */ 2422static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 2423 u16 *duplex) 2424{ 2425 s32 ret_val; 2426 u16 phy_data; 2427 2428 /* Read PHY Specific Status Register (17) */ 2429 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 2430 if (ret_val) 2431 return ret_val; 2432 2433 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 2434 return ATLX_ERR_PHY_RES; 2435 2436 switch (phy_data & MII_ATLX_PSSR_SPEED) { 2437 case MII_ATLX_PSSR_100MBS: 2438 *speed = SPEED_100; 2439 break; 2440 case MII_ATLX_PSSR_10MBS: 2441 *speed = SPEED_10; 2442 break; 2443 default: 2444 return ATLX_ERR_PHY_SPEED; 2445 } 2446 2447 if (phy_data & MII_ATLX_PSSR_DPLX) 2448 *duplex = FULL_DUPLEX; 2449 else 2450 *duplex = HALF_DUPLEX; 2451 2452 return 0; 2453} 2454 2455/* 2456 * Reads the value from a PHY register 2457 * hw - Struct containing variables accessed by shared code 2458 * reg_addr - address of the PHY register to read 2459 */ 2460static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) 2461{ 2462 u32 val; 2463 int i; 2464 2465 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 2466 MDIO_START | 2467 MDIO_SUP_PREAMBLE | 2468 MDIO_RW | 2469 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2470 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2471 2472 wmb(); 2473 2474 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2475 udelay(2); 2476 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2477 if (!(val & (MDIO_START | MDIO_BUSY))) 2478 break; 2479 wmb(); 2480 } 2481 if (!(val & (MDIO_START | MDIO_BUSY))) { 2482 *phy_data = (u16)val; 2483 return 0; 2484 } 2485 2486 return ATLX_ERR_PHY; 2487} 2488 2489/* 2490 * Writes a value to a PHY register 2491 * hw - Struct containing variables accessed by shared code 2492 * reg_addr - address of the PHY register to write 2493 * data - data to write to the PHY 2494 */ 2495static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) 2496{ 2497 int i; 2498 u32 val; 2499 2500 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 2501 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 2502 MDIO_SUP_PREAMBLE | 2503 MDIO_START | 2504 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2505 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2506 2507 wmb(); 2508 2509 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2510 udelay(2); 2511 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2512 if (!(val & (MDIO_START | MDIO_BUSY))) 2513 break; 2514 2515 wmb(); 2516 } 2517 2518 if (!(val & (MDIO_START | MDIO_BUSY))) 2519 return 0; 2520 2521 return ATLX_ERR_PHY; 2522} 2523 2524/* 2525 * Configures PHY autoneg and flow control advertisement settings 2526 * 2527 * hw - Struct containing variables accessed by shared code 2528 */ 2529static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) 2530{ 2531 s16 mii_autoneg_adv_reg; 2532 2533 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2534 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 2535 2536 /* Need to parse autoneg_advertised and set up 2537 * the appropriate PHY registers. First we will parse for 2538 * autoneg_advertised software override. Since we can advertise 2539 * a plethora of combinations, we need to check each bit 2540 * individually. 2541 */ 2542 2543 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2544 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2545 * the 1000Base-T Control Register (Address 9). */ 2546 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 2547 2548 /* Need to parse MediaType and setup the 2549 * appropriate PHY registers. */ 2550 switch (hw->MediaType) { 2551 case MEDIA_TYPE_AUTO_SENSOR: 2552 mii_autoneg_adv_reg |= 2553 (MII_AR_10T_HD_CAPS | 2554 MII_AR_10T_FD_CAPS | 2555 MII_AR_100TX_HD_CAPS| 2556 MII_AR_100TX_FD_CAPS); 2557 hw->autoneg_advertised = 2558 ADVERTISE_10_HALF | 2559 ADVERTISE_10_FULL | 2560 ADVERTISE_100_HALF| 2561 ADVERTISE_100_FULL; 2562 break; 2563 case MEDIA_TYPE_100M_FULL: 2564 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 2565 hw->autoneg_advertised = ADVERTISE_100_FULL; 2566 break; 2567 case MEDIA_TYPE_100M_HALF: 2568 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 2569 hw->autoneg_advertised = ADVERTISE_100_HALF; 2570 break; 2571 case MEDIA_TYPE_10M_FULL: 2572 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 2573 hw->autoneg_advertised = ADVERTISE_10_FULL; 2574 break; 2575 default: 2576 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 2577 hw->autoneg_advertised = ADVERTISE_10_HALF; 2578 break; 2579 } 2580 2581 /* flow control fixed to enable all */ 2582 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 2583 2584 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 2585 2586 return atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 2587} 2588 2589/* 2590 * Resets the PHY and make all config validate 2591 * 2592 * hw - Struct containing variables accessed by shared code 2593 * 2594 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 2595 */ 2596static s32 atl2_phy_commit(struct atl2_hw *hw) 2597{ 2598 s32 ret_val; 2599 u16 phy_data; 2600 2601 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2602 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); 2603 if (ret_val) { 2604 u32 val; 2605 int i; 2606 /* pcie serdes link may be down ! */ 2607 for (i = 0; i < 25; i++) { 2608 msleep(1); 2609 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2610 if (!(val & (MDIO_START | MDIO_BUSY))) 2611 break; 2612 } 2613 2614 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 2615 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); 2616 return ret_val; 2617 } 2618 } 2619 return 0; 2620} 2621 2622static s32 atl2_phy_init(struct atl2_hw *hw) 2623{ 2624 s32 ret_val; 2625 u16 phy_val; 2626 2627 if (hw->phy_configured) 2628 return 0; 2629 2630 /* Enable PHY */ 2631 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); 2632 ATL2_WRITE_FLUSH(hw); 2633 msleep(1); 2634 2635 /* check if the PHY is in powersaving mode */ 2636 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2637 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2638 2639 /* 024E / 124E 0r 0274 / 1274 ? */ 2640 if (phy_val & 0x1000) { 2641 phy_val &= ~0x1000; 2642 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); 2643 } 2644 2645 msleep(1); 2646 2647 /*Enable PHY LinkChange Interrupt */ 2648 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); 2649 if (ret_val) 2650 return ret_val; 2651 2652 /* setup AutoNeg parameters */ 2653 ret_val = atl2_phy_setup_autoneg_adv(hw); 2654 if (ret_val) 2655 return ret_val; 2656 2657 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ 2658 ret_val = atl2_phy_commit(hw); 2659 if (ret_val) 2660 return ret_val; 2661 2662 hw->phy_configured = true; 2663 2664 return ret_val; 2665} 2666 2667static void atl2_set_mac_addr(struct atl2_hw *hw) 2668{ 2669 u32 value; 2670 /* 00-0B-6A-F6-00-DC 2671 * 0: 6AF600DC 1: 000B 2672 * low dword */ 2673 value = (((u32)hw->mac_addr[2]) << 24) | 2674 (((u32)hw->mac_addr[3]) << 16) | 2675 (((u32)hw->mac_addr[4]) << 8) | 2676 (((u32)hw->mac_addr[5])); 2677 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 2678 /* hight dword */ 2679 value = (((u32)hw->mac_addr[0]) << 8) | 2680 (((u32)hw->mac_addr[1])); 2681 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 2682} 2683 2684/* 2685 * check_eeprom_exist 2686 * return 0 if eeprom exist 2687 */ 2688static int atl2_check_eeprom_exist(struct atl2_hw *hw) 2689{ 2690 u32 value; 2691 2692 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2693 if (value & SPI_FLASH_CTRL_EN_VPD) { 2694 value &= ~SPI_FLASH_CTRL_EN_VPD; 2695 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2696 } 2697 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); 2698 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 2699} 2700 2701/* FIXME: This doesn't look right. -- CHS */ 2702static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) 2703{ 2704 return true; 2705} 2706 2707static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) 2708{ 2709 int i; 2710 u32 Control; 2711 2712 if (Offset & 0x3) 2713 return false; /* address do not align */ 2714 2715 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); 2716 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 2717 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); 2718 2719 for (i = 0; i < 10; i++) { 2720 msleep(2); 2721 Control = ATL2_READ_REG(hw, REG_VPD_CAP); 2722 if (Control & VPD_CAP_VPD_FLAG) 2723 break; 2724 } 2725 2726 if (Control & VPD_CAP_VPD_FLAG) { 2727 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); 2728 return true; 2729 } 2730 return false; /* timeout */ 2731} 2732 2733static void atl2_force_ps(struct atl2_hw *hw) 2734{ 2735 u16 phy_val; 2736 2737 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2738 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2739 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); 2740 2741 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); 2742 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); 2743 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); 2744 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); 2745} 2746 2747/* This is the only thing that needs to be changed to adjust the 2748 * maximum number of ports that the driver can manage. 2749 */ 2750#define ATL2_MAX_NIC 4 2751 2752#define OPTION_UNSET -1 2753#define OPTION_DISABLED 0 2754#define OPTION_ENABLED 1 2755 2756/* All parameters are treated the same, as an integer array of values. 2757 * This macro just reduces the need to repeat the same declaration code 2758 * over and over (plus this helps to avoid typo bugs). 2759 */ 2760#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} 2761#ifndef module_param_array 2762/* Module Parameters are always initialized to -1, so that the driver 2763 * can tell the difference between no user specified value or the 2764 * user asking for the default value. 2765 * The true default values are loaded in when atl2_check_options is called. 2766 * 2767 * This is a GCC extension to ANSI C. 2768 * See the item "Labeled Elements in Initializers" in the section 2769 * "Extensions to the C Language Family" of the GCC documentation. 2770 */ 2771 2772#define ATL2_PARAM(X, desc) \ 2773 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ 2774 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ 2775 MODULE_PARM_DESC(X, desc); 2776#else 2777#define ATL2_PARAM(X, desc) \ 2778 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ 2779 static unsigned int num_##X; \ 2780 module_param_array_named(X, X, int, &num_##X, 0); \ 2781 MODULE_PARM_DESC(X, desc); 2782#endif 2783 2784/* 2785 * Transmit Memory Size 2786 * Valid Range: 64-2048 2787 * Default Value: 128 2788 */ 2789#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ 2790#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ 2791#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ 2792ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); 2793 2794/* 2795 * Receive Memory Block Count 2796 * Valid Range: 16-512 2797 * Default Value: 128 2798 */ 2799#define ATL2_MIN_RXD_COUNT 16 2800#define ATL2_MAX_RXD_COUNT 512 2801#define ATL2_DEFAULT_RXD_COUNT 64 2802ATL2_PARAM(RxMemBlock, "Number of receive memory block"); 2803 2804/* 2805 * User Specified MediaType Override 2806 * 2807 * Valid Range: 0-5 2808 * - 0 - auto-negotiate at all supported speeds 2809 * - 1 - only link at 1000Mbps Full Duplex 2810 * - 2 - only link at 100Mbps Full Duplex 2811 * - 3 - only link at 100Mbps Half Duplex 2812 * - 4 - only link at 10Mbps Full Duplex 2813 * - 5 - only link at 10Mbps Half Duplex 2814 * Default Value: 0 2815 */ 2816ATL2_PARAM(MediaType, "MediaType Select"); 2817 2818/* 2819 * Interrupt Moderate Timer in units of 2048 ns (~2 us) 2820 * Valid Range: 10-65535 2821 * Default Value: 45000(90ms) 2822 */ 2823#define INT_MOD_DEFAULT_CNT 100 /* 200us */ 2824#define INT_MOD_MAX_CNT 65000 2825#define INT_MOD_MIN_CNT 50 2826ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); 2827 2828/* 2829 * FlashVendor 2830 * Valid Range: 0-2 2831 * 0 - Atmel 2832 * 1 - SST 2833 * 2 - ST 2834 */ 2835ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); 2836 2837#define AUTONEG_ADV_DEFAULT 0x2F 2838#define AUTONEG_ADV_MASK 0x2F 2839#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 2840 2841#define FLASH_VENDOR_DEFAULT 0 2842#define FLASH_VENDOR_MIN 0 2843#define FLASH_VENDOR_MAX 2 2844 2845struct atl2_option { 2846 enum { enable_option, range_option, list_option } type; 2847 char *name; 2848 char *err; 2849 int def; 2850 union { 2851 struct { /* range_option info */ 2852 int min; 2853 int max; 2854 } r; 2855 struct { /* list_option info */ 2856 int nr; 2857 struct atl2_opt_list { int i; char *str; } *p; 2858 } l; 2859 } arg; 2860}; 2861 2862static int atl2_validate_option(int *value, struct atl2_option *opt) 2863{ 2864 int i; 2865 struct atl2_opt_list *ent; 2866 2867 if (*value == OPTION_UNSET) { 2868 *value = opt->def; 2869 return 0; 2870 } 2871 2872 switch (opt->type) { 2873 case enable_option: 2874 switch (*value) { 2875 case OPTION_ENABLED: 2876 printk(KERN_INFO "%s Enabled\n", opt->name); 2877 return 0; 2878 case OPTION_DISABLED: 2879 printk(KERN_INFO "%s Disabled\n", opt->name); 2880 return 0; 2881 } 2882 break; 2883 case range_option: 2884 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 2885 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 2886 return 0; 2887 } 2888 break; 2889 case list_option: 2890 for (i = 0; i < opt->arg.l.nr; i++) { 2891 ent = &opt->arg.l.p[i]; 2892 if (*value == ent->i) { 2893 if (ent->str[0] != '\0') 2894 printk(KERN_INFO "%s\n", ent->str); 2895 return 0; 2896 } 2897 } 2898 break; 2899 default: 2900 BUG(); 2901 } 2902 2903 printk(KERN_INFO "Invalid %s specified (%i) %s\n", 2904 opt->name, *value, opt->err); 2905 *value = opt->def; 2906 return -1; 2907} 2908 2909/** 2910 * atl2_check_options - Range Checking for Command Line Parameters 2911 * @adapter: board private structure 2912 * 2913 * This routine checks all command line parameters for valid user 2914 * input. If an invalid value is given, or if no user specified 2915 * value exists, a default value is used. The final value is stored 2916 * in a variable in the adapter structure. 2917 */ 2918static void atl2_check_options(struct atl2_adapter *adapter) 2919{ 2920 int val; 2921 struct atl2_option opt; 2922 int bd = adapter->bd_number; 2923 if (bd >= ATL2_MAX_NIC) { 2924 printk(KERN_NOTICE "Warning: no configuration for board #%i\n", 2925 bd); 2926 printk(KERN_NOTICE "Using defaults for all values\n"); 2927#ifndef module_param_array 2928 bd = ATL2_MAX_NIC; 2929#endif 2930 } 2931 2932 /* Bytes of Transmit Memory */ 2933 opt.type = range_option; 2934 opt.name = "Bytes of Transmit Memory"; 2935 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); 2936 opt.def = ATL2_DEFAULT_TX_MEMSIZE; 2937 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; 2938 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; 2939#ifdef module_param_array 2940 if (num_TxMemSize > bd) { 2941#endif 2942 val = TxMemSize[bd]; 2943 atl2_validate_option(&val, &opt); 2944 adapter->txd_ring_size = ((u32) val) * 1024; 2945#ifdef module_param_array 2946 } else 2947 adapter->txd_ring_size = ((u32)opt.def) * 1024; 2948#endif 2949 /* txs ring size: */ 2950 adapter->txs_ring_size = adapter->txd_ring_size / 128; 2951 if (adapter->txs_ring_size > 160) 2952 adapter->txs_ring_size = 160; 2953 2954 /* Receive Memory Block Count */ 2955 opt.type = range_option; 2956 opt.name = "Number of receive memory block"; 2957 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); 2958 opt.def = ATL2_DEFAULT_RXD_COUNT; 2959 opt.arg.r.min = ATL2_MIN_RXD_COUNT; 2960 opt.arg.r.max = ATL2_MAX_RXD_COUNT; 2961#ifdef module_param_array 2962 if (num_RxMemBlock > bd) { 2963#endif 2964 val = RxMemBlock[bd]; 2965 atl2_validate_option(&val, &opt); 2966 adapter->rxd_ring_size = (u32)val; 2967 /* FIXME */ 2968 /* ((u16)val)&~1; */ /* even number */ 2969#ifdef module_param_array 2970 } else 2971 adapter->rxd_ring_size = (u32)opt.def; 2972#endif 2973 /* init RXD Flow control value */ 2974 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; 2975 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > 2976 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : 2977 (adapter->rxd_ring_size / 12); 2978 2979 /* Interrupt Moderate Timer */ 2980 opt.type = range_option; 2981 opt.name = "Interrupt Moderate Timer"; 2982 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); 2983 opt.def = INT_MOD_DEFAULT_CNT; 2984 opt.arg.r.min = INT_MOD_MIN_CNT; 2985 opt.arg.r.max = INT_MOD_MAX_CNT; 2986#ifdef module_param_array 2987 if (num_IntModTimer > bd) { 2988#endif 2989 val = IntModTimer[bd]; 2990 atl2_validate_option(&val, &opt); 2991 adapter->imt = (u16) val; 2992#ifdef module_param_array 2993 } else 2994 adapter->imt = (u16)(opt.def); 2995#endif 2996 /* Flash Vendor */ 2997 opt.type = range_option; 2998 opt.name = "SPI Flash Vendor"; 2999 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); 3000 opt.def = FLASH_VENDOR_DEFAULT; 3001 opt.arg.r.min = FLASH_VENDOR_MIN; 3002 opt.arg.r.max = FLASH_VENDOR_MAX; 3003#ifdef module_param_array 3004 if (num_FlashVendor > bd) { 3005#endif 3006 val = FlashVendor[bd]; 3007 atl2_validate_option(&val, &opt); 3008 adapter->hw.flash_vendor = (u8) val; 3009#ifdef module_param_array 3010 } else 3011 adapter->hw.flash_vendor = (u8)(opt.def); 3012#endif 3013 /* MediaType */ 3014 opt.type = range_option; 3015 opt.name = "Speed/Duplex Selection"; 3016 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); 3017 opt.def = MEDIA_TYPE_AUTO_SENSOR; 3018 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; 3019 opt.arg.r.max = MEDIA_TYPE_10M_HALF; 3020#ifdef module_param_array 3021 if (num_MediaType > bd) { 3022#endif 3023 val = MediaType[bd]; 3024 atl2_validate_option(&val, &opt); 3025 adapter->hw.MediaType = (u16) val; 3026#ifdef module_param_array 3027 } else 3028 adapter->hw.MediaType = (u16)(opt.def); 3029#endif 3030}
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