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atl1.c
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linux-6.19.14/drivers/net/ethernet/atheros/atlx/atl1.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> 5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> 6 * 7 * Derived from Intel e1000 driver 8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 9 * 10 * Contact Information: 11 * Xiong Huang <xiong.huang@atheros.com> 12 * Jie Yang <jie.yang@atheros.com> 13 * Chris Snook <csnook@redhat.com> 14 * Jay Cliburn <jcliburn@gmail.com> 15 * 16 * This version is adapted from the Attansic reference driver. 17 * 18 * TODO: 19 * Add more ethtool functions. 20 * Fix abstruse irq enable/disable condition described here: 21 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2 22 * 23 * NEEDS TESTING: 24 * VLAN 25 * multicast 26 * promiscuous mode 27 * interrupt coalescing 28 * SMP torture testing 29 */ 30 31#include <linux/atomic.h> 32#include <asm/byteorder.h> 33 34#include <linux/compiler.h> 35#include <linux/crc32.h> 36#include <linux/delay.h> 37#include <linux/dma-mapping.h> 38#include <linux/etherdevice.h> 39#include <linux/hardirq.h> 40#include <linux/if_ether.h> 41#include <linux/if_vlan.h> 42#include <linux/in.h> 43#include <linux/interrupt.h> 44#include <linux/ip.h> 45#include <linux/irqflags.h> 46#include <linux/irqreturn.h> 47#include <linux/jiffies.h> 48#include <linux/mii.h> 49#include <linux/module.h> 50#include <linux/net.h> 51#include <linux/netdevice.h> 52#include <linux/pci.h> 53#include <linux/pci_ids.h> 54#include <linux/pm.h> 55#include <linux/skbuff.h> 56#include <linux/slab.h> 57#include <linux/spinlock.h> 58#include <linux/string.h> 59#include <linux/tcp.h> 60#include <linux/timer.h> 61#include <linux/types.h> 62#include <linux/workqueue.h> 63 64#include <net/checksum.h> 65 66#include "atl1.h" 67 68MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, " 69 "Chris Snook <csnook@redhat.com>, " 70 "Jay Cliburn <jcliburn@gmail.com>"); 71MODULE_LICENSE("GPL"); 72 73/* Temporary hack for merging atl1 and atl2 */ 74#include "atlx.c" 75 76static const struct ethtool_ops atl1_ethtool_ops; 77 78/* 79 * This is the only thing that needs to be changed to adjust the 80 * maximum number of ports that the driver can manage. 81 */ 82#define ATL1_MAX_NIC 4 83 84#define OPTION_UNSET -1 85#define OPTION_DISABLED 0 86#define OPTION_ENABLED 1 87 88#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET } 89 90/* 91 * Interrupt Moderate Timer in units of 2 us 92 * 93 * Valid Range: 10-65535 94 * 95 * Default Value: 100 (200us) 96 */ 97static int int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT; 98static unsigned int num_int_mod_timer; 99module_param_array_named(int_mod_timer, int_mod_timer, int, 100 &num_int_mod_timer, 0); 101MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer"); 102 103#define DEFAULT_INT_MOD_CNT 100 /* 200us */ 104#define MAX_INT_MOD_CNT 65000 105#define MIN_INT_MOD_CNT 50 106 107struct atl1_option { 108 enum { enable_option, range_option, list_option } type; 109 char *name; 110 char *err; 111 int def; 112 union { 113 struct { /* range_option info */ 114 int min; 115 int max; 116 } r; 117 struct { /* list_option info */ 118 int nr; 119 struct atl1_opt_list { 120 int i; 121 char *str; 122 } *p; 123 } l; 124 } arg; 125}; 126 127static int atl1_validate_option(int *value, struct atl1_option *opt, 128 struct pci_dev *pdev) 129{ 130 if (*value == OPTION_UNSET) { 131 *value = opt->def; 132 return 0; 133 } 134 135 switch (opt->type) { 136 case enable_option: 137 switch (*value) { 138 case OPTION_ENABLED: 139 dev_info(&pdev->dev, "%s enabled\n", opt->name); 140 return 0; 141 case OPTION_DISABLED: 142 dev_info(&pdev->dev, "%s disabled\n", opt->name); 143 return 0; 144 } 145 break; 146 case range_option: 147 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 148 dev_info(&pdev->dev, "%s set to %i\n", opt->name, 149 *value); 150 return 0; 151 } 152 break; 153 case list_option:{ 154 int i; 155 struct atl1_opt_list *ent; 156 157 for (i = 0; i < opt->arg.l.nr; i++) { 158 ent = &opt->arg.l.p[i]; 159 if (*value == ent->i) { 160 if (ent->str[0] != '\0') 161 dev_info(&pdev->dev, "%s\n", 162 ent->str); 163 return 0; 164 } 165 } 166 } 167 break; 168 169 default: 170 break; 171 } 172 173 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n", 174 opt->name, *value, opt->err); 175 *value = opt->def; 176 return -1; 177} 178 179/** 180 * atl1_check_options - Range Checking for Command Line Parameters 181 * @adapter: board private structure 182 * 183 * This routine checks all command line parameters for valid user 184 * input. If an invalid value is given, or if no user specified 185 * value exists, a default value is used. The final value is stored 186 * in a variable in the adapter structure. 187 */ 188static void atl1_check_options(struct atl1_adapter *adapter) 189{ 190 struct pci_dev *pdev = adapter->pdev; 191 int bd = adapter->bd_number; 192 if (bd >= ATL1_MAX_NIC) { 193 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd); 194 dev_notice(&pdev->dev, "using defaults for all values\n"); 195 } 196 { /* Interrupt Moderate Timer */ 197 struct atl1_option opt = { 198 .type = range_option, 199 .name = "Interrupt Moderator Timer", 200 .err = "using default of " 201 __MODULE_STRING(DEFAULT_INT_MOD_CNT), 202 .def = DEFAULT_INT_MOD_CNT, 203 .arg = {.r = {.min = MIN_INT_MOD_CNT, 204 .max = MAX_INT_MOD_CNT} } 205 }; 206 int val; 207 if (num_int_mod_timer > bd) { 208 val = int_mod_timer[bd]; 209 atl1_validate_option(&val, &opt, pdev); 210 adapter->imt = (u16) val; 211 } else 212 adapter->imt = (u16) (opt.def); 213 } 214} 215 216/* 217 * atl1_pci_tbl - PCI Device ID Table 218 */ 219static const struct pci_device_id atl1_pci_tbl[] = { 220 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)}, 221 /* required last entry */ 222 {0,} 223}; 224MODULE_DEVICE_TABLE(pci, atl1_pci_tbl); 225 226static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | 227 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; 228 229static int debug = -1; 230module_param(debug, int, 0); 231MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)"); 232 233/* 234 * Reset the transmit and receive units; mask and clear all interrupts. 235 * hw - Struct containing variables accessed by shared code 236 * return : 0 or idle status (if error) 237 */ 238static s32 atl1_reset_hw(struct atl1_hw *hw) 239{ 240 struct pci_dev *pdev = hw->back->pdev; 241 struct atl1_adapter *adapter = hw->back; 242 u32 icr; 243 int i; 244 245 /* 246 * Clear Interrupt mask to stop board from generating 247 * interrupts & Clear any pending interrupt events 248 */ 249 /* 250 * atlx_irq_disable(adapter); 251 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR); 252 */ 253 254 /* 255 * Issue Soft Reset to the MAC. This will reset the chip's 256 * transmit, receive, DMA. It will not effect 257 * the current PCI configuration. The global reset bit is self- 258 * clearing, and should clear within a microsecond. 259 */ 260 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL); 261 ioread32(hw->hw_addr + REG_MASTER_CTRL); 262 263 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE); 264 ioread16(hw->hw_addr + REG_PHY_ENABLE); 265 266 /* delay about 1ms */ 267 msleep(1); 268 269 /* Wait at least 10ms for All module to be Idle */ 270 for (i = 0; i < 10; i++) { 271 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS); 272 if (!icr) 273 break; 274 /* delay 1 ms */ 275 msleep(1); 276 /* FIXME: still the right way to do this? */ 277 cpu_relax(); 278 } 279 280 if (icr) { 281 if (netif_msg_hw(adapter)) 282 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr); 283 return icr; 284 } 285 286 return 0; 287} 288 289/* function about EEPROM 290 * 291 * check_eeprom_exist 292 * return 0 if eeprom exist 293 */ 294static int atl1_check_eeprom_exist(struct atl1_hw *hw) 295{ 296 u32 value; 297 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 298 if (value & SPI_FLASH_CTRL_EN_VPD) { 299 value &= ~SPI_FLASH_CTRL_EN_VPD; 300 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 301 } 302 303 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST); 304 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 305} 306 307static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value) 308{ 309 int i; 310 u32 control; 311 312 if (offset & 3) 313 /* address do not align */ 314 return false; 315 316 iowrite32(0, hw->hw_addr + REG_VPD_DATA); 317 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 318 iowrite32(control, hw->hw_addr + REG_VPD_CAP); 319 ioread32(hw->hw_addr + REG_VPD_CAP); 320 321 for (i = 0; i < 10; i++) { 322 msleep(2); 323 control = ioread32(hw->hw_addr + REG_VPD_CAP); 324 if (control & VPD_CAP_VPD_FLAG) 325 break; 326 } 327 if (control & VPD_CAP_VPD_FLAG) { 328 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA); 329 return true; 330 } 331 /* timeout */ 332 return false; 333} 334 335/* 336 * Reads the value from a PHY register 337 * hw - Struct containing variables accessed by shared code 338 * reg_addr - address of the PHY register to read 339 */ 340static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data) 341{ 342 u32 val; 343 int i; 344 345 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 346 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 << 347 MDIO_CLK_SEL_SHIFT; 348 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); 349 ioread32(hw->hw_addr + REG_MDIO_CTRL); 350 351 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 352 udelay(2); 353 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 354 if (!(val & (MDIO_START | MDIO_BUSY))) 355 break; 356 } 357 if (!(val & (MDIO_START | MDIO_BUSY))) { 358 *phy_data = (u16) val; 359 return 0; 360 } 361 return ATLX_ERR_PHY; 362} 363 364#define CUSTOM_SPI_CS_SETUP 2 365#define CUSTOM_SPI_CLK_HI 2 366#define CUSTOM_SPI_CLK_LO 2 367#define CUSTOM_SPI_CS_HOLD 2 368#define CUSTOM_SPI_CS_HI 3 369 370static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf) 371{ 372 int i; 373 u32 value; 374 375 iowrite32(0, hw->hw_addr + REG_SPI_DATA); 376 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR); 377 378 value = SPI_FLASH_CTRL_WAIT_READY | 379 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 380 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI & 381 SPI_FLASH_CTRL_CLK_HI_MASK) << 382 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO & 383 SPI_FLASH_CTRL_CLK_LO_MASK) << 384 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD & 385 SPI_FLASH_CTRL_CS_HOLD_MASK) << 386 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI & 387 SPI_FLASH_CTRL_CS_HI_MASK) << 388 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) << 389 SPI_FLASH_CTRL_INS_SHIFT; 390 391 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 392 393 value |= SPI_FLASH_CTRL_START; 394 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 395 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 396 397 for (i = 0; i < 10; i++) { 398 msleep(1); 399 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 400 if (!(value & SPI_FLASH_CTRL_START)) 401 break; 402 } 403 404 if (value & SPI_FLASH_CTRL_START) 405 return false; 406 407 *buf = ioread32(hw->hw_addr + REG_SPI_DATA); 408 409 return true; 410} 411 412/* 413 * get_permanent_address 414 * return 0 if get valid mac address, 415 */ 416static int atl1_get_permanent_address(struct atl1_hw *hw) 417{ 418 u32 addr[2]; 419 u32 i, control; 420 u16 reg; 421 u8 eth_addr[ETH_ALEN]; 422 bool key_valid; 423 424 if (is_valid_ether_addr(hw->perm_mac_addr)) 425 return 0; 426 427 /* init */ 428 addr[0] = addr[1] = 0; 429 430 if (!atl1_check_eeprom_exist(hw)) { 431 reg = 0; 432 key_valid = false; 433 /* Read out all EEPROM content */ 434 i = 0; 435 while (1) { 436 if (atl1_read_eeprom(hw, i + 0x100, &control)) { 437 if (key_valid) { 438 if (reg == REG_MAC_STA_ADDR) 439 addr[0] = control; 440 else if (reg == (REG_MAC_STA_ADDR + 4)) 441 addr[1] = control; 442 key_valid = false; 443 } else if ((control & 0xff) == 0x5A) { 444 key_valid = true; 445 reg = (u16) (control >> 16); 446 } else 447 break; 448 } else 449 /* read error */ 450 break; 451 i += 4; 452 } 453 454 *(u32 *) ð_addr[2] = swab32(addr[0]); 455 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 456 if (is_valid_ether_addr(eth_addr)) { 457 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 458 return 0; 459 } 460 } 461 462 /* see if SPI FLAGS exist ? */ 463 addr[0] = addr[1] = 0; 464 reg = 0; 465 key_valid = false; 466 i = 0; 467 while (1) { 468 if (atl1_spi_read(hw, i + 0x1f000, &control)) { 469 if (key_valid) { 470 if (reg == REG_MAC_STA_ADDR) 471 addr[0] = control; 472 else if (reg == (REG_MAC_STA_ADDR + 4)) 473 addr[1] = control; 474 key_valid = false; 475 } else if ((control & 0xff) == 0x5A) { 476 key_valid = true; 477 reg = (u16) (control >> 16); 478 } else 479 /* data end */ 480 break; 481 } else 482 /* read error */ 483 break; 484 i += 4; 485 } 486 487 *(u32 *) ð_addr[2] = swab32(addr[0]); 488 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 489 if (is_valid_ether_addr(eth_addr)) { 490 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 491 return 0; 492 } 493 494 /* 495 * On some motherboards, the MAC address is written by the 496 * BIOS directly to the MAC register during POST, and is 497 * not stored in eeprom. If all else thus far has failed 498 * to fetch the permanent MAC address, try reading it directly. 499 */ 500 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR); 501 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4)); 502 *(u32 *) ð_addr[2] = swab32(addr[0]); 503 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 504 if (is_valid_ether_addr(eth_addr)) { 505 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 506 return 0; 507 } 508 509 return 1; 510} 511 512/* 513 * Reads the adapter's MAC address from the EEPROM 514 * hw - Struct containing variables accessed by shared code 515 */ 516static s32 atl1_read_mac_addr(struct atl1_hw *hw) 517{ 518 s32 ret = 0; 519 u16 i; 520 521 if (atl1_get_permanent_address(hw)) { 522 eth_random_addr(hw->perm_mac_addr); 523 ret = 1; 524 } 525 526 for (i = 0; i < ETH_ALEN; i++) 527 hw->mac_addr[i] = hw->perm_mac_addr[i]; 528 return ret; 529} 530 531/* 532 * Hashes an address to determine its location in the multicast table 533 * hw - Struct containing variables accessed by shared code 534 * mc_addr - the multicast address to hash 535 * 536 * atl1_hash_mc_addr 537 * purpose 538 * set hash value for a multicast address 539 * hash calcu processing : 540 * 1. calcu 32bit CRC for multicast address 541 * 2. reverse crc with MSB to LSB 542 */ 543static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr) 544{ 545 u32 crc32, value = 0; 546 int i; 547 548 crc32 = ether_crc_le(6, mc_addr); 549 for (i = 0; i < 32; i++) 550 value |= (((crc32 >> i) & 1) << (31 - i)); 551 552 return value; 553} 554 555/* 556 * Sets the bit in the multicast table corresponding to the hash value. 557 * hw - Struct containing variables accessed by shared code 558 * hash_value - Multicast address hash value 559 */ 560static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value) 561{ 562 u32 hash_bit, hash_reg; 563 u32 mta; 564 565 /* 566 * The HASH Table is a register array of 2 32-bit registers. 567 * It is treated like an array of 64 bits. We want to set 568 * bit BitArray[hash_value]. So we figure out what register 569 * the bit is in, read it, OR in the new bit, then write 570 * back the new value. The register is determined by the 571 * upper 7 bits of the hash value and the bit within that 572 * register are determined by the lower 5 bits of the value. 573 */ 574 hash_reg = (hash_value >> 31) & 0x1; 575 hash_bit = (hash_value >> 26) & 0x1F; 576 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); 577 mta |= (1 << hash_bit); 578 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); 579} 580 581/* 582 * Writes a value to a PHY register 583 * hw - Struct containing variables accessed by shared code 584 * reg_addr - address of the PHY register to write 585 * data - data to write to the PHY 586 */ 587static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data) 588{ 589 int i; 590 u32 val; 591 592 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 593 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 594 MDIO_SUP_PREAMBLE | 595 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 596 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); 597 ioread32(hw->hw_addr + REG_MDIO_CTRL); 598 599 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 600 udelay(2); 601 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 602 if (!(val & (MDIO_START | MDIO_BUSY))) 603 break; 604 } 605 606 if (!(val & (MDIO_START | MDIO_BUSY))) 607 return 0; 608 609 return ATLX_ERR_PHY; 610} 611 612/* 613 * Make L001's PHY out of Power Saving State (bug) 614 * hw - Struct containing variables accessed by shared code 615 * when power on, L001's PHY always on Power saving State 616 * (Gigabit Link forbidden) 617 */ 618static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw) 619{ 620 s32 ret; 621 ret = atl1_write_phy_reg(hw, 29, 0x0029); 622 if (ret) 623 return ret; 624 return atl1_write_phy_reg(hw, 30, 0); 625} 626 627/* 628 * Resets the PHY and make all config validate 629 * hw - Struct containing variables accessed by shared code 630 * 631 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 632 */ 633static s32 atl1_phy_reset(struct atl1_hw *hw) 634{ 635 struct pci_dev *pdev = hw->back->pdev; 636 struct atl1_adapter *adapter = hw->back; 637 s32 ret_val; 638 u16 phy_data; 639 640 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 641 hw->media_type == MEDIA_TYPE_1000M_FULL) 642 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 643 else { 644 switch (hw->media_type) { 645 case MEDIA_TYPE_100M_FULL: 646 phy_data = 647 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 648 MII_CR_RESET; 649 break; 650 case MEDIA_TYPE_100M_HALF: 651 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 652 break; 653 case MEDIA_TYPE_10M_FULL: 654 phy_data = 655 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 656 break; 657 default: 658 /* MEDIA_TYPE_10M_HALF: */ 659 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 660 break; 661 } 662 } 663 664 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data); 665 if (ret_val) { 666 u32 val; 667 int i; 668 /* pcie serdes link may be down! */ 669 if (netif_msg_hw(adapter)) 670 dev_dbg(&pdev->dev, "pcie phy link down\n"); 671 672 for (i = 0; i < 25; i++) { 673 msleep(1); 674 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 675 if (!(val & (MDIO_START | MDIO_BUSY))) 676 break; 677 } 678 679 if ((val & (MDIO_START | MDIO_BUSY)) != 0) { 680 if (netif_msg_hw(adapter)) 681 dev_warn(&pdev->dev, 682 "pcie link down at least 25ms\n"); 683 return ret_val; 684 } 685 } 686 return 0; 687} 688 689/* 690 * Configures PHY autoneg and flow control advertisement settings 691 * hw - Struct containing variables accessed by shared code 692 */ 693static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw) 694{ 695 s32 ret_val; 696 s16 mii_autoneg_adv_reg; 697 s16 mii_1000t_ctrl_reg; 698 699 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 700 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 701 702 /* Read the MII 1000Base-T Control Register (Address 9). */ 703 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK; 704 705 /* 706 * First we clear all the 10/100 mb speed bits in the Auto-Neg 707 * Advertisement Register (Address 4) and the 1000 mb speed bits in 708 * the 1000Base-T Control Register (Address 9). 709 */ 710 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 711 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK; 712 713 /* 714 * Need to parse media_type and set up 715 * the appropriate PHY registers. 716 */ 717 switch (hw->media_type) { 718 case MEDIA_TYPE_AUTO_SENSOR: 719 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | 720 MII_AR_10T_FD_CAPS | 721 MII_AR_100TX_HD_CAPS | 722 MII_AR_100TX_FD_CAPS); 723 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; 724 break; 725 726 case MEDIA_TYPE_1000M_FULL: 727 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; 728 break; 729 730 case MEDIA_TYPE_100M_FULL: 731 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 732 break; 733 734 case MEDIA_TYPE_100M_HALF: 735 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 736 break; 737 738 case MEDIA_TYPE_10M_FULL: 739 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 740 break; 741 742 default: 743 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 744 break; 745 } 746 747 /* flow control fixed to enable all */ 748 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 749 750 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 751 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; 752 753 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 754 if (ret_val) 755 return ret_val; 756 757 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg); 758 if (ret_val) 759 return ret_val; 760 761 return 0; 762} 763 764/* 765 * Configures link settings. 766 * hw - Struct containing variables accessed by shared code 767 * Assumes the hardware has previously been reset and the 768 * transmitter and receiver are not enabled. 769 */ 770static s32 atl1_setup_link(struct atl1_hw *hw) 771{ 772 struct pci_dev *pdev = hw->back->pdev; 773 struct atl1_adapter *adapter = hw->back; 774 s32 ret_val; 775 776 /* 777 * Options: 778 * PHY will advertise value(s) parsed from 779 * autoneg_advertised and fc 780 * no matter what autoneg is , We will not wait link result. 781 */ 782 ret_val = atl1_phy_setup_autoneg_adv(hw); 783 if (ret_val) { 784 if (netif_msg_link(adapter)) 785 dev_dbg(&pdev->dev, 786 "error setting up autonegotiation\n"); 787 return ret_val; 788 } 789 /* SW.Reset , En-Auto-Neg if needed */ 790 ret_val = atl1_phy_reset(hw); 791 if (ret_val) { 792 if (netif_msg_link(adapter)) 793 dev_dbg(&pdev->dev, "error resetting phy\n"); 794 return ret_val; 795 } 796 hw->phy_configured = true; 797 return ret_val; 798} 799 800static void atl1_init_flash_opcode(struct atl1_hw *hw) 801{ 802 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 803 /* Atmel */ 804 hw->flash_vendor = 0; 805 806 /* Init OP table */ 807 iowrite8(flash_table[hw->flash_vendor].cmd_program, 808 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM); 809 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase, 810 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE); 811 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase, 812 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE); 813 iowrite8(flash_table[hw->flash_vendor].cmd_rdid, 814 hw->hw_addr + REG_SPI_FLASH_OP_RDID); 815 iowrite8(flash_table[hw->flash_vendor].cmd_wren, 816 hw->hw_addr + REG_SPI_FLASH_OP_WREN); 817 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr, 818 hw->hw_addr + REG_SPI_FLASH_OP_RDSR); 819 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr, 820 hw->hw_addr + REG_SPI_FLASH_OP_WRSR); 821 iowrite8(flash_table[hw->flash_vendor].cmd_read, 822 hw->hw_addr + REG_SPI_FLASH_OP_READ); 823} 824 825/* 826 * Performs basic configuration of the adapter. 827 * hw - Struct containing variables accessed by shared code 828 * Assumes that the controller has previously been reset and is in a 829 * post-reset uninitialized state. Initializes multicast table, 830 * and Calls routines to setup link 831 * Leaves the transmit and receive units disabled and uninitialized. 832 */ 833static s32 atl1_init_hw(struct atl1_hw *hw) 834{ 835 u32 ret_val = 0; 836 837 /* Zero out the Multicast HASH table */ 838 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE); 839 /* clear the old settings from the multicast hash table */ 840 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2)); 841 842 atl1_init_flash_opcode(hw); 843 844 if (!hw->phy_configured) { 845 /* enable GPHY LinkChange Interrupt */ 846 ret_val = atl1_write_phy_reg(hw, 18, 0xC00); 847 if (ret_val) 848 return ret_val; 849 /* make PHY out of power-saving state */ 850 ret_val = atl1_phy_leave_power_saving(hw); 851 if (ret_val) 852 return ret_val; 853 /* Call a subroutine to configure the link */ 854 ret_val = atl1_setup_link(hw); 855 } 856 return ret_val; 857} 858 859/* 860 * Detects the current speed and duplex settings of the hardware. 861 * hw - Struct containing variables accessed by shared code 862 * speed - Speed of the connection 863 * duplex - Duplex setting of the connection 864 */ 865static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex) 866{ 867 struct pci_dev *pdev = hw->back->pdev; 868 struct atl1_adapter *adapter = hw->back; 869 s32 ret_val; 870 u16 phy_data; 871 872 /* ; --- Read PHY Specific Status Register (17) */ 873 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 874 if (ret_val) 875 return ret_val; 876 877 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 878 return ATLX_ERR_PHY_RES; 879 880 switch (phy_data & MII_ATLX_PSSR_SPEED) { 881 case MII_ATLX_PSSR_1000MBS: 882 *speed = SPEED_1000; 883 break; 884 case MII_ATLX_PSSR_100MBS: 885 *speed = SPEED_100; 886 break; 887 case MII_ATLX_PSSR_10MBS: 888 *speed = SPEED_10; 889 break; 890 default: 891 if (netif_msg_hw(adapter)) 892 dev_dbg(&pdev->dev, "error getting speed\n"); 893 return ATLX_ERR_PHY_SPEED; 894 } 895 if (phy_data & MII_ATLX_PSSR_DPLX) 896 *duplex = FULL_DUPLEX; 897 else 898 *duplex = HALF_DUPLEX; 899 900 return 0; 901} 902 903static void atl1_set_mac_addr(struct atl1_hw *hw) 904{ 905 u32 value; 906 /* 907 * 00-0B-6A-F6-00-DC 908 * 0: 6AF600DC 1: 000B 909 * low dword 910 */ 911 value = (((u32) hw->mac_addr[2]) << 24) | 912 (((u32) hw->mac_addr[3]) << 16) | 913 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5])); 914 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); 915 /* high dword */ 916 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); 917 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2)); 918} 919 920/** 921 * atl1_sw_init - Initialize general software structures (struct atl1_adapter) 922 * @adapter: board private structure to initialize 923 * 924 * atl1_sw_init initializes the Adapter private data structure. 925 * Fields are initialized based on PCI device information and 926 * OS network device settings (MTU size). 927 */ 928static int atl1_sw_init(struct atl1_adapter *adapter) 929{ 930 struct atl1_hw *hw = &adapter->hw; 931 struct net_device *netdev = adapter->netdev; 932 933 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 934 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 935 936 adapter->wol = 0; 937 device_set_wakeup_enable(&adapter->pdev->dev, false); 938 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7; 939 adapter->ict = 50000; /* 100ms */ 940 adapter->link_speed = SPEED_0; /* hardware init */ 941 adapter->link_duplex = FULL_DUPLEX; 942 943 hw->phy_configured = false; 944 hw->preamble_len = 7; 945 hw->ipgt = 0x60; 946 hw->min_ifg = 0x50; 947 hw->ipgr1 = 0x40; 948 hw->ipgr2 = 0x60; 949 hw->max_retry = 0xf; 950 hw->lcol = 0x37; 951 hw->jam_ipg = 7; 952 hw->rfd_burst = 8; 953 hw->rrd_burst = 8; 954 hw->rfd_fetch_gap = 1; 955 hw->rx_jumbo_th = adapter->rx_buffer_len / 8; 956 hw->rx_jumbo_lkah = 1; 957 hw->rrd_ret_timer = 16; 958 hw->tpd_burst = 4; 959 hw->tpd_fetch_th = 16; 960 hw->txf_burst = 0x100; 961 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3; 962 hw->tpd_fetch_gap = 1; 963 hw->rcb_value = atl1_rcb_64; 964 hw->dma_ord = atl1_dma_ord_enh; 965 hw->dmar_block = atl1_dma_req_256; 966 hw->dmaw_block = atl1_dma_req_256; 967 hw->cmb_rrd = 4; 968 hw->cmb_tpd = 4; 969 hw->cmb_rx_timer = 1; /* about 2us */ 970 hw->cmb_tx_timer = 1; /* about 2us */ 971 hw->smb_timer = 100000; /* about 200ms */ 972 973 spin_lock_init(&adapter->lock); 974 spin_lock_init(&adapter->mb_lock); 975 976 return 0; 977} 978 979static int mdio_read(struct net_device *netdev, int phy_id, int reg_num) 980{ 981 struct atl1_adapter *adapter = netdev_priv(netdev); 982 u16 result; 983 984 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result); 985 986 return result; 987} 988 989static void mdio_write(struct net_device *netdev, int phy_id, int reg_num, 990 int val) 991{ 992 struct atl1_adapter *adapter = netdev_priv(netdev); 993 994 atl1_write_phy_reg(&adapter->hw, reg_num, val); 995} 996 997static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 998{ 999 struct atl1_adapter *adapter = netdev_priv(netdev); 1000 unsigned long flags; 1001 int retval; 1002 1003 if (!netif_running(netdev)) 1004 return -EINVAL; 1005 1006 spin_lock_irqsave(&adapter->lock, flags); 1007 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); 1008 spin_unlock_irqrestore(&adapter->lock, flags); 1009 1010 return retval; 1011} 1012 1013/** 1014 * atl1_setup_ring_resources - allocate Tx / RX descriptor resources 1015 * @adapter: board private structure 1016 * 1017 * Return 0 on success, negative on failure 1018 */ 1019static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter) 1020{ 1021 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1022 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1023 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1024 struct atl1_ring_header *ring_header = &adapter->ring_header; 1025 struct pci_dev *pdev = adapter->pdev; 1026 int size; 1027 u8 offset = 0; 1028 1029 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count); 1030 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL); 1031 if (unlikely(!tpd_ring->buffer_info)) { 1032 if (netif_msg_drv(adapter)) 1033 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n", 1034 size); 1035 goto err_nomem; 1036 } 1037 rfd_ring->buffer_info = 1038 (tpd_ring->buffer_info + tpd_ring->count); 1039 1040 /* 1041 * real ring DMA buffer 1042 * each ring/block may need up to 8 bytes for alignment, hence the 1043 * additional 40 bytes tacked onto the end. 1044 */ 1045 ring_header->size = 1046 sizeof(struct tx_packet_desc) * tpd_ring->count 1047 + sizeof(struct rx_free_desc) * rfd_ring->count 1048 + sizeof(struct rx_return_desc) * rrd_ring->count 1049 + sizeof(struct coals_msg_block) 1050 + sizeof(struct stats_msg_block) 1051 + 40; 1052 1053 ring_header->desc = dma_alloc_coherent(&pdev->dev, ring_header->size, 1054 &ring_header->dma, GFP_KERNEL); 1055 if (unlikely(!ring_header->desc)) { 1056 if (netif_msg_drv(adapter)) 1057 dev_err(&pdev->dev, "dma_alloc_coherent failed\n"); 1058 goto err_nomem; 1059 } 1060 1061 /* init TPD ring */ 1062 tpd_ring->dma = ring_header->dma; 1063 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0; 1064 tpd_ring->dma += offset; 1065 tpd_ring->desc = (u8 *) ring_header->desc + offset; 1066 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count; 1067 1068 /* init RFD ring */ 1069 rfd_ring->dma = tpd_ring->dma + tpd_ring->size; 1070 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0; 1071 rfd_ring->dma += offset; 1072 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset); 1073 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count; 1074 1075 1076 /* init RRD ring */ 1077 rrd_ring->dma = rfd_ring->dma + rfd_ring->size; 1078 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0; 1079 rrd_ring->dma += offset; 1080 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset); 1081 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count; 1082 1083 1084 /* init CMB */ 1085 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size; 1086 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0; 1087 adapter->cmb.dma += offset; 1088 adapter->cmb.cmb = (struct coals_msg_block *) 1089 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset)); 1090 1091 /* init SMB */ 1092 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block); 1093 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0; 1094 adapter->smb.dma += offset; 1095 adapter->smb.smb = (struct stats_msg_block *) 1096 ((u8 *) adapter->cmb.cmb + 1097 (sizeof(struct coals_msg_block) + offset)); 1098 1099 return 0; 1100 1101err_nomem: 1102 kfree(tpd_ring->buffer_info); 1103 return -ENOMEM; 1104} 1105 1106static void atl1_init_ring_ptrs(struct atl1_adapter *adapter) 1107{ 1108 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1109 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1110 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1111 1112 atomic_set(&tpd_ring->next_to_use, 0); 1113 atomic_set(&tpd_ring->next_to_clean, 0); 1114 1115 rfd_ring->next_to_clean = 0; 1116 atomic_set(&rfd_ring->next_to_use, 0); 1117 1118 rrd_ring->next_to_use = 0; 1119 atomic_set(&rrd_ring->next_to_clean, 0); 1120} 1121 1122/** 1123 * atl1_clean_rx_ring - Free RFD Buffers 1124 * @adapter: board private structure 1125 */ 1126static void atl1_clean_rx_ring(struct atl1_adapter *adapter) 1127{ 1128 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1129 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1130 struct atl1_buffer *buffer_info; 1131 struct pci_dev *pdev = adapter->pdev; 1132 unsigned long size; 1133 unsigned int i; 1134 1135 /* Free all the Rx ring sk_buffs */ 1136 for (i = 0; i < rfd_ring->count; i++) { 1137 buffer_info = &rfd_ring->buffer_info[i]; 1138 if (buffer_info->dma) { 1139 dma_unmap_page(&pdev->dev, buffer_info->dma, 1140 buffer_info->length, DMA_FROM_DEVICE); 1141 buffer_info->dma = 0; 1142 } 1143 if (buffer_info->skb) { 1144 dev_kfree_skb(buffer_info->skb); 1145 buffer_info->skb = NULL; 1146 } 1147 } 1148 1149 size = sizeof(struct atl1_buffer) * rfd_ring->count; 1150 memset(rfd_ring->buffer_info, 0, size); 1151 1152 /* Zero out the descriptor ring */ 1153 memset(rfd_ring->desc, 0, rfd_ring->size); 1154 1155 rfd_ring->next_to_clean = 0; 1156 atomic_set(&rfd_ring->next_to_use, 0); 1157 1158 rrd_ring->next_to_use = 0; 1159 atomic_set(&rrd_ring->next_to_clean, 0); 1160} 1161 1162/** 1163 * atl1_clean_tx_ring - Free Tx Buffers 1164 * @adapter: board private structure 1165 */ 1166static void atl1_clean_tx_ring(struct atl1_adapter *adapter) 1167{ 1168 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1169 struct atl1_buffer *buffer_info; 1170 struct pci_dev *pdev = adapter->pdev; 1171 unsigned long size; 1172 unsigned int i; 1173 1174 /* Free all the Tx ring sk_buffs */ 1175 for (i = 0; i < tpd_ring->count; i++) { 1176 buffer_info = &tpd_ring->buffer_info[i]; 1177 if (buffer_info->dma) { 1178 dma_unmap_page(&pdev->dev, buffer_info->dma, 1179 buffer_info->length, DMA_TO_DEVICE); 1180 buffer_info->dma = 0; 1181 } 1182 } 1183 1184 for (i = 0; i < tpd_ring->count; i++) { 1185 buffer_info = &tpd_ring->buffer_info[i]; 1186 if (buffer_info->skb) { 1187 dev_kfree_skb_any(buffer_info->skb); 1188 buffer_info->skb = NULL; 1189 } 1190 } 1191 1192 size = sizeof(struct atl1_buffer) * tpd_ring->count; 1193 memset(tpd_ring->buffer_info, 0, size); 1194 1195 /* Zero out the descriptor ring */ 1196 memset(tpd_ring->desc, 0, tpd_ring->size); 1197 1198 atomic_set(&tpd_ring->next_to_use, 0); 1199 atomic_set(&tpd_ring->next_to_clean, 0); 1200} 1201 1202/** 1203 * atl1_free_ring_resources - Free Tx / RX descriptor Resources 1204 * @adapter: board private structure 1205 * 1206 * Free all transmit software resources 1207 */ 1208static void atl1_free_ring_resources(struct atl1_adapter *adapter) 1209{ 1210 struct pci_dev *pdev = adapter->pdev; 1211 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1212 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1213 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1214 struct atl1_ring_header *ring_header = &adapter->ring_header; 1215 1216 atl1_clean_tx_ring(adapter); 1217 atl1_clean_rx_ring(adapter); 1218 1219 kfree(tpd_ring->buffer_info); 1220 dma_free_coherent(&pdev->dev, ring_header->size, ring_header->desc, 1221 ring_header->dma); 1222 1223 tpd_ring->buffer_info = NULL; 1224 tpd_ring->desc = NULL; 1225 tpd_ring->dma = 0; 1226 1227 rfd_ring->buffer_info = NULL; 1228 rfd_ring->desc = NULL; 1229 rfd_ring->dma = 0; 1230 1231 rrd_ring->desc = NULL; 1232 rrd_ring->dma = 0; 1233 1234 adapter->cmb.dma = 0; 1235 adapter->cmb.cmb = NULL; 1236 1237 adapter->smb.dma = 0; 1238 adapter->smb.smb = NULL; 1239} 1240 1241static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter) 1242{ 1243 u32 value; 1244 struct atl1_hw *hw = &adapter->hw; 1245 struct net_device *netdev = adapter->netdev; 1246 /* Config MAC CTRL Register */ 1247 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN; 1248 /* duplex */ 1249 if (FULL_DUPLEX == adapter->link_duplex) 1250 value |= MAC_CTRL_DUPLX; 1251 /* speed */ 1252 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ? 1253 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) << 1254 MAC_CTRL_SPEED_SHIFT); 1255 /* flow control */ 1256 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1257 /* PAD & CRC */ 1258 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1259 /* preamble length */ 1260 value |= (((u32) adapter->hw.preamble_len 1261 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1262 /* vlan */ 1263 __atlx_vlan_mode(netdev->features, &value); 1264 /* rx checksum 1265 if (adapter->rx_csum) 1266 value |= MAC_CTRL_RX_CHKSUM_EN; 1267 */ 1268 /* filter mode */ 1269 value |= MAC_CTRL_BC_EN; 1270 if (netdev->flags & IFF_PROMISC) 1271 value |= MAC_CTRL_PROMIS_EN; 1272 else if (netdev->flags & IFF_ALLMULTI) 1273 value |= MAC_CTRL_MC_ALL_EN; 1274 /* value |= MAC_CTRL_LOOPBACK; */ 1275 iowrite32(value, hw->hw_addr + REG_MAC_CTRL); 1276} 1277 1278static u32 atl1_check_link(struct atl1_adapter *adapter) 1279{ 1280 struct atl1_hw *hw = &adapter->hw; 1281 struct net_device *netdev = adapter->netdev; 1282 u32 ret_val; 1283 u16 speed, duplex, phy_data; 1284 int reconfig = 0; 1285 1286 /* MII_BMSR must read twice */ 1287 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 1288 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 1289 if (!(phy_data & BMSR_LSTATUS)) { 1290 /* link down */ 1291 if (netif_carrier_ok(netdev)) { 1292 /* old link state: Up */ 1293 if (netif_msg_link(adapter)) 1294 dev_info(&adapter->pdev->dev, "link is down\n"); 1295 adapter->link_speed = SPEED_0; 1296 netif_carrier_off(netdev); 1297 } 1298 return 0; 1299 } 1300 1301 /* Link Up */ 1302 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex); 1303 if (ret_val) 1304 return ret_val; 1305 1306 switch (hw->media_type) { 1307 case MEDIA_TYPE_1000M_FULL: 1308 if (speed != SPEED_1000 || duplex != FULL_DUPLEX) 1309 reconfig = 1; 1310 break; 1311 case MEDIA_TYPE_100M_FULL: 1312 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1313 reconfig = 1; 1314 break; 1315 case MEDIA_TYPE_100M_HALF: 1316 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1317 reconfig = 1; 1318 break; 1319 case MEDIA_TYPE_10M_FULL: 1320 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1321 reconfig = 1; 1322 break; 1323 case MEDIA_TYPE_10M_HALF: 1324 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1325 reconfig = 1; 1326 break; 1327 } 1328 1329 /* link result is our setting */ 1330 if (!reconfig) { 1331 if (adapter->link_speed != speed || 1332 adapter->link_duplex != duplex) { 1333 adapter->link_speed = speed; 1334 adapter->link_duplex = duplex; 1335 atl1_setup_mac_ctrl(adapter); 1336 if (netif_msg_link(adapter)) 1337 dev_info(&adapter->pdev->dev, 1338 "%s link is up %d Mbps %s\n", 1339 netdev->name, adapter->link_speed, 1340 adapter->link_duplex == FULL_DUPLEX ? 1341 "full duplex" : "half duplex"); 1342 } 1343 if (!netif_carrier_ok(netdev)) { 1344 /* Link down -> Up */ 1345 netif_carrier_on(netdev); 1346 } 1347 return 0; 1348 } 1349 1350 /* change original link status */ 1351 if (netif_carrier_ok(netdev)) { 1352 adapter->link_speed = SPEED_0; 1353 netif_carrier_off(netdev); 1354 netif_stop_queue(netdev); 1355 } 1356 1357 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR && 1358 hw->media_type != MEDIA_TYPE_1000M_FULL) { 1359 switch (hw->media_type) { 1360 case MEDIA_TYPE_100M_FULL: 1361 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 1362 MII_CR_RESET; 1363 break; 1364 case MEDIA_TYPE_100M_HALF: 1365 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 1366 break; 1367 case MEDIA_TYPE_10M_FULL: 1368 phy_data = 1369 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 1370 break; 1371 default: 1372 /* MEDIA_TYPE_10M_HALF: */ 1373 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 1374 break; 1375 } 1376 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 1377 return 0; 1378 } 1379 1380 /* auto-neg, insert timer to re-config phy */ 1381 if (!adapter->phy_timer_pending) { 1382 adapter->phy_timer_pending = true; 1383 mod_timer(&adapter->phy_config_timer, 1384 round_jiffies(jiffies + 3 * HZ)); 1385 } 1386 1387 return 0; 1388} 1389 1390static void set_flow_ctrl_old(struct atl1_adapter *adapter) 1391{ 1392 u32 hi, lo, value; 1393 1394 /* RFD Flow Control */ 1395 value = adapter->rfd_ring.count; 1396 hi = value / 16; 1397 if (hi < 2) 1398 hi = 2; 1399 lo = value * 7 / 8; 1400 1401 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 1402 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); 1403 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); 1404 1405 /* RRD Flow Control */ 1406 value = adapter->rrd_ring.count; 1407 lo = value / 16; 1408 hi = value * 7 / 8; 1409 if (lo < 2) 1410 lo = 2; 1411 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | 1412 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); 1413 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH); 1414} 1415 1416static void set_flow_ctrl_new(struct atl1_hw *hw) 1417{ 1418 u32 hi, lo, value; 1419 1420 /* RXF Flow Control */ 1421 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); 1422 lo = value / 16; 1423 if (lo < 192) 1424 lo = 192; 1425 hi = value * 7 / 8; 1426 if (hi < lo) 1427 hi = lo + 16; 1428 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 1429 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); 1430 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH); 1431 1432 /* RRD Flow Control */ 1433 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); 1434 lo = value / 8; 1435 hi = value * 7 / 8; 1436 if (lo < 2) 1437 lo = 2; 1438 if (hi < lo) 1439 hi = lo + 3; 1440 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | 1441 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); 1442 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); 1443} 1444 1445/** 1446 * atl1_configure - Configure Transmit&Receive Unit after Reset 1447 * @adapter: board private structure 1448 * 1449 * Configure the Tx /Rx unit of the MAC after a reset. 1450 */ 1451static u32 atl1_configure(struct atl1_adapter *adapter) 1452{ 1453 struct atl1_hw *hw = &adapter->hw; 1454 u32 value; 1455 1456 /* clear interrupt status */ 1457 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR); 1458 1459 /* set MAC Address */ 1460 value = (((u32) hw->mac_addr[2]) << 24) | 1461 (((u32) hw->mac_addr[3]) << 16) | 1462 (((u32) hw->mac_addr[4]) << 8) | 1463 (((u32) hw->mac_addr[5])); 1464 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); 1465 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); 1466 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); 1467 1468 /* tx / rx ring */ 1469 1470 /* HI base address */ 1471 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32), 1472 hw->hw_addr + REG_DESC_BASE_ADDR_HI); 1473 /* LO base address */ 1474 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL), 1475 hw->hw_addr + REG_DESC_RFD_ADDR_LO); 1476 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL), 1477 hw->hw_addr + REG_DESC_RRD_ADDR_LO); 1478 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL), 1479 hw->hw_addr + REG_DESC_TPD_ADDR_LO); 1480 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL), 1481 hw->hw_addr + REG_DESC_CMB_ADDR_LO); 1482 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL), 1483 hw->hw_addr + REG_DESC_SMB_ADDR_LO); 1484 1485 /* element count */ 1486 value = adapter->rrd_ring.count; 1487 value <<= 16; 1488 value += adapter->rfd_ring.count; 1489 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE); 1490 iowrite32(adapter->tpd_ring.count, hw->hw_addr + 1491 REG_DESC_TPD_RING_SIZE); 1492 1493 /* Load Ptr */ 1494 iowrite32(1, hw->hw_addr + REG_LOAD_PTR); 1495 1496 /* config Mailbox */ 1497 value = ((atomic_read(&adapter->tpd_ring.next_to_use) 1498 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) | 1499 ((atomic_read(&adapter->rrd_ring.next_to_clean) 1500 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) | 1501 ((atomic_read(&adapter->rfd_ring.next_to_use) 1502 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT); 1503 iowrite32(value, hw->hw_addr + REG_MAILBOX); 1504 1505 /* config IPG/IFG */ 1506 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) 1507 << MAC_IPG_IFG_IPGT_SHIFT) | 1508 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) 1509 << MAC_IPG_IFG_MIFG_SHIFT) | 1510 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) 1511 << MAC_IPG_IFG_IPGR1_SHIFT) | 1512 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) 1513 << MAC_IPG_IFG_IPGR2_SHIFT); 1514 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG); 1515 1516 /* config Half-Duplex Control */ 1517 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 1518 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) 1519 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 1520 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 1521 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 1522 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) 1523 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 1524 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL); 1525 1526 /* set Interrupt Moderator Timer */ 1527 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT); 1528 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL); 1529 1530 /* set Interrupt Clear Timer */ 1531 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER); 1532 1533 /* set max frame size hw will accept */ 1534 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU); 1535 1536 /* jumbo size & rrd retirement timer */ 1537 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) 1538 << RXQ_JMBOSZ_TH_SHIFT) | 1539 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK) 1540 << RXQ_JMBO_LKAH_SHIFT) | 1541 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK) 1542 << RXQ_RRD_TIMER_SHIFT); 1543 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM); 1544 1545 /* Flow Control */ 1546 switch (hw->dev_rev) { 1547 case 0x8001: 1548 case 0x9001: 1549 case 0x9002: 1550 case 0x9003: 1551 set_flow_ctrl_old(adapter); 1552 break; 1553 default: 1554 set_flow_ctrl_new(hw); 1555 break; 1556 } 1557 1558 /* config TXQ */ 1559 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) 1560 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) | 1561 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK) 1562 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) | 1563 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK) 1564 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE | 1565 TXQ_CTRL_EN; 1566 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL); 1567 1568 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */ 1569 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) 1570 << TX_JUMBO_TASK_TH_SHIFT) | 1571 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK) 1572 << TX_TPD_MIN_IPG_SHIFT); 1573 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); 1574 1575 /* config RXQ */ 1576 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) 1577 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) | 1578 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK) 1579 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) | 1580 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK) 1581 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN | 1582 RXQ_CTRL_EN; 1583 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL); 1584 1585 /* config DMA Engine */ 1586 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) 1587 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) | 1588 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) 1589 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN | 1590 DMA_CTRL_DMAW_EN; 1591 value |= (u32) hw->dma_ord; 1592 if (atl1_rcb_128 == hw->rcb_value) 1593 value |= DMA_CTRL_RCB_VALUE; 1594 iowrite32(value, hw->hw_addr + REG_DMA_CTRL); 1595 1596 /* config CMB / SMB */ 1597 value = (hw->cmb_tpd > adapter->tpd_ring.count) ? 1598 hw->cmb_tpd : adapter->tpd_ring.count; 1599 value <<= 16; 1600 value |= hw->cmb_rrd; 1601 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH); 1602 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16); 1603 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER); 1604 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER); 1605 1606 /* --- enable CMB / SMB */ 1607 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN; 1608 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL); 1609 1610 value = ioread32(adapter->hw.hw_addr + REG_ISR); 1611 if (unlikely((value & ISR_PHY_LINKDOWN) != 0)) 1612 value = 1; /* config failed */ 1613 else 1614 value = 0; 1615 1616 /* clear all interrupt status */ 1617 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR); 1618 iowrite32(0, adapter->hw.hw_addr + REG_ISR); 1619 return value; 1620} 1621 1622/* 1623 * atl1_pcie_patch - Patch for PCIE module 1624 */ 1625static void atl1_pcie_patch(struct atl1_adapter *adapter) 1626{ 1627 u32 value; 1628 1629 /* much vendor magic here */ 1630 value = 0x6500; 1631 iowrite32(value, adapter->hw.hw_addr + 0x12FC); 1632 /* pcie flow control mode change */ 1633 value = ioread32(adapter->hw.hw_addr + 0x1008); 1634 value |= 0x8000; 1635 iowrite32(value, adapter->hw.hw_addr + 0x1008); 1636} 1637 1638/* 1639 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400 1640 * on PCI Command register is disable. 1641 * The function enable this bit. 1642 * Brackett, 2006/03/15 1643 */ 1644static void atl1_via_workaround(struct atl1_adapter *adapter) 1645{ 1646 unsigned long value; 1647 1648 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); 1649 if (value & PCI_COMMAND_INTX_DISABLE) 1650 value &= ~PCI_COMMAND_INTX_DISABLE; 1651 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); 1652} 1653 1654static void atl1_inc_smb(struct atl1_adapter *adapter) 1655{ 1656 struct net_device *netdev = adapter->netdev; 1657 struct stats_msg_block *smb = adapter->smb.smb; 1658 1659 u64 new_rx_errors = smb->rx_frag + 1660 smb->rx_fcs_err + 1661 smb->rx_len_err + 1662 smb->rx_sz_ov + 1663 smb->rx_rxf_ov + 1664 smb->rx_rrd_ov + 1665 smb->rx_align_err; 1666 u64 new_tx_errors = smb->tx_late_col + 1667 smb->tx_abort_col + 1668 smb->tx_underrun + 1669 smb->tx_trunc; 1670 1671 /* Fill out the OS statistics structure */ 1672 adapter->soft_stats.rx_packets += smb->rx_ok + new_rx_errors; 1673 adapter->soft_stats.tx_packets += smb->tx_ok + new_tx_errors; 1674 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt; 1675 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt; 1676 adapter->soft_stats.multicast += smb->rx_mcast; 1677 adapter->soft_stats.collisions += smb->tx_1_col + 1678 smb->tx_2_col + 1679 smb->tx_late_col + 1680 smb->tx_abort_col; 1681 1682 /* Rx Errors */ 1683 adapter->soft_stats.rx_errors += new_rx_errors; 1684 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov; 1685 adapter->soft_stats.rx_length_errors += smb->rx_len_err; 1686 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err; 1687 adapter->soft_stats.rx_frame_errors += smb->rx_align_err; 1688 1689 adapter->soft_stats.rx_pause += smb->rx_pause; 1690 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov; 1691 adapter->soft_stats.rx_trunc += smb->rx_sz_ov; 1692 1693 /* Tx Errors */ 1694 adapter->soft_stats.tx_errors += new_tx_errors; 1695 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun; 1696 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col; 1697 adapter->soft_stats.tx_window_errors += smb->tx_late_col; 1698 1699 adapter->soft_stats.excecol += smb->tx_abort_col; 1700 adapter->soft_stats.deffer += smb->tx_defer; 1701 adapter->soft_stats.scc += smb->tx_1_col; 1702 adapter->soft_stats.mcc += smb->tx_2_col; 1703 adapter->soft_stats.latecol += smb->tx_late_col; 1704 adapter->soft_stats.tx_underrun += smb->tx_underrun; 1705 adapter->soft_stats.tx_trunc += smb->tx_trunc; 1706 adapter->soft_stats.tx_pause += smb->tx_pause; 1707 1708 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes; 1709 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes; 1710 netdev->stats.multicast = adapter->soft_stats.multicast; 1711 netdev->stats.collisions = adapter->soft_stats.collisions; 1712 netdev->stats.rx_errors = adapter->soft_stats.rx_errors; 1713 netdev->stats.rx_length_errors = 1714 adapter->soft_stats.rx_length_errors; 1715 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors; 1716 netdev->stats.rx_frame_errors = 1717 adapter->soft_stats.rx_frame_errors; 1718 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors; 1719 netdev->stats.rx_dropped = adapter->soft_stats.rx_rrd_ov; 1720 netdev->stats.tx_errors = adapter->soft_stats.tx_errors; 1721 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors; 1722 netdev->stats.tx_aborted_errors = 1723 adapter->soft_stats.tx_aborted_errors; 1724 netdev->stats.tx_window_errors = 1725 adapter->soft_stats.tx_window_errors; 1726 netdev->stats.tx_carrier_errors = 1727 adapter->soft_stats.tx_carrier_errors; 1728 1729 netdev->stats.rx_packets = adapter->soft_stats.rx_packets; 1730 netdev->stats.tx_packets = adapter->soft_stats.tx_packets; 1731} 1732 1733static void atl1_update_mailbox(struct atl1_adapter *adapter) 1734{ 1735 unsigned long flags; 1736 u32 tpd_next_to_use; 1737 u32 rfd_next_to_use; 1738 u32 rrd_next_to_clean; 1739 u32 value; 1740 1741 spin_lock_irqsave(&adapter->mb_lock, flags); 1742 1743 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); 1744 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use); 1745 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean); 1746 1747 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << 1748 MB_RFD_PROD_INDX_SHIFT) | 1749 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << 1750 MB_RRD_CONS_INDX_SHIFT) | 1751 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << 1752 MB_TPD_PROD_INDX_SHIFT); 1753 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); 1754 1755 spin_unlock_irqrestore(&adapter->mb_lock, flags); 1756} 1757 1758static void atl1_clean_alloc_flag(struct atl1_adapter *adapter, 1759 struct rx_return_desc *rrd, u16 offset) 1760{ 1761 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1762 1763 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) { 1764 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0; 1765 if (++rfd_ring->next_to_clean == rfd_ring->count) { 1766 rfd_ring->next_to_clean = 0; 1767 } 1768 } 1769} 1770 1771static void atl1_update_rfd_index(struct atl1_adapter *adapter, 1772 struct rx_return_desc *rrd) 1773{ 1774 u16 num_buf; 1775 1776 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) / 1777 adapter->rx_buffer_len; 1778 if (rrd->num_buf == num_buf) 1779 /* clean alloc flag for bad rrd */ 1780 atl1_clean_alloc_flag(adapter, rrd, num_buf); 1781} 1782 1783static void atl1_rx_checksum(struct atl1_adapter *adapter, 1784 struct rx_return_desc *rrd, struct sk_buff *skb) 1785{ 1786 struct pci_dev *pdev = adapter->pdev; 1787 1788 /* 1789 * The L1 hardware contains a bug that erroneously sets the 1790 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a 1791 * fragmented IP packet is received, even though the packet 1792 * is perfectly valid and its checksum is correct. There's 1793 * no way to distinguish between one of these good packets 1794 * and a packet that actually contains a TCP/UDP checksum 1795 * error, so all we can do is allow it to be handed up to 1796 * the higher layers and let it be sorted out there. 1797 */ 1798 1799 skb_checksum_none_assert(skb); 1800 1801 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { 1802 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC | 1803 ERR_FLAG_CODE | ERR_FLAG_OV)) { 1804 adapter->hw_csum_err++; 1805 if (netif_msg_rx_err(adapter)) 1806 dev_printk(KERN_DEBUG, &pdev->dev, 1807 "rx checksum error\n"); 1808 return; 1809 } 1810 } 1811 1812 /* not IPv4 */ 1813 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4)) 1814 /* checksum is invalid, but it's not an IPv4 pkt, so ok */ 1815 return; 1816 1817 /* IPv4 packet */ 1818 if (likely(!(rrd->err_flg & 1819 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) { 1820 skb->ip_summed = CHECKSUM_UNNECESSARY; 1821 adapter->hw_csum_good++; 1822 return; 1823 } 1824} 1825 1826/** 1827 * atl1_alloc_rx_buffers - Replace used receive buffers 1828 * @adapter: address of board private structure 1829 */ 1830static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter) 1831{ 1832 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1833 struct pci_dev *pdev = adapter->pdev; 1834 struct page *page; 1835 unsigned long offset; 1836 struct atl1_buffer *buffer_info, *next_info; 1837 struct sk_buff *skb; 1838 u16 num_alloc = 0; 1839 u16 rfd_next_to_use, next_next; 1840 struct rx_free_desc *rfd_desc; 1841 1842 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use); 1843 if (++next_next == rfd_ring->count) 1844 next_next = 0; 1845 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; 1846 next_info = &rfd_ring->buffer_info[next_next]; 1847 1848 while (!buffer_info->alloced && !next_info->alloced) { 1849 if (buffer_info->skb) { 1850 buffer_info->alloced = 1; 1851 goto next; 1852 } 1853 1854 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); 1855 1856 skb = netdev_alloc_skb_ip_align(adapter->netdev, 1857 adapter->rx_buffer_len); 1858 if (unlikely(!skb)) { 1859 /* Better luck next round */ 1860 adapter->soft_stats.rx_dropped++; 1861 break; 1862 } 1863 1864 page = virt_to_page(skb->data); 1865 offset = offset_in_page(skb->data); 1866 buffer_info->dma = dma_map_page(&pdev->dev, page, offset, 1867 adapter->rx_buffer_len, 1868 DMA_FROM_DEVICE); 1869 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 1870 kfree_skb(skb); 1871 adapter->soft_stats.rx_dropped++; 1872 break; 1873 } 1874 1875 buffer_info->alloced = 1; 1876 buffer_info->skb = skb; 1877 buffer_info->length = (u16)adapter->rx_buffer_len; 1878 1879 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 1880 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len); 1881 rfd_desc->coalese = 0; 1882 1883next: 1884 rfd_next_to_use = next_next; 1885 if (unlikely(++next_next == rfd_ring->count)) 1886 next_next = 0; 1887 1888 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; 1889 next_info = &rfd_ring->buffer_info[next_next]; 1890 num_alloc++; 1891 } 1892 1893 if (num_alloc) { 1894 /* 1895 * Force memory writes to complete before letting h/w 1896 * know there are new descriptors to fetch. (Only 1897 * applicable for weak-ordered memory model archs, 1898 * such as IA-64). 1899 */ 1900 wmb(); 1901 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use); 1902 } 1903 return num_alloc; 1904} 1905 1906static int atl1_intr_rx(struct atl1_adapter *adapter, int budget) 1907{ 1908 int i, count; 1909 u16 length; 1910 u16 rrd_next_to_clean; 1911 u32 value; 1912 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1913 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1914 struct atl1_buffer *buffer_info; 1915 struct rx_return_desc *rrd; 1916 struct sk_buff *skb; 1917 1918 count = 0; 1919 1920 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean); 1921 1922 while (count < budget) { 1923 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean); 1924 i = 1; 1925 if (likely(rrd->xsz.valid)) { /* packet valid */ 1926chk_rrd: 1927 /* check rrd status */ 1928 if (likely(rrd->num_buf == 1)) 1929 goto rrd_ok; 1930 else if (netif_msg_rx_err(adapter)) { 1931 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1932 "unexpected RRD buffer count\n"); 1933 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1934 "rx_buf_len = %d\n", 1935 adapter->rx_buffer_len); 1936 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1937 "RRD num_buf = %d\n", 1938 rrd->num_buf); 1939 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1940 "RRD pkt_len = %d\n", 1941 rrd->xsz.xsum_sz.pkt_size); 1942 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1943 "RRD pkt_flg = 0x%08X\n", 1944 rrd->pkt_flg); 1945 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1946 "RRD err_flg = 0x%08X\n", 1947 rrd->err_flg); 1948 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1949 "RRD vlan_tag = 0x%08X\n", 1950 rrd->vlan_tag); 1951 } 1952 1953 /* rrd seems to be bad */ 1954 if (unlikely(i-- > 0)) { 1955 /* rrd may not be DMAed completely */ 1956 udelay(1); 1957 goto chk_rrd; 1958 } 1959 /* bad rrd */ 1960 if (netif_msg_rx_err(adapter)) 1961 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1962 "bad RRD\n"); 1963 /* see if update RFD index */ 1964 if (rrd->num_buf > 1) 1965 atl1_update_rfd_index(adapter, rrd); 1966 1967 /* update rrd */ 1968 rrd->xsz.valid = 0; 1969 if (++rrd_next_to_clean == rrd_ring->count) 1970 rrd_next_to_clean = 0; 1971 count++; 1972 continue; 1973 } else { /* current rrd still not be updated */ 1974 1975 break; 1976 } 1977rrd_ok: 1978 /* clean alloc flag for bad rrd */ 1979 atl1_clean_alloc_flag(adapter, rrd, 0); 1980 1981 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx]; 1982 if (++rfd_ring->next_to_clean == rfd_ring->count) 1983 rfd_ring->next_to_clean = 0; 1984 1985 /* update rrd next to clean */ 1986 if (++rrd_next_to_clean == rrd_ring->count) 1987 rrd_next_to_clean = 0; 1988 count++; 1989 1990 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { 1991 if (!(rrd->err_flg & 1992 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM 1993 | ERR_FLAG_LEN))) { 1994 /* packet error, don't need upstream */ 1995 buffer_info->alloced = 0; 1996 rrd->xsz.valid = 0; 1997 continue; 1998 } 1999 } 2000 2001 /* Good Receive */ 2002 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 2003 buffer_info->length, DMA_FROM_DEVICE); 2004 buffer_info->dma = 0; 2005 skb = buffer_info->skb; 2006 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size); 2007 2008 skb_put(skb, length - ETH_FCS_LEN); 2009 2010 /* Receive Checksum Offload */ 2011 atl1_rx_checksum(adapter, rrd, skb); 2012 skb->protocol = eth_type_trans(skb, adapter->netdev); 2013 2014 if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) { 2015 u16 vlan_tag = (rrd->vlan_tag >> 4) | 2016 ((rrd->vlan_tag & 7) << 13) | 2017 ((rrd->vlan_tag & 8) << 9); 2018 2019 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 2020 } 2021 netif_receive_skb(skb); 2022 2023 /* let protocol layer free skb */ 2024 buffer_info->skb = NULL; 2025 buffer_info->alloced = 0; 2026 rrd->xsz.valid = 0; 2027 } 2028 2029 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean); 2030 2031 atl1_alloc_rx_buffers(adapter); 2032 2033 /* update mailbox ? */ 2034 if (count) { 2035 u32 tpd_next_to_use; 2036 u32 rfd_next_to_use; 2037 2038 spin_lock(&adapter->mb_lock); 2039 2040 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); 2041 rfd_next_to_use = 2042 atomic_read(&adapter->rfd_ring.next_to_use); 2043 rrd_next_to_clean = 2044 atomic_read(&adapter->rrd_ring.next_to_clean); 2045 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << 2046 MB_RFD_PROD_INDX_SHIFT) | 2047 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << 2048 MB_RRD_CONS_INDX_SHIFT) | 2049 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << 2050 MB_TPD_PROD_INDX_SHIFT); 2051 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); 2052 spin_unlock(&adapter->mb_lock); 2053 } 2054 2055 return count; 2056} 2057 2058static int atl1_intr_tx(struct atl1_adapter *adapter) 2059{ 2060 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2061 struct atl1_buffer *buffer_info; 2062 u16 sw_tpd_next_to_clean; 2063 u16 cmb_tpd_next_to_clean; 2064 int count = 0; 2065 2066 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean); 2067 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx); 2068 2069 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) { 2070 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean]; 2071 if (buffer_info->dma) { 2072 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 2073 buffer_info->length, DMA_TO_DEVICE); 2074 buffer_info->dma = 0; 2075 } 2076 2077 if (buffer_info->skb) { 2078 dev_consume_skb_irq(buffer_info->skb); 2079 buffer_info->skb = NULL; 2080 } 2081 2082 if (++sw_tpd_next_to_clean == tpd_ring->count) 2083 sw_tpd_next_to_clean = 0; 2084 2085 count++; 2086 } 2087 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean); 2088 2089 if (netif_queue_stopped(adapter->netdev) && 2090 netif_carrier_ok(adapter->netdev)) 2091 netif_wake_queue(adapter->netdev); 2092 2093 return count; 2094} 2095 2096static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring) 2097{ 2098 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean); 2099 u16 next_to_use = atomic_read(&tpd_ring->next_to_use); 2100 return (next_to_clean > next_to_use) ? 2101 next_to_clean - next_to_use - 1 : 2102 tpd_ring->count + next_to_clean - next_to_use - 1; 2103} 2104 2105static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb, 2106 struct tx_packet_desc *ptpd) 2107{ 2108 u8 hdr_len, ip_off; 2109 u32 real_len; 2110 2111 if (skb_shinfo(skb)->gso_size) { 2112 int err; 2113 2114 err = skb_cow_head(skb, 0); 2115 if (err < 0) 2116 return err; 2117 2118 if (skb->protocol == htons(ETH_P_IP)) { 2119 struct iphdr *iph = ip_hdr(skb); 2120 2121 real_len = (((unsigned char *)iph - skb->data) + 2122 ntohs(iph->tot_len)); 2123 if (real_len < skb->len) { 2124 err = pskb_trim(skb, real_len); 2125 if (err) 2126 return err; 2127 } 2128 hdr_len = skb_tcp_all_headers(skb); 2129 if (skb->len == hdr_len) { 2130 iph->check = 0; 2131 tcp_hdr(skb)->check = 2132 ~csum_tcpudp_magic(iph->saddr, 2133 iph->daddr, tcp_hdrlen(skb), 2134 IPPROTO_TCP, 0); 2135 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << 2136 TPD_IPHL_SHIFT; 2137 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & 2138 TPD_TCPHDRLEN_MASK) << 2139 TPD_TCPHDRLEN_SHIFT; 2140 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT; 2141 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT; 2142 return 1; 2143 } 2144 2145 iph->check = 0; 2146 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 2147 iph->daddr, 0, IPPROTO_TCP, 0); 2148 ip_off = (unsigned char *)iph - 2149 (unsigned char *) skb_network_header(skb); 2150 if (ip_off == 8) /* 802.3-SNAP frame */ 2151 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; 2152 else if (ip_off != 0) 2153 return -2; 2154 2155 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << 2156 TPD_IPHL_SHIFT; 2157 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & 2158 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT; 2159 ptpd->word3 |= (skb_shinfo(skb)->gso_size & 2160 TPD_MSS_MASK) << TPD_MSS_SHIFT; 2161 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT; 2162 return 3; 2163 } 2164 } 2165 return 0; 2166} 2167 2168static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb, 2169 struct tx_packet_desc *ptpd) 2170{ 2171 u8 css, cso; 2172 2173 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 2174 css = skb_checksum_start_offset(skb); 2175 cso = css + (u8) skb->csum_offset; 2176 if (unlikely(css & 0x1)) { 2177 /* L1 hardware requires an even number here */ 2178 if (netif_msg_tx_err(adapter)) 2179 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2180 "payload offset not an even number\n"); 2181 return -1; 2182 } 2183 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) << 2184 TPD_PLOADOFFSET_SHIFT; 2185 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) << 2186 TPD_CCSUMOFFSET_SHIFT; 2187 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT; 2188 return true; 2189 } 2190 return 0; 2191} 2192 2193static bool atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb, 2194 struct tx_packet_desc *ptpd) 2195{ 2196 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2197 struct atl1_buffer *buffer_info; 2198 u16 buf_len = skb->len; 2199 struct page *page; 2200 unsigned long offset; 2201 unsigned int nr_frags; 2202 unsigned int f; 2203 int retval; 2204 u16 first_mapped; 2205 u16 next_to_use; 2206 u16 data_len; 2207 u8 hdr_len; 2208 2209 buf_len -= skb->data_len; 2210 nr_frags = skb_shinfo(skb)->nr_frags; 2211 next_to_use = atomic_read(&tpd_ring->next_to_use); 2212 first_mapped = next_to_use; 2213 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2214 BUG_ON(buffer_info->skb); 2215 /* put skb in last TPD */ 2216 buffer_info->skb = NULL; 2217 2218 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK; 2219 if (retval) { 2220 /* TSO */ 2221 hdr_len = skb_tcp_all_headers(skb); 2222 buffer_info->length = hdr_len; 2223 page = virt_to_page(skb->data); 2224 offset = offset_in_page(skb->data); 2225 buffer_info->dma = dma_map_page(&adapter->pdev->dev, page, 2226 offset, hdr_len, 2227 DMA_TO_DEVICE); 2228 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) 2229 goto dma_err; 2230 2231 if (++next_to_use == tpd_ring->count) 2232 next_to_use = 0; 2233 2234 if (buf_len > hdr_len) { 2235 int i, nseg; 2236 2237 data_len = buf_len - hdr_len; 2238 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) / 2239 ATL1_MAX_TX_BUF_LEN; 2240 for (i = 0; i < nseg; i++) { 2241 buffer_info = 2242 &tpd_ring->buffer_info[next_to_use]; 2243 buffer_info->skb = NULL; 2244 buffer_info->length = 2245 (ATL1_MAX_TX_BUF_LEN >= 2246 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len; 2247 data_len -= buffer_info->length; 2248 page = virt_to_page(skb->data + 2249 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); 2250 offset = offset_in_page(skb->data + 2251 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); 2252 buffer_info->dma = dma_map_page(&adapter->pdev->dev, 2253 page, offset, 2254 buffer_info->length, 2255 DMA_TO_DEVICE); 2256 if (dma_mapping_error(&adapter->pdev->dev, 2257 buffer_info->dma)) 2258 goto dma_err; 2259 if (++next_to_use == tpd_ring->count) 2260 next_to_use = 0; 2261 } 2262 } 2263 } else { 2264 /* not TSO */ 2265 buffer_info->length = buf_len; 2266 page = virt_to_page(skb->data); 2267 offset = offset_in_page(skb->data); 2268 buffer_info->dma = dma_map_page(&adapter->pdev->dev, page, 2269 offset, buf_len, 2270 DMA_TO_DEVICE); 2271 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) 2272 goto dma_err; 2273 if (++next_to_use == tpd_ring->count) 2274 next_to_use = 0; 2275 } 2276 2277 for (f = 0; f < nr_frags; f++) { 2278 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 2279 u16 i, nseg; 2280 2281 buf_len = skb_frag_size(frag); 2282 2283 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) / 2284 ATL1_MAX_TX_BUF_LEN; 2285 for (i = 0; i < nseg; i++) { 2286 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2287 BUG_ON(buffer_info->skb); 2288 2289 buffer_info->skb = NULL; 2290 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ? 2291 ATL1_MAX_TX_BUF_LEN : buf_len; 2292 buf_len -= buffer_info->length; 2293 buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev, 2294 frag, i * ATL1_MAX_TX_BUF_LEN, 2295 buffer_info->length, DMA_TO_DEVICE); 2296 if (dma_mapping_error(&adapter->pdev->dev, 2297 buffer_info->dma)) 2298 goto dma_err; 2299 2300 if (++next_to_use == tpd_ring->count) 2301 next_to_use = 0; 2302 } 2303 } 2304 2305 /* last tpd's buffer-info */ 2306 buffer_info->skb = skb; 2307 2308 return true; 2309 2310 dma_err: 2311 while (first_mapped != next_to_use) { 2312 buffer_info = &tpd_ring->buffer_info[first_mapped]; 2313 dma_unmap_page(&adapter->pdev->dev, 2314 buffer_info->dma, 2315 buffer_info->length, 2316 DMA_TO_DEVICE); 2317 buffer_info->dma = 0; 2318 2319 if (++first_mapped == tpd_ring->count) 2320 first_mapped = 0; 2321 } 2322 return false; 2323} 2324 2325static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count, 2326 struct tx_packet_desc *ptpd) 2327{ 2328 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2329 struct atl1_buffer *buffer_info; 2330 struct tx_packet_desc *tpd; 2331 u16 j; 2332 u32 val; 2333 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use); 2334 2335 for (j = 0; j < count; j++) { 2336 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2337 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use); 2338 if (tpd != ptpd) 2339 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc)); 2340 tpd->buffer_addr = cpu_to_le64(buffer_info->dma); 2341 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT); 2342 tpd->word2 |= (cpu_to_le16(buffer_info->length) & 2343 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT; 2344 2345 /* 2346 * if this is the first packet in a TSO chain, set 2347 * TPD_HDRFLAG, otherwise, clear it. 2348 */ 2349 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & 2350 TPD_SEGMENT_EN_MASK; 2351 if (val) { 2352 if (!j) 2353 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT; 2354 else 2355 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT); 2356 } 2357 2358 if (j == (count - 1)) 2359 tpd->word3 |= 1 << TPD_EOP_SHIFT; 2360 2361 if (++next_to_use == tpd_ring->count) 2362 next_to_use = 0; 2363 } 2364 /* 2365 * Force memory writes to complete before letting h/w 2366 * know there are new descriptors to fetch. (Only 2367 * applicable for weak-ordered memory model archs, 2368 * such as IA-64). 2369 */ 2370 wmb(); 2371 2372 atomic_set(&tpd_ring->next_to_use, next_to_use); 2373} 2374 2375static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb, 2376 struct net_device *netdev) 2377{ 2378 struct atl1_adapter *adapter = netdev_priv(netdev); 2379 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2380 int len; 2381 int tso; 2382 int count = 1; 2383 int ret_val; 2384 struct tx_packet_desc *ptpd; 2385 u16 vlan_tag; 2386 unsigned int nr_frags = 0; 2387 unsigned int mss = 0; 2388 unsigned int f; 2389 unsigned int proto_hdr_len; 2390 2391 len = skb_headlen(skb); 2392 2393 if (unlikely(skb->len <= 0)) 2394 goto drop_packet; 2395 2396 nr_frags = skb_shinfo(skb)->nr_frags; 2397 for (f = 0; f < nr_frags; f++) { 2398 unsigned int f_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); 2399 count += (f_size + ATL1_MAX_TX_BUF_LEN - 1) / 2400 ATL1_MAX_TX_BUF_LEN; 2401 } 2402 2403 mss = skb_shinfo(skb)->gso_size; 2404 if (mss) { 2405 if (skb->protocol == htons(ETH_P_IP)) { 2406 proto_hdr_len = skb_tcp_all_headers(skb); 2407 if (unlikely(proto_hdr_len > len)) 2408 goto drop_packet; 2409 2410 /* need additional TPD ? */ 2411 if (proto_hdr_len != len) 2412 count += (len - proto_hdr_len + 2413 ATL1_MAX_TX_BUF_LEN - 1) / 2414 ATL1_MAX_TX_BUF_LEN; 2415 } 2416 } 2417 2418 if (atl1_tpd_avail(&adapter->tpd_ring) < count) { 2419 /* not enough descriptors */ 2420 netif_stop_queue(netdev); 2421 if (netif_msg_tx_queued(adapter)) 2422 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2423 "tx busy\n"); 2424 return NETDEV_TX_BUSY; 2425 } 2426 2427 ptpd = ATL1_TPD_DESC(tpd_ring, 2428 (u16) atomic_read(&tpd_ring->next_to_use)); 2429 memset(ptpd, 0, sizeof(struct tx_packet_desc)); 2430 2431 if (skb_vlan_tag_present(skb)) { 2432 vlan_tag = skb_vlan_tag_get(skb); 2433 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) | 2434 ((vlan_tag >> 9) & 0x8); 2435 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT; 2436 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) << 2437 TPD_VLANTAG_SHIFT; 2438 } 2439 2440 tso = atl1_tso(adapter, skb, ptpd); 2441 if (tso < 0) 2442 goto drop_packet; 2443 2444 if (!tso) { 2445 ret_val = atl1_tx_csum(adapter, skb, ptpd); 2446 if (ret_val < 0) 2447 goto drop_packet; 2448 } 2449 2450 if (!atl1_tx_map(adapter, skb, ptpd)) 2451 goto drop_packet; 2452 2453 atl1_tx_queue(adapter, count, ptpd); 2454 atl1_update_mailbox(adapter); 2455 return NETDEV_TX_OK; 2456 2457drop_packet: 2458 adapter->soft_stats.tx_errors++; 2459 dev_kfree_skb_any(skb); 2460 return NETDEV_TX_OK; 2461} 2462 2463static int atl1_rings_clean(struct napi_struct *napi, int budget) 2464{ 2465 struct atl1_adapter *adapter = container_of(napi, struct atl1_adapter, napi); 2466 int work_done = atl1_intr_rx(adapter, budget); 2467 2468 if (atl1_intr_tx(adapter)) 2469 work_done = budget; 2470 2471 /* Let's come again to process some more packets */ 2472 if (work_done >= budget) 2473 return work_done; 2474 2475 napi_complete_done(napi, work_done); 2476 /* re-enable Interrupt */ 2477 if (likely(adapter->int_enabled)) 2478 atlx_imr_set(adapter, IMR_NORMAL_MASK); 2479 return work_done; 2480} 2481 2482static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter) 2483{ 2484 if (!napi_schedule(&adapter->napi)) 2485 /* It is possible in case even the RX/TX ints are disabled via IMR 2486 * register the ISR bits are set anyway (but do not produce IRQ). 2487 * To handle such situation the napi functions used to check is 2488 * something scheduled or not. 2489 */ 2490 return 0; 2491 2492 /* 2493 * Disable RX/TX ints via IMR register if it is 2494 * allowed. NAPI handler must reenable them in same 2495 * way. 2496 */ 2497 if (!adapter->int_enabled) 2498 return 1; 2499 2500 atlx_imr_set(adapter, IMR_NORXTX_MASK); 2501 return 1; 2502} 2503 2504/** 2505 * atl1_intr - Interrupt Handler 2506 * @irq: interrupt number 2507 * @data: pointer to a network interface device structure 2508 */ 2509static irqreturn_t atl1_intr(int irq, void *data) 2510{ 2511 struct atl1_adapter *adapter = netdev_priv(data); 2512 u32 status; 2513 2514 status = adapter->cmb.cmb->int_stats; 2515 if (!status) 2516 return IRQ_NONE; 2517 2518 /* clear CMB interrupt status at once, 2519 * but leave rx/tx interrupt status in case it should be dropped 2520 * only if rx/tx processing queued. In other case interrupt 2521 * can be lost. 2522 */ 2523 adapter->cmb.cmb->int_stats = status & (ISR_CMB_TX | ISR_CMB_RX); 2524 2525 if (status & ISR_GPHY) /* clear phy status */ 2526 atlx_clear_phy_int(adapter); 2527 2528 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 2529 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); 2530 2531 /* check if SMB intr */ 2532 if (status & ISR_SMB) 2533 atl1_inc_smb(adapter); 2534 2535 /* check if PCIE PHY Link down */ 2536 if (status & ISR_PHY_LINKDOWN) { 2537 if (netif_msg_intr(adapter)) 2538 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2539 "pcie phy link down %x\n", status); 2540 if (netif_running(adapter->netdev)) { /* reset MAC */ 2541 atlx_irq_disable(adapter); 2542 schedule_work(&adapter->reset_dev_task); 2543 return IRQ_HANDLED; 2544 } 2545 } 2546 2547 /* check if DMA read/write error ? */ 2548 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 2549 if (netif_msg_intr(adapter)) 2550 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2551 "pcie DMA r/w error (status = 0x%x)\n", 2552 status); 2553 atlx_irq_disable(adapter); 2554 schedule_work(&adapter->reset_dev_task); 2555 return IRQ_HANDLED; 2556 } 2557 2558 /* link event */ 2559 if (status & ISR_GPHY) { 2560 adapter->soft_stats.tx_carrier_errors++; 2561 atl1_check_for_link(adapter); 2562 } 2563 2564 /* transmit or receive event */ 2565 if (status & (ISR_CMB_TX | ISR_CMB_RX) && 2566 atl1_sched_rings_clean(adapter)) 2567 adapter->cmb.cmb->int_stats = adapter->cmb.cmb->int_stats & 2568 ~(ISR_CMB_TX | ISR_CMB_RX); 2569 2570 /* rx exception */ 2571 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN | 2572 ISR_RRD_OV | ISR_HOST_RFD_UNRUN | 2573 ISR_HOST_RRD_OV))) { 2574 if (netif_msg_intr(adapter)) 2575 dev_printk(KERN_DEBUG, 2576 &adapter->pdev->dev, 2577 "rx exception, ISR = 0x%x\n", 2578 status); 2579 atl1_sched_rings_clean(adapter); 2580 } 2581 2582 /* re-enable Interrupt */ 2583 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR); 2584 return IRQ_HANDLED; 2585} 2586 2587 2588/** 2589 * atl1_phy_config - Timer Call-back 2590 * @t: timer_list containing pointer to netdev cast into an unsigned long 2591 */ 2592static void atl1_phy_config(struct timer_list *t) 2593{ 2594 struct atl1_adapter *adapter = timer_container_of(adapter, t, 2595 phy_config_timer); 2596 struct atl1_hw *hw = &adapter->hw; 2597 unsigned long flags; 2598 2599 spin_lock_irqsave(&adapter->lock, flags); 2600 adapter->phy_timer_pending = false; 2601 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 2602 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg); 2603 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN); 2604 spin_unlock_irqrestore(&adapter->lock, flags); 2605} 2606 2607/* 2608 * Orphaned vendor comment left intact here: 2609 * <vendor comment> 2610 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT 2611 * will assert. We do soft reset <0x1400=1> according 2612 * with the SPEC. BUT, it seemes that PCIE or DMA 2613 * state-machine will not be reset. DMAR_TO_INT will 2614 * assert again and again. 2615 * </vendor comment> 2616 */ 2617 2618static int atl1_reset(struct atl1_adapter *adapter) 2619{ 2620 int ret; 2621 ret = atl1_reset_hw(&adapter->hw); 2622 if (ret) 2623 return ret; 2624 return atl1_init_hw(&adapter->hw); 2625} 2626 2627static s32 atl1_up(struct atl1_adapter *adapter) 2628{ 2629 struct net_device *netdev = adapter->netdev; 2630 int err; 2631 int irq_flags = 0; 2632 2633 /* hardware has been reset, we need to reload some things */ 2634 atlx_set_multi(netdev); 2635 atl1_init_ring_ptrs(adapter); 2636 atlx_restore_vlan(adapter); 2637 err = atl1_alloc_rx_buffers(adapter); 2638 if (unlikely(!err)) 2639 /* no RX BUFFER allocated */ 2640 return -ENOMEM; 2641 2642 if (unlikely(atl1_configure(adapter))) { 2643 err = -EIO; 2644 goto err_up; 2645 } 2646 2647 err = pci_enable_msi(adapter->pdev); 2648 if (err) { 2649 if (netif_msg_ifup(adapter)) 2650 dev_info(&adapter->pdev->dev, 2651 "Unable to enable MSI: %d\n", err); 2652 irq_flags |= IRQF_SHARED; 2653 } 2654 2655 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags, 2656 netdev->name, netdev); 2657 if (unlikely(err)) 2658 goto err_up; 2659 2660 napi_enable(&adapter->napi); 2661 atlx_irq_enable(adapter); 2662 atl1_check_link(adapter); 2663 netif_start_queue(netdev); 2664 return 0; 2665 2666err_up: 2667 pci_disable_msi(adapter->pdev); 2668 /* free rx_buffers */ 2669 atl1_clean_rx_ring(adapter); 2670 return err; 2671} 2672 2673static void atl1_down(struct atl1_adapter *adapter) 2674{ 2675 struct net_device *netdev = adapter->netdev; 2676 2677 napi_disable(&adapter->napi); 2678 netif_stop_queue(netdev); 2679 timer_delete_sync(&adapter->phy_config_timer); 2680 adapter->phy_timer_pending = false; 2681 2682 atlx_irq_disable(adapter); 2683 free_irq(adapter->pdev->irq, netdev); 2684 pci_disable_msi(adapter->pdev); 2685 atl1_reset_hw(&adapter->hw); 2686 adapter->cmb.cmb->int_stats = 0; 2687 2688 adapter->link_speed = SPEED_0; 2689 adapter->link_duplex = -1; 2690 netif_carrier_off(netdev); 2691 2692 atl1_clean_tx_ring(adapter); 2693 atl1_clean_rx_ring(adapter); 2694} 2695 2696static void atl1_reset_dev_task(struct work_struct *work) 2697{ 2698 struct atl1_adapter *adapter = 2699 container_of(work, struct atl1_adapter, reset_dev_task); 2700 struct net_device *netdev = adapter->netdev; 2701 2702 netif_device_detach(netdev); 2703 atl1_down(adapter); 2704 atl1_up(adapter); 2705 netif_device_attach(netdev); 2706} 2707 2708/** 2709 * atl1_change_mtu - Change the Maximum Transfer Unit 2710 * @netdev: network interface device structure 2711 * @new_mtu: new value for maximum frame size 2712 * 2713 * Returns 0 on success, negative on failure 2714 */ 2715static int atl1_change_mtu(struct net_device *netdev, int new_mtu) 2716{ 2717 struct atl1_adapter *adapter = netdev_priv(netdev); 2718 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 2719 2720 adapter->hw.max_frame_size = max_frame; 2721 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3; 2722 adapter->rx_buffer_len = (max_frame + 7) & ~7; 2723 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8; 2724 2725 WRITE_ONCE(netdev->mtu, new_mtu); 2726 if (netif_running(netdev)) { 2727 atl1_down(adapter); 2728 atl1_up(adapter); 2729 } 2730 2731 return 0; 2732} 2733 2734/** 2735 * atl1_open - Called when a network interface is made active 2736 * @netdev: network interface device structure 2737 * 2738 * Returns 0 on success, negative value on failure 2739 * 2740 * The open entry point is called when a network interface is made 2741 * active by the system (IFF_UP). At this point all resources needed 2742 * for transmit and receive operations are allocated, the interrupt 2743 * handler is registered with the OS, the watchdog timer is started, 2744 * and the stack is notified that the interface is ready. 2745 */ 2746static int atl1_open(struct net_device *netdev) 2747{ 2748 struct atl1_adapter *adapter = netdev_priv(netdev); 2749 int err; 2750 2751 netif_carrier_off(netdev); 2752 2753 /* allocate transmit descriptors */ 2754 err = atl1_setup_ring_resources(adapter); 2755 if (err) 2756 return err; 2757 2758 err = atl1_up(adapter); 2759 if (err) 2760 goto err_up; 2761 2762 return 0; 2763 2764err_up: 2765 atl1_reset(adapter); 2766 return err; 2767} 2768 2769/** 2770 * atl1_close - Disables a network interface 2771 * @netdev: network interface device structure 2772 * 2773 * Returns 0, this is not allowed to fail 2774 * 2775 * The close entry point is called when an interface is de-activated 2776 * by the OS. The hardware is still under the drivers control, but 2777 * needs to be disabled. A global MAC reset is issued to stop the 2778 * hardware, and all transmit and receive resources are freed. 2779 */ 2780static int atl1_close(struct net_device *netdev) 2781{ 2782 struct atl1_adapter *adapter = netdev_priv(netdev); 2783 atl1_down(adapter); 2784 atl1_free_ring_resources(adapter); 2785 return 0; 2786} 2787 2788#ifdef CONFIG_PM_SLEEP 2789static int atl1_suspend(struct device *dev) 2790{ 2791 struct net_device *netdev = dev_get_drvdata(dev); 2792 struct atl1_adapter *adapter = netdev_priv(netdev); 2793 struct atl1_hw *hw = &adapter->hw; 2794 u32 ctrl = 0; 2795 u32 wufc = adapter->wol; 2796 u32 val; 2797 u16 speed; 2798 u16 duplex; 2799 2800 netif_device_detach(netdev); 2801 if (netif_running(netdev)) 2802 atl1_down(adapter); 2803 2804 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 2805 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 2806 val = ctrl & BMSR_LSTATUS; 2807 if (val) 2808 wufc &= ~ATLX_WUFC_LNKC; 2809 if (!wufc) 2810 goto disable_wol; 2811 2812 if (val) { 2813 val = atl1_get_speed_and_duplex(hw, &speed, &duplex); 2814 if (val) { 2815 if (netif_msg_ifdown(adapter)) 2816 dev_printk(KERN_DEBUG, dev, 2817 "error getting speed/duplex\n"); 2818 goto disable_wol; 2819 } 2820 2821 ctrl = 0; 2822 2823 /* enable magic packet WOL */ 2824 if (wufc & ATLX_WUFC_MAG) 2825 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 2826 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 2827 ioread32(hw->hw_addr + REG_WOL_CTRL); 2828 2829 /* configure the mac */ 2830 ctrl = MAC_CTRL_RX_EN; 2831 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 : 2832 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT); 2833 if (duplex == FULL_DUPLEX) 2834 ctrl |= MAC_CTRL_DUPLX; 2835 ctrl |= (((u32)adapter->hw.preamble_len & 2836 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 2837 __atlx_vlan_mode(netdev->features, &ctrl); 2838 if (wufc & ATLX_WUFC_MAG) 2839 ctrl |= MAC_CTRL_BC_EN; 2840 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL); 2841 ioread32(hw->hw_addr + REG_MAC_CTRL); 2842 2843 /* poke the PHY */ 2844 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2845 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 2846 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); 2847 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2848 } else { 2849 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 2850 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 2851 ioread32(hw->hw_addr + REG_WOL_CTRL); 2852 iowrite32(0, hw->hw_addr + REG_MAC_CTRL); 2853 ioread32(hw->hw_addr + REG_MAC_CTRL); 2854 hw->phy_configured = false; 2855 } 2856 2857 return 0; 2858 2859 disable_wol: 2860 iowrite32(0, hw->hw_addr + REG_WOL_CTRL); 2861 ioread32(hw->hw_addr + REG_WOL_CTRL); 2862 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2863 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 2864 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); 2865 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2866 hw->phy_configured = false; 2867 2868 return 0; 2869} 2870 2871static int atl1_resume(struct device *dev) 2872{ 2873 struct net_device *netdev = dev_get_drvdata(dev); 2874 struct atl1_adapter *adapter = netdev_priv(netdev); 2875 2876 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL); 2877 2878 atl1_reset_hw(&adapter->hw); 2879 2880 if (netif_running(netdev)) { 2881 adapter->cmb.cmb->int_stats = 0; 2882 atl1_up(adapter); 2883 } 2884 netif_device_attach(netdev); 2885 2886 return 0; 2887} 2888#endif 2889 2890static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume); 2891 2892static void atl1_shutdown(struct pci_dev *pdev) 2893{ 2894 struct net_device *netdev = pci_get_drvdata(pdev); 2895 struct atl1_adapter *adapter = netdev_priv(netdev); 2896 2897#ifdef CONFIG_PM_SLEEP 2898 atl1_suspend(&pdev->dev); 2899#endif 2900 pci_wake_from_d3(pdev, adapter->wol); 2901 pci_set_power_state(pdev, PCI_D3hot); 2902} 2903 2904#ifdef CONFIG_NET_POLL_CONTROLLER 2905static void atl1_poll_controller(struct net_device *netdev) 2906{ 2907 disable_irq(netdev->irq); 2908 atl1_intr(netdev->irq, netdev); 2909 enable_irq(netdev->irq); 2910} 2911#endif 2912 2913static const struct net_device_ops atl1_netdev_ops = { 2914 .ndo_open = atl1_open, 2915 .ndo_stop = atl1_close, 2916 .ndo_start_xmit = atl1_xmit_frame, 2917 .ndo_set_rx_mode = atlx_set_multi, 2918 .ndo_validate_addr = eth_validate_addr, 2919 .ndo_set_mac_address = atl1_set_mac, 2920 .ndo_change_mtu = atl1_change_mtu, 2921 .ndo_fix_features = atlx_fix_features, 2922 .ndo_set_features = atlx_set_features, 2923 .ndo_eth_ioctl = atlx_ioctl, 2924 .ndo_tx_timeout = atlx_tx_timeout, 2925#ifdef CONFIG_NET_POLL_CONTROLLER 2926 .ndo_poll_controller = atl1_poll_controller, 2927#endif 2928}; 2929 2930/** 2931 * atl1_probe - Device Initialization Routine 2932 * @pdev: PCI device information struct 2933 * @ent: entry in atl1_pci_tbl 2934 * 2935 * Returns 0 on success, negative on failure 2936 * 2937 * atl1_probe initializes an adapter identified by a pci_dev structure. 2938 * The OS initialization, configuring of the adapter private structure, 2939 * and a hardware reset occur. 2940 */ 2941static int atl1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2942{ 2943 struct net_device *netdev; 2944 struct atl1_adapter *adapter; 2945 static int cards_found = 0; 2946 int err; 2947 2948 err = pci_enable_device(pdev); 2949 if (err) 2950 return err; 2951 2952 /* 2953 * The atl1 chip can DMA to 64-bit addresses, but it uses a single 2954 * shared register for the high 32 bits, so only a single, aligned, 2955 * 4 GB physical address range can be used at a time. 2956 * 2957 * Supporting 64-bit DMA on this hardware is more trouble than it's 2958 * worth. It is far easier to limit to 32-bit DMA than update 2959 * various kernel subsystems to support the mechanics required by a 2960 * fixed-high-32-bit system. 2961 */ 2962 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 2963 if (err) { 2964 dev_err(&pdev->dev, "no usable DMA configuration\n"); 2965 goto err_dma; 2966 } 2967 /* 2968 * Mark all PCI regions associated with PCI device 2969 * pdev as being reserved by owner atl1_driver_name 2970 */ 2971 err = pci_request_regions(pdev, ATLX_DRIVER_NAME); 2972 if (err) 2973 goto err_request_regions; 2974 2975 /* 2976 * Enables bus-mastering on the device and calls 2977 * pcibios_set_master to do the needed arch specific settings 2978 */ 2979 pci_set_master(pdev); 2980 2981 netdev = alloc_etherdev(sizeof(struct atl1_adapter)); 2982 if (!netdev) { 2983 err = -ENOMEM; 2984 goto err_alloc_etherdev; 2985 } 2986 SET_NETDEV_DEV(netdev, &pdev->dev); 2987 2988 pci_set_drvdata(pdev, netdev); 2989 adapter = netdev_priv(netdev); 2990 adapter->netdev = netdev; 2991 adapter->pdev = pdev; 2992 adapter->hw.back = adapter; 2993 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg); 2994 2995 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0); 2996 if (!adapter->hw.hw_addr) { 2997 err = -EIO; 2998 goto err_pci_iomap; 2999 } 3000 /* get device revision number */ 3001 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + 3002 (REG_MASTER_CTRL + 2)); 3003 3004 /* set default ring resource counts */ 3005 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD; 3006 adapter->tpd_ring.count = ATL1_DEFAULT_TPD; 3007 3008 adapter->mii.dev = netdev; 3009 adapter->mii.mdio_read = mdio_read; 3010 adapter->mii.mdio_write = mdio_write; 3011 adapter->mii.phy_id_mask = 0x1f; 3012 adapter->mii.reg_num_mask = 0x1f; 3013 3014 netdev->netdev_ops = &atl1_netdev_ops; 3015 netdev->watchdog_timeo = 5 * HZ; 3016 netif_napi_add(netdev, &adapter->napi, atl1_rings_clean); 3017 3018 netdev->ethtool_ops = &atl1_ethtool_ops; 3019 adapter->bd_number = cards_found; 3020 3021 /* setup the private structure */ 3022 err = atl1_sw_init(adapter); 3023 if (err) 3024 goto err_common; 3025 3026 netdev->features = NETIF_F_HW_CSUM; 3027 netdev->features |= NETIF_F_SG; 3028 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3029 3030 netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO | 3031 NETIF_F_HW_VLAN_CTAG_RX; 3032 3033 /* is this valid? see atl1_setup_mac_ctrl() */ 3034 netdev->features |= NETIF_F_RXCSUM; 3035 3036 /* MTU range: 42 - 10218 */ 3037 netdev->min_mtu = ETH_ZLEN - (ETH_HLEN + VLAN_HLEN); 3038 netdev->max_mtu = MAX_JUMBO_FRAME_SIZE - 3039 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 3040 3041 /* 3042 * patch for some L1 of old version, 3043 * the final version of L1 may not need these 3044 * patches 3045 */ 3046 /* atl1_pcie_patch(adapter); */ 3047 3048 /* really reset GPHY core */ 3049 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); 3050 3051 /* 3052 * reset the controller to 3053 * put the device in a known good starting state 3054 */ 3055 if (atl1_reset_hw(&adapter->hw)) { 3056 err = -EIO; 3057 goto err_common; 3058 } 3059 3060 /* copy the MAC address out of the EEPROM */ 3061 if (atl1_read_mac_addr(&adapter->hw)) { 3062 /* mark random mac */ 3063 netdev->addr_assign_type = NET_ADDR_RANDOM; 3064 } 3065 eth_hw_addr_set(netdev, adapter->hw.mac_addr); 3066 3067 if (!is_valid_ether_addr(netdev->dev_addr)) { 3068 err = -EIO; 3069 goto err_common; 3070 } 3071 3072 atl1_check_options(adapter); 3073 3074 /* pre-init the MAC, and setup link */ 3075 err = atl1_init_hw(&adapter->hw); 3076 if (err) { 3077 err = -EIO; 3078 goto err_common; 3079 } 3080 3081 atl1_pcie_patch(adapter); 3082 /* assume we have no link for now */ 3083 netif_carrier_off(netdev); 3084 3085 timer_setup(&adapter->phy_config_timer, atl1_phy_config, 0); 3086 adapter->phy_timer_pending = false; 3087 3088 INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task); 3089 3090 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task); 3091 3092 err = register_netdev(netdev); 3093 if (err) 3094 goto err_common; 3095 3096 cards_found++; 3097 atl1_via_workaround(adapter); 3098 return 0; 3099 3100err_common: 3101 pci_iounmap(pdev, adapter->hw.hw_addr); 3102err_pci_iomap: 3103 free_netdev(netdev); 3104err_alloc_etherdev: 3105 pci_release_regions(pdev); 3106err_dma: 3107err_request_regions: 3108 pci_disable_device(pdev); 3109 return err; 3110} 3111 3112/** 3113 * atl1_remove - Device Removal Routine 3114 * @pdev: PCI device information struct 3115 * 3116 * atl1_remove is called by the PCI subsystem to alert the driver 3117 * that it should release a PCI device. The could be caused by a 3118 * Hot-Plug event, or because the driver is going to be removed from 3119 * memory. 3120 */ 3121static void atl1_remove(struct pci_dev *pdev) 3122{ 3123 struct net_device *netdev = pci_get_drvdata(pdev); 3124 struct atl1_adapter *adapter; 3125 /* Device not available. Return. */ 3126 if (!netdev) 3127 return; 3128 3129 adapter = netdev_priv(netdev); 3130 3131 /* 3132 * Some atl1 boards lack persistent storage for their MAC, and get it 3133 * from the BIOS during POST. If we've been messing with the MAC 3134 * address, we need to save the permanent one. 3135 */ 3136 if (!ether_addr_equal_unaligned(adapter->hw.mac_addr, 3137 adapter->hw.perm_mac_addr)) { 3138 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, 3139 ETH_ALEN); 3140 atl1_set_mac_addr(&adapter->hw); 3141 } 3142 3143 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); 3144 unregister_netdev(netdev); 3145 pci_iounmap(pdev, adapter->hw.hw_addr); 3146 pci_release_regions(pdev); 3147 free_netdev(netdev); 3148 pci_disable_device(pdev); 3149} 3150 3151static struct pci_driver atl1_driver = { 3152 .name = ATLX_DRIVER_NAME, 3153 .id_table = atl1_pci_tbl, 3154 .probe = atl1_probe, 3155 .remove = atl1_remove, 3156 .shutdown = atl1_shutdown, 3157 .driver.pm = &atl1_pm_ops, 3158}; 3159 3160struct atl1_stats { 3161 char stat_string[ETH_GSTRING_LEN]; 3162 int sizeof_stat; 3163 int stat_offset; 3164}; 3165 3166#define ATL1_STAT(m) \ 3167 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m) 3168 3169static struct atl1_stats atl1_gstrings_stats[] = { 3170 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)}, 3171 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)}, 3172 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)}, 3173 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)}, 3174 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)}, 3175 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)}, 3176 {"multicast", ATL1_STAT(soft_stats.multicast)}, 3177 {"collisions", ATL1_STAT(soft_stats.collisions)}, 3178 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)}, 3179 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, 3180 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)}, 3181 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)}, 3182 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)}, 3183 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, 3184 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)}, 3185 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)}, 3186 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)}, 3187 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)}, 3188 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)}, 3189 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)}, 3190 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)}, 3191 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)}, 3192 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)}, 3193 {"tx_underrun", ATL1_STAT(soft_stats.tx_underrun)}, 3194 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)}, 3195 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)}, 3196 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)}, 3197 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)}, 3198 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)} 3199}; 3200 3201static void atl1_get_ethtool_stats(struct net_device *netdev, 3202 struct ethtool_stats *stats, u64 *data) 3203{ 3204 struct atl1_adapter *adapter = netdev_priv(netdev); 3205 int i; 3206 char *p; 3207 3208 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { 3209 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset; 3210 data[i] = (atl1_gstrings_stats[i].sizeof_stat == 3211 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 3212 } 3213 3214} 3215 3216static int atl1_get_sset_count(struct net_device *netdev, int sset) 3217{ 3218 switch (sset) { 3219 case ETH_SS_STATS: 3220 return ARRAY_SIZE(atl1_gstrings_stats); 3221 default: 3222 return -EOPNOTSUPP; 3223 } 3224} 3225 3226static int atl1_get_link_ksettings(struct net_device *netdev, 3227 struct ethtool_link_ksettings *cmd) 3228{ 3229 struct atl1_adapter *adapter = netdev_priv(netdev); 3230 struct atl1_hw *hw = &adapter->hw; 3231 u32 supported, advertising; 3232 3233 supported = (SUPPORTED_10baseT_Half | 3234 SUPPORTED_10baseT_Full | 3235 SUPPORTED_100baseT_Half | 3236 SUPPORTED_100baseT_Full | 3237 SUPPORTED_1000baseT_Full | 3238 SUPPORTED_Autoneg | SUPPORTED_TP); 3239 advertising = ADVERTISED_TP; 3240 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3241 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3242 advertising |= ADVERTISED_Autoneg; 3243 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) { 3244 advertising |= ADVERTISED_Autoneg; 3245 advertising |= 3246 (ADVERTISED_10baseT_Half | 3247 ADVERTISED_10baseT_Full | 3248 ADVERTISED_100baseT_Half | 3249 ADVERTISED_100baseT_Full | 3250 ADVERTISED_1000baseT_Full); 3251 } else 3252 advertising |= (ADVERTISED_1000baseT_Full); 3253 } 3254 cmd->base.port = PORT_TP; 3255 cmd->base.phy_address = 0; 3256 3257 if (netif_carrier_ok(adapter->netdev)) { 3258 u16 link_speed, link_duplex; 3259 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex); 3260 cmd->base.speed = link_speed; 3261 if (link_duplex == FULL_DUPLEX) 3262 cmd->base.duplex = DUPLEX_FULL; 3263 else 3264 cmd->base.duplex = DUPLEX_HALF; 3265 } else { 3266 cmd->base.speed = SPEED_UNKNOWN; 3267 cmd->base.duplex = DUPLEX_UNKNOWN; 3268 } 3269 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3270 hw->media_type == MEDIA_TYPE_1000M_FULL) 3271 cmd->base.autoneg = AUTONEG_ENABLE; 3272 else 3273 cmd->base.autoneg = AUTONEG_DISABLE; 3274 3275 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3276 supported); 3277 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3278 advertising); 3279 3280 return 0; 3281} 3282 3283static int atl1_set_link_ksettings(struct net_device *netdev, 3284 const struct ethtool_link_ksettings *cmd) 3285{ 3286 struct atl1_adapter *adapter = netdev_priv(netdev); 3287 struct atl1_hw *hw = &adapter->hw; 3288 u16 phy_data; 3289 int ret_val = 0; 3290 u16 old_media_type = hw->media_type; 3291 3292 if (netif_running(adapter->netdev)) { 3293 if (netif_msg_link(adapter)) 3294 dev_dbg(&adapter->pdev->dev, 3295 "ethtool shutting down adapter\n"); 3296 atl1_down(adapter); 3297 } 3298 3299 if (cmd->base.autoneg == AUTONEG_ENABLE) 3300 hw->media_type = MEDIA_TYPE_AUTO_SENSOR; 3301 else { 3302 u32 speed = cmd->base.speed; 3303 if (speed == SPEED_1000) { 3304 if (cmd->base.duplex != DUPLEX_FULL) { 3305 if (netif_msg_link(adapter)) 3306 dev_warn(&adapter->pdev->dev, 3307 "1000M half is invalid\n"); 3308 ret_val = -EINVAL; 3309 goto exit_sset; 3310 } 3311 hw->media_type = MEDIA_TYPE_1000M_FULL; 3312 } else if (speed == SPEED_100) { 3313 if (cmd->base.duplex == DUPLEX_FULL) 3314 hw->media_type = MEDIA_TYPE_100M_FULL; 3315 else 3316 hw->media_type = MEDIA_TYPE_100M_HALF; 3317 } else { 3318 if (cmd->base.duplex == DUPLEX_FULL) 3319 hw->media_type = MEDIA_TYPE_10M_FULL; 3320 else 3321 hw->media_type = MEDIA_TYPE_10M_HALF; 3322 } 3323 } 3324 3325 if (atl1_phy_setup_autoneg_adv(hw)) { 3326 ret_val = -EINVAL; 3327 if (netif_msg_link(adapter)) 3328 dev_warn(&adapter->pdev->dev, 3329 "invalid ethtool speed/duplex setting\n"); 3330 goto exit_sset; 3331 } 3332 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3333 hw->media_type == MEDIA_TYPE_1000M_FULL) 3334 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 3335 else { 3336 switch (hw->media_type) { 3337 case MEDIA_TYPE_100M_FULL: 3338 phy_data = 3339 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 3340 MII_CR_RESET; 3341 break; 3342 case MEDIA_TYPE_100M_HALF: 3343 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 3344 break; 3345 case MEDIA_TYPE_10M_FULL: 3346 phy_data = 3347 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 3348 break; 3349 default: 3350 /* MEDIA_TYPE_10M_HALF: */ 3351 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 3352 break; 3353 } 3354 } 3355 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 3356exit_sset: 3357 if (ret_val) 3358 hw->media_type = old_media_type; 3359 3360 if (netif_running(adapter->netdev)) { 3361 if (netif_msg_link(adapter)) 3362 dev_dbg(&adapter->pdev->dev, 3363 "ethtool starting adapter\n"); 3364 atl1_up(adapter); 3365 } else if (!ret_val) { 3366 if (netif_msg_link(adapter)) 3367 dev_dbg(&adapter->pdev->dev, 3368 "ethtool resetting adapter\n"); 3369 atl1_reset(adapter); 3370 } 3371 return ret_val; 3372} 3373 3374static void atl1_get_drvinfo(struct net_device *netdev, 3375 struct ethtool_drvinfo *drvinfo) 3376{ 3377 struct atl1_adapter *adapter = netdev_priv(netdev); 3378 3379 strscpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver)); 3380 strscpy(drvinfo->bus_info, pci_name(adapter->pdev), 3381 sizeof(drvinfo->bus_info)); 3382} 3383 3384static void atl1_get_wol(struct net_device *netdev, 3385 struct ethtool_wolinfo *wol) 3386{ 3387 struct atl1_adapter *adapter = netdev_priv(netdev); 3388 3389 wol->supported = WAKE_MAGIC; 3390 wol->wolopts = 0; 3391 if (adapter->wol & ATLX_WUFC_MAG) 3392 wol->wolopts |= WAKE_MAGIC; 3393} 3394 3395static int atl1_set_wol(struct net_device *netdev, 3396 struct ethtool_wolinfo *wol) 3397{ 3398 struct atl1_adapter *adapter = netdev_priv(netdev); 3399 3400 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | 3401 WAKE_ARP | WAKE_MAGICSECURE)) 3402 return -EOPNOTSUPP; 3403 adapter->wol = 0; 3404 if (wol->wolopts & WAKE_MAGIC) 3405 adapter->wol |= ATLX_WUFC_MAG; 3406 3407 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 3408 3409 return 0; 3410} 3411 3412static u32 atl1_get_msglevel(struct net_device *netdev) 3413{ 3414 struct atl1_adapter *adapter = netdev_priv(netdev); 3415 return adapter->msg_enable; 3416} 3417 3418static void atl1_set_msglevel(struct net_device *netdev, u32 value) 3419{ 3420 struct atl1_adapter *adapter = netdev_priv(netdev); 3421 adapter->msg_enable = value; 3422} 3423 3424static int atl1_get_regs_len(struct net_device *netdev) 3425{ 3426 return ATL1_REG_COUNT * sizeof(u32); 3427} 3428 3429static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 3430 void *p) 3431{ 3432 struct atl1_adapter *adapter = netdev_priv(netdev); 3433 struct atl1_hw *hw = &adapter->hw; 3434 unsigned int i; 3435 u32 *regbuf = p; 3436 3437 for (i = 0; i < ATL1_REG_COUNT; i++) { 3438 /* 3439 * This switch statement avoids reserved regions 3440 * of register space. 3441 */ 3442 switch (i) { 3443 case 6 ... 9: 3444 case 14: 3445 case 29 ... 31: 3446 case 34 ... 63: 3447 case 75 ... 127: 3448 case 136 ... 1023: 3449 case 1027 ... 1087: 3450 case 1091 ... 1151: 3451 case 1194 ... 1195: 3452 case 1200 ... 1201: 3453 case 1206 ... 1213: 3454 case 1216 ... 1279: 3455 case 1290 ... 1311: 3456 case 1323 ... 1343: 3457 case 1358 ... 1359: 3458 case 1368 ... 1375: 3459 case 1378 ... 1383: 3460 case 1388 ... 1391: 3461 case 1393 ... 1395: 3462 case 1402 ... 1403: 3463 case 1410 ... 1471: 3464 case 1522 ... 1535: 3465 /* reserved region; don't read it */ 3466 regbuf[i] = 0; 3467 break; 3468 default: 3469 /* unreserved region */ 3470 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32))); 3471 } 3472 } 3473} 3474 3475static void atl1_get_ringparam(struct net_device *netdev, 3476 struct ethtool_ringparam *ring, 3477 struct kernel_ethtool_ringparam *kernel_ring, 3478 struct netlink_ext_ack *extack) 3479{ 3480 struct atl1_adapter *adapter = netdev_priv(netdev); 3481 struct atl1_tpd_ring *txdr = &adapter->tpd_ring; 3482 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring; 3483 3484 ring->rx_max_pending = ATL1_MAX_RFD; 3485 ring->tx_max_pending = ATL1_MAX_TPD; 3486 ring->rx_pending = rxdr->count; 3487 ring->tx_pending = txdr->count; 3488} 3489 3490static int atl1_set_ringparam(struct net_device *netdev, 3491 struct ethtool_ringparam *ring, 3492 struct kernel_ethtool_ringparam *kernel_ring, 3493 struct netlink_ext_ack *extack) 3494{ 3495 struct atl1_adapter *adapter = netdev_priv(netdev); 3496 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring; 3497 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring; 3498 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring; 3499 3500 struct atl1_tpd_ring tpd_old, tpd_new; 3501 struct atl1_rfd_ring rfd_old, rfd_new; 3502 struct atl1_rrd_ring rrd_old, rrd_new; 3503 struct atl1_ring_header rhdr_old, rhdr_new; 3504 struct atl1_smb smb; 3505 struct atl1_cmb cmb; 3506 int err; 3507 3508 tpd_old = adapter->tpd_ring; 3509 rfd_old = adapter->rfd_ring; 3510 rrd_old = adapter->rrd_ring; 3511 rhdr_old = adapter->ring_header; 3512 3513 if (netif_running(adapter->netdev)) 3514 atl1_down(adapter); 3515 3516 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD); 3517 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD : 3518 rfdr->count; 3519 rfdr->count = (rfdr->count + 3) & ~3; 3520 rrdr->count = rfdr->count; 3521 3522 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD); 3523 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD : 3524 tpdr->count; 3525 tpdr->count = (tpdr->count + 3) & ~3; 3526 3527 if (netif_running(adapter->netdev)) { 3528 /* try to get new resources before deleting old */ 3529 err = atl1_setup_ring_resources(adapter); 3530 if (err) 3531 goto err_setup_ring; 3532 3533 /* 3534 * save the new, restore the old in order to free it, 3535 * then restore the new back again 3536 */ 3537 3538 rfd_new = adapter->rfd_ring; 3539 rrd_new = adapter->rrd_ring; 3540 tpd_new = adapter->tpd_ring; 3541 rhdr_new = adapter->ring_header; 3542 adapter->rfd_ring = rfd_old; 3543 adapter->rrd_ring = rrd_old; 3544 adapter->tpd_ring = tpd_old; 3545 adapter->ring_header = rhdr_old; 3546 /* 3547 * Save SMB and CMB, since atl1_free_ring_resources 3548 * will clear them. 3549 */ 3550 smb = adapter->smb; 3551 cmb = adapter->cmb; 3552 atl1_free_ring_resources(adapter); 3553 adapter->rfd_ring = rfd_new; 3554 adapter->rrd_ring = rrd_new; 3555 adapter->tpd_ring = tpd_new; 3556 adapter->ring_header = rhdr_new; 3557 adapter->smb = smb; 3558 adapter->cmb = cmb; 3559 3560 err = atl1_up(adapter); 3561 if (err) 3562 return err; 3563 } 3564 return 0; 3565 3566err_setup_ring: 3567 adapter->rfd_ring = rfd_old; 3568 adapter->rrd_ring = rrd_old; 3569 adapter->tpd_ring = tpd_old; 3570 adapter->ring_header = rhdr_old; 3571 atl1_up(adapter); 3572 return err; 3573} 3574 3575static void atl1_get_pauseparam(struct net_device *netdev, 3576 struct ethtool_pauseparam *epause) 3577{ 3578 struct atl1_adapter *adapter = netdev_priv(netdev); 3579 struct atl1_hw *hw = &adapter->hw; 3580 3581 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3582 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3583 epause->autoneg = AUTONEG_ENABLE; 3584 } else { 3585 epause->autoneg = AUTONEG_DISABLE; 3586 } 3587 epause->rx_pause = 1; 3588 epause->tx_pause = 1; 3589} 3590 3591static int atl1_set_pauseparam(struct net_device *netdev, 3592 struct ethtool_pauseparam *epause) 3593{ 3594 struct atl1_adapter *adapter = netdev_priv(netdev); 3595 struct atl1_hw *hw = &adapter->hw; 3596 3597 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3598 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3599 epause->autoneg = AUTONEG_ENABLE; 3600 } else { 3601 epause->autoneg = AUTONEG_DISABLE; 3602 } 3603 3604 epause->rx_pause = 1; 3605 epause->tx_pause = 1; 3606 3607 return 0; 3608} 3609 3610static void atl1_get_strings(struct net_device *netdev, u32 stringset, 3611 u8 *data) 3612{ 3613 u8 *p = data; 3614 int i; 3615 3616 switch (stringset) { 3617 case ETH_SS_STATS: 3618 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { 3619 memcpy(p, atl1_gstrings_stats[i].stat_string, 3620 ETH_GSTRING_LEN); 3621 p += ETH_GSTRING_LEN; 3622 } 3623 break; 3624 } 3625} 3626 3627static int atl1_nway_reset(struct net_device *netdev) 3628{ 3629 struct atl1_adapter *adapter = netdev_priv(netdev); 3630 struct atl1_hw *hw = &adapter->hw; 3631 3632 if (netif_running(netdev)) { 3633 u16 phy_data; 3634 atl1_down(adapter); 3635 3636 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3637 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3638 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 3639 } else { 3640 switch (hw->media_type) { 3641 case MEDIA_TYPE_100M_FULL: 3642 phy_data = MII_CR_FULL_DUPLEX | 3643 MII_CR_SPEED_100 | MII_CR_RESET; 3644 break; 3645 case MEDIA_TYPE_100M_HALF: 3646 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 3647 break; 3648 case MEDIA_TYPE_10M_FULL: 3649 phy_data = MII_CR_FULL_DUPLEX | 3650 MII_CR_SPEED_10 | MII_CR_RESET; 3651 break; 3652 default: 3653 /* MEDIA_TYPE_10M_HALF */ 3654 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 3655 } 3656 } 3657 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 3658 atl1_up(adapter); 3659 } 3660 return 0; 3661} 3662 3663static const struct ethtool_ops atl1_ethtool_ops = { 3664 .get_drvinfo = atl1_get_drvinfo, 3665 .get_wol = atl1_get_wol, 3666 .set_wol = atl1_set_wol, 3667 .get_msglevel = atl1_get_msglevel, 3668 .set_msglevel = atl1_set_msglevel, 3669 .get_regs_len = atl1_get_regs_len, 3670 .get_regs = atl1_get_regs, 3671 .get_ringparam = atl1_get_ringparam, 3672 .set_ringparam = atl1_set_ringparam, 3673 .get_pauseparam = atl1_get_pauseparam, 3674 .set_pauseparam = atl1_set_pauseparam, 3675 .get_link = ethtool_op_get_link, 3676 .get_strings = atl1_get_strings, 3677 .nway_reset = atl1_nway_reset, 3678 .get_ethtool_stats = atl1_get_ethtool_stats, 3679 .get_sset_count = atl1_get_sset_count, 3680 .get_link_ksettings = atl1_get_link_ksettings, 3681 .set_link_ksettings = atl1_set_link_ksettings, 3682}; 3683 3684module_pci_driver(atl1_driver);
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