hw_atl_llh.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/* Atlantic Network Driver
   3 *
   4 * Copyright (C) 2014-2019 aQuantia Corporation
   5 * Copyright (C) 2019-2020 Marvell International Ltd.
   6 */
   7
   8/* File hw_atl_llh.c: Definitions of bitfield and register access functions for
   9 * Atlantic registers.
  10 */
  11
  12#include "hw_atl_llh.h"
  13#include "hw_atl_llh_internal.h"
  14#include "../aq_hw_utils.h"
  15
  16void hw_atl_ts_reset_set(struct aq_hw_s *aq_hw, u32 val)
  17{
  18	aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_RESET_ADR,
  19			    HW_ATL_TS_RESET_MSK,
  20			    HW_ATL_TS_RESET_SHIFT,
  21			    val);
  22}
  23
  24void hw_atl_ts_power_down_set(struct aq_hw_s *aq_hw, u32 val)
  25{
  26	aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR,
  27			    HW_ATL_TS_POWER_DOWN_MSK,
  28			    HW_ATL_TS_POWER_DOWN_SHIFT,
  29			    val);
  30}
  31
  32u32 hw_atl_ts_power_down_get(struct aq_hw_s *aq_hw)
  33{
  34	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR,
  35				  HW_ATL_TS_POWER_DOWN_MSK,
  36				  HW_ATL_TS_POWER_DOWN_SHIFT);
  37}
  38
  39u32 hw_atl_ts_ready_get(struct aq_hw_s *aq_hw)
  40{
  41	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_ADR,
  42				  HW_ATL_TS_READY_MSK,
  43				  HW_ATL_TS_READY_SHIFT);
  44}
  45
  46u32 hw_atl_ts_ready_latch_high_get(struct aq_hw_s *aq_hw)
  47{
  48	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_LATCH_HIGH_ADR,
  49				  HW_ATL_TS_READY_LATCH_HIGH_MSK,
  50				  HW_ATL_TS_READY_LATCH_HIGH_SHIFT);
  51}
  52
  53u32 hw_atl_ts_data_get(struct aq_hw_s *aq_hw)
  54{
  55	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_DATA_OUT_ADR,
  56				  HW_ATL_TS_DATA_OUT_MSK,
  57				  HW_ATL_TS_DATA_OUT_SHIFT);
  58}
  59
  60u32 hw_atl_smb0_bus_busy_get(struct aq_hw_s *aq_hw)
  61{
  62	return aq_hw_read_reg_bit(aq_hw, HW_ATL_SMB0_BUS_BUSY_ADR,
  63				HW_ATL_SMB0_BUS_BUSY_MSK,
  64				HW_ATL_SMB0_BUS_BUSY_SHIFT);
  65}
  66
  67u32 hw_atl_smb0_byte_transfer_complete_get(struct aq_hw_s *aq_hw)
  68{
  69	return aq_hw_read_reg_bit(aq_hw, HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_ADR,
  70				HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_MSK,
  71				HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_SHIFT);
  72}
  73
  74u32 hw_atl_smb0_receive_acknowledged_get(struct aq_hw_s *aq_hw)
  75{
  76	return aq_hw_read_reg_bit(aq_hw, HW_ATL_SMB0_RX_ACKNOWLEDGED_ADR,
  77				HW_ATL_SMB0_RX_ACKNOWLEDGED_MSK,
  78				HW_ATL_SMB0_RX_ACKNOWLEDGED_SHIFT);
  79}
  80
  81u32 hw_atl_smb0_repeated_start_detect_get(struct aq_hw_s *aq_hw)
  82{
  83	return aq_hw_read_reg_bit(aq_hw, HW_ATL_SMB0_REPEATED_START_DETECT_ADR,
  84				HW_ATL_SMB0_REPEATED_START_DETECT_MSK,
  85				HW_ATL_SMB0_REPEATED_START_DETECT_SHIFT);
  86}
  87
  88u32 hw_atl_smb0_rx_data_get(struct aq_hw_s *aq_hw)
  89{
  90	return aq_hw_read_reg(aq_hw, HW_ATL_SMB0_RECEIVED_DATA_ADR);
  91}
  92
  93void hw_atl_smb0_tx_data_set(struct aq_hw_s *aq_hw, u32 data)
  94{
  95	return aq_hw_write_reg(aq_hw, HW_ATL_SMB0_TRANSMITTED_DATA_ADR, data);
  96}
  97
  98void hw_atl_smb0_provisioning2_set(struct aq_hw_s *aq_hw, u32 data)
  99{
 100	return aq_hw_write_reg(aq_hw, HW_ATL_SMB0_PROVISIONING2_ADR, data);
 101}
 102
 103/* global */
 104void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
 105				u32 semaphore)
 106{
 107	aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
 108}
 109
 110u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
 111{
 112	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
 113}
 114
 115void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
 116{
 117	aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
 118			    HW_ATL_GLB_REG_RES_DIS_MSK,
 119			    HW_ATL_GLB_REG_RES_DIS_SHIFT,
 120			    glb_reg_res_dis);
 121}
 122
 123void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
 124{
 125	aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
 126			    HW_ATL_GLB_SOFT_RES_MSK,
 127			    HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
 128}
 129
 130u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
 131{
 132	return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
 133				  HW_ATL_GLB_SOFT_RES_MSK,
 134				  HW_ATL_GLB_SOFT_RES_SHIFT);
 135}
 136
 137u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
 138{
 139	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
 140}
 141
 142/* stats */
 143u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
 144{
 145	return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
 146}
 147
 148u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
 149{
 150	return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
 151}
 152
 153u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
 154{
 155	return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
 156}
 157
 158u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
 159{
 160	return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
 161}
 162
 163u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
 164{
 165	return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
 166}
 167
 168/* interrupt */
 169void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
 170				     u32 irq_auto_masklsw)
 171{
 172	aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
 173}
 174
 175void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
 176				  u32 rx)
 177{
 178/* register address for bitfield imr_rx{r}_en */
 179	static u32 itr_imr_rxren_adr[32] = {
 180			0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 181			0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 182			0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 183			0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 184			0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 185			0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 186			0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 187			0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 188		};
 189
 190/* bitmask for bitfield imr_rx{r}_en */
 191	static u32 itr_imr_rxren_msk[32] = {
 192			0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 193			0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 194			0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 195			0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 196			0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 197			0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 198			0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 199			0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
 200		};
 201
 202/* lower bit position of bitfield imr_rx{r}_en */
 203	static u32 itr_imr_rxren_shift[32] = {
 204			15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 205			15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 206			15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 207			15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
 208		};
 209
 210	aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
 211			    itr_imr_rxren_msk[rx],
 212			    itr_imr_rxren_shift[rx],
 213			    irq_map_en_rx);
 214}
 215
 216void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
 217				  u32 tx)
 218{
 219/* register address for bitfield imr_tx{t}_en */
 220	static u32 itr_imr_txten_adr[32] = {
 221			0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 222			0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 223			0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 224			0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 225			0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 226			0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 227			0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 228			0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 229		};
 230
 231/* bitmask for bitfield imr_tx{t}_en */
 232	static u32 itr_imr_txten_msk[32] = {
 233			0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 234			0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 235			0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 236			0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 237			0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 238			0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 239			0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 240			0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
 241		};
 242
 243/* lower bit position of bitfield imr_tx{t}_en */
 244	static u32 itr_imr_txten_shift[32] = {
 245			31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 246			31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 247			31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 248			31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
 249		};
 250
 251	aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
 252			    itr_imr_txten_msk[tx],
 253			    itr_imr_txten_shift[tx],
 254			    irq_map_en_tx);
 255}
 256
 257void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
 258{
 259/* register address for bitfield imr_rx{r}[4:0] */
 260	static u32 itr_imr_rxr_adr[32] = {
 261			0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 262			0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 263			0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 264			0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 265			0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 266			0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 267			0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 268			0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 269		};
 270
 271/* bitmask for bitfield imr_rx{r}[4:0] */
 272	static u32 itr_imr_rxr_msk[32] = {
 273			0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 274			0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 275			0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 276			0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 277			0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 278			0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 279			0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 280			0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU
 281		};
 282
 283/* lower bit position of bitfield imr_rx{r}[4:0] */
 284	static u32 itr_imr_rxr_shift[32] = {
 285			8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 286			8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 287			8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 288			8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
 289		};
 290
 291	aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
 292			    itr_imr_rxr_msk[rx],
 293			    itr_imr_rxr_shift[rx],
 294			    irq_map_rx);
 295}
 296
 297void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
 298{
 299/* register address for bitfield imr_tx{t}[4:0] */
 300	static u32 itr_imr_txt_adr[32] = {
 301			0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 302			0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 303			0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 304			0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 305			0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 306			0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 307			0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 308			0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 309		};
 310
 311/* bitmask for bitfield imr_tx{t}[4:0] */
 312	static u32 itr_imr_txt_msk[32] = {
 313			0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 314			0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 315			0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 316			0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 317			0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 318			0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 319			0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 320			0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U
 321		};
 322
 323/* lower bit position of bitfield imr_tx{t}[4:0] */
 324	static u32 itr_imr_txt_shift[32] = {
 325			24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 326			24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 327			24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 328			24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
 329		};
 330
 331	aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
 332			    itr_imr_txt_msk[tx],
 333			    itr_imr_txt_shift[tx],
 334			    irq_map_tx);
 335}
 336
 337void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
 338				     u32 irq_msk_clearlsw)
 339{
 340	aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
 341}
 342
 343void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
 344{
 345	aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
 346}
 347
 348void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
 349{
 350	aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
 351			    HW_ATL_ITR_REG_RES_DSBL_MSK,
 352			    HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
 353}
 354
 355void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
 356					u32 irq_status_clearlsw)
 357{
 358	aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
 359}
 360
 361u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
 362{
 363	return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
 364}
 365
 366u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
 367{
 368	return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 369				  HW_ATL_ITR_RES_SHIFT);
 370}
 371
 372void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
 373{
 374	aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 375			    HW_ATL_ITR_RES_SHIFT, res_irq);
 376}
 377
 378/* set RSC interrupt */
 379void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable)
 380{
 381	aq_hw_write_reg(aq_hw, HW_ATL_ITR_RSC_EN_ADR, enable);
 382}
 383
 384/* set RSC delay */
 385void hw_atl_itr_rsc_delay_set(struct aq_hw_s *aq_hw, u32 delay)
 386{
 387	aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RSC_DELAY_ADR,
 388			    HW_ATL_ITR_RSC_DELAY_MSK,
 389			    HW_ATL_ITR_RSC_DELAY_SHIFT,
 390			    delay);
 391}
 392
 393/* rdm */
 394void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
 395{
 396	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
 397			    HW_ATL_RDM_DCADCPUID_MSK,
 398			    HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
 399}
 400
 401void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
 402{
 403	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
 404			    HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
 405}
 406
 407void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
 408{
 409	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
 410			    HW_ATL_RDM_DCA_MODE_MSK,
 411			    HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
 412}
 413
 414void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
 415					   u32 rx_desc_data_buff_size,
 416					   u32 descriptor)
 417{
 418	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
 419			    HW_ATL_RDM_DESCDDATA_SIZE_MSK,
 420			    HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,
 421			    rx_desc_data_buff_size);
 422}
 423
 424void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
 425				   u32 dca)
 426{
 427	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
 428			    HW_ATL_RDM_DCADDESC_EN_MSK,
 429			    HW_ATL_RDM_DCADDESC_EN_SHIFT,
 430			    rx_desc_dca_en);
 431}
 432
 433void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
 434			       u32 descriptor)
 435{
 436	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
 437			    HW_ATL_RDM_DESCDEN_MSK,
 438			    HW_ATL_RDM_DESCDEN_SHIFT,
 439			    rx_desc_en);
 440}
 441
 442void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
 443					   u32 rx_desc_head_buff_size,
 444					   u32 descriptor)
 445{
 446	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
 447			    HW_ATL_RDM_DESCDHDR_SIZE_MSK,
 448			    HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,
 449			    rx_desc_head_buff_size);
 450}
 451
 452void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
 453					   u32 rx_desc_head_splitting,
 454					   u32 descriptor)
 455{
 456	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
 457			    HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
 458			    HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,
 459			    rx_desc_head_splitting);
 460}
 461
 462u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
 463{
 464	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
 465				  HW_ATL_RDM_DESCDHD_MSK,
 466				  HW_ATL_RDM_DESCDHD_SHIFT);
 467}
 468
 469void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
 470				u32 descriptor)
 471{
 472	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
 473			    HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
 474			    rx_desc_len);
 475}
 476
 477void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
 478				u32 descriptor)
 479{
 480	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
 481			    HW_ATL_RDM_DESCDRESET_MSK,
 482			    HW_ATL_RDM_DESCDRESET_SHIFT,
 483			    rx_desc_res);
 484}
 485
 486void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
 487					 u32 rx_desc_wr_wb_irq_en)
 488{
 489	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
 490			    HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
 491			    HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,
 492			    rx_desc_wr_wb_irq_en);
 493}
 494
 495void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
 496				   u32 dca)
 497{
 498	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
 499			    HW_ATL_RDM_DCADHDR_EN_MSK,
 500			    HW_ATL_RDM_DCADHDR_EN_SHIFT,
 501			    rx_head_dca_en);
 502}
 503
 504void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
 505				  u32 dca)
 506{
 507	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
 508			    HW_ATL_RDM_DCADPAY_EN_MSK,
 509			    HW_ATL_RDM_DCADPAY_EN_SHIFT,
 510			    rx_pld_dca_en);
 511}
 512
 513void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
 514				      u32 rdm_intr_moder_en)
 515{
 516	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
 517			    HW_ATL_RDM_INT_RIM_EN_MSK,
 518			    HW_ATL_RDM_INT_RIM_EN_SHIFT,
 519			    rdm_intr_moder_en);
 520}
 521
 522/* reg */
 523void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
 524				u32 regidx)
 525{
 526	aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
 527}
 528
 529u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
 530{
 531	return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
 532}
 533
 534void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
 535{
 536	aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
 537}
 538
 539void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
 540{
 541	aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
 542}
 543
 544void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 545					       u32 rx_dma_desc_base_addrlsw,
 546					       u32 descriptor)
 547{
 548	aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 549			rx_dma_desc_base_addrlsw);
 550}
 551
 552void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 553					       u32 rx_dma_desc_base_addrmsw,
 554					       u32 descriptor)
 555{
 556	aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 557			rx_dma_desc_base_addrmsw);
 558}
 559
 560u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
 561{
 562	return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
 563}
 564
 565void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 566					 u32 rx_dma_desc_tail_ptr,
 567					 u32 descriptor)
 568{
 569	aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 570			rx_dma_desc_tail_ptr);
 571}
 572
 573void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
 574					u32 rx_flr_mcst_flr_msk)
 575{
 576	aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
 577			rx_flr_mcst_flr_msk);
 578}
 579
 580void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
 581				    u32 filter)
 582{
 583	aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
 584			rx_flr_mcst_flr);
 585}
 586
 587void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
 588				       u32 rx_flr_rss_control1)
 589{
 590	aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
 591			rx_flr_rss_control1);
 592}
 593
 594void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
 595				    u32 rx_filter_control2)
 596{
 597	aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
 598}
 599
 600void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 601				       u32 rx_intr_moderation_ctl,
 602				       u32 queue)
 603{
 604	aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
 605			rx_intr_moderation_ctl);
 606}
 607
 608void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
 609				     u32 tx_dma_debug_ctl)
 610{
 611	aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
 612}
 613
 614void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 615					       u32 tx_dma_desc_base_addrlsw,
 616					       u32 descriptor)
 617{
 618	aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 619			tx_dma_desc_base_addrlsw);
 620}
 621
 622void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 623					       u32 tx_dma_desc_base_addrmsw,
 624					       u32 descriptor)
 625{
 626	aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 627			tx_dma_desc_base_addrmsw);
 628}
 629
 630void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 631					 u32 tx_dma_desc_tail_ptr,
 632					 u32 descriptor)
 633{
 634	aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 635			tx_dma_desc_tail_ptr);
 636}
 637
 638void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 639				       u32 tx_intr_moderation_ctl,
 640				       u32 queue)
 641{
 642	aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
 643			tx_intr_moderation_ctl);
 644}
 645
 646/* RPB: rx packet buffer */
 647void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
 648{
 649	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
 650			    HW_ATL_RPB_DMA_SYS_LBK_MSK,
 651			    HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
 652}
 653
 654void hw_atl_rpb_dma_net_lbk_set(struct aq_hw_s *aq_hw, u32 dma_net_lbk)
 655{
 656	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_NET_LBK_ADR,
 657			    HW_ATL_RPB_DMA_NET_LBK_MSK,
 658			    HW_ATL_RPB_DMA_NET_LBK_SHIFT, dma_net_lbk);
 659}
 660
 661void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
 662					   u32 rx_traf_class_mode)
 663{
 664	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
 665			    HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
 666			    HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
 667			    rx_traf_class_mode);
 668}
 669
 670u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw)
 671{
 672	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
 673			HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
 674			HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT);
 675}
 676
 677void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
 678{
 679	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
 680			    HW_ATL_RPB_RX_BUF_EN_MSK,
 681			    HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
 682}
 683
 684void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 685						u32 rx_buff_hi_threshold_per_tc,
 686						u32 buffer)
 687{
 688	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
 689			    HW_ATL_RPB_RXBHI_THRESH_MSK,
 690			    HW_ATL_RPB_RXBHI_THRESH_SHIFT,
 691			    rx_buff_hi_threshold_per_tc);
 692}
 693
 694void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 695						u32 rx_buff_lo_threshold_per_tc,
 696						u32 buffer)
 697{
 698	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
 699			    HW_ATL_RPB_RXBLO_THRESH_MSK,
 700			    HW_ATL_RPB_RXBLO_THRESH_SHIFT,
 701			    rx_buff_lo_threshold_per_tc);
 702}
 703
 704void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
 705{
 706	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
 707			    HW_ATL_RPB_RX_FC_MODE_MSK,
 708			    HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
 709}
 710
 711void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw)
 712{
 713	u32 val;
 714
 715	val = aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
 716				 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
 717				 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT);
 718
 719	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
 720			    HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
 721			    HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
 722			    val ^ 1);
 723}
 724
 725u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw)
 726{
 727	return aq_hw_read_reg_bit(aq_hw, RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR,
 728				  RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK,
 729				  RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT);
 730}
 731
 732void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
 733					    u32 rx_pkt_buff_size_per_tc, u32 buffer)
 734{
 735	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
 736			    HW_ATL_RPB_RXBBUF_SIZE_MSK,
 737			    HW_ATL_RPB_RXBBUF_SIZE_SHIFT,
 738			    rx_pkt_buff_size_per_tc);
 739}
 740
 741void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw,
 742				      u32 rx_xoff_en_per_tc, u32 buffer)
 743{
 744	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
 745			    HW_ATL_RPB_RXBXOFF_EN_MSK,
 746			    HW_ATL_RPB_RXBXOFF_EN_SHIFT,
 747			    rx_xoff_en_per_tc);
 748}
 749
 750/* rpf */
 751
 752void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
 753					       u32 l2broadcast_count_threshold)
 754{
 755	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
 756			    HW_ATL_RPFL2BC_THRESH_MSK,
 757			    HW_ATL_RPFL2BC_THRESH_SHIFT,
 758			    l2broadcast_count_threshold);
 759}
 760
 761void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
 762{
 763	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
 764			    HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
 765}
 766
 767void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
 768				       u32 l2broadcast_flr_act)
 769{
 770	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
 771			    HW_ATL_RPFL2BC_ACT_MSK,
 772			    HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
 773}
 774
 775void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
 776				      u32 l2multicast_flr_en,
 777				      u32 filter)
 778{
 779	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
 780			    HW_ATL_RPFL2MC_ENF_MSK,
 781			    HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
 782}
 783
 784u32 hw_atl_rpfl2promiscuous_mode_en_get(struct aq_hw_s *aq_hw)
 785{
 786	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
 787				  HW_ATL_RPFL2PROMIS_MODE_MSK,
 788				  HW_ATL_RPFL2PROMIS_MODE_SHIFT);
 789}
 790
 791void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
 792					 u32 l2promiscuous_mode_en)
 793{
 794	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
 795			    HW_ATL_RPFL2PROMIS_MODE_MSK,
 796			    HW_ATL_RPFL2PROMIS_MODE_SHIFT,
 797			    l2promiscuous_mode_en);
 798}
 799
 800void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
 801				     u32 l2unicast_flr_act,
 802				     u32 filter)
 803{
 804	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
 805			    HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
 806			    l2unicast_flr_act);
 807}
 808
 809void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
 810				u32 filter)
 811{
 812	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
 813			    HW_ATL_RPFL2UC_ENF_MSK,
 814			    HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
 815}
 816
 817void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
 818					     u32 l2unicast_dest_addresslsw,
 819					     u32 filter)
 820{
 821	aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
 822			l2unicast_dest_addresslsw);
 823}
 824
 825void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
 826					     u32 l2unicast_dest_addressmsw,
 827					     u32 filter)
 828{
 829	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
 830			    HW_ATL_RPFL2UC_DAFMSW_MSK,
 831			    HW_ATL_RPFL2UC_DAFMSW_SHIFT,
 832			    l2unicast_dest_addressmsw);
 833}
 834
 835void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
 836					    u32 l2_accept_all_mc_packets)
 837{
 838	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
 839			    HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
 840			    HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,
 841			    l2_accept_all_mc_packets);
 842}
 843
 844void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
 845					     u32 user_priority, u32 tc)
 846{
 847/* register address for bitfield rx_tc_up{t}[2:0] */
 848	static u32 rpf_rpb_rx_tc_upt_adr[8] = {
 849			0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,
 850			0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U
 851		};
 852
 853/* bitmask for bitfield rx_tc_up{t}[2:0] */
 854	static u32 rpf_rpb_rx_tc_upt_msk[8] = {
 855			0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
 856			0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
 857		};
 858
 859/* lower bit position of bitfield rx_tc_up{t}[2:0] */
 860	static u32 rpf_rpb_rx_tc_upt_shft[8] = {
 861			0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
 862		};
 863
 864	aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[user_priority],
 865			    rpf_rpb_rx_tc_upt_msk[user_priority],
 866			    rpf_rpb_rx_tc_upt_shft[user_priority], tc);
 867}
 868
 869void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
 870{
 871	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
 872			    HW_ATL_RPF_RSS_KEY_ADDR_MSK,
 873			    HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,
 874			    rss_key_addr);
 875}
 876
 877void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
 878{
 879	aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
 880			rss_key_wr_data);
 881}
 882
 883u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
 884{
 885	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 886				  HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 887				  HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
 888}
 889
 890void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
 891{
 892	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 893			    HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 894			    HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,
 895			    rss_key_wr_en);
 896}
 897
 898void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
 899				       u32 rss_redir_tbl_addr)
 900{
 901	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
 902			    HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
 903			    HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,
 904			    rss_redir_tbl_addr);
 905}
 906
 907void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
 908					  u32 rss_redir_tbl_wr_data)
 909{
 910	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
 911			    HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
 912			    HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,
 913			    rss_redir_tbl_wr_data);
 914}
 915
 916u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
 917{
 918	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 919				  HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 920				  HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
 921}
 922
 923void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
 924{
 925	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 926			    HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 927			    HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
 928}
 929
 930void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
 931				       u32 tpo_to_rpf_sys_lbk)
 932{
 933	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
 934			    HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
 935			    HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,
 936			    tpo_to_rpf_sys_lbk);
 937}
 938
 939void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
 940{
 941	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
 942			    HW_ATL_RPF_VL_INNER_TPID_MSK,
 943			    HW_ATL_RPF_VL_INNER_TPID_SHIFT,
 944			    vlan_inner_etht);
 945}
 946
 947void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
 948{
 949	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
 950			    HW_ATL_RPF_VL_OUTER_TPID_MSK,
 951			    HW_ATL_RPF_VL_OUTER_TPID_SHIFT,
 952			    vlan_outer_etht);
 953}
 954
 955void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
 956				      u32 vlan_prom_mode_en)
 957{
 958	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
 959			    HW_ATL_RPF_VL_PROMIS_MODE_MSK,
 960			    HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,
 961			    vlan_prom_mode_en);
 962}
 963
 964u32 hw_atl_rpf_vlan_prom_mode_en_get(struct aq_hw_s *aq_hw)
 965{
 966	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
 967				  HW_ATL_RPF_VL_PROMIS_MODE_MSK,
 968				  HW_ATL_RPF_VL_PROMIS_MODE_SHIFT);
 969}
 970
 971void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
 972						 u32 vlan_acc_untagged_packets)
 973{
 974	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
 975			    HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
 976			    HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
 977			    vlan_acc_untagged_packets);
 978}
 979
 980void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
 981				      u32 vlan_untagged_act)
 982{
 983	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
 984			    HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
 985			    HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,
 986			    vlan_untagged_act);
 987}
 988
 989void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
 990				u32 filter)
 991{
 992	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
 993			    HW_ATL_RPF_VL_EN_F_MSK,
 994			    HW_ATL_RPF_VL_EN_F_SHIFT,
 995			    vlan_flr_en);
 996}
 997
 998void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
 999				 u32 filter)
1000{
1001	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
1002			    HW_ATL_RPF_VL_ACT_F_MSK,
1003			    HW_ATL_RPF_VL_ACT_F_SHIFT,
1004			    vlan_flr_act);
1005}
1006
1007void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
1008				u32 filter)
1009{
1010	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
1011			    HW_ATL_RPF_VL_ID_F_MSK,
1012			    HW_ATL_RPF_VL_ID_F_SHIFT,
1013			    vlan_id_flr);
1014}
1015
1016void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
1017				    u32 filter)
1018{
1019	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter),
1020			    HW_ATL_RPF_VL_RXQ_EN_F_MSK,
1021			    HW_ATL_RPF_VL_RXQ_EN_F_SHIFT,
1022			    vlan_rxq_en);
1023}
1024
1025void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
1026				 u32 filter)
1027{
1028	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),
1029			    HW_ATL_RPF_VL_RXQ_F_MSK,
1030			    HW_ATL_RPF_VL_RXQ_F_SHIFT,
1031			    vlan_rxq);
1032};
1033
1034void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
1035				u32 filter)
1036{
1037	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
1038			    HW_ATL_RPF_ET_ENF_MSK,
1039			    HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
1040}
1041
1042void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
1043					  u32 etht_user_priority_en, u32 filter)
1044{
1045	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
1046			    HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
1047			    etht_user_priority_en);
1048}
1049
1050void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
1051				     u32 etht_rx_queue_en,
1052				     u32 filter)
1053{
1054	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
1055			    HW_ATL_RPF_ET_RXQFEN_MSK,
1056			    HW_ATL_RPF_ET_RXQFEN_SHIFT,
1057			    etht_rx_queue_en);
1058}
1059
1060void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
1061				       u32 etht_user_priority,
1062				       u32 filter)
1063{
1064	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
1065			    HW_ATL_RPF_ET_UPF_MSK,
1066			    HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
1067}
1068
1069void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
1070				  u32 filter)
1071{
1072	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
1073			    HW_ATL_RPF_ET_RXQF_MSK,
1074			    HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
1075}
1076
1077void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
1078				   u32 filter)
1079{
1080	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
1081			    HW_ATL_RPF_ET_MNG_RXQF_MSK,
1082			    HW_ATL_RPF_ET_MNG_RXQF_SHIFT,
1083			    etht_mgt_queue);
1084}
1085
1086void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
1087				 u32 filter)
1088{
1089	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
1090			    HW_ATL_RPF_ET_ACTF_MSK,
1091			    HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
1092}
1093
1094void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
1095{
1096	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
1097			    HW_ATL_RPF_ET_VALF_MSK,
1098			    HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
1099}
1100
1101void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
1102{
1103	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter),
1104			    HW_ATL_RPF_L4_SPD_MSK,
1105			    HW_ATL_RPF_L4_SPD_SHIFT, val);
1106}
1107
1108void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
1109{
1110	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter),
1111			    HW_ATL_RPF_L4_DPD_MSK,
1112			    HW_ATL_RPF_L4_DPD_SHIFT, val);
1113}
1114
1115/* RPO: rx packet offload */
1116void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1117					      u32 ipv4header_crc_offload_en)
1118{
1119	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
1120			    HW_ATL_RPO_IPV4CHK_EN_MSK,
1121			    HW_ATL_RPO_IPV4CHK_EN_SHIFT,
1122			    ipv4header_crc_offload_en);
1123}
1124
1125void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
1126					   u32 rx_desc_vlan_stripping,
1127					   u32 descriptor)
1128{
1129	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
1130			    HW_ATL_RPO_DESCDVL_STRIP_MSK,
1131			    HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
1132			    rx_desc_vlan_stripping);
1133}
1134
1135void hw_atl_rpo_outer_vlan_tag_mode_set(void *context,
1136					u32 outervlantagmode)
1137{
1138	aq_hw_write_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1139			    HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1140			    HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT,
1141			    outervlantagmode);
1142}
1143
1144u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context)
1145{
1146	return aq_hw_read_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1147				  HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1148				  HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT);
1149}
1150
1151void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1152					   u32 tcp_udp_crc_offload_en)
1153{
1154	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
1155			    HW_ATL_RPOL4CHK_EN_MSK,
1156			    HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
1157}
1158
1159void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
1160{
1161	aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
1162}
1163
1164void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
1165					      u32 lro_patch_optimization_en)
1166{
1167	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
1168			    HW_ATL_RPO_LRO_PTOPT_EN_MSK,
1169			    HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,
1170			    lro_patch_optimization_en);
1171}
1172
1173void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
1174				      u32 lro_qsessions_lim)
1175{
1176	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
1177			    HW_ATL_RPO_LRO_QSES_LMT_MSK,
1178			    HW_ATL_RPO_LRO_QSES_LMT_SHIFT,
1179			    lro_qsessions_lim);
1180}
1181
1182void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
1183				       u32 lro_total_desc_lim)
1184{
1185	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
1186			    HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
1187			    HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,
1188			    lro_total_desc_lim);
1189}
1190
1191void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
1192					     u32 lro_min_pld_of_first_pkt)
1193{
1194	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
1195			    HW_ATL_RPO_LRO_PKT_MIN_MSK,
1196			    HW_ATL_RPO_LRO_PKT_MIN_SHIFT,
1197			    lro_min_pld_of_first_pkt);
1198}
1199
1200void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
1201{
1202	aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
1203}
1204
1205void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
1206					       u32 lro_max_number_of_descriptors,
1207					       u32 lro)
1208{
1209/* Register address for bitfield lro{L}_des_max[1:0] */
1210	static u32 rpo_lro_ldes_max_adr[32] = {
1211			0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1212			0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1213			0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1214			0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1215			0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1216			0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1217			0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
1218			0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
1219		};
1220
1221/* Bitmask for bitfield lro{L}_des_max[1:0] */
1222	static u32 rpo_lro_ldes_max_msk[32] = {
1223			0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1224			0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1225			0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1226			0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1227			0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1228			0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1229			0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1230			0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1231		};
1232
1233/* Lower bit position of bitfield lro{L}_des_max[1:0] */
1234	static u32 rpo_lro_ldes_max_shift[32] = {
1235			0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1236			0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1237			0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1238			0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1239		};
1240
1241	aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1242			    rpo_lro_ldes_max_msk[lro],
1243			    rpo_lro_ldes_max_shift[lro],
1244			    lro_max_number_of_descriptors);
1245}
1246
1247void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1248					  u32 lro_time_base_divider)
1249{
1250	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
1251			    HW_ATL_RPO_LRO_TB_DIV_MSK,
1252			    HW_ATL_RPO_LRO_TB_DIV_SHIFT,
1253			    lro_time_base_divider);
1254}
1255
1256void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1257					  u32 lro_inactive_interval)
1258{
1259	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
1260			    HW_ATL_RPO_LRO_INA_IVAL_MSK,
1261			    HW_ATL_RPO_LRO_INA_IVAL_SHIFT,
1262			    lro_inactive_interval);
1263}
1264
1265void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1266						u32 lro_max_coal_interval)
1267{
1268	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
1269			    HW_ATL_RPO_LRO_MAX_IVAL_MSK,
1270			    HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
1271			    lro_max_coal_interval);
1272}
1273
1274/* rx */
1275void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1276{
1277	aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
1278			    HW_ATL_RX_REG_RES_DSBL_MSK,
1279			    HW_ATL_RX_REG_RES_DSBL_SHIFT,
1280			    rx_reg_res_dis);
1281}
1282
1283/* tdm */
1284void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1285{
1286	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
1287			    HW_ATL_TDM_DCADCPUID_MSK,
1288			    HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
1289}
1290
1291void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1292					  u32 large_send_offload_en)
1293{
1294	aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
1295}
1296
1297void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1298{
1299	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
1300			    HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
1301}
1302
1303void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1304{
1305	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
1306			    HW_ATL_TDM_DCA_MODE_MSK,
1307			    HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
1308}
1309
1310void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
1311				   u32 dca)
1312{
1313	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
1314			    HW_ATL_TDM_DCADDESC_EN_MSK,
1315			    HW_ATL_TDM_DCADDESC_EN_SHIFT,
1316			    tx_desc_dca_en);
1317}
1318
1319void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
1320			       u32 descriptor)
1321{
1322	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
1323			    HW_ATL_TDM_DESCDEN_MSK,
1324			    HW_ATL_TDM_DESCDEN_SHIFT,
1325			    tx_desc_en);
1326}
1327
1328u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1329{
1330	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
1331				  HW_ATL_TDM_DESCDHD_MSK,
1332				  HW_ATL_TDM_DESCDHD_SHIFT);
1333}
1334
1335void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1336				u32 descriptor)
1337{
1338	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
1339			    HW_ATL_TDM_DESCDLEN_MSK,
1340			    HW_ATL_TDM_DESCDLEN_SHIFT,
1341			    tx_desc_len);
1342}
1343
1344void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1345					 u32 tx_desc_wr_wb_irq_en)
1346{
1347	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
1348			    HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
1349			    HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,
1350			    tx_desc_wr_wb_irq_en);
1351}
1352
1353void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1354					    u32 tx_desc_wr_wb_threshold,
1355					    u32 descriptor)
1356{
1357	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
1358			    HW_ATL_TDM_DESCDWRB_THRESH_MSK,
1359			    HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,
1360			    tx_desc_wr_wb_threshold);
1361}
1362
1363void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1364				      u32 tdm_irq_moderation_en)
1365{
1366	aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
1367			    HW_ATL_TDM_INT_MOD_EN_MSK,
1368			    HW_ATL_TDM_INT_MOD_EN_SHIFT,
1369			    tdm_irq_moderation_en);
1370}
1371
1372/* thm */
1373void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1374					      u32 lso_tcp_flag_of_first_pkt)
1375{
1376	aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
1377			    HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
1378			    HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,
1379			    lso_tcp_flag_of_first_pkt);
1380}
1381
1382void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1383					     u32 lso_tcp_flag_of_last_pkt)
1384{
1385	aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
1386			    HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
1387			    HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,
1388			    lso_tcp_flag_of_last_pkt);
1389}
1390
1391void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1392					       u32 lso_tcp_flag_of_middle_pkt)
1393{
1394	aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
1395			    HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
1396			    HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,
1397			    lso_tcp_flag_of_middle_pkt);
1398}
1399
1400/* TPB: tx packet buffer */
1401void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1402{
1403	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
1404			    HW_ATL_TPB_TX_BUF_EN_MSK,
1405			    HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
1406}
1407
1408u32 hw_atl_tpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw)
1409{
1410	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1411			HW_ATL_TPB_TX_TC_MODE_MSK,
1412			HW_ATL_TPB_TX_TC_MODE_SHIFT);
1413}
1414
1415void hw_atl_tpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
1416				   u32 tx_traf_class_mode)
1417{
1418	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1419			HW_ATL_TPB_TX_TC_MODE_MSK,
1420			HW_ATL_TPB_TX_TC_MODE_SHIFT,
1421			tx_traf_class_mode);
1422}
1423
1424void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1425						u32 tx_buff_hi_threshold_per_tc,
1426					 u32 buffer)
1427{
1428	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
1429			    HW_ATL_TPB_TXBHI_THRESH_MSK,
1430			    HW_ATL_TPB_TXBHI_THRESH_SHIFT,
1431			    tx_buff_hi_threshold_per_tc);
1432}
1433
1434void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1435						u32 tx_buff_lo_threshold_per_tc,
1436					 u32 buffer)
1437{
1438	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
1439			    HW_ATL_TPB_TXBLO_THRESH_MSK,
1440			    HW_ATL_TPB_TXBLO_THRESH_SHIFT,
1441			    tx_buff_lo_threshold_per_tc);
1442}
1443
1444void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1445{
1446	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
1447			    HW_ATL_TPB_DMA_SYS_LBK_MSK,
1448			    HW_ATL_TPB_DMA_SYS_LBK_SHIFT,
1449			    tx_dma_sys_lbk_en);
1450}
1451
1452void hw_atl_tpb_tx_dma_net_lbk_en_set(struct aq_hw_s *aq_hw,
1453				      u32 tx_dma_net_lbk_en)
1454{
1455	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_NET_LBK_ADR,
1456			    HW_ATL_TPB_DMA_NET_LBK_MSK,
1457			    HW_ATL_TPB_DMA_NET_LBK_SHIFT,
1458			    tx_dma_net_lbk_en);
1459}
1460
1461void hw_atl_tpb_tx_tx_clk_gate_en_set(struct aq_hw_s *aq_hw,
1462				      u32 tx_clk_gate_en)
1463{
1464	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_CLK_GATE_EN_ADR,
1465			    HW_ATL_TPB_TX_CLK_GATE_EN_MSK,
1466			    HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT,
1467			    tx_clk_gate_en);
1468}
1469
1470void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1471
1472					    u32 tx_pkt_buff_size_per_tc, u32 buffer)
1473{
1474	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
1475			    HW_ATL_TPB_TXBBUF_SIZE_MSK,
1476			    HW_ATL_TPB_TXBBUF_SIZE_SHIFT,
1477			    tx_pkt_buff_size_per_tc);
1478}
1479
1480void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1481{
1482	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
1483			    HW_ATL_TPB_TX_SCP_INS_EN_MSK,
1484			    HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,
1485			    tx_path_scp_ins_en);
1486}
1487
1488/* TPO: tx packet offload */
1489void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1490					      u32 ipv4header_crc_offload_en)
1491{
1492	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
1493			    HW_ATL_TPO_IPV4CHK_EN_MSK,
1494			    HW_ATL_TPO_IPV4CHK_EN_SHIFT,
1495			    ipv4header_crc_offload_en);
1496}
1497
1498void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1499					   u32 tcp_udp_crc_offload_en)
1500{
1501	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
1502			    HW_ATL_TPOL4CHK_EN_MSK,
1503			    HW_ATL_TPOL4CHK_EN_SHIFT,
1504			    tcp_udp_crc_offload_en);
1505}
1506
1507void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1508				      u32 tx_pkt_sys_lbk_en)
1509{
1510	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
1511			    HW_ATL_TPO_PKT_SYS_LBK_MSK,
1512			    HW_ATL_TPO_PKT_SYS_LBK_SHIFT,
1513			    tx_pkt_sys_lbk_en);
1514}
1515
1516/* TPS: tx packet scheduler */
1517void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1518					      u32 tx_pkt_shed_data_arb_mode)
1519{
1520	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
1521			    HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
1522			    HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,
1523			    tx_pkt_shed_data_arb_mode);
1524}
1525
1526void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1527							u32 curr_time_res)
1528{
1529	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
1530			    HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
1531			    HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,
1532			    curr_time_res);
1533}
1534
1535void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1536					      u32 tx_pkt_shed_desc_rate_lim)
1537{
1538	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
1539			    HW_ATL_TPS_DESC_RATE_LIM_MSK,
1540			    HW_ATL_TPS_DESC_RATE_LIM_SHIFT,
1541			    tx_pkt_shed_desc_rate_lim);
1542}
1543
1544void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1545						 u32 arb_mode)
1546{
1547	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
1548			    HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
1549			    HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
1550			    arb_mode);
1551}
1552
1553void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1554						   const u32 tc,
1555						   const u32 max_credit)
1556{
1557	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
1558			    HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
1559			    HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
1560			    max_credit);
1561}
1562
1563void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1564					       const u32 tc,
1565					       const u32 weight)
1566{
1567	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
1568			    HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
1569			    HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1570			    weight);
1571}
1572
1573void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1574						 u32 arb_mode)
1575{
1576	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
1577			    HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
1578			    HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
1579			    arb_mode);
1580}
1581
1582void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1583						   const u32 tc,
1584						   const u32 max_credit)
1585{
1586	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
1587			    HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
1588			    HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
1589			    max_credit);
1590}
1591
1592void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1593					       const u32 tc,
1594					       const u32 weight)
1595{
1596	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
1597			    HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
1598			    HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1599			    weight);
1600}
1601
1602void hw_atl_tps_tx_desc_rate_mode_set(struct aq_hw_s *aq_hw,
1603				      const u32 rate_mode)
1604{
1605	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_TX_DESC_RATE_MODE_ADR,
1606			    HW_ATL_TPS_TX_DESC_RATE_MODE_MSK,
1607			    HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT,
1608			    rate_mode);
1609}
1610
1611void hw_atl_tps_tx_desc_rate_en_set(struct aq_hw_s *aq_hw, const u32 desc,
1612				    const u32 enable)
1613{
1614	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_EN_ADR(desc),
1615			    HW_ATL_TPS_DESC_RATE_EN_MSK,
1616			    HW_ATL_TPS_DESC_RATE_EN_SHIFT,
1617			    enable);
1618}
1619
1620void hw_atl_tps_tx_desc_rate_x_set(struct aq_hw_s *aq_hw, const u32 desc,
1621				   const u32 rate_int)
1622{
1623	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_X_ADR(desc),
1624			    HW_ATL_TPS_DESC_RATE_X_MSK,
1625			    HW_ATL_TPS_DESC_RATE_X_SHIFT,
1626			    rate_int);
1627}
1628
1629void hw_atl_tps_tx_desc_rate_y_set(struct aq_hw_s *aq_hw, const u32 desc,
1630				   const u32 rate_frac)
1631{
1632	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_Y_ADR(desc),
1633			    HW_ATL_TPS_DESC_RATE_Y_MSK,
1634			    HW_ATL_TPS_DESC_RATE_Y_SHIFT,
1635			    rate_frac);
1636}
1637
1638/* tx */
1639void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1640{
1641	aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
1642			    HW_ATL_TX_REG_RES_DSBL_MSK,
1643			    HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);
1644}
1645
1646/* msm */
1647u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1648{
1649	return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
1650				  HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
1651				  HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
1652}
1653
1654void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1655					       u32 reg_addr_for_indirect_addr)
1656{
1657	aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
1658			    HW_ATL_MSM_REG_ADDR_MSK,
1659			    HW_ATL_MSM_REG_ADDR_SHIFT,
1660			    reg_addr_for_indirect_addr);
1661}
1662
1663void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1664{
1665	aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
1666			    HW_ATL_MSM_REG_RD_STROBE_MSK,
1667			    HW_ATL_MSM_REG_RD_STROBE_SHIFT,
1668			    reg_rd_strobe);
1669}
1670
1671u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1672{
1673	return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
1674}
1675
1676void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1677{
1678	aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
1679}
1680
1681void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1682{
1683	aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
1684			    HW_ATL_MSM_REG_WR_STROBE_MSK,
1685			    HW_ATL_MSM_REG_WR_STROBE_SHIFT,
1686			    reg_wr_strobe);
1687}
1688
1689/* pci */
1690void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1691{
1692	aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
1693			    HW_ATL_PCI_REG_RES_DSBL_MSK,
1694			    HW_ATL_PCI_REG_RES_DSBL_SHIFT,
1695			    pci_reg_res_dis);
1696}
1697
1698void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
1699					u32 glb_cpu_scratch_scp,
1700					u32 scratch_scp)
1701{
1702	aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
1703			glb_cpu_scratch_scp);
1704}
1705
1706void hw_atl_pcs_ptp_clock_read_enable(struct aq_hw_s *aq_hw,
1707				      u32 ptp_clock_read_enable)
1708{
1709	aq_hw_write_reg_bit(aq_hw, HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR,
1710			    HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK,
1711			    HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT,
1712			    ptp_clock_read_enable);
1713}
1714
1715u32 hw_atl_pcs_ptp_clock_get(struct aq_hw_s *aq_hw, u32 index)
1716{
1717	return aq_hw_read_reg(aq_hw, HW_ATL_PCS_PTP_TS_VAL_ADDR(index));
1718}
1719
1720void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
1721{
1722	aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR,
1723			    HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK,
1724			    HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,
1725			    up_force_intr);
1726}
1727
1728void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1729{
1730	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U);
1731}
1732
1733void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1734{
1735	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), 0U);
1736}
1737
1738void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location)
1739{
1740	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), 0U);
1741}
1742
1743void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1744{
1745	int i;
1746
1747	for (i = 0; i < 4; ++i)
1748		aq_hw_write_reg(aq_hw,
1749				HW_ATL_RPF_L3_DSTA_ADR(location + i),
1750				0U);
1751}
1752
1753void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1754{
1755	int i;
1756
1757	for (i = 0; i < 4; ++i)
1758		aq_hw_write_reg(aq_hw,
1759				HW_ATL_RPF_L3_SRCA_ADR(location + i),
1760				0U);
1761}
1762
1763void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1764				       u32 ipv4_dest)
1765{
1766	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location),
1767			ipv4_dest);
1768}
1769
1770void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1771				      u32 ipv4_src)
1772{
1773	aq_hw_write_reg(aq_hw,
1774			HW_ATL_RPF_L3_SRCA_ADR(location),
1775			ipv4_src);
1776}
1777
1778void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd)
1779{
1780	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), cmd);
1781}
1782
1783void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1784				      u32 *ipv6_src)
1785{
1786	int i;
1787
1788	for (i = 0; i < 4; ++i)
1789		aq_hw_write_reg(aq_hw,
1790				HW_ATL_RPF_L3_SRCA_ADR(location + i),
1791				ipv6_src[3 - i]);
1792}
1793
1794void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1795				       u32 *ipv6_dest)
1796{
1797	int i;
1798
1799	for (i = 0; i < 4; ++i)
1800		aq_hw_write_reg(aq_hw,
1801				HW_ATL_RPF_L3_DSTA_ADR(location + i),
1802				ipv6_dest[3 - i]);
1803}
1804
1805u32 hw_atl_sem_ram_get(struct aq_hw_s *self)
1806{
1807	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
1808}
1809
1810u32 hw_atl_sem_mdio_get(struct aq_hw_s *self)
1811{
1812	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_MDIO);
1813}
1814
1815u32 hw_atl_sem_reset1_get(struct aq_hw_s *self)
1816{
1817	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RESET1);
1818}
1819
1820u32 hw_atl_sem_reset2_get(struct aq_hw_s *self)
1821{
1822	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RESET2);
1823}
1824
1825u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp)
1826{
1827	return aq_hw_read_reg(aq_hw,
1828			      HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp));
1829}
1830
1831u32 hw_atl_scrpad12_get(struct aq_hw_s *self)
1832{
1833	return  hw_atl_scrpad_get(self, 0xB);
1834}
1835
1836u32 hw_atl_scrpad25_get(struct aq_hw_s *self)
1837{
1838	return hw_atl_scrpad_get(self, 0x18);
1839}
1840
1841void hw_atl_glb_mdio_iface1_set(struct aq_hw_s *aq_hw, u32 value)
1842{
1843	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1), value);
1844}
1845
1846u32 hw_atl_glb_mdio_iface1_get(struct aq_hw_s *aq_hw)
1847{
1848	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1));
1849}
1850
1851void hw_atl_glb_mdio_iface2_set(struct aq_hw_s *aq_hw, u32 value)
1852{
1853	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2), value);
1854}
1855
1856u32 hw_atl_glb_mdio_iface2_get(struct aq_hw_s *aq_hw)
1857{
1858	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2));
1859}
1860
1861void hw_atl_glb_mdio_iface3_set(struct aq_hw_s *aq_hw, u32 value)
1862{
1863	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3), value);
1864}
1865
1866u32 hw_atl_glb_mdio_iface3_get(struct aq_hw_s *aq_hw)
1867{
1868	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3));
1869}
1870
1871void hw_atl_glb_mdio_iface4_set(struct aq_hw_s *aq_hw, u32 value)
1872{
1873	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4), value);
1874}
1875
1876u32 hw_atl_glb_mdio_iface4_get(struct aq_hw_s *aq_hw)
1877{
1878	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4));
1879}
1880
1881void hw_atl_glb_mdio_iface5_set(struct aq_hw_s *aq_hw, u32 value)
1882{
1883	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5), value);
1884}
1885
1886u32 hw_atl_glb_mdio_iface5_get(struct aq_hw_s *aq_hw)
1887{
1888	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5));
1889}
1890
1891u32 hw_atl_mdio_busy_get(struct aq_hw_s *aq_hw)
1892{
1893	return aq_hw_read_reg_bit(aq_hw, HW_ATL_MDIO_BUSY_ADR,
1894				  HW_ATL_MDIO_BUSY_MSK,
1895				  HW_ATL_MDIO_BUSY_SHIFT);
1896}