aq_hw.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Atlantic Network Driver
  3 *
  4 * Copyright (C) 2014-2019 aQuantia Corporation
  5 * Copyright (C) 2019-2020 Marvell International Ltd.
  6 */
  7
  8/* File aq_hw.h: Declaration of abstract interface for NIC hardware specific
  9 * functions.
 10 */
 11
 12#ifndef AQ_HW_H
 13#define AQ_HW_H
 14
 15#include "aq_common.h"
 16#include "aq_rss.h"
 17#include "hw_atl/hw_atl_utils.h"
 18
 19#define AQ_HW_MAC_COUNTER_HZ   312500000ll
 20#define AQ_HW_PHY_COUNTER_HZ   160000000ll
 21
 22enum aq_tc_mode {
 23	AQ_TC_MODE_INVALID = -1,
 24	AQ_TC_MODE_8TCS,
 25	AQ_TC_MODE_4TCS,
 26};
 27
 28#define AQ_RX_FIRST_LOC_FVLANID     0U
 29#define AQ_RX_LAST_LOC_FVLANID	   15U
 30#define AQ_RX_FIRST_LOC_FETHERT    16U
 31#define AQ_RX_LAST_LOC_FETHERT	   31U
 32#define AQ_RX_FIRST_LOC_FL3L4	   32U
 33#define AQ_RX_LAST_LOC_FL3L4	   39U
 34#define AQ_RX_MAX_RXNFC_LOC	   AQ_RX_LAST_LOC_FL3L4
 35#define AQ_VLAN_MAX_FILTERS   \
 36			(AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U)
 37#define AQ_RX_QUEUE_NOT_ASSIGNED   0xFFU
 38
 39#define AQ_FRAC_PER_NS 0x100000000LL
 40
 41/* Used for rate to Mbps conversion */
 42#define AQ_MBPS_DIVISOR         125000 /* 1000000 / 8 */
 43
 44/* NIC H/W capabilities */
 45struct aq_hw_caps_s {
 46	u64 hw_features;
 47	u64 link_speed_msk;
 48	unsigned int hw_priv_flags;
 49	u32 media_type;
 50	u32 rxds_max;
 51	u32 txds_max;
 52	u32 rxds_min;
 53	u32 txds_min;
 54	u32 txhwb_alignment;
 55	u32 irq_mask;
 56	u32 vecs;
 57	u32 mtu;
 58	u32 mac_regs_count;
 59	u32 hw_alive_check_addr;
 60	u8 msix_irqs;
 61	u8 tcs_max;
 62	u8 rxd_alignment;
 63	u8 rxd_size;
 64	u8 txd_alignment;
 65	u8 txd_size;
 66	u8 tx_rings;
 67	u8 rx_rings;
 68	bool flow_control;
 69	bool is_64_dma;
 70	bool op64bit;
 71	u32 quirks;
 72	u32 priv_data_len;
 73};
 74
 75struct aq_hw_link_status_s {
 76	unsigned int mbps;
 77	bool full_duplex;
 78	u32 lp_link_speed_msk;
 79	u32 lp_flow_control;
 80};
 81
 82struct aq_stats_s {
 83	u64 brc;
 84	u64 btc;
 85	u64 uprc;
 86	u64 mprc;
 87	u64 bprc;
 88	u64 erpt;
 89	u64 uptc;
 90	u64 mptc;
 91	u64 bptc;
 92	u64 erpr;
 93	u64 mbtc;
 94	u64 bbtc;
 95	u64 mbrc;
 96	u64 bbrc;
 97	u64 ubrc;
 98	u64 ubtc;
 99	u64 dpc;
100	u64 dma_pkt_rc;
101	u64 dma_pkt_tc;
102	u64 dma_oct_rc;
103	u64 dma_oct_tc;
104};
105
106#define AQ_HW_IRQ_INVALID 0U
107#define AQ_HW_IRQ_INTX	  1U
108#define AQ_HW_IRQ_MSI     2U
109#define AQ_HW_IRQ_MSIX    3U
110
111#define AQ_HW_SERVICE_IRQS   1U
112
113#define AQ_HW_POWER_STATE_D0   0U
114#define AQ_HW_POWER_STATE_D3   3U
115
116#define	AQ_FW_WAKE_ON_LINK_RTPM BIT(10)
117
118#define AQ_HW_FLAG_STARTED     0x00000004U
119#define AQ_HW_FLAG_STOPPING    0x00000008U
120#define AQ_HW_FLAG_RESETTING   0x00000010U
121#define AQ_HW_FLAG_CLOSING     0x00000020U
122#define AQ_HW_PTP_AVAILABLE    0x01000000U
123#define AQ_HW_LINK_DOWN        0x04000000U
124#define AQ_HW_FLAG_ERR_UNPLUG  0x40000000U
125#define AQ_HW_FLAG_ERR_HW      0x80000000U
126
127#define AQ_HW_FLAG_ERRORS      (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG)
128
129#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \
130			AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \
131			AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)
132
133#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
134					AQ_NIC_LINK_DOWN)
135
136#define AQ_HW_MEDIA_TYPE_TP    1U
137#define AQ_HW_MEDIA_TYPE_FIBRE 2U
138
139#define AQ_HW_TXD_MULTIPLE 8U
140#define AQ_HW_RXD_MULTIPLE 8U
141
142#define AQ_HW_QUEUES_MAX                32U
143#define AQ_HW_MULTICAST_ADDRESS_MAX     32U
144
145#define AQ_HW_PTP_TC                    2U
146
147#define AQ_HW_LED_BLINK    0x2U
148#define AQ_HW_LED_DEFAULT  0x0U
149
150#define AQ_HW_MEDIA_DETECT_CNT 6000
151
152enum aq_priv_flags {
153	AQ_HW_LOOPBACK_DMA_SYS,
154	AQ_HW_LOOPBACK_PKT_SYS,
155	AQ_HW_LOOPBACK_DMA_NET,
156	AQ_HW_LOOPBACK_PHYINT_SYS,
157	AQ_HW_LOOPBACK_PHYEXT_SYS,
158};
159
160#define AQ_HW_LOOPBACK_MASK	(BIT(AQ_HW_LOOPBACK_DMA_SYS) |\
161				 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\
162				 BIT(AQ_HW_LOOPBACK_DMA_NET) |\
163				 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\
164				 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS))
165
166#define ATL_HW_CHIP_MIPS         0x00000001U
167#define ATL_HW_CHIP_TPO2         0x00000002U
168#define ATL_HW_CHIP_RPF2         0x00000004U
169#define ATL_HW_CHIP_MPI_AQ       0x00000010U
170#define ATL_HW_CHIP_ATLANTIC     0x00800000U
171#define ATL_HW_CHIP_REVISION_A0  0x01000000U
172#define ATL_HW_CHIP_REVISION_B0  0x02000000U
173#define ATL_HW_CHIP_REVISION_B1  0x04000000U
174#define ATL_HW_CHIP_ANTIGUA      0x08000000U
175
176#define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \
177	(_HW_)->chip_features))
178
179struct aq_hw_s {
180	atomic_t flags;
181	u8 rbl_enabled:1;
182	struct aq_nic_cfg_s *aq_nic_cfg;
183	const struct aq_fw_ops *aq_fw_ops;
184	void __iomem *mmio;
185	struct aq_hw_link_status_s aq_link_status;
186	struct hw_atl_utils_mbox mbox;
187	struct hw_atl_stats_s last_stats;
188	struct aq_stats_s curr_stats;
189	u64 speed;
190	u32 itr_tx;
191	u32 itr_rx;
192	unsigned int chip_features;
193	u32 fw_ver_actual;
194	atomic_t dpc;
195	u32 mbox_addr;
196	u32 rpc_addr;
197	u32 settings_addr;
198	u32 rpc_tid;
199	struct hw_atl_utils_fw_rpc rpc;
200	s64 ptp_clk_offset;
201	u16 phy_id;
202	void *priv;
203};
204
205struct aq_ring_s;
206struct aq_ring_param_s;
207struct sk_buff;
208struct aq_rx_filter_l3l4;
209
210struct aq_hw_ops {
211
212	int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
213			       unsigned int frags);
214
215	int (*hw_ring_rx_receive)(struct aq_hw_s *self,
216				  struct aq_ring_s *aq_ring);
217
218	int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
219			       unsigned int sw_tail_old);
220
221	int (*hw_ring_tx_head_update)(struct aq_hw_s *self,
222				      struct aq_ring_s *aq_ring);
223
224	int (*hw_set_mac_address)(struct aq_hw_s *self, const u8 *mac_addr);
225
226	int (*hw_soft_reset)(struct aq_hw_s *self);
227
228	int (*hw_prepare)(struct aq_hw_s *self,
229			  const struct aq_fw_ops **fw_ops);
230
231	int (*hw_reset)(struct aq_hw_s *self);
232
233	int (*hw_init)(struct aq_hw_s *self, const u8 *mac_addr);
234
235	int (*hw_start)(struct aq_hw_s *self);
236
237	int (*hw_stop)(struct aq_hw_s *self);
238
239	int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
240			       struct aq_ring_param_s *aq_ring_param);
241
242	int (*hw_ring_tx_start)(struct aq_hw_s *self,
243				struct aq_ring_s *aq_ring);
244
245	int (*hw_ring_tx_stop)(struct aq_hw_s *self,
246			       struct aq_ring_s *aq_ring);
247
248	int (*hw_ring_rx_init)(struct aq_hw_s *self,
249			       struct aq_ring_s *aq_ring,
250			       struct aq_ring_param_s *aq_ring_param);
251
252	int (*hw_ring_rx_start)(struct aq_hw_s *self,
253				struct aq_ring_s *aq_ring);
254
255	int (*hw_ring_rx_stop)(struct aq_hw_s *self,
256			       struct aq_ring_s *aq_ring);
257
258	int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask);
259
260	int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask);
261
262	int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask);
263
264	int (*hw_packet_filter_set)(struct aq_hw_s *self,
265				    unsigned int packet_filter);
266
267	int (*hw_filter_l3l4_set)(struct aq_hw_s *self,
268				  struct aq_rx_filter_l3l4 *data);
269
270	int (*hw_filter_l3l4_clear)(struct aq_hw_s *self,
271				    struct aq_rx_filter_l3l4 *data);
272
273	int (*hw_filter_l2_set)(struct aq_hw_s *self,
274				struct aq_rx_filter_l2 *data);
275
276	int (*hw_filter_l2_clear)(struct aq_hw_s *self,
277				  struct aq_rx_filter_l2 *data);
278
279	int (*hw_filter_vlan_set)(struct aq_hw_s *self,
280				  struct aq_rx_filter_vlan *aq_vlans);
281
282	int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable);
283
284	int (*hw_multicast_list_set)(struct aq_hw_s *self,
285				     u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX]
286				     [ETH_ALEN],
287				     u32 count);
288
289	int (*hw_interrupt_moderation_set)(struct aq_hw_s *self);
290
291	int (*hw_rss_set)(struct aq_hw_s *self,
292			  struct aq_rss_parameters *rss_params);
293
294	int (*hw_rss_hash_set)(struct aq_hw_s *self,
295			       struct aq_rss_parameters *rss_params);
296
297	int (*hw_tc_rate_limit_set)(struct aq_hw_s *self);
298
299	int (*hw_get_regs)(struct aq_hw_s *self,
300			   const struct aq_hw_caps_s *aq_hw_caps,
301			   u32 *regs_buff);
302
303	struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self);
304
305	u32 (*hw_get_fw_version)(struct aq_hw_s *self);
306
307	int (*hw_set_offload)(struct aq_hw_s *self,
308			      struct aq_nic_cfg_s *aq_nic_cfg);
309
310	int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self,
311				    struct aq_ring_s *aq_ring);
312
313	int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self,
314				       struct aq_ring_s *ring);
315
316	void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp);
317
318	int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta);
319
320	int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta);
321
322	int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts);
323
324	int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time);
325
326	int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start,
327			     u32 period);
328
329	int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index,
330				    u32 enable);
331
332	int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts);
333
334	u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len,
335			     u64 *timestamp);
336
337	int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len,
338			    u64 *timestamp);
339
340	int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc);
341
342	int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable);
343
344	int (*hw_get_mac_temp)(struct aq_hw_s *self, u32 *temp);
345
346	int (*hw_read_module_eeprom)(struct aq_hw_s *self, u8 dev_addr,
347				     u8 reg_start_addr, int len, u8 *data);
348};
349
350struct aq_fw_ops {
351	int (*init)(struct aq_hw_s *self);
352
353	int (*deinit)(struct aq_hw_s *self);
354
355	int (*reset)(struct aq_hw_s *self);
356
357	int (*renegotiate)(struct aq_hw_s *self);
358
359	int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac);
360
361	int (*set_link_speed)(struct aq_hw_s *self, u32 speed);
362
363	int (*set_state)(struct aq_hw_s *self,
364			 enum hal_atl_utils_fw_state_e state);
365
366	int (*update_link_status)(struct aq_hw_s *self);
367
368	int (*update_stats)(struct aq_hw_s *self);
369
370	int (*get_mac_temp)(struct aq_hw_s *self, int *temp);
371
372	int (*get_phy_temp)(struct aq_hw_s *self, int *temp);
373
374	u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode);
375
376	int (*set_flow_control)(struct aq_hw_s *self);
377
378	int (*led_control)(struct aq_hw_s *self, u32 mode);
379
380	int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable);
381
382	int (*set_power)(struct aq_hw_s *self, unsigned int power_state,
383			 const u8 *mac);
384
385	int (*send_fw_request)(struct aq_hw_s *self,
386			       const struct hw_fw_request_iface *fw_req,
387			       size_t size);
388
389	void (*enable_ptp)(struct aq_hw_s *self, int enable);
390
391	void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj);
392
393	int (*set_eee_rate)(struct aq_hw_s *self, u32 speed);
394
395	int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate,
396			    u32 *supported_rates);
397
398	int (*set_downshift)(struct aq_hw_s *self, u32 counter);
399
400	int (*set_media_detect)(struct aq_hw_s *self, bool enable);
401
402	u32 (*get_link_capabilities)(struct aq_hw_s *self);
403
404	int (*send_macsec_req)(struct aq_hw_s *self,
405			       struct macsec_msg_fw_request *msg,
406			       struct macsec_msg_fw_response *resp);
407};
408
409#endif /* AQ_HW_H */