xgene_enet_xgmac.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/* Applied Micro X-Gene SoC Ethernet Driver
  3 *
  4 * Copyright (c) 2014, Applied Micro Circuits Corporation
  5 * Authors: Iyappan Subramanian <isubramanian@apm.com>
  6 *	    Keyur Chudgar <kchudgar@apm.com>
  7 */
  8
  9#include <linux/acpi.h>
 10#include <linux/clk.h>
 11#include <linux/err.h>
 12#include <linux/gpio/consumer.h>
 13#include <linux/io.h>
 14#include <linux/types.h>
 15#include <linux/workqueue.h>
 16
 17#include "xgene_enet_main.h"
 18#include "xgene_enet_hw.h"
 19#include "xgene_enet_xgmac.h"
 20
 21static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
 22			      u32 offset, u32 val)
 23{
 24	void __iomem *addr = pdata->eth_csr_addr + offset;
 25
 26	iowrite32(val, addr);
 27}
 28
 29static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
 30				  u32 offset, u32 val)
 31{
 32	void __iomem *addr = pdata->eth_ring_if_addr + offset;
 33
 34	iowrite32(val, addr);
 35}
 36
 37static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
 38				   u32 offset, u32 val)
 39{
 40	void __iomem *addr = pdata->eth_diag_csr_addr + offset;
 41
 42	iowrite32(val, addr);
 43}
 44
 45static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
 46				   void __iomem *cmd, void __iomem *cmd_done,
 47				   u32 wr_addr, u32 wr_data)
 48{
 49	u32 done;
 50	u8 wait = 10;
 51
 52	iowrite32(wr_addr, addr);
 53	iowrite32(wr_data, wr);
 54	iowrite32(XGENE_ENET_WR_CMD, cmd);
 55
 56	/* wait for write command to complete */
 57	while (!(done = ioread32(cmd_done)) && wait--)
 58		udelay(1);
 59
 60	if (!done)
 61		return false;
 62
 63	iowrite32(0, cmd);
 64
 65	return true;
 66}
 67
 68static void xgene_enet_wr_pcs(struct xgene_enet_pdata *pdata,
 69			      u32 wr_addr, u32 wr_data)
 70{
 71	void __iomem *addr, *wr, *cmd, *cmd_done;
 72
 73	addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET;
 74	wr = pdata->pcs_addr + PCS_WRITE_REG_OFFSET;
 75	cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET;
 76	cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET;
 77
 78	if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
 79		netdev_err(pdata->ndev, "PCS write failed, addr: %04x\n",
 80			   wr_addr);
 81}
 82
 83static void xgene_enet_wr_axg_csr(struct xgene_enet_pdata *pdata,
 84				  u32 offset, u32 val)
 85{
 86	void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
 87
 88	iowrite32(val, addr);
 89}
 90
 91static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
 92			      u32 offset, u32 *val)
 93{
 94	void __iomem *addr = pdata->eth_csr_addr + offset;
 95
 96	*val = ioread32(addr);
 97}
 98
 99static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
100				   u32 offset, u32 *val)
101{
102	void __iomem *addr = pdata->eth_diag_csr_addr + offset;
103
104	*val = ioread32(addr);
105}
106
107static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
108				   void __iomem *cmd, void __iomem *cmd_done,
109				   u32 rd_addr, u32 *rd_data)
110{
111	u32 done;
112	u8 wait = 10;
113
114	iowrite32(rd_addr, addr);
115	iowrite32(XGENE_ENET_RD_CMD, cmd);
116
117	/* wait for read command to complete */
118	while (!(done = ioread32(cmd_done)) && wait--)
119		udelay(1);
120
121	if (!done)
122		return false;
123
124	*rd_data = ioread32(rd);
125	iowrite32(0, cmd);
126
127	return true;
128}
129
130static bool xgene_enet_rd_pcs(struct xgene_enet_pdata *pdata,
131			      u32 rd_addr, u32 *rd_data)
132{
133	void __iomem *addr, *rd, *cmd, *cmd_done;
134	bool success;
135
136	addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET;
137	rd = pdata->pcs_addr + PCS_READ_REG_OFFSET;
138	cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET;
139	cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET;
140
141	success = xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data);
142	if (!success)
143		netdev_err(pdata->ndev, "PCS read failed, addr: %04x\n",
144			   rd_addr);
145
146	return success;
147}
148
149static void xgene_enet_rd_axg_csr(struct xgene_enet_pdata *pdata,
150				  u32 offset, u32 *val)
151{
152	void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
153
154	*val = ioread32(addr);
155}
156
157static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
158{
159	struct net_device *ndev = pdata->ndev;
160	u32 data;
161	u8 wait = 10;
162
163	xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
164	do {
165		usleep_range(100, 110);
166		xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
167	} while ((data != 0xffffffff) && wait--);
168
169	if (data != 0xffffffff) {
170		netdev_err(ndev, "Failed to release memory from shutdown\n");
171		return -ENODEV;
172	}
173
174	return 0;
175}
176
177static void xgene_xgmac_get_drop_cnt(struct xgene_enet_pdata *pdata,
178				     u32 *rx, u32 *tx)
179{
180	u32 count;
181
182	xgene_enet_rd_axg_csr(pdata, XGENET_ICM_ECM_DROP_COUNT_REG0, &count);
183	*rx = ICM_DROP_COUNT(count);
184	*tx = ECM_DROP_COUNT(count);
185	/* Errata: 10GE_4 - ICM_ECM_DROP_COUNT not clear-on-read */
186	xgene_enet_rd_axg_csr(pdata, XGENET_ECM_CONFIG0_REG_0, &count);
187}
188
189static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
190{
191	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);
192	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0);
193	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0);
194	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0);
195}
196
197static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)
198{
199	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST);
200	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);
201}
202
203static void xgene_pcs_reset(struct xgene_enet_pdata *pdata)
204{
205	u32 data;
206
207	if (!xgene_enet_rd_pcs(pdata, PCS_CONTROL_1, &data))
208		return;
209
210	xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data | PCS_CTRL_PCS_RST);
211	xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data & ~PCS_CTRL_PCS_RST);
212}
213
214static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
215{
216	const u8 *dev_addr = pdata->ndev->dev_addr;
217	u32 addr0, addr1;
218
219	addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
220		(dev_addr[1] << 8) | dev_addr[0];
221	addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
222
223	xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0);
224	xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
225}
226
227static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata,
228				u16 mss, u8 index)
229{
230	u8 offset;
231	u32 data;
232
233	offset = (index < 2) ? 0 : 4;
234	xgene_enet_rd_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, &data);
235
236	if (!(index & 0x1))
237		data = SET_VAL(TSO_MSS1, data >> TSO_MSS1_POS) |
238			SET_VAL(TSO_MSS0, mss);
239	else
240		data = SET_VAL(TSO_MSS1, mss) | SET_VAL(TSO_MSS0, data);
241
242	xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, data);
243}
244
245static void xgene_xgmac_set_frame_size(struct xgene_enet_pdata *pdata, int size)
246{
247	xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR,
248			  ((((size + 2) >> 2) << 16) | size));
249}
250
251static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
252{
253	u32 data;
254
255	xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data);
256
257	return data;
258}
259
260static void xgene_xgmac_enable_tx_pause(struct xgene_enet_pdata *pdata,
261					bool enable)
262{
263	u32 data;
264
265	xgene_enet_rd_axg_csr(pdata, XGENET_CSR_ECM_CFG_0_ADDR, &data);
266
267	if (enable)
268		data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN;
269	else
270		data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN);
271
272	xgene_enet_wr_axg_csr(pdata, XGENET_CSR_ECM_CFG_0_ADDR, data);
273}
274
275static void xgene_xgmac_flowctl_tx(struct xgene_enet_pdata *pdata, bool enable)
276{
277	u32 data;
278
279	data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1);
280
281	if (enable)
282		data |= HSTTCTLEN;
283	else
284		data &= ~HSTTCTLEN;
285
286	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
287
288	pdata->mac_ops->enable_tx_pause(pdata, enable);
289}
290
291static void xgene_xgmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable)
292{
293	u32 data;
294
295	data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1);
296
297	if (enable)
298		data |= HSTRCTLEN;
299	else
300		data &= ~HSTRCTLEN;
301
302	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
303}
304
305static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
306{
307	u32 data;
308
309	xgene_xgmac_reset(pdata);
310
311	data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1);
312	data |= HSTPPEN;
313	data &= ~HSTLENCHK;
314	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
315
316	xgene_xgmac_set_mac_addr(pdata);
317
318	xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
319	data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
320	/* Errata 10GE_1 - FIFO threshold default value incorrect */
321	RSIF_CLE_BUFF_THRESH_SET(&data, XG_RSIF_CLE_BUFF_THRESH);
322	xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);
323
324	/* Errata 10GE_1 - FIFO threshold default value incorrect */
325	xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data);
326	RSIF_PLC_CLE_BUFF_THRESH_SET(&data, XG_RSIF_PLC_CLE_BUFF_THRESH);
327	xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, data);
328
329	xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);
330	data |= BIT(12);
331	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
332	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);
333	xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);
334	xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);
335
336	/* Configure HW pause frame generation */
337	xgene_enet_rd_axg_csr(pdata, XGENET_CSR_MULTI_DPF0_ADDR, &data);
338	data = (DEF_QUANTA << 16) | (data & 0xFFFF);
339	xgene_enet_wr_axg_csr(pdata, XGENET_CSR_MULTI_DPF0_ADDR, data);
340
341	if (pdata->enet_id != XGENE_ENET1) {
342		xgene_enet_rd_axg_csr(pdata, XGENET_CSR_MULTI_DPF1_ADDR, &data);
343		data = (NORM_PAUSE_OPCODE << 16) | (data & 0xFFFF);
344		xgene_enet_wr_axg_csr(pdata, XGENET_CSR_MULTI_DPF1_ADDR, data);
345	}
346
347	data = (XG_DEF_PAUSE_OFF_THRES << 16) | XG_DEF_PAUSE_THRES;
348	xgene_enet_wr_csr(pdata, XG_RXBUF_PAUSE_THRESH, data);
349
350	xgene_xgmac_flowctl_tx(pdata, pdata->tx_pause);
351	xgene_xgmac_flowctl_rx(pdata, pdata->rx_pause);
352}
353
354static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata)
355{
356	u32 data;
357
358	data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1);
359	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN);
360}
361
362static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata)
363{
364	u32 data;
365
366	data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1);
367	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN);
368}
369
370static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata)
371{
372	u32 data;
373
374	data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1);
375	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN);
376}
377
378static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata)
379{
380	u32 data;
381
382	data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1);
383	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN);
384}
385
386static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
387{
388	struct device *dev = &pdata->pdev->dev;
389
390	if (!xgene_ring_mgr_init(pdata))
391		return -ENODEV;
392
393	if (dev->of_node) {
394		clk_prepare_enable(pdata->clk);
395		udelay(5);
396		clk_disable_unprepare(pdata->clk);
397		udelay(5);
398		clk_prepare_enable(pdata->clk);
399		udelay(5);
400	} else {
401#ifdef CONFIG_ACPI
402		acpi_status status;
403
404		status = acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
405					      "_RST", NULL, NULL);
406		if (ACPI_FAILURE(status)) {
407			acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
408					     "_INI", NULL, NULL);
409		}
410#endif
411	}
412
413	xgene_enet_ecc_init(pdata);
414	xgene_enet_config_ring_if_assoc(pdata);
415
416	return 0;
417}
418
419static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,
420				    u32 dst_ring_num, u16 bufpool_id,
421				    u16 nxtbufpool_id)
422{
423	u32 cb, fpsel, nxtfpsel;
424
425	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb);
426	cb |= CFG_CLE_BYPASS_EN0;
427	CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
428	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);
429
430	fpsel = xgene_enet_get_fpsel(bufpool_id);
431	nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id);
432	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);
433	CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
434	CFG_CLE_FPSEL0_SET(&cb, fpsel);
435	CFG_CLE_NXTFPSEL0_SET(&cb, nxtfpsel);
436	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);
437	pr_info("+ cle_bypass: fpsel: %d nxtfpsel: %d\n", fpsel, nxtfpsel);
438}
439
440static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
441{
442	struct device *dev = &pdata->pdev->dev;
443
444	if (dev->of_node) {
445		if (!IS_ERR(pdata->clk))
446			clk_disable_unprepare(pdata->clk);
447	}
448}
449
450static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
451			     struct xgene_enet_desc_ring *ring)
452{
453	u32 addr, data;
454
455	if (xgene_enet_is_bufpool(ring->id)) {
456		addr = ENET_CFGSSQMIFPRESET_ADDR;
457		data = BIT(xgene_enet_get_fpsel(ring->id));
458	} else {
459		addr = ENET_CFGSSQMIWQRESET_ADDR;
460		data = BIT(xgene_enet_ring_bufnum(ring->id));
461	}
462
463	xgene_enet_wr_ring_if(pdata, addr, data);
464}
465
466static int xgene_enet_gpio_lookup(struct xgene_enet_pdata *pdata)
467{
468	struct device *dev = &pdata->pdev->dev;
469
470	pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN);
471	if (IS_ERR(pdata->sfp_rdy))
472		pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN);
473
474	if (IS_ERR(pdata->sfp_rdy))
475		return -ENODEV;
476
477	return 0;
478}
479
480static void xgene_enet_link_state(struct work_struct *work)
481{
482	struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),
483					 struct xgene_enet_pdata, link_work);
484	struct net_device *ndev = pdata->ndev;
485	u32 link_status, poll_interval;
486
487	link_status = xgene_enet_link_status(pdata);
488	if (pdata->sfp_gpio_en && link_status &&
489	    (!IS_ERR(pdata->sfp_rdy) || !xgene_enet_gpio_lookup(pdata)) &&
490	    !gpiod_get_value(pdata->sfp_rdy))
491		link_status = 0;
492
493	if (link_status) {
494		if (!netif_carrier_ok(ndev)) {
495			netif_carrier_on(ndev);
496			xgene_xgmac_rx_enable(pdata);
497			xgene_xgmac_tx_enable(pdata);
498			netdev_info(ndev, "Link is Up - 10Gbps\n");
499		}
500		poll_interval = PHY_POLL_LINK_ON;
501	} else {
502		if (netif_carrier_ok(ndev)) {
503			xgene_xgmac_rx_disable(pdata);
504			xgene_xgmac_tx_disable(pdata);
505			netif_carrier_off(ndev);
506			netdev_info(ndev, "Link is Down\n");
507		}
508		poll_interval = PHY_POLL_LINK_OFF;
509
510		xgene_pcs_reset(pdata);
511	}
512
513	schedule_delayed_work(&pdata->link_work, poll_interval);
514}
515
516const struct xgene_mac_ops xgene_xgmac_ops = {
517	.init = xgene_xgmac_init,
518	.reset = xgene_xgmac_reset,
519	.rx_enable = xgene_xgmac_rx_enable,
520	.tx_enable = xgene_xgmac_tx_enable,
521	.rx_disable = xgene_xgmac_rx_disable,
522	.tx_disable = xgene_xgmac_tx_disable,
523	.set_mac_addr = xgene_xgmac_set_mac_addr,
524	.set_framesize = xgene_xgmac_set_frame_size,
525	.set_mss = xgene_xgmac_set_mss,
526	.get_drop_cnt = xgene_xgmac_get_drop_cnt,
527	.link_state = xgene_enet_link_state,
528	.enable_tx_pause = xgene_xgmac_enable_tx_pause,
529	.flowctl_rx = xgene_xgmac_flowctl_rx,
530	.flowctl_tx = xgene_xgmac_flowctl_tx
531};
532
533const struct xgene_port_ops xgene_xgport_ops = {
534	.reset = xgene_enet_reset,
535	.clear = xgene_enet_clear,
536	.cle_bypass = xgene_enet_xgcle_bypass,
537	.shutdown = xgene_enet_shutdown,
538};