xgene_enet_hw.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/* Applied Micro X-Gene SoC Ethernet Driver
   3 *
   4 * Copyright (c) 2014, Applied Micro Circuits Corporation
   5 * Authors: Iyappan Subramanian <isubramanian@apm.com>
   6 *	    Ravi Patel <rapatel@apm.com>
   7 *	    Keyur Chudgar <kchudgar@apm.com>
   8 */
   9
  10#include "xgene_enet_main.h"
  11#include "xgene_enet_hw.h"
  12
  13static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
  14{
  15	u32 *ring_cfg = ring->state;
  16	u64 addr = ring->dma;
  17	enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;
  18
  19	ring_cfg[4] |= (1 << SELTHRSH_POS) &
  20			CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN);
  21	ring_cfg[3] |= ACCEPTLERR;
  22	ring_cfg[2] |= QCOHERENT;
  23
  24	addr >>= 8;
  25	ring_cfg[2] |= (addr << RINGADDRL_POS) &
  26			CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN);
  27	addr >>= RINGADDRL_LEN;
  28	ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN);
  29	ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) &
  30			CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN);
  31}
  32
  33static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
  34{
  35	u32 *ring_cfg = ring->state;
  36	bool is_bufpool;
  37	u32 val;
  38
  39	is_bufpool = xgene_enet_is_bufpool(ring->id);
  40	val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR;
  41	ring_cfg[4] |= (val << RINGTYPE_POS) &
  42			CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN);
  43
  44	if (is_bufpool) {
  45		ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) &
  46				CREATE_MASK(RINGMODE_POS, RINGMODE_LEN);
  47	}
  48}
  49
  50static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
  51{
  52	u32 *ring_cfg = ring->state;
  53
  54	ring_cfg[3] |= RECOMBBUF;
  55	ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) &
  56			CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN);
  57	ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN);
  58}
  59
  60static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
  61				 u32 offset, u32 data)
  62{
  63	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
  64
  65	iowrite32(data, pdata->ring_csr_addr + offset);
  66}
  67
  68static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,
  69				 u32 offset, u32 *data)
  70{
  71	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
  72
  73	*data = ioread32(pdata->ring_csr_addr + offset);
  74}
  75
  76static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
  77{
  78	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
  79	int i;
  80
  81	xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
  82	for (i = 0; i < pdata->ring_ops->num_ring_config; i++) {
  83		xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
  84				     ring->state[i]);
  85	}
  86}
  87
  88static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
  89{
  90	memset(ring->state, 0, sizeof(ring->state));
  91	xgene_enet_write_ring_state(ring);
  92}
  93
  94static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
  95{
  96	xgene_enet_ring_set_type(ring);
  97
  98	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 ||
  99	    xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1)
 100		xgene_enet_ring_set_recombbuf(ring);
 101
 102	xgene_enet_ring_init(ring);
 103	xgene_enet_write_ring_state(ring);
 104}
 105
 106static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
 107{
 108	u32 ring_id_val, ring_id_buf;
 109	bool is_bufpool;
 110
 111	is_bufpool = xgene_enet_is_bufpool(ring->id);
 112
 113	ring_id_val = ring->id & GENMASK(9, 0);
 114	ring_id_val |= OVERWRITE;
 115
 116	ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
 117	ring_id_buf |= PREFETCH_BUF_EN;
 118	if (is_bufpool)
 119		ring_id_buf |= IS_BUFFER_POOL;
 120
 121	xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
 122	xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
 123}
 124
 125static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
 126{
 127	u32 ring_id;
 128
 129	ring_id = ring->id | OVERWRITE;
 130	xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
 131	xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
 132}
 133
 134static struct xgene_enet_desc_ring *xgene_enet_setup_ring(
 135				    struct xgene_enet_desc_ring *ring)
 136{
 137	u32 size = ring->size;
 138	u32 i, data;
 139	bool is_bufpool;
 140
 141	xgene_enet_clr_ring_state(ring);
 142	xgene_enet_set_ring_state(ring);
 143	xgene_enet_set_ring_id(ring);
 144
 145	ring->slots = xgene_enet_get_numslots(ring->id, size);
 146
 147	is_bufpool = xgene_enet_is_bufpool(ring->id);
 148	if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
 149		return ring;
 150
 151	for (i = 0; i < ring->slots; i++)
 152		xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
 153
 154	xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
 155	data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));
 156	xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
 157
 158	return ring;
 159}
 160
 161static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
 162{
 163	u32 data;
 164	bool is_bufpool;
 165
 166	is_bufpool = xgene_enet_is_bufpool(ring->id);
 167	if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
 168		goto out;
 169
 170	xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
 171	data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));
 172	xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
 173
 174out:
 175	xgene_enet_clr_desc_ring_id(ring);
 176	xgene_enet_clr_ring_state(ring);
 177}
 178
 179static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)
 180{
 181	iowrite32(count, ring->cmd);
 182}
 183
 184static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
 185{
 186	u32 __iomem *cmd_base = ring->cmd_base;
 187	u32 ring_state, num_msgs;
 188
 189	ring_state = ioread32(&cmd_base[1]);
 190	num_msgs = GET_VAL(NUMMSGSINQ, ring_state);
 191
 192	return num_msgs;
 193}
 194
 195void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
 196			    enum xgene_enet_err_code status)
 197{
 198	switch (status) {
 199	case INGRESS_CRC:
 200		ring->rx_crc_errors++;
 201		break;
 202	case INGRESS_CHECKSUM:
 203	case INGRESS_CHECKSUM_COMPUTE:
 204		ring->rx_errors++;
 205		break;
 206	case INGRESS_TRUNC_FRAME:
 207		ring->rx_frame_errors++;
 208		break;
 209	case INGRESS_PKT_LEN:
 210		ring->rx_length_errors++;
 211		break;
 212	case INGRESS_PKT_UNDER:
 213		ring->rx_frame_errors++;
 214		break;
 215	case INGRESS_FIFO_OVERRUN:
 216		ring->rx_fifo_errors++;
 217		break;
 218	default:
 219		break;
 220	}
 221}
 222
 223static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
 224			      u32 offset, u32 val)
 225{
 226	void __iomem *addr = pdata->eth_csr_addr + offset;
 227
 228	iowrite32(val, addr);
 229}
 230
 231static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
 232				  u32 offset, u32 val)
 233{
 234	void __iomem *addr = pdata->eth_ring_if_addr + offset;
 235
 236	iowrite32(val, addr);
 237}
 238
 239static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
 240				   u32 offset, u32 val)
 241{
 242	void __iomem *addr = pdata->eth_diag_csr_addr + offset;
 243
 244	iowrite32(val, addr);
 245}
 246
 247static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
 248				  u32 offset, u32 val)
 249{
 250	void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
 251
 252	iowrite32(val, addr);
 253}
 254
 255void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, u32 wr_data)
 256{
 257	void __iomem *addr, *wr, *cmd, *cmd_done;
 258	struct net_device *ndev = pdata->ndev;
 259	u8 wait = 10;
 260	u32 done;
 261
 262	if (pdata->mdio_driver && ndev->phydev &&
 263	    phy_interface_mode_is_rgmii(pdata->phy_mode)) {
 264		struct mii_bus *bus = ndev->phydev->mdio.bus;
 265
 266		return xgene_mdio_wr_mac(bus->priv, wr_addr, wr_data);
 267	}
 268
 269	addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
 270	wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
 271	cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
 272	cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
 273
 274	spin_lock(&pdata->mac_lock);
 275	iowrite32(wr_addr, addr);
 276	iowrite32(wr_data, wr);
 277	iowrite32(XGENE_ENET_WR_CMD, cmd);
 278
 279	while (!(done = ioread32(cmd_done)) && wait--)
 280		udelay(1);
 281
 282	if (!done)
 283		netdev_err(ndev, "mac write failed, addr: %04x data: %08x\n",
 284			   wr_addr, wr_data);
 285
 286	iowrite32(0, cmd);
 287	spin_unlock(&pdata->mac_lock);
 288}
 289
 290static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
 291			      u32 offset, u32 *val)
 292{
 293	void __iomem *addr = pdata->eth_csr_addr + offset;
 294
 295	*val = ioread32(addr);
 296}
 297
 298static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
 299				   u32 offset, u32 *val)
 300{
 301	void __iomem *addr = pdata->eth_diag_csr_addr + offset;
 302
 303	*val = ioread32(addr);
 304}
 305
 306static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata,
 307				  u32 offset, u32 *val)
 308{
 309	void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
 310
 311	*val = ioread32(addr);
 312}
 313
 314u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr)
 315{
 316	void __iomem *addr, *rd, *cmd, *cmd_done;
 317	struct net_device *ndev = pdata->ndev;
 318	u32 done, rd_data;
 319	u8 wait = 10;
 320
 321	if (pdata->mdio_driver && ndev->phydev &&
 322	    phy_interface_mode_is_rgmii(pdata->phy_mode)) {
 323		struct mii_bus *bus = ndev->phydev->mdio.bus;
 324
 325		return xgene_mdio_rd_mac(bus->priv, rd_addr);
 326	}
 327
 328	addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
 329	rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
 330	cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
 331	cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
 332
 333	spin_lock(&pdata->mac_lock);
 334	iowrite32(rd_addr, addr);
 335	iowrite32(XGENE_ENET_RD_CMD, cmd);
 336
 337	while (!(done = ioread32(cmd_done)) && wait--)
 338		udelay(1);
 339
 340	if (!done)
 341		netdev_err(ndev, "mac read failed, addr: %04x\n", rd_addr);
 342
 343	rd_data = ioread32(rd);
 344	iowrite32(0, cmd);
 345	spin_unlock(&pdata->mac_lock);
 346
 347	return rd_data;
 348}
 349
 350u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr)
 351{
 352	void __iomem *addr, *rd, *cmd, *cmd_done;
 353	u32 done, rd_data;
 354	u8 wait = 10;
 355
 356	addr = pdata->mcx_stats_addr + STAT_ADDR_REG_OFFSET;
 357	rd = pdata->mcx_stats_addr + STAT_READ_REG_OFFSET;
 358	cmd = pdata->mcx_stats_addr + STAT_COMMAND_REG_OFFSET;
 359	cmd_done = pdata->mcx_stats_addr + STAT_COMMAND_DONE_REG_OFFSET;
 360
 361	spin_lock(&pdata->stats_lock);
 362	iowrite32(rd_addr, addr);
 363	iowrite32(XGENE_ENET_RD_CMD, cmd);
 364
 365	while (!(done = ioread32(cmd_done)) && wait--)
 366		udelay(1);
 367
 368	if (!done)
 369		netdev_err(pdata->ndev, "mac stats read failed, addr: %04x\n",
 370			   rd_addr);
 371
 372	rd_data = ioread32(rd);
 373	iowrite32(0, cmd);
 374	spin_unlock(&pdata->stats_lock);
 375
 376	return rd_data;
 377}
 378
 379static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata)
 380{
 381	const u8 *dev_addr = pdata->ndev->dev_addr;
 382	u32 addr0, addr1;
 383
 384	addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
 385		(dev_addr[1] << 8) | dev_addr[0];
 386	addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
 387
 388	xgene_enet_wr_mac(pdata, STATION_ADDR0_ADDR, addr0);
 389	xgene_enet_wr_mac(pdata, STATION_ADDR1_ADDR, addr1);
 390}
 391
 392static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
 393{
 394	struct net_device *ndev = pdata->ndev;
 395	u32 data;
 396	u8 wait = 10;
 397
 398	xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
 399	do {
 400		usleep_range(100, 110);
 401		xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
 402	} while ((data != 0xffffffff) && wait--);
 403
 404	if (data != 0xffffffff) {
 405		netdev_err(ndev, "Failed to release memory from shutdown\n");
 406		return -ENODEV;
 407	}
 408
 409	return 0;
 410}
 411
 412static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
 413{
 414	xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1);
 415	xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, 0);
 416}
 417
 418static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata)
 419{
 420	struct device *dev = &pdata->pdev->dev;
 421
 422	if (dev->of_node) {
 423		struct clk *parent = clk_get_parent(pdata->clk);
 424		long rate = rgmii_clock(pdata->phy_speed);
 425
 426		if (rate < 0)
 427			rate = 125000000;
 428
 429		clk_set_rate(parent, rate);
 430	}
 431#ifdef CONFIG_ACPI
 432	else {
 433		switch (pdata->phy_speed) {
 434		case SPEED_10:
 435			acpi_evaluate_object(ACPI_HANDLE(dev),
 436					     "S10", NULL, NULL);
 437			break;
 438		case SPEED_100:
 439			acpi_evaluate_object(ACPI_HANDLE(dev),
 440					     "S100", NULL, NULL);
 441			break;
 442		default:
 443			acpi_evaluate_object(ACPI_HANDLE(dev),
 444					     "S1G", NULL, NULL);
 445			break;
 446		}
 447	}
 448#endif
 449}
 450
 451static void xgene_gmac_set_speed(struct xgene_enet_pdata *pdata)
 452{
 453	u32 icm0, icm2, mc2;
 454	u32 intf_ctl, rgmii, value;
 455
 456	xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0);
 457	xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2);
 458	mc2 = xgene_enet_rd_mac(pdata, MAC_CONFIG_2_ADDR);
 459	intf_ctl = xgene_enet_rd_mac(pdata, INTERFACE_CONTROL_ADDR);
 460	xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii);
 461
 462	switch (pdata->phy_speed) {
 463	case SPEED_10:
 464		ENET_INTERFACE_MODE2_SET(&mc2, 1);
 465		intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE);
 466		CFG_MACMODE_SET(&icm0, 0);
 467		CFG_WAITASYNCRD_SET(&icm2, 500);
 468		rgmii &= ~CFG_SPEED_1250;
 469		break;
 470	case SPEED_100:
 471		ENET_INTERFACE_MODE2_SET(&mc2, 1);
 472		intf_ctl &= ~ENET_GHD_MODE;
 473		intf_ctl |= ENET_LHD_MODE;
 474		CFG_MACMODE_SET(&icm0, 1);
 475		CFG_WAITASYNCRD_SET(&icm2, 80);
 476		rgmii &= ~CFG_SPEED_1250;
 477		break;
 478	default:
 479		ENET_INTERFACE_MODE2_SET(&mc2, 2);
 480		intf_ctl &= ~ENET_LHD_MODE;
 481		intf_ctl |= ENET_GHD_MODE;
 482		CFG_MACMODE_SET(&icm0, 2);
 483		CFG_WAITASYNCRD_SET(&icm2, 0);
 484		CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay);
 485		CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay);
 486		rgmii |= CFG_SPEED_1250;
 487
 488		xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
 489		value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
 490		xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
 491		break;
 492	}
 493
 494	mc2 |= FULL_DUPLEX2 | PAD_CRC | LENGTH_CHK;
 495	xgene_enet_wr_mac(pdata, MAC_CONFIG_2_ADDR, mc2);
 496	xgene_enet_wr_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl);
 497	xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
 498	xgene_enet_configure_clock(pdata);
 499
 500	xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0);
 501	xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2);
 502}
 503
 504static void xgene_enet_set_frame_size(struct xgene_enet_pdata *pdata, int size)
 505{
 506	xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size);
 507}
 508
 509static void xgene_gmac_enable_tx_pause(struct xgene_enet_pdata *pdata,
 510				       bool enable)
 511{
 512	u32 data;
 513
 514	xgene_enet_rd_mcx_csr(pdata, CSR_ECM_CFG_0_ADDR, &data);
 515
 516	if (enable)
 517		data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN;
 518	else
 519		data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN);
 520
 521	xgene_enet_wr_mcx_csr(pdata, CSR_ECM_CFG_0_ADDR, data);
 522}
 523
 524static void xgene_gmac_flowctl_tx(struct xgene_enet_pdata *pdata, bool enable)
 525{
 526	u32 data;
 527
 528	data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
 529
 530	if (enable)
 531		data |= TX_FLOW_EN;
 532	else
 533		data &= ~TX_FLOW_EN;
 534
 535	xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data);
 536
 537	pdata->mac_ops->enable_tx_pause(pdata, enable);
 538}
 539
 540static void xgene_gmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable)
 541{
 542	u32 data;
 543
 544	data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
 545
 546	if (enable)
 547		data |= RX_FLOW_EN;
 548	else
 549		data &= ~RX_FLOW_EN;
 550
 551	xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data);
 552}
 553
 554static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
 555{
 556	u32 value;
 557
 558	if (!pdata->mdio_driver)
 559		xgene_gmac_reset(pdata);
 560
 561	xgene_gmac_set_speed(pdata);
 562	xgene_gmac_set_mac_addr(pdata);
 563
 564	/* Adjust MDC clock frequency */
 565	value = xgene_enet_rd_mac(pdata, MII_MGMT_CONFIG_ADDR);
 566	MGMT_CLOCK_SEL_SET(&value, 7);
 567	xgene_enet_wr_mac(pdata, MII_MGMT_CONFIG_ADDR, value);
 568
 569	/* Enable drop if bufpool not available */
 570	xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value);
 571	value |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
 572	xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value);
 573
 574	/* Rtype should be copied from FP */
 575	xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
 576
 577	/* Configure HW pause frame generation */
 578	xgene_enet_rd_mcx_csr(pdata, CSR_MULTI_DPF0_ADDR, &value);
 579	value = (DEF_QUANTA << 16) | (value & 0xFFFF);
 580	xgene_enet_wr_mcx_csr(pdata, CSR_MULTI_DPF0_ADDR, value);
 581
 582	xgene_enet_wr_csr(pdata, RXBUF_PAUSE_THRESH, DEF_PAUSE_THRES);
 583	xgene_enet_wr_csr(pdata, RXBUF_PAUSE_OFF_THRESH, DEF_PAUSE_OFF_THRES);
 584
 585	xgene_gmac_flowctl_tx(pdata, pdata->tx_pause);
 586	xgene_gmac_flowctl_rx(pdata, pdata->rx_pause);
 587
 588	/* Rx-Tx traffic resume */
 589	xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
 590
 591	xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value);
 592	value &= ~TX_DV_GATE_EN0;
 593	value &= ~RX_DV_GATE_EN0;
 594	value |= RESUME_RX0;
 595	xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value);
 596
 597	xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
 598}
 599
 600static void xgene_gmac_get_drop_cnt(struct xgene_enet_pdata *pdata,
 601				    u32 *rx, u32 *tx)
 602{
 603	u32 count;
 604
 605	xgene_enet_rd_mcx_csr(pdata, ICM_ECM_DROP_COUNT_REG0_ADDR, &count);
 606	*rx = ICM_DROP_COUNT(count);
 607	*tx = ECM_DROP_COUNT(count);
 608	/* Errata: 10GE_4 - Fix ICM_ECM_DROP_COUNT not clear-on-read */
 609	xgene_enet_rd_mcx_csr(pdata, ECM_CONFIG0_REG_0_ADDR, &count);
 610}
 611
 612static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
 613{
 614	u32 val = 0xffffffff;
 615
 616	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val);
 617	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val);
 618	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val);
 619	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val);
 620}
 621
 622static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
 623				  u32 dst_ring_num, u16 bufpool_id,
 624				  u16 nxtbufpool_id)
 625{
 626	u32 cb;
 627	u32 fpsel, nxtfpsel;
 628
 629	fpsel = xgene_enet_get_fpsel(bufpool_id);
 630	nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id);
 631
 632	xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
 633	cb |= CFG_CLE_BYPASS_EN0;
 634	CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
 635	CFG_CLE_IP_HDR_LEN_SET(&cb, 0);
 636	xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
 637
 638	xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
 639	CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
 640	CFG_CLE_FPSEL0_SET(&cb, fpsel);
 641	CFG_CLE_NXTFPSEL0_SET(&cb, nxtfpsel);
 642	xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb);
 643}
 644
 645static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata)
 646{
 647	u32 data;
 648
 649	data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
 650	xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN);
 651}
 652
 653static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata)
 654{
 655	u32 data;
 656
 657	data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
 658	xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN);
 659}
 660
 661static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata)
 662{
 663	u32 data;
 664
 665	data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
 666	xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN);
 667}
 668
 669static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata)
 670{
 671	u32 data;
 672
 673	data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
 674	xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN);
 675}
 676
 677bool xgene_ring_mgr_init(struct xgene_enet_pdata *p)
 678{
 679	if (!ioread32(p->ring_csr_addr + CLKEN_ADDR))
 680		return false;
 681
 682	if (ioread32(p->ring_csr_addr + SRST_ADDR))
 683		return false;
 684
 685	return true;
 686}
 687
 688static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
 689{
 690	struct device *dev = &pdata->pdev->dev;
 691
 692	if (!xgene_ring_mgr_init(pdata))
 693		return -ENODEV;
 694
 695	if (pdata->mdio_driver) {
 696		xgene_enet_config_ring_if_assoc(pdata);
 697		return 0;
 698	}
 699
 700	if (dev->of_node) {
 701		clk_prepare_enable(pdata->clk);
 702		udelay(5);
 703		clk_disable_unprepare(pdata->clk);
 704		udelay(5);
 705		clk_prepare_enable(pdata->clk);
 706		udelay(5);
 707	} else {
 708#ifdef CONFIG_ACPI
 709		acpi_status status;
 710
 711		status = acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
 712					      "_RST", NULL, NULL);
 713		if (ACPI_FAILURE(status)) {
 714			acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
 715					     "_INI", NULL, NULL);
 716		}
 717#endif
 718	}
 719
 720	xgene_enet_ecc_init(pdata);
 721	xgene_enet_config_ring_if_assoc(pdata);
 722
 723	return 0;
 724}
 725
 726static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
 727			     struct xgene_enet_desc_ring *ring)
 728{
 729	u32 addr, data;
 730
 731	if (xgene_enet_is_bufpool(ring->id)) {
 732		addr = ENET_CFGSSQMIFPRESET_ADDR;
 733		data = BIT(xgene_enet_get_fpsel(ring->id));
 734	} else {
 735		addr = ENET_CFGSSQMIWQRESET_ADDR;
 736		data = BIT(xgene_enet_ring_bufnum(ring->id));
 737	}
 738
 739	xgene_enet_wr_ring_if(pdata, addr, data);
 740}
 741
 742static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata)
 743{
 744	struct device *dev = &pdata->pdev->dev;
 745
 746	if (dev->of_node) {
 747		if (!IS_ERR(pdata->clk))
 748			clk_disable_unprepare(pdata->clk);
 749	}
 750}
 751
 752static u32 xgene_enet_flowctrl_cfg(struct net_device *ndev)
 753{
 754	struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 755	struct phy_device *phydev = ndev->phydev;
 756	u16 lcladv, rmtadv = 0;
 757	u32 rx_pause, tx_pause;
 758	u8 flowctl = 0;
 759
 760	if (!phydev->duplex || !pdata->pause_autoneg)
 761		return 0;
 762
 763	if (pdata->tx_pause)
 764		flowctl |= FLOW_CTRL_TX;
 765
 766	if (pdata->rx_pause)
 767		flowctl |= FLOW_CTRL_RX;
 768
 769	lcladv = mii_advertise_flowctrl(flowctl);
 770
 771	if (phydev->pause)
 772		rmtadv = LPA_PAUSE_CAP;
 773
 774	if (phydev->asym_pause)
 775		rmtadv |= LPA_PAUSE_ASYM;
 776
 777	flowctl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
 778	tx_pause = !!(flowctl & FLOW_CTRL_TX);
 779	rx_pause = !!(flowctl & FLOW_CTRL_RX);
 780
 781	if (tx_pause != pdata->tx_pause) {
 782		pdata->tx_pause = tx_pause;
 783		pdata->mac_ops->flowctl_tx(pdata, pdata->tx_pause);
 784	}
 785
 786	if (rx_pause != pdata->rx_pause) {
 787		pdata->rx_pause = rx_pause;
 788		pdata->mac_ops->flowctl_rx(pdata, pdata->rx_pause);
 789	}
 790
 791	return 0;
 792}
 793
 794static void xgene_enet_adjust_link(struct net_device *ndev)
 795{
 796	struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 797	const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
 798	struct phy_device *phydev = ndev->phydev;
 799
 800	if (phydev->link) {
 801		if (pdata->phy_speed != phydev->speed) {
 802			pdata->phy_speed = phydev->speed;
 803			mac_ops->set_speed(pdata);
 804			mac_ops->rx_enable(pdata);
 805			mac_ops->tx_enable(pdata);
 806			phy_print_status(phydev);
 807		}
 808
 809		xgene_enet_flowctrl_cfg(ndev);
 810	} else {
 811		mac_ops->rx_disable(pdata);
 812		mac_ops->tx_disable(pdata);
 813		pdata->phy_speed = SPEED_UNKNOWN;
 814		phy_print_status(phydev);
 815	}
 816}
 817
 818#ifdef CONFIG_ACPI
 819static struct acpi_device *acpi_phy_find_device(struct device *dev)
 820{
 821	struct fwnode_reference_args args;
 822	struct fwnode_handle *fw_node;
 823	int status;
 824
 825	fw_node = acpi_fwnode_handle(ACPI_COMPANION(dev));
 826	status = acpi_node_get_property_reference(fw_node, "phy-handle", 0,
 827						  &args);
 828	if (ACPI_FAILURE(status) || !is_acpi_device_node(args.fwnode)) {
 829		dev_dbg(dev, "No matching phy in ACPI table\n");
 830		return NULL;
 831	}
 832
 833	return to_acpi_device_node(args.fwnode);
 834}
 835#endif
 836
 837int xgene_enet_phy_connect(struct net_device *ndev)
 838{
 839	struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 840	struct device_node *np;
 841	struct phy_device *phy_dev;
 842	struct device *dev = &pdata->pdev->dev;
 843	int i;
 844
 845	if (dev->of_node) {
 846		for (i = 0 ; i < 2; i++) {
 847			np = of_parse_phandle(dev->of_node, "phy-handle", i);
 848			phy_dev = of_phy_connect(ndev, np,
 849						 &xgene_enet_adjust_link,
 850						 0, pdata->phy_mode);
 851			of_node_put(np);
 852			if (phy_dev)
 853				break;
 854		}
 855
 856		if (!phy_dev) {
 857			netdev_err(ndev, "Could not connect to PHY\n");
 858			return -ENODEV;
 859		}
 860	} else {
 861#ifdef CONFIG_ACPI
 862		struct acpi_device *adev = acpi_phy_find_device(dev);
 863		if (adev)
 864			phy_dev = adev->driver_data;
 865		else
 866			phy_dev = NULL;
 867
 868		if (!phy_dev ||
 869		    phy_connect_direct(ndev, phy_dev, &xgene_enet_adjust_link,
 870				       pdata->phy_mode)) {
 871			netdev_err(ndev, "Could not connect to PHY\n");
 872			return  -ENODEV;
 873		}
 874#else
 875		return -ENODEV;
 876#endif
 877	}
 878
 879	pdata->phy_speed = SPEED_UNKNOWN;
 880	phy_remove_link_mode(phy_dev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
 881	phy_remove_link_mode(phy_dev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
 882	phy_remove_link_mode(phy_dev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
 883	phy_support_asym_pause(phy_dev);
 884
 885	return 0;
 886}
 887
 888static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata,
 889				  struct mii_bus *mdio)
 890{
 891	struct device *dev = &pdata->pdev->dev;
 892	struct net_device *ndev = pdata->ndev;
 893	struct phy_device *phy;
 894	struct device_node *child_np;
 895	struct device_node *mdio_np = NULL;
 896	u32 phy_addr;
 897	int ret;
 898
 899	if (dev->of_node) {
 900		for_each_child_of_node(dev->of_node, child_np) {
 901			if (of_device_is_compatible(child_np,
 902						    "apm,xgene-mdio")) {
 903				mdio_np = child_np;
 904				break;
 905			}
 906		}
 907
 908		if (!mdio_np) {
 909			netdev_dbg(ndev, "No mdio node in the dts\n");
 910			return -ENXIO;
 911		}
 912
 913		return of_mdiobus_register(mdio, mdio_np);
 914	}
 915
 916	/* Mask out all PHYs from auto probing. */
 917	mdio->phy_mask = ~0;
 918
 919	/* Register the MDIO bus */
 920	ret = mdiobus_register(mdio);
 921	if (ret)
 922		return ret;
 923
 924	ret = device_property_read_u32(dev, "phy-channel", &phy_addr);
 925	if (ret)
 926		ret = device_property_read_u32(dev, "phy-addr", &phy_addr);
 927	if (ret)
 928		return -EINVAL;
 929
 930	phy = xgene_enet_phy_register(mdio, phy_addr);
 931	if (!phy)
 932		return -EIO;
 933
 934	return ret;
 935}
 936
 937int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
 938{
 939	struct net_device *ndev = pdata->ndev;
 940	struct mii_bus *mdio_bus;
 941	int ret;
 942
 943	mdio_bus = mdiobus_alloc();
 944	if (!mdio_bus)
 945		return -ENOMEM;
 946
 947	mdio_bus->name = "APM X-Gene MDIO bus";
 948	mdio_bus->read = xgene_mdio_rgmii_read;
 949	mdio_bus->write = xgene_mdio_rgmii_write;
 950	snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii",
 951		 ndev->name);
 952
 953	mdio_bus->priv = (void __force *)pdata->mcx_mac_addr;
 954	mdio_bus->parent = &pdata->pdev->dev;
 955
 956	ret = xgene_mdiobus_register(pdata, mdio_bus);
 957	if (ret) {
 958		netdev_err(ndev, "Failed to register MDIO bus\n");
 959		mdiobus_free(mdio_bus);
 960		return ret;
 961	}
 962	pdata->mdio_bus = mdio_bus;
 963
 964	ret = xgene_enet_phy_connect(ndev);
 965	if (ret)
 966		xgene_enet_mdio_remove(pdata);
 967
 968	return ret;
 969}
 970
 971void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata)
 972{
 973	struct net_device *ndev = pdata->ndev;
 974
 975	if (ndev->phydev)
 976		phy_disconnect(ndev->phydev);
 977}
 978
 979void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata)
 980{
 981	struct net_device *ndev = pdata->ndev;
 982
 983	if (ndev->phydev)
 984		phy_disconnect(ndev->phydev);
 985
 986	mdiobus_unregister(pdata->mdio_bus);
 987	mdiobus_free(pdata->mdio_bus);
 988	pdata->mdio_bus = NULL;
 989}
 990
 991const struct xgene_mac_ops xgene_gmac_ops = {
 992	.init = xgene_gmac_init,
 993	.reset = xgene_gmac_reset,
 994	.rx_enable = xgene_gmac_rx_enable,
 995	.tx_enable = xgene_gmac_tx_enable,
 996	.rx_disable = xgene_gmac_rx_disable,
 997	.tx_disable = xgene_gmac_tx_disable,
 998	.get_drop_cnt = xgene_gmac_get_drop_cnt,
 999	.set_speed = xgene_gmac_set_speed,
1000	.set_mac_addr = xgene_gmac_set_mac_addr,
1001	.set_framesize = xgene_enet_set_frame_size,
1002	.enable_tx_pause = xgene_gmac_enable_tx_pause,
1003	.flowctl_tx     = xgene_gmac_flowctl_tx,
1004	.flowctl_rx     = xgene_gmac_flowctl_rx,
1005};
1006
1007const struct xgene_port_ops xgene_gport_ops = {
1008	.reset = xgene_enet_reset,
1009	.clear = xgene_enet_clear,
1010	.cle_bypass = xgene_enet_cle_bypass,
1011	.shutdown = xgene_gport_shutdown,
1012};
1013
1014struct xgene_ring_ops xgene_ring1_ops = {
1015	.num_ring_config = NUM_RING_CONFIG,
1016	.num_ring_id_shift = 6,
1017	.setup = xgene_enet_setup_ring,
1018	.clear = xgene_enet_clear_ring,
1019	.wr_cmd = xgene_enet_wr_cmd,
1020	.len = xgene_enet_ring_len,
1021};