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xgbe.h
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linux-6.19.14/drivers/net/ethernet/amd/xgbe/xgbe.h
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8#ifndef __XGBE_H__ 9#define __XGBE_H__ 10 11#include <linux/dma-mapping.h> 12#include <linux/netdevice.h> 13#include <linux/workqueue.h> 14#include <linux/phy.h> 15#include <linux/if_vlan.h> 16#include <linux/bitops.h> 17#include <linux/ptp_clock_kernel.h> 18#include <linux/timecounter.h> 19#include <linux/net_tstamp.h> 20#include <net/dcbnl.h> 21#include <linux/completion.h> 22#include <linux/cpumask.h> 23#include <linux/interrupt.h> 24#include <linux/dcache.h> 25#include <linux/ethtool.h> 26#include <linux/list.h> 27 28#define XGBE_DRV_NAME "amd-xgbe" 29#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 30 31/* Descriptor related defines */ 32#define XGBE_TX_DESC_CNT 512 33#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 34#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 35#define XGBE_RX_DESC_CNT 512 36 37#define XGBE_TX_DESC_CNT_MIN 64 38#define XGBE_TX_DESC_CNT_MAX 4096 39#define XGBE_RX_DESC_CNT_MIN 64 40#define XGBE_RX_DESC_CNT_MAX 4096 41 42#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 43 44/* Descriptors required for maximum contiguous TSO/GSO packet */ 45#define XGBE_TX_MAX_SPLIT \ 46 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 47 48/* Maximum possible descriptors needed for an SKB: 49 * - Maximum number of SKB frags 50 * - Maximum descriptors for contiguous TSO/GSO packet 51 * - Possible context descriptor 52 * - Possible TSO header descriptor 53 */ 54#define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 55 56#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 57#define XGBE_RX_BUF_ALIGN 64 58#define XGBE_SKB_ALLOC_SIZE 256 59#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 60 61#define XGBE_MAX_DMA_CHANNELS 16 62#define XGBE_MAX_QUEUES 16 63#define XGBE_PRIORITY_QUEUES 8 64#define XGBE_DMA_STOP_TIMEOUT 1 65 66/* DMA cache settings - Outer sharable, write-back, write-allocate */ 67#define XGBE_DMA_OS_ARCR 0x002b2b2b 68#define XGBE_DMA_OS_AWCR 0x2f2f2f2f 69 70/* DMA cache settings - System, no caches used */ 71#define XGBE_DMA_SYS_ARCR 0x00303030 72#define XGBE_DMA_SYS_AWCR 0x30303030 73 74/* DMA cache settings - PCI device */ 75#define XGBE_DMA_PCI_ARCR 0x000f0f0f 76#define XGBE_DMA_PCI_AWCR 0x0f0f0f0f 77#define XGBE_DMA_PCI_AWARCR 0x00000f0f 78 79/* DMA channel interrupt modes */ 80#define XGBE_IRQ_MODE_EDGE 0 81#define XGBE_IRQ_MODE_LEVEL 1 82 83#define XGBE_ETH_FRAME_HDR (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) 84#define XGMAC_MIN_PACKET 60 85#define XGMAC_STD_PACKET_MTU 1500 86#define XGMAC_MAX_STD_PACKET 1518 87#define XGMAC_JUMBO_PACKET_MTU 9000 88#define XGMAC_MAX_JUMBO_PACKET 9018 89#define XGMAC_GIANT_PACKET_MTU 16368 90#define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 91 92#define XGMAC_PFC_DATA_LEN 46 93#define XGMAC_PFC_DELAYS 14000 94 95#define XGMAC_PRIO_QUEUES(_cnt) \ 96 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 97 98/* Common property names */ 99#define XGBE_MAC_ADDR_PROPERTY "mac-address" 100#define XGBE_PHY_MODE_PROPERTY "phy-mode" 101#define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 102#define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 103 104/* Device-tree clock names */ 105#define XGBE_DMA_CLOCK "dma_clk" 106#define XGBE_PTP_CLOCK "ptp_clk" 107 108/* ACPI property names */ 109#define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 110#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 111 112/* PCI BAR mapping */ 113#define XGBE_XGMAC_BAR 0 114#define XGBE_XPCS_BAR 1 115#define XGBE_MAC_PROP_OFFSET 0x1d000 116#define XGBE_I2C_CTRL_OFFSET 0x1e000 117 118/* PCI MSI/MSIx support */ 119#define XGBE_MSI_BASE_COUNT 4 120#define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 121 122/* Initial PTP register values based on Link Speed. */ 123#define MAC_TICNR_1G_INITVAL 0x10 124#define MAC_TECNR_1G_INITVAL 0x28 125 126#define MAC_TICSNR_10G_INITVAL 0x33 127#define MAC_TECNR_10G_INITVAL 0x14 128#define MAC_TECSNR_10G_INITVAL 0xCC 129 130/* PCI clock frequencies */ 131#define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 132#define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 133 134/* Timestamp support - values based on 50MHz PTP clock 135 * 50MHz => 20 nsec 136 */ 137#define XGBE_TSTAMP_SSINC 20 138#define XGBE_TSTAMP_SNSINC 0 139#define XGBE_PTP_ACT_CLK_FREQ 500000000 140 141#define XGBE_V2_TSTAMP_SSINC 0xA 142#define XGBE_V2_TSTAMP_SNSINC 0 143#define XGBE_V2_PTP_ACT_CLK_FREQ 1000000000 144 145/* Define maximum supported values */ 146#define XGBE_MAX_PPS_OUT 4 147#define XGBE_MAX_AUX_SNAP 4 148 149/* Driver PMT macros */ 150#define XGMAC_DRIVER_CONTEXT 1 151#define XGMAC_IOCTL_CONTEXT 2 152 153#define XGMAC_FIFO_MIN_ALLOC 2048 154#define XGMAC_FIFO_UNIT 256 155#define XGMAC_FIFO_ALIGN(_x) \ 156 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 157#define XGMAC_FIFO_FC_OFF 2048 158#define XGMAC_FIFO_FC_MIN 4096 159 160#define XGBE_TC_MIN_QUANTUM 10 161 162/* Helper macro for descriptor handling 163 * Always use XGBE_GET_DESC_DATA to access the descriptor data 164 * since the index is free-running and needs to be and-ed 165 * with the descriptor count value of the ring to index to 166 * the proper descriptor data. 167 */ 168#define XGBE_GET_DESC_DATA(_ring, _idx) \ 169 ((_ring)->rdata + \ 170 ((_idx) & ((_ring)->rdesc_count - 1))) 171 172/* Default coalescing parameters */ 173#define XGMAC_INIT_DMA_TX_USECS 1000 174#define XGMAC_INIT_DMA_TX_FRAMES 25 175#define XGMAC_MAX_COAL_TX_TICK 100000 176 177#define XGMAC_MAX_DMA_RIWT 0xff 178#define XGMAC_INIT_DMA_RX_USECS 30 179#define XGMAC_INIT_DMA_RX_FRAMES 25 180 181/* Flow control queue count */ 182#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 183 184/* Flow control threshold units */ 185#define XGMAC_FLOW_CONTROL_UNIT 512 186#define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 187 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 188#define XGMAC_FLOW_CONTROL_VALUE(_x) \ 189 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 190#define XGMAC_FLOW_CONTROL_MAX 33280 191 192/* Maximum MAC address hash table size (256 bits = 8 bytes) */ 193#define XGBE_MAC_HASH_TABLE_SIZE 8 194 195/* Receive Side Scaling */ 196#define XGBE_RSS_HASH_KEY_SIZE 40 197#define XGBE_RSS_MAX_TABLE_SIZE 256 198#define XGBE_RSS_LOOKUP_TABLE_TYPE 0 199#define XGBE_RSS_HASH_KEY_TYPE 1 200 201/* Auto-negotiation */ 202#define XGBE_AN_MS_TIMEOUT 500 203#define XGBE_LINK_TIMEOUT 5 204#define XGBE_KR_TRAINING_WAIT_ITER 50 205 206#define XGBE_SGMII_AN_LINK_DUPLEX BIT(1) 207#define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 208#define XGBE_SGMII_AN_LINK_SPEED_10 0x00 209#define XGBE_SGMII_AN_LINK_SPEED_100 0x04 210#define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 211#define XGBE_SGMII_AN_LINK_STATUS BIT(4) 212 213/* ECC correctable error notification window (seconds) */ 214#define XGBE_ECC_LIMIT 60 215 216/* MDIO port types */ 217#define XGMAC_MAX_C22_PORT 3 218 219/* Link mode bit operations */ 220#define XGBE_ZERO_SUP(_ls) \ 221 ethtool_link_ksettings_zero_link_mode((_ls), supported) 222 223#define XGBE_SET_SUP(_ls, _mode) \ 224 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode) 225 226#define XGBE_CLR_SUP(_ls, _mode) \ 227 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode) 228 229#define XGBE_IS_SUP(_ls, _mode) \ 230 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode) 231 232#define XGBE_ZERO_ADV(_ls) \ 233 ethtool_link_ksettings_zero_link_mode((_ls), advertising) 234 235#define XGBE_SET_ADV(_ls, _mode) \ 236 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode) 237 238#define XGBE_CLR_ADV(_ls, _mode) \ 239 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode) 240 241#define XGBE_ADV(_ls, _mode) \ 242 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode) 243 244#define XGBE_ZERO_LP_ADV(_ls) \ 245 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising) 246 247#define XGBE_SET_LP_ADV(_ls, _mode) \ 248 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode) 249 250#define XGBE_CLR_LP_ADV(_ls, _mode) \ 251 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode) 252 253#define XGBE_LP_ADV(_ls, _mode) \ 254 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode) 255 256#define XGBE_LM_COPY(_dst, _dname, _src, _sname) \ 257 bitmap_copy((_dst)->link_modes._dname, \ 258 (_src)->link_modes._sname, \ 259 __ETHTOOL_LINK_MODE_MASK_NBITS) 260 261/* XGBE PCI device id */ 262#define XGBE_RV_PCI_DEVICE_ID 0x15d0 263#define XGBE_YC_PCI_DEVICE_ID 0x14b5 264#define XGBE_RN_PCI_DEVICE_ID 0x1630 265 266 /* Generic low and high masks */ 267#define XGBE_GEN_HI_MASK GENMASK(31, 16) 268#define XGBE_GEN_LO_MASK GENMASK(15, 0) 269 270struct xgbe_prv_data; 271 272struct xgbe_packet_data { 273 struct sk_buff *skb; 274 275 unsigned int attributes; 276 277 unsigned int errors; 278 279 unsigned int rdesc_count; 280 unsigned int length; 281 282 unsigned int header_len; 283 unsigned int tcp_header_len; 284 unsigned int tcp_payload_len; 285 unsigned short mss; 286 287 unsigned short vlan_ctag; 288 289 u64 rx_tstamp; 290 291 u32 rss_hash; 292 enum pkt_hash_types rss_hash_type; 293 294 unsigned int tx_packets; 295 unsigned int tx_bytes; 296}; 297 298/* Common Rx and Tx descriptor mapping */ 299struct xgbe_ring_desc { 300 __le32 desc0; 301 __le32 desc1; 302 __le32 desc2; 303 __le32 desc3; 304}; 305 306/* Page allocation related values */ 307struct xgbe_page_alloc { 308 struct page *pages; 309 unsigned int pages_len; 310 unsigned int pages_offset; 311 312 dma_addr_t pages_dma; 313}; 314 315/* Ring entry buffer data */ 316struct xgbe_buffer_data { 317 struct xgbe_page_alloc pa; 318 struct xgbe_page_alloc pa_unmap; 319 320 dma_addr_t dma_base; 321 unsigned long dma_off; 322 unsigned int dma_len; 323}; 324 325/* Tx-related ring data */ 326struct xgbe_tx_ring_data { 327 unsigned int packets; /* BQL packet count */ 328 unsigned int bytes; /* BQL byte count */ 329}; 330 331/* Rx-related ring data */ 332struct xgbe_rx_ring_data { 333 struct xgbe_buffer_data hdr; /* Header locations */ 334 struct xgbe_buffer_data buf; /* Payload locations */ 335 336 unsigned short hdr_len; /* Length of received header */ 337 unsigned short len; /* Length of received packet */ 338}; 339 340/* Structure used to hold information related to the descriptor 341 * and the packet associated with the descriptor (always use 342 * the XGBE_GET_DESC_DATA macro to access this data from the ring) 343 */ 344struct xgbe_ring_data { 345 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 346 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 347 348 struct sk_buff *skb; /* Virtual address of SKB */ 349 dma_addr_t skb_dma; /* DMA address of SKB data */ 350 unsigned int skb_dma_len; /* Length of SKB DMA area */ 351 352 struct xgbe_tx_ring_data tx; /* Tx-related data */ 353 struct xgbe_rx_ring_data rx; /* Rx-related data */ 354 355 unsigned int mapped_as_page; 356 357 /* Incomplete receive save location. If the budget is exhausted 358 * or the last descriptor (last normal descriptor or a following 359 * context descriptor) has not been DMA'd yet the current state 360 * of the receive processing needs to be saved. 361 */ 362 unsigned int state_saved; 363 struct { 364 struct sk_buff *skb; 365 unsigned int len; 366 unsigned int error; 367 } state; 368}; 369 370struct xgbe_ring { 371 /* Ring lock - used just for TX rings at the moment */ 372 spinlock_t lock; 373 374 /* Per packet related information */ 375 struct xgbe_packet_data packet_data; 376 377 /* Virtual/DMA addresses and count of allocated descriptor memory */ 378 struct xgbe_ring_desc *rdesc; 379 dma_addr_t rdesc_dma; 380 unsigned int rdesc_count; 381 382 /* Array of descriptor data corresponding the descriptor memory 383 * (always use the XGBE_GET_DESC_DATA macro to access this data) 384 */ 385 struct xgbe_ring_data *rdata; 386 387 /* Page allocation for RX buffers */ 388 struct xgbe_page_alloc rx_hdr_pa; 389 struct xgbe_page_alloc rx_buf_pa; 390 int node; 391 392 /* Ring index values 393 * cur - Tx: index of descriptor to be used for current transfer 394 * Rx: index of descriptor to check for packet availability 395 * dirty - Tx: index of descriptor to check for transfer complete 396 * Rx: index of descriptor to check for buffer reallocation 397 */ 398 unsigned int cur; 399 unsigned int dirty; 400 401 /* Coalesce frame count used for interrupt bit setting */ 402 unsigned int coalesce_count; 403 404 union { 405 struct { 406 unsigned int queue_stopped; 407 unsigned int xmit_more; 408 unsigned short cur_mss; 409 unsigned short cur_vlan_ctag; 410 } tx; 411 }; 412} ____cacheline_aligned; 413 414/* Structure used to describe the descriptor rings associated with 415 * a DMA channel. 416 */ 417struct xgbe_channel { 418 char name[20]; 419 420 /* Address of private data area for device */ 421 struct xgbe_prv_data *pdata; 422 423 /* Queue index and base address of queue's DMA registers */ 424 unsigned int queue_index; 425 void __iomem *dma_regs; 426 427 /* Per channel interrupt irq number */ 428 int dma_irq; 429 char dma_irq_name[IFNAMSIZ + 32]; 430 431 /* Netdev related settings */ 432 struct napi_struct napi; 433 434 /* Per channel interrupt enablement tracker */ 435 unsigned int curr_ier; 436 unsigned int saved_ier; 437 438 unsigned int tx_timer_active; 439 struct timer_list tx_timer; 440 441 struct xgbe_ring *tx_ring; 442 struct xgbe_ring *rx_ring; 443 444 int node; 445 cpumask_t affinity_mask; 446} ____cacheline_aligned; 447 448enum xgbe_state { 449 XGBE_DOWN, 450 XGBE_LINK_INIT, 451 XGBE_LINK_ERR, 452 XGBE_STOPPED, 453}; 454 455enum xgbe_int { 456 XGMAC_INT_DMA_CH_SR_TI, 457 XGMAC_INT_DMA_CH_SR_TPS, 458 XGMAC_INT_DMA_CH_SR_TBU, 459 XGMAC_INT_DMA_CH_SR_RI, 460 XGMAC_INT_DMA_CH_SR_RBU, 461 XGMAC_INT_DMA_CH_SR_RPS, 462 XGMAC_INT_DMA_CH_SR_TI_RI, 463 XGMAC_INT_DMA_CH_SR_FBE, 464 XGMAC_INT_DMA_ALL, 465}; 466 467enum xgbe_int_state { 468 XGMAC_INT_STATE_SAVE, 469 XGMAC_INT_STATE_RESTORE, 470}; 471 472enum xgbe_ecc_sec { 473 XGBE_ECC_SEC_TX, 474 XGBE_ECC_SEC_RX, 475 XGBE_ECC_SEC_DESC, 476}; 477 478enum xgbe_speed { 479 XGBE_SPEED_1000 = 0, 480 XGBE_SPEED_2500, 481 XGBE_SPEED_10000, 482 XGBE_SPEEDS, 483}; 484 485enum xgbe_xpcs_access { 486 XGBE_XPCS_ACCESS_V1 = 0, 487 XGBE_XPCS_ACCESS_V2, 488 XGBE_XPCS_ACCESS_V3, 489}; 490 491enum xgbe_an_mode { 492 XGBE_AN_MODE_CL73 = 0, 493 XGBE_AN_MODE_CL73_REDRV, 494 XGBE_AN_MODE_CL37, 495 XGBE_AN_MODE_CL37_SGMII, 496 XGBE_AN_MODE_NONE, 497}; 498 499enum xgbe_an { 500 XGBE_AN_READY = 0, 501 XGBE_AN_PAGE_RECEIVED, 502 XGBE_AN_INCOMPAT_LINK, 503 XGBE_AN_COMPLETE, 504 XGBE_AN_NO_LINK, 505 XGBE_AN_ERROR, 506}; 507 508enum xgbe_rx { 509 XGBE_RX_BPA = 0, 510 XGBE_RX_XNP, 511 XGBE_RX_COMPLETE, 512 XGBE_RX_ERROR, 513}; 514 515enum xgbe_mode { 516 XGBE_MODE_KX_1000 = 0, 517 XGBE_MODE_KX_2500, 518 XGBE_MODE_KR, 519 XGBE_MODE_X, 520 XGBE_MODE_SGMII_10, 521 XGBE_MODE_SGMII_100, 522 XGBE_MODE_SGMII_1000, 523 XGBE_MODE_SFI, 524 XGBE_MODE_UNKNOWN, 525}; 526 527enum xgbe_speedset { 528 XGBE_SPEEDSET_1000_10000 = 0, 529 XGBE_SPEEDSET_2500_10000, 530}; 531 532enum xgbe_mdio_mode { 533 XGBE_MDIO_MODE_NONE = 0, 534 XGBE_MDIO_MODE_CL22, 535 XGBE_MDIO_MODE_CL45, 536}; 537 538enum xgbe_mb_cmd { 539 XGBE_MB_CMD_POWER_OFF = 0, 540 XGBE_MB_CMD_SET_1G, 541 XGBE_MB_CMD_SET_2_5G, 542 XGBE_MB_CMD_SET_10G_SFI, 543 XGBE_MB_CMD_SET_10G_KR, 544 XGBE_MB_CMD_RRC 545}; 546 547enum xgbe_mb_subcmd { 548 XGBE_MB_SUBCMD_NONE = 0, 549 XGBE_MB_SUBCMD_RX_ADAP, 550 551 /* 10GbE SFP subcommands */ 552 XGBE_MB_SUBCMD_ACTIVE = 0, 553 XGBE_MB_SUBCMD_PASSIVE_1M, 554 XGBE_MB_SUBCMD_PASSIVE_3M, 555 XGBE_MB_SUBCMD_PASSIVE_OTHER, 556 557 /* 1GbE Mode subcommands */ 558 XGBE_MB_SUBCMD_10MBITS = 0, 559 XGBE_MB_SUBCMD_100MBITS, 560 XGBE_MB_SUBCMD_1G_SGMII, 561 XGBE_MB_SUBCMD_1G_KX 562}; 563 564struct xgbe_phy { 565 struct ethtool_link_ksettings lks; 566 567 int address; 568 569 int autoneg; 570 int speed; 571 int duplex; 572 573 int link; 574 575 int pause_autoneg; 576 int tx_pause; 577 int rx_pause; 578}; 579 580enum xgbe_i2c_cmd { 581 XGBE_I2C_CMD_READ = 0, 582 XGBE_I2C_CMD_WRITE, 583}; 584 585struct xgbe_i2c_op { 586 enum xgbe_i2c_cmd cmd; 587 588 unsigned int target; 589 590 void *buf; 591 unsigned int len; 592}; 593 594struct xgbe_i2c_op_state { 595 struct xgbe_i2c_op *op; 596 597 unsigned int tx_len; 598 unsigned char *tx_buf; 599 600 unsigned int rx_len; 601 unsigned char *rx_buf; 602 603 unsigned int tx_abort_source; 604 605 int ret; 606}; 607 608struct xgbe_i2c { 609 unsigned int started; 610 unsigned int max_speed_mode; 611 unsigned int rx_fifo_size; 612 unsigned int tx_fifo_size; 613 614 struct xgbe_i2c_op_state op_state; 615}; 616 617struct xgbe_mmc_stats { 618 /* Tx Stats */ 619 u64 txoctetcount_gb; 620 u64 txframecount_gb; 621 u64 txbroadcastframes_g; 622 u64 txmulticastframes_g; 623 u64 tx64octets_gb; 624 u64 tx65to127octets_gb; 625 u64 tx128to255octets_gb; 626 u64 tx256to511octets_gb; 627 u64 tx512to1023octets_gb; 628 u64 tx1024tomaxoctets_gb; 629 u64 txunicastframes_gb; 630 u64 txmulticastframes_gb; 631 u64 txbroadcastframes_gb; 632 u64 txunderflowerror; 633 u64 txoctetcount_g; 634 u64 txframecount_g; 635 u64 txpauseframes; 636 u64 txvlanframes_g; 637 638 /* Rx Stats */ 639 u64 rxframecount_gb; 640 u64 rxoctetcount_gb; 641 u64 rxoctetcount_g; 642 u64 rxbroadcastframes_g; 643 u64 rxmulticastframes_g; 644 u64 rxcrcerror; 645 u64 rxrunterror; 646 u64 rxjabbererror; 647 u64 rxundersize_g; 648 u64 rxoversize_g; 649 u64 rx64octets_gb; 650 u64 rx65to127octets_gb; 651 u64 rx128to255octets_gb; 652 u64 rx256to511octets_gb; 653 u64 rx512to1023octets_gb; 654 u64 rx1024tomaxoctets_gb; 655 u64 rxunicastframes_g; 656 u64 rxlengtherror; 657 u64 rxoutofrangetype; 658 u64 rxpauseframes; 659 u64 rxfifooverflow; 660 u64 rxvlanframes_gb; 661 u64 rxwatchdogerror; 662}; 663 664struct xgbe_ext_stats { 665 u64 tx_tso_packets; 666 u64 rx_split_header_packets; 667 u64 rx_buffer_unavailable; 668 669 u64 txq_packets[XGBE_MAX_DMA_CHANNELS]; 670 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS]; 671 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS]; 672 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 673 674 u64 tx_vxlan_packets; 675 u64 rx_vxlan_packets; 676 u64 rx_csum_errors; 677 u64 rx_vxlan_csum_errors; 678}; 679 680struct xgbe_pps_config { 681 struct timespec64 start; 682 struct timespec64 period; 683}; 684 685struct xgbe_hw_if { 686 int (*tx_complete)(struct xgbe_ring_desc *); 687 688 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr); 689 int (*config_rx_mode)(struct xgbe_prv_data *); 690 691 int (*enable_rx_csum)(struct xgbe_prv_data *); 692 int (*disable_rx_csum)(struct xgbe_prv_data *); 693 694 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 695 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 696 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 697 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 698 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 699 700 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 701 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 702 int (*set_speed)(struct xgbe_prv_data *, int); 703 704 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 705 enum xgbe_mdio_mode); 706 int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int); 707 int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16); 708 int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int); 709 int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int, 710 u16); 711 712 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 713 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 714 715 void (*enable_tx)(struct xgbe_prv_data *); 716 void (*disable_tx)(struct xgbe_prv_data *); 717 void (*enable_rx)(struct xgbe_prv_data *); 718 void (*disable_rx)(struct xgbe_prv_data *); 719 720 void (*powerup_tx)(struct xgbe_prv_data *); 721 void (*powerdown_tx)(struct xgbe_prv_data *); 722 void (*powerup_rx)(struct xgbe_prv_data *); 723 void (*powerdown_rx)(struct xgbe_prv_data *); 724 725 int (*init)(struct xgbe_prv_data *); 726 int (*exit)(struct xgbe_prv_data *); 727 728 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 729 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 730 void (*dev_xmit)(struct xgbe_channel *); 731 int (*dev_read)(struct xgbe_channel *); 732 void (*tx_desc_init)(struct xgbe_channel *); 733 void (*rx_desc_init)(struct xgbe_channel *); 734 void (*tx_desc_reset)(struct xgbe_ring_data *); 735 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 736 unsigned int); 737 int (*is_last_desc)(struct xgbe_ring_desc *); 738 int (*is_context_desc)(struct xgbe_ring_desc *); 739 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 740 741 /* For FLOW ctrl */ 742 int (*config_tx_flow_control)(struct xgbe_prv_data *); 743 int (*config_rx_flow_control)(struct xgbe_prv_data *); 744 745 /* For RX coalescing */ 746 int (*config_rx_coalesce)(struct xgbe_prv_data *); 747 int (*config_tx_coalesce)(struct xgbe_prv_data *); 748 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 749 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 750 751 /* For RX and TX threshold config */ 752 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 753 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 754 755 /* For RX and TX Store and Forward Mode config */ 756 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 757 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 758 759 /* For TX DMA Operate on Second Frame config */ 760 int (*config_osp_mode)(struct xgbe_prv_data *); 761 762 /* For MMC statistics */ 763 void (*rx_mmc_int)(struct xgbe_prv_data *); 764 void (*tx_mmc_int)(struct xgbe_prv_data *); 765 void (*read_mmc_stats)(struct xgbe_prv_data *); 766 767 /* For Data Center Bridging config */ 768 void (*config_tc)(struct xgbe_prv_data *); 769 void (*config_dcb_tc)(struct xgbe_prv_data *); 770 void (*config_dcb_pfc)(struct xgbe_prv_data *); 771 772 /* For Receive Side Scaling */ 773 int (*enable_rss)(struct xgbe_prv_data *); 774 int (*disable_rss)(struct xgbe_prv_data *); 775 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 776 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 777 778 /* For ECC */ 779 void (*disable_ecc_ded)(struct xgbe_prv_data *); 780 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); 781 782 /* For VXLAN */ 783 void (*enable_vxlan)(struct xgbe_prv_data *); 784 void (*disable_vxlan)(struct xgbe_prv_data *); 785 void (*set_vxlan_id)(struct xgbe_prv_data *); 786 787 /* For Split Header */ 788 void (*enable_sph)(struct xgbe_prv_data *pdata); 789 void (*disable_sph)(struct xgbe_prv_data *pdata); 790}; 791 792/* This structure represents implementation specific routines for an 793 * implementation of a PHY. All routines are required unless noted below. 794 * Optional routines: 795 * an_pre, an_post 796 * kr_training_pre, kr_training_post 797 * module_info, module_eeprom 798 */ 799struct xgbe_phy_impl_if { 800 /* Perform Setup/teardown actions */ 801 int (*init)(struct xgbe_prv_data *); 802 void (*exit)(struct xgbe_prv_data *); 803 804 /* Perform start/stop specific actions */ 805 int (*reset)(struct xgbe_prv_data *); 806 int (*start)(struct xgbe_prv_data *); 807 void (*stop)(struct xgbe_prv_data *); 808 809 /* Return the link status */ 810 int (*link_status)(struct xgbe_prv_data *, int *); 811 812 /* Indicate if a particular speed is valid */ 813 bool (*valid_speed)(struct xgbe_prv_data *, int); 814 815 /* Check if the specified mode can/should be used */ 816 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 817 /* Switch the PHY into various modes */ 818 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 819 /* Retrieve mode needed for a specific speed */ 820 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 821 /* Retrieve new/next mode when trying to auto-negotiate */ 822 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 823 /* Retrieve current mode */ 824 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 825 826 /* Retrieve current auto-negotiation mode */ 827 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 828 829 /* Configure auto-negotiation settings */ 830 int (*an_config)(struct xgbe_prv_data *); 831 832 /* Set/override auto-negotiation advertisement settings */ 833 void (*an_advertising)(struct xgbe_prv_data *, 834 struct ethtool_link_ksettings *); 835 836 /* Process results of auto-negotiation */ 837 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 838 839 /* Pre/Post auto-negotiation support */ 840 void (*an_pre)(struct xgbe_prv_data *); 841 void (*an_post)(struct xgbe_prv_data *); 842 843 /* Pre/Post KR training enablement support */ 844 void (*kr_training_pre)(struct xgbe_prv_data *); 845 void (*kr_training_post)(struct xgbe_prv_data *); 846 847 /* SFP module related info */ 848 int (*module_info)(struct xgbe_prv_data *pdata, 849 struct ethtool_modinfo *modinfo); 850 int (*module_eeprom)(struct xgbe_prv_data *pdata, 851 struct ethtool_eeprom *eeprom, u8 *data); 852}; 853 854struct xgbe_phy_if { 855 /* For PHY setup/teardown */ 856 int (*phy_init)(struct xgbe_prv_data *); 857 void (*phy_exit)(struct xgbe_prv_data *); 858 859 /* For PHY support when setting device up/down */ 860 int (*phy_reset)(struct xgbe_prv_data *); 861 int (*phy_start)(struct xgbe_prv_data *); 862 void (*phy_stop)(struct xgbe_prv_data *); 863 864 /* For PHY support while device is up */ 865 void (*phy_status)(struct xgbe_prv_data *); 866 int (*phy_config_aneg)(struct xgbe_prv_data *); 867 868 /* For PHY settings validation */ 869 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 870 871 /* For single interrupt support */ 872 irqreturn_t (*an_isr)(struct xgbe_prv_data *); 873 874 /* For ethtool PHY support */ 875 int (*module_info)(struct xgbe_prv_data *pdata, 876 struct ethtool_modinfo *modinfo); 877 int (*module_eeprom)(struct xgbe_prv_data *pdata, 878 struct ethtool_eeprom *eeprom, u8 *data); 879 880 /* PHY implementation specific services */ 881 struct xgbe_phy_impl_if phy_impl; 882}; 883 884struct xgbe_i2c_if { 885 /* For initial I2C setup */ 886 int (*i2c_init)(struct xgbe_prv_data *); 887 888 /* For I2C support when setting device up/down */ 889 int (*i2c_start)(struct xgbe_prv_data *); 890 void (*i2c_stop)(struct xgbe_prv_data *); 891 892 /* For performing I2C operations */ 893 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 894 895 /* For single interrupt support */ 896 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *); 897}; 898 899struct xgbe_desc_if { 900 int (*alloc_ring_resources)(struct xgbe_prv_data *); 901 void (*free_ring_resources)(struct xgbe_prv_data *); 902 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 903 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 904 struct xgbe_ring_data *); 905 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 906 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 907 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 908}; 909 910/* This structure contains flags that indicate what hardware features 911 * or configurations are present in the device. 912 */ 913struct xgbe_hw_features { 914 /* HW Version */ 915 unsigned int version; 916 917 /* HW Feature Register0 */ 918 unsigned int gmii; /* 1000 Mbps support */ 919 unsigned int vlhash; /* VLAN Hash Filter */ 920 unsigned int sma; /* SMA(MDIO) Interface */ 921 unsigned int rwk; /* PMT remote wake-up packet */ 922 unsigned int mgk; /* PMT magic packet */ 923 unsigned int mmc; /* RMON module */ 924 unsigned int aoe; /* ARP Offload */ 925 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 926 unsigned int eee; /* Energy Efficient Ethernet */ 927 unsigned int tx_coe; /* Tx Checksum Offload */ 928 unsigned int rx_coe; /* Rx Checksum Offload */ 929 unsigned int addn_mac; /* Additional MAC Addresses */ 930 unsigned int ts_src; /* Timestamp Source */ 931 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 932 unsigned int vxn; /* VXLAN/NVGRE */ 933 934 /* HW Feature Register1 */ 935 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 936 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 937 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 938 unsigned int dma_width; /* DMA width */ 939 unsigned int dcb; /* DCB Feature */ 940 unsigned int sph; /* Split Header Feature */ 941 unsigned int tso; /* TCP Segmentation Offload */ 942 unsigned int dma_debug; /* DMA Debug Registers */ 943 unsigned int rss; /* Receive Side Scaling */ 944 unsigned int tc_cnt; /* Number of Traffic Classes */ 945 unsigned int hash_table_size; /* Hash Table Size */ 946 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 947 948 /* HW Feature Register2 */ 949 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 950 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 951 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 952 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 953 unsigned int pps_out_num; /* Number of PPS outputs */ 954 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 955}; 956 957struct xgbe_version_data { 958 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 959 enum xgbe_xpcs_access xpcs_access; 960 unsigned int mmc_64bit; 961 unsigned int tx_max_fifo_size; 962 unsigned int rx_max_fifo_size; 963 unsigned int tx_tstamp_workaround; 964 unsigned int tstamp_ptp_clock_freq; 965 unsigned int ecc_support; 966 unsigned int i2c_support; 967 unsigned int irq_reissue_support; 968 unsigned int tx_desc_prefetch; 969 unsigned int rx_desc_prefetch; 970 unsigned int an_cdr_workaround; 971 unsigned int enable_rrc; 972}; 973 974struct xgbe_prv_data { 975 struct net_device *netdev; 976 struct pci_dev *pcidev; 977 struct platform_device *platdev; 978 struct acpi_device *adev; 979 struct device *dev; 980 struct platform_device *phy_platdev; 981 struct device *phy_dev; 982 unsigned int smn_base; 983 984 /* Version related data */ 985 struct xgbe_version_data *vdata; 986 987 /* ACPI or DT flag */ 988 unsigned int use_acpi; 989 990 /* XGMAC/XPCS related mmio registers */ 991 void __iomem *xgmac_regs; /* XGMAC CSRs */ 992 void __iomem *xpcs_regs; /* XPCS MMD registers */ 993 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ 994 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ 995 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ 996 void __iomem *xprop_regs; /* XGBE property registers */ 997 void __iomem *xi2c_regs; /* XGBE I2C CSRs */ 998 999 /* Port property registers */ 1000 unsigned int pp0; 1001 unsigned int pp1; 1002 unsigned int pp2; 1003 unsigned int pp3; 1004 unsigned int pp4; 1005 1006 /* XPCS indirect addressing lock */ 1007 spinlock_t xpcs_lock; 1008 unsigned int xpcs_window_def_reg; 1009 unsigned int xpcs_window_sel_reg; 1010 unsigned int xpcs_window; 1011 unsigned int xpcs_window_size; 1012 unsigned int xpcs_window_mask; 1013 1014 /* RSS addressing mutex */ 1015 struct mutex rss_mutex; 1016 1017 /* Flags representing xgbe_state */ 1018 unsigned long dev_state; 1019 1020 /* ECC support */ 1021 unsigned long tx_sec_period; 1022 unsigned long tx_ded_period; 1023 unsigned long rx_sec_period; 1024 unsigned long rx_ded_period; 1025 unsigned long desc_sec_period; 1026 unsigned long desc_ded_period; 1027 1028 unsigned int tx_sec_count; 1029 unsigned int tx_ded_count; 1030 unsigned int rx_sec_count; 1031 unsigned int rx_ded_count; 1032 unsigned int desc_ded_count; 1033 unsigned int desc_sec_count; 1034 1035 int dev_irq; 1036 int ecc_irq; 1037 int i2c_irq; 1038 int channel_irq[XGBE_MAX_DMA_CHANNELS]; 1039 1040 unsigned int per_channel_irq; 1041 unsigned int irq_count; 1042 unsigned int channel_irq_count; 1043 unsigned int channel_irq_mode; 1044 1045 char ecc_name[IFNAMSIZ + 32]; 1046 1047 struct xgbe_hw_if hw_if; 1048 struct xgbe_phy_if phy_if; 1049 struct xgbe_desc_if desc_if; 1050 struct xgbe_i2c_if i2c_if; 1051 1052 /* AXI DMA settings */ 1053 unsigned int coherent; 1054 unsigned int arcr; 1055 unsigned int awcr; 1056 unsigned int awarcr; 1057 1058 /* Service routine support */ 1059 struct workqueue_struct *dev_workqueue; 1060 struct work_struct service_work; 1061 struct timer_list service_timer; 1062 1063 /* Rings for Tx/Rx on a DMA channel */ 1064 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1065 unsigned int tx_max_channel_count; 1066 unsigned int rx_max_channel_count; 1067 unsigned int channel_count; 1068 unsigned int tx_ring_count; 1069 unsigned int tx_desc_count; 1070 unsigned int rx_ring_count; 1071 unsigned int rx_desc_count; 1072 1073 unsigned int new_tx_ring_count; 1074 unsigned int new_rx_ring_count; 1075 1076 unsigned int tx_max_q_count; 1077 unsigned int rx_max_q_count; 1078 unsigned int tx_q_count; 1079 unsigned int rx_q_count; 1080 1081 /* Tx/Rx common settings */ 1082 unsigned int blen; 1083 unsigned int pbl; 1084 unsigned int aal; 1085 unsigned int rd_osr_limit; 1086 unsigned int wr_osr_limit; 1087 1088 /* Tx settings */ 1089 unsigned int tx_sf_mode; 1090 unsigned int tx_threshold; 1091 unsigned int tx_osp_mode; 1092 unsigned int tx_max_fifo_size; 1093 1094 /* Rx settings */ 1095 unsigned int rx_sf_mode; 1096 unsigned int rx_threshold; 1097 unsigned int rx_max_fifo_size; 1098 1099 /* Tx coalescing settings */ 1100 unsigned int tx_usecs; 1101 unsigned int tx_frames; 1102 1103 /* Rx coalescing settings */ 1104 unsigned int rx_riwt; 1105 unsigned int rx_usecs; 1106 unsigned int rx_frames; 1107 1108 /* Current Rx buffer size */ 1109 unsigned int rx_buf_size; 1110 1111 /* Flow control settings */ 1112 unsigned int pause_autoneg; 1113 unsigned int tx_pause; 1114 unsigned int rx_pause; 1115 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1116 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1117 1118 /* Receive Side Scaling settings */ 1119 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1120 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1121 u32 rss_options; 1122 1123 /* VXLAN settings */ 1124 u16 vxlan_port; 1125 1126 /* Netdev related settings */ 1127 unsigned char mac_addr[ETH_ALEN]; 1128 netdev_features_t netdev_features; 1129 struct napi_struct napi; 1130 struct xgbe_mmc_stats mmc_stats; 1131 struct xgbe_ext_stats ext_stats; 1132 1133 /* Filtering support */ 1134 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1135 1136 /* Device clocks */ 1137 struct clk *sysclk; 1138 unsigned long sysclk_rate; 1139 struct clk *ptpclk; 1140 unsigned long ptpclk_rate; 1141 1142 /* Timestamp support */ 1143 spinlock_t tstamp_lock; 1144 struct ptp_clock_info ptp_clock_info; 1145 struct ptp_clock *ptp_clock; 1146 struct kernel_hwtstamp_config tstamp_config; 1147 unsigned int tstamp_addend; 1148 struct work_struct tx_tstamp_work; 1149 struct sk_buff *tx_tstamp_skb; 1150 u64 tx_tstamp; 1151 1152 /* Pulse Per Second output */ 1153 struct xgbe_pps_config pps[XGBE_MAX_PPS_OUT]; 1154 1155 /* DCB support */ 1156 struct ieee_ets *ets; 1157 struct ieee_pfc *pfc; 1158 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1159 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1160 unsigned int pfcq[XGBE_MAX_QUEUES]; 1161 unsigned int pfc_rfa; 1162 u8 num_tcs; 1163 1164 /* Hardware features of the device */ 1165 struct xgbe_hw_features hw_feat; 1166 1167 /* Device work structures */ 1168 struct work_struct restart_work; 1169 struct work_struct stopdev_work; 1170 1171 /* Keeps track of power mode */ 1172 unsigned int power_down; 1173 1174 /* Network interface message level setting */ 1175 u32 msg_enable; 1176 1177 /* Current PHY settings */ 1178 phy_interface_t phy_mode; 1179 int phy_link; 1180 int phy_speed; 1181 1182 /* MDIO/PHY related settings */ 1183 unsigned int phy_started; 1184 void *phy_data; 1185 struct xgbe_phy phy; 1186 int mdio_mmd; 1187 unsigned long link_check; 1188 struct completion mdio_complete; 1189 1190 unsigned int kr_redrv; 1191 1192 char an_name[IFNAMSIZ + 32]; 1193 struct workqueue_struct *an_workqueue; 1194 1195 int an_irq; 1196 struct work_struct an_irq_work; 1197 1198 /* Auto-negotiation state machine support */ 1199 unsigned int an_int; 1200 unsigned int an_status; 1201 struct mutex an_mutex; 1202 enum xgbe_an an_result; 1203 enum xgbe_an an_state; 1204 enum xgbe_rx kr_state; 1205 enum xgbe_rx kx_state; 1206 struct work_struct an_work; 1207 unsigned int an_again; 1208 unsigned int an_supported; 1209 unsigned int parallel_detect; 1210 unsigned int fec_ability; 1211 unsigned long an_start; 1212 unsigned long kr_start_time; 1213 enum xgbe_an_mode an_mode; 1214 1215 /* I2C support */ 1216 struct xgbe_i2c i2c; 1217 struct mutex i2c_mutex; 1218 struct completion i2c_complete; 1219 char i2c_name[IFNAMSIZ + 32]; 1220 1221 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1222 1223 unsigned int isr_as_bh_work; 1224 struct work_struct dev_bh_work; 1225 struct work_struct ecc_bh_work; 1226 struct work_struct i2c_bh_work; 1227 struct work_struct an_bh_work; 1228 1229 struct dentry *xgbe_debugfs; 1230 1231 unsigned int debugfs_xgmac_reg; 1232 1233 unsigned int debugfs_xpcs_mmd; 1234 unsigned int debugfs_xpcs_reg; 1235 1236 unsigned int debugfs_xprop_reg; 1237 1238 unsigned int debugfs_xi2c_reg; 1239 1240 bool debugfs_an_cdr_workaround; 1241 bool debugfs_an_cdr_track_early; 1242 bool en_rx_adap; 1243 int rx_adapt_retries; 1244 bool rx_adapt_done; 1245 /* Flag to track if data path (TX/RX) was stopped for RX adaptation. 1246 * This prevents packet corruption during the adaptation window. 1247 */ 1248 bool data_path_stopped; 1249 bool mode_set; 1250 bool sph; 1251}; 1252 1253/* Function prototypes*/ 1254struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); 1255void xgbe_free_pdata(struct xgbe_prv_data *); 1256void xgbe_set_counts(struct xgbe_prv_data *); 1257int xgbe_config_netdev(struct xgbe_prv_data *); 1258void xgbe_deconfig_netdev(struct xgbe_prv_data *); 1259 1260int xgbe_platform_init(void); 1261void xgbe_platform_exit(void); 1262#ifdef CONFIG_PCI 1263int xgbe_pci_init(void); 1264void xgbe_pci_exit(void); 1265#else 1266static inline int xgbe_pci_init(void) { return 0; } 1267static inline void xgbe_pci_exit(void) { } 1268#endif 1269 1270void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1271void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1272void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1273void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1274void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1275void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1276const struct net_device_ops *xgbe_get_netdev_ops(void); 1277const struct ethtool_ops *xgbe_get_ethtool_ops(void); 1278const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void); 1279 1280#ifdef CONFIG_AMD_XGBE_DCB 1281const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 1282#endif 1283 1284void xgbe_ptp_register(struct xgbe_prv_data *); 1285void xgbe_ptp_unregister(struct xgbe_prv_data *); 1286void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1287 unsigned int, unsigned int, unsigned int); 1288void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1289 unsigned int); 1290void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 1291void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1292int xgbe_powerup(struct net_device *, unsigned int); 1293int xgbe_powerdown(struct net_device *, unsigned int); 1294void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1295void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1296void xgbe_restart_dev(struct xgbe_prv_data *pdata); 1297void xgbe_full_restart_dev(struct xgbe_prv_data *pdata); 1298 1299/* For Timestamp config */ 1300void xgbe_config_tstamp(struct xgbe_prv_data *pdata, unsigned int mac_tscr); 1301u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata); 1302u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata); 1303void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1304 struct xgbe_ring_desc *rdesc); 1305void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1306 struct xgbe_ring_desc *rdesc); 1307void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1308 unsigned int addend); 1309void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1310 unsigned int nsec); 1311void xgbe_tx_tstamp(struct work_struct *work); 1312int xgbe_get_hwtstamp_settings(struct net_device *netdev, 1313 struct kernel_hwtstamp_config *config); 1314int xgbe_set_hwtstamp_settings(struct net_device *netdev, 1315 struct kernel_hwtstamp_config *config, 1316 struct netlink_ext_ack *extack); 1317void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, 1318 struct sk_buff *skb, 1319 struct xgbe_packet_data *packet); 1320int xgbe_init_ptp(struct xgbe_prv_data *pdata); 1321void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1322 unsigned int nsec); 1323 1324int xgbe_pps_config(struct xgbe_prv_data *pdata, struct xgbe_pps_config *cfg, 1325 int index, bool on); 1326 1327/* Selftest functions */ 1328void xgbe_selftest_run(struct net_device *dev, 1329 struct ethtool_test *etest, u64 *buf); 1330void xgbe_selftest_get_strings(struct xgbe_prv_data *pdata, u8 *data); 1331int xgbe_selftest_get_count(struct xgbe_prv_data *pdata); 1332 1333/* Loopback control */ 1334int xgbe_enable_mac_loopback(struct xgbe_prv_data *pdata); 1335void xgbe_disable_mac_loopback(struct xgbe_prv_data *pdata); 1336 1337#ifdef CONFIG_DEBUG_FS 1338void xgbe_debugfs_init(struct xgbe_prv_data *); 1339void xgbe_debugfs_exit(struct xgbe_prv_data *); 1340void xgbe_debugfs_rename(struct xgbe_prv_data *pdata); 1341#else 1342static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 1343static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 1344static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {} 1345#endif /* CONFIG_DEBUG_FS */ 1346 1347/* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 1348#if 0 1349#define YDEBUG 1350#define YDEBUG_MDIO 1351#endif 1352 1353/* For debug prints */ 1354#ifdef YDEBUG 1355#define DBGPR(x...) pr_alert(x) 1356#else 1357#define DBGPR(x...) do { } while (0) 1358#endif 1359 1360#ifdef YDEBUG_MDIO 1361#define DBGPR_MDIO(x...) pr_alert(x) 1362#else 1363#define DBGPR_MDIO(x...) do { } while (0) 1364#endif 1365 1366#endif
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