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xgbe-phy-v2.c
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linux-6.19.14/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8#include <linux/module.h> 9#include <linux/device.h> 10#include <linux/kmod.h> 11#include <linux/mdio.h> 12#include <linux/phy.h> 13#include <linux/ethtool.h> 14 15#include "xgbe.h" 16#include "xgbe-common.h" 17 18#define XGBE_PHY_PORT_SPEED_10 BIT(0) 19#define XGBE_PHY_PORT_SPEED_100 BIT(1) 20#define XGBE_PHY_PORT_SPEED_1000 BIT(2) 21#define XGBE_PHY_PORT_SPEED_2500 BIT(3) 22#define XGBE_PHY_PORT_SPEED_10000 BIT(4) 23 24#define XGBE_MUTEX_RELEASE 0x80000000 25 26#define XGBE_SFP_DIRECT 7 27 28/* I2C target addresses */ 29#define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 30#define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 31#define XGBE_SFP_PHY_ADDRESS 0x56 32#define XGBE_GPIO_ADDRESS_PCA9555 0x20 33 34/* SFP sideband signal indicators */ 35#define XGBE_GPIO_NO_TX_FAULT BIT(0) 36#define XGBE_GPIO_NO_RATE_SELECT BIT(1) 37#define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 38#define XGBE_GPIO_NO_RX_LOS BIT(3) 39 40/* Rate-change complete wait/retry count */ 41#define XGBE_RATECHANGE_COUNT 500 42 43/* CDR delay values for KR support (in usec) */ 44#define XGBE_CDR_DELAY_INIT 10000 45#define XGBE_CDR_DELAY_INC 10000 46#define XGBE_CDR_DELAY_MAX 100000 47 48/* RRC frequency during link status check */ 49#define XGBE_RRC_FREQUENCY 10 50 51enum xgbe_port_mode { 52 XGBE_PORT_MODE_RSVD = 0, 53 XGBE_PORT_MODE_BACKPLANE, 54 XGBE_PORT_MODE_BACKPLANE_2500, 55 XGBE_PORT_MODE_1000BASE_T, 56 XGBE_PORT_MODE_1000BASE_X, 57 XGBE_PORT_MODE_NBASE_T, 58 XGBE_PORT_MODE_10GBASE_T, 59 XGBE_PORT_MODE_10GBASE_R, 60 XGBE_PORT_MODE_SFP, 61 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 62 XGBE_PORT_MODE_MAX, 63}; 64 65enum xgbe_conn_type { 66 XGBE_CONN_TYPE_NONE = 0, 67 XGBE_CONN_TYPE_SFP, 68 XGBE_CONN_TYPE_MDIO, 69 XGBE_CONN_TYPE_RSVD1, 70 XGBE_CONN_TYPE_BACKPLANE, 71 XGBE_CONN_TYPE_MAX, 72}; 73 74/* SFP/SFP+ related definitions */ 75enum xgbe_sfp_comm { 76 XGBE_SFP_COMM_DIRECT = 0, 77 XGBE_SFP_COMM_PCA9545, 78}; 79 80enum xgbe_sfp_cable { 81 XGBE_SFP_CABLE_UNKNOWN = 0, 82 XGBE_SFP_CABLE_ACTIVE, 83 XGBE_SFP_CABLE_PASSIVE, 84 XGBE_SFP_CABLE_FIBER, 85}; 86 87enum xgbe_sfp_base { 88 XGBE_SFP_BASE_UNKNOWN = 0, 89 XGBE_SFP_BASE_1000_T, 90 XGBE_SFP_BASE_1000_SX, 91 XGBE_SFP_BASE_1000_LX, 92 XGBE_SFP_BASE_1000_CX, 93 XGBE_SFP_BASE_10000_SR, 94 XGBE_SFP_BASE_10000_LR, 95 XGBE_SFP_BASE_10000_LRM, 96 XGBE_SFP_BASE_10000_ER, 97 XGBE_SFP_BASE_10000_CR, 98}; 99 100enum xgbe_sfp_speed { 101 XGBE_SFP_SPEED_UNKNOWN = 0, 102 XGBE_SFP_SPEED_100_1000, 103 XGBE_SFP_SPEED_1000, 104 XGBE_SFP_SPEED_10000, 105}; 106 107/* SFP Serial ID Base ID values relative to an offset of 0 */ 108#define XGBE_SFP_BASE_ID 0 109#define XGBE_SFP_ID_SFP 0x03 110 111#define XGBE_SFP_BASE_EXT_ID 1 112#define XGBE_SFP_EXT_ID_SFP 0x04 113 114#define XGBE_SFP_BASE_10GBE_CC 3 115#define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 116#define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 117#define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 118#define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 119 120#define XGBE_SFP_BASE_1GBE_CC 6 121#define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 122#define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 123#define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 124#define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 125 126#define XGBE_SFP_BASE_CABLE 8 127#define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 128#define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 129 130#define XGBE_SFP_BASE_BR 12 131#define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 132#define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 133 134#define XGBE_SFP_BASE_CU_CABLE_LEN 18 135 136#define XGBE_SFP_BASE_VENDOR_NAME 20 137#define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 138#define XGBE_SFP_BASE_VENDOR_PN 40 139#define XGBE_SFP_BASE_VENDOR_PN_LEN 16 140#define XGBE_SFP_BASE_VENDOR_REV 56 141#define XGBE_SFP_BASE_VENDOR_REV_LEN 4 142 143#define XGBE_SFP_BASE_CC 63 144 145/* SFP Serial ID Extended ID values relative to an offset of 64 */ 146#define XGBE_SFP_BASE_VENDOR_SN 4 147#define XGBE_SFP_BASE_VENDOR_SN_LEN 16 148 149#define XGBE_SFP_EXTD_OPT1 1 150#define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 151#define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 152 153#define XGBE_SFP_EXTD_DIAG 28 154#define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 155 156#define XGBE_SFP_EXTD_SFF_8472 30 157 158#define XGBE_SFP_EXTD_CC 31 159 160struct xgbe_sfp_eeprom { 161 u8 base[64]; 162 u8 extd[32]; 163 u8 vendor[32]; 164}; 165 166#define XGBE_SFP_DIAGS_SUPPORTED(_x) \ 167 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 168 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 169 170#define XGBE_SFP_EEPROM_BASE_LEN 256 171#define XGBE_SFP_EEPROM_DIAG_LEN 256 172#define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \ 173 XGBE_SFP_EEPROM_DIAG_LEN) 174 175#define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 176#define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 177 178#define XGBE_MOLEX_VENDOR "Molex Inc. " 179 180struct xgbe_sfp_ascii { 181 union { 182 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 183 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 184 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 185 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 186 } u; 187}; 188 189/* MDIO PHY reset types */ 190enum xgbe_mdio_reset { 191 XGBE_MDIO_RESET_NONE = 0, 192 XGBE_MDIO_RESET_I2C_GPIO, 193 XGBE_MDIO_RESET_INT_GPIO, 194 XGBE_MDIO_RESET_MAX, 195}; 196 197/* Re-driver related definitions */ 198enum xgbe_phy_redrv_if { 199 XGBE_PHY_REDRV_IF_MDIO = 0, 200 XGBE_PHY_REDRV_IF_I2C, 201 XGBE_PHY_REDRV_IF_MAX, 202}; 203 204enum xgbe_phy_redrv_model { 205 XGBE_PHY_REDRV_MODEL_4223 = 0, 206 XGBE_PHY_REDRV_MODEL_4227, 207 XGBE_PHY_REDRV_MODEL_MAX, 208}; 209 210enum xgbe_phy_redrv_mode { 211 XGBE_PHY_REDRV_MODE_CX = 5, 212 XGBE_PHY_REDRV_MODE_SR = 9, 213}; 214 215#define XGBE_PHY_REDRV_MODE_REG 0x12b0 216 217/* PHY related configuration information */ 218struct xgbe_phy_data { 219 enum xgbe_port_mode port_mode; 220 221 unsigned int port_id; 222 223 unsigned int port_speeds; 224 225 enum xgbe_conn_type conn_type; 226 227 enum xgbe_mode cur_mode; 228 enum xgbe_mode start_mode; 229 230 unsigned int rrc_count; 231 232 unsigned int mdio_addr; 233 234 /* SFP Support */ 235 enum xgbe_sfp_comm sfp_comm; 236 unsigned int sfp_mux_address; 237 unsigned int sfp_mux_channel; 238 239 unsigned int sfp_gpio_address; 240 unsigned int sfp_gpio_mask; 241 unsigned int sfp_gpio_inputs; 242 unsigned int sfp_gpio_rx_los; 243 unsigned int sfp_gpio_tx_fault; 244 unsigned int sfp_gpio_mod_absent; 245 unsigned int sfp_gpio_rate_select; 246 247 unsigned int sfp_rx_los; 248 unsigned int sfp_tx_fault; 249 unsigned int sfp_mod_absent; 250 unsigned int sfp_changed; 251 unsigned int sfp_phy_avail; 252 unsigned int sfp_cable_len; 253 enum xgbe_sfp_base sfp_base; 254 enum xgbe_sfp_cable sfp_cable; 255 enum xgbe_sfp_speed sfp_speed; 256 struct xgbe_sfp_eeprom sfp_eeprom; 257 258 /* External PHY support */ 259 enum xgbe_mdio_mode phydev_mode; 260 struct mii_bus *mii; 261 struct phy_device *phydev; 262 enum xgbe_mdio_reset mdio_reset; 263 unsigned int mdio_reset_addr; 264 unsigned int mdio_reset_gpio; 265 266 /* Re-driver support */ 267 unsigned int redrv; 268 unsigned int redrv_if; 269 unsigned int redrv_addr; 270 unsigned int redrv_lane; 271 unsigned int redrv_model; 272 273 /* KR AN support */ 274 unsigned int phy_cdr_notrack; 275 unsigned int phy_cdr_delay; 276}; 277 278/* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 279static DEFINE_MUTEX(xgbe_phy_comm_lock); 280 281static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 282static void xgbe_phy_rrc(struct xgbe_prv_data *pdata); 283static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 284 enum xgbe_mb_cmd cmd, 285 enum xgbe_mb_subcmd sub_cmd); 286 287static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 288 struct xgbe_i2c_op *i2c_op) 289{ 290 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 291} 292 293static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 294 unsigned int val) 295{ 296 struct xgbe_phy_data *phy_data = pdata->phy_data; 297 struct xgbe_i2c_op i2c_op; 298 __be16 *redrv_val; 299 u8 redrv_data[5], csum; 300 unsigned int i, retry; 301 int ret; 302 303 /* High byte of register contains read/write indicator */ 304 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 305 redrv_data[1] = reg & 0xff; 306 redrv_val = (__be16 *)&redrv_data[2]; 307 *redrv_val = cpu_to_be16(val); 308 309 /* Calculate 1 byte checksum */ 310 csum = 0; 311 for (i = 0; i < 4; i++) { 312 csum += redrv_data[i]; 313 if (redrv_data[i] > csum) 314 csum++; 315 } 316 redrv_data[4] = ~csum; 317 318 retry = 1; 319again1: 320 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 321 i2c_op.target = phy_data->redrv_addr; 322 i2c_op.len = sizeof(redrv_data); 323 i2c_op.buf = redrv_data; 324 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 325 if (ret) { 326 if ((ret == -EAGAIN) && retry--) 327 goto again1; 328 329 return ret; 330 } 331 332 retry = 1; 333again2: 334 i2c_op.cmd = XGBE_I2C_CMD_READ; 335 i2c_op.target = phy_data->redrv_addr; 336 i2c_op.len = 1; 337 i2c_op.buf = redrv_data; 338 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 339 if (ret) { 340 if ((ret == -EAGAIN) && retry--) 341 goto again2; 342 343 return ret; 344 } 345 346 if (redrv_data[0] != 0xff) { 347 netif_dbg(pdata, drv, pdata->netdev, 348 "Redriver write checksum error\n"); 349 ret = -EIO; 350 } 351 352 return ret; 353} 354 355static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 356 void *val, unsigned int val_len) 357{ 358 struct xgbe_i2c_op i2c_op; 359 int retry, ret; 360 361 retry = 1; 362again: 363 /* Write the specfied register */ 364 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 365 i2c_op.target = target; 366 i2c_op.len = val_len; 367 i2c_op.buf = val; 368 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 369 if ((ret == -EAGAIN) && retry--) 370 goto again; 371 372 return ret; 373} 374 375static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 376 void *reg, unsigned int reg_len, 377 void *val, unsigned int val_len) 378{ 379 struct xgbe_i2c_op i2c_op; 380 int retry, ret; 381 382 retry = 1; 383again1: 384 /* Set the specified register to read */ 385 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 386 i2c_op.target = target; 387 i2c_op.len = reg_len; 388 i2c_op.buf = reg; 389 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 390 if (ret) { 391 if ((ret == -EAGAIN) && retry--) 392 goto again1; 393 394 return ret; 395 } 396 397 retry = 1; 398again2: 399 /* Read the specfied register */ 400 i2c_op.cmd = XGBE_I2C_CMD_READ; 401 i2c_op.target = target; 402 i2c_op.len = val_len; 403 i2c_op.buf = val; 404 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 405 if ((ret == -EAGAIN) && retry--) 406 goto again2; 407 408 return ret; 409} 410 411static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 412{ 413 struct xgbe_phy_data *phy_data = pdata->phy_data; 414 struct xgbe_i2c_op i2c_op; 415 u8 mux_channel; 416 417 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 418 return 0; 419 420 /* Select no mux channels */ 421 mux_channel = 0; 422 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 423 i2c_op.target = phy_data->sfp_mux_address; 424 i2c_op.len = sizeof(mux_channel); 425 i2c_op.buf = &mux_channel; 426 427 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 428} 429 430static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 431{ 432 struct xgbe_phy_data *phy_data = pdata->phy_data; 433 struct xgbe_i2c_op i2c_op; 434 u8 mux_channel; 435 436 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 437 return 0; 438 439 /* Select desired mux channel */ 440 mux_channel = 1 << phy_data->sfp_mux_channel; 441 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 442 i2c_op.target = phy_data->sfp_mux_address; 443 i2c_op.len = sizeof(mux_channel); 444 i2c_op.buf = &mux_channel; 445 446 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 447} 448 449static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 450{ 451 mutex_unlock(&xgbe_phy_comm_lock); 452} 453 454static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 455{ 456 struct xgbe_phy_data *phy_data = pdata->phy_data; 457 unsigned long timeout; 458 unsigned int mutex_id; 459 460 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 461 * the driver needs to take the software mutex and then the hardware 462 * mutexes before being able to use the busses. 463 */ 464 mutex_lock(&xgbe_phy_comm_lock); 465 466 /* Clear the mutexes */ 467 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 468 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 469 470 /* Mutex formats are the same for I2C and MDIO/GPIO */ 471 mutex_id = 0; 472 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 473 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 474 475 timeout = jiffies + (5 * HZ); 476 while (time_before(jiffies, timeout)) { 477 /* Must be all zeroes in order to obtain the mutex */ 478 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 479 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 480 usleep_range(100, 200); 481 continue; 482 } 483 484 /* Obtain the mutex */ 485 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 486 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 487 488 return 0; 489 } 490 491 mutex_unlock(&xgbe_phy_comm_lock); 492 493 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 494 495 return -ETIMEDOUT; 496} 497 498static int xgbe_phy_mdio_mii_write_c22(struct xgbe_prv_data *pdata, int addr, 499 int reg, u16 val) 500{ 501 struct xgbe_phy_data *phy_data = pdata->phy_data; 502 503 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 504 return -EOPNOTSUPP; 505 506 return pdata->hw_if.write_ext_mii_regs_c22(pdata, addr, reg, val); 507} 508 509static int xgbe_phy_mdio_mii_write_c45(struct xgbe_prv_data *pdata, int addr, 510 int devad, int reg, u16 val) 511{ 512 struct xgbe_phy_data *phy_data = pdata->phy_data; 513 514 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 515 return -EOPNOTSUPP; 516 517 return pdata->hw_if.write_ext_mii_regs_c45(pdata, addr, devad, 518 reg, val); 519} 520 521static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 522{ 523 __be16 *mii_val; 524 u8 mii_data[3]; 525 int ret; 526 527 ret = xgbe_phy_sfp_get_mux(pdata); 528 if (ret) 529 return ret; 530 531 mii_data[0] = reg & 0xff; 532 mii_val = (__be16 *)&mii_data[1]; 533 *mii_val = cpu_to_be16(val); 534 535 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 536 mii_data, sizeof(mii_data)); 537 538 xgbe_phy_sfp_put_mux(pdata); 539 540 return ret; 541} 542 543static int xgbe_phy_mii_write_c22(struct mii_bus *mii, int addr, int reg, 544 u16 val) 545{ 546 struct xgbe_prv_data *pdata = mii->priv; 547 struct xgbe_phy_data *phy_data = pdata->phy_data; 548 int ret; 549 550 ret = xgbe_phy_get_comm_ownership(pdata); 551 if (ret) 552 return ret; 553 554 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 555 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 556 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 557 ret = xgbe_phy_mdio_mii_write_c22(pdata, addr, reg, val); 558 else 559 ret = -EOPNOTSUPP; 560 561 xgbe_phy_put_comm_ownership(pdata); 562 563 return ret; 564} 565 566static int xgbe_phy_mii_write_c45(struct mii_bus *mii, int addr, int devad, 567 int reg, u16 val) 568{ 569 struct xgbe_prv_data *pdata = mii->priv; 570 struct xgbe_phy_data *phy_data = pdata->phy_data; 571 int ret; 572 573 ret = xgbe_phy_get_comm_ownership(pdata); 574 if (ret) 575 return ret; 576 577 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 578 ret = -EOPNOTSUPP; 579 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 580 ret = xgbe_phy_mdio_mii_write_c45(pdata, addr, devad, reg, val); 581 else 582 ret = -EOPNOTSUPP; 583 584 xgbe_phy_put_comm_ownership(pdata); 585 586 return ret; 587} 588 589static int xgbe_phy_mdio_mii_read_c22(struct xgbe_prv_data *pdata, int addr, 590 int reg) 591{ 592 struct xgbe_phy_data *phy_data = pdata->phy_data; 593 594 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 595 return -EOPNOTSUPP; 596 597 return pdata->hw_if.read_ext_mii_regs_c22(pdata, addr, reg); 598} 599 600static int xgbe_phy_mdio_mii_read_c45(struct xgbe_prv_data *pdata, int addr, 601 int devad, int reg) 602{ 603 struct xgbe_phy_data *phy_data = pdata->phy_data; 604 605 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 606 return -EOPNOTSUPP; 607 608 return pdata->hw_if.read_ext_mii_regs_c45(pdata, addr, devad, reg); 609} 610 611static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 612{ 613 __be16 mii_val; 614 u8 mii_reg; 615 int ret; 616 617 ret = xgbe_phy_sfp_get_mux(pdata); 618 if (ret) 619 return ret; 620 621 mii_reg = reg; 622 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 623 &mii_reg, sizeof(mii_reg), 624 &mii_val, sizeof(mii_val)); 625 if (!ret) 626 ret = be16_to_cpu(mii_val); 627 628 xgbe_phy_sfp_put_mux(pdata); 629 630 return ret; 631} 632 633static int xgbe_phy_mii_read_c22(struct mii_bus *mii, int addr, int reg) 634{ 635 struct xgbe_prv_data *pdata = mii->priv; 636 struct xgbe_phy_data *phy_data = pdata->phy_data; 637 int ret; 638 639 ret = xgbe_phy_get_comm_ownership(pdata); 640 if (ret) 641 return ret; 642 643 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 644 ret = xgbe_phy_i2c_mii_read(pdata, reg); 645 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 646 ret = xgbe_phy_mdio_mii_read_c22(pdata, addr, reg); 647 else 648 ret = -EOPNOTSUPP; 649 650 xgbe_phy_put_comm_ownership(pdata); 651 652 return ret; 653} 654 655static int xgbe_phy_mii_read_c45(struct mii_bus *mii, int addr, int devad, 656 int reg) 657{ 658 struct xgbe_prv_data *pdata = mii->priv; 659 struct xgbe_phy_data *phy_data = pdata->phy_data; 660 int ret; 661 662 ret = xgbe_phy_get_comm_ownership(pdata); 663 if (ret) 664 return ret; 665 666 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 667 ret = -EOPNOTSUPP; 668 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 669 ret = xgbe_phy_mdio_mii_read_c45(pdata, addr, devad, reg); 670 else 671 ret = -EOPNOTSUPP; 672 673 xgbe_phy_put_comm_ownership(pdata); 674 675 return ret; 676} 677 678static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 679{ 680 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 681 struct xgbe_phy_data *phy_data = pdata->phy_data; 682 683 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 684 return; 685 686 XGBE_ZERO_SUP(lks); 687 688 if (phy_data->sfp_mod_absent) { 689 pdata->phy.speed = SPEED_UNKNOWN; 690 pdata->phy.duplex = DUPLEX_UNKNOWN; 691 pdata->phy.autoneg = AUTONEG_ENABLE; 692 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 693 694 XGBE_SET_SUP(lks, Autoneg); 695 XGBE_SET_SUP(lks, Pause); 696 XGBE_SET_SUP(lks, Asym_Pause); 697 XGBE_SET_SUP(lks, TP); 698 XGBE_SET_SUP(lks, FIBRE); 699 700 XGBE_LM_COPY(lks, advertising, lks, supported); 701 702 return; 703 } 704 705 switch (phy_data->sfp_base) { 706 case XGBE_SFP_BASE_1000_T: 707 case XGBE_SFP_BASE_1000_SX: 708 case XGBE_SFP_BASE_1000_LX: 709 case XGBE_SFP_BASE_1000_CX: 710 pdata->phy.speed = SPEED_UNKNOWN; 711 pdata->phy.duplex = DUPLEX_UNKNOWN; 712 pdata->phy.autoneg = AUTONEG_ENABLE; 713 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 714 XGBE_SET_SUP(lks, Autoneg); 715 XGBE_SET_SUP(lks, Pause); 716 XGBE_SET_SUP(lks, Asym_Pause); 717 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 718 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) 719 XGBE_SET_SUP(lks, 10baseT_Full); 720 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 721 XGBE_SET_SUP(lks, 100baseT_Full); 722 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 723 XGBE_SET_SUP(lks, 1000baseT_Full); 724 } else { 725 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 726 XGBE_SET_SUP(lks, 1000baseX_Full); 727 } 728 break; 729 case XGBE_SFP_BASE_10000_SR: 730 case XGBE_SFP_BASE_10000_LR: 731 case XGBE_SFP_BASE_10000_LRM: 732 case XGBE_SFP_BASE_10000_ER: 733 case XGBE_SFP_BASE_10000_CR: 734 pdata->phy.speed = SPEED_10000; 735 pdata->phy.duplex = DUPLEX_FULL; 736 pdata->phy.autoneg = AUTONEG_DISABLE; 737 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 738 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 739 switch (phy_data->sfp_base) { 740 case XGBE_SFP_BASE_10000_SR: 741 XGBE_SET_SUP(lks, 10000baseSR_Full); 742 break; 743 case XGBE_SFP_BASE_10000_LR: 744 XGBE_SET_SUP(lks, 10000baseLR_Full); 745 break; 746 case XGBE_SFP_BASE_10000_LRM: 747 XGBE_SET_SUP(lks, 10000baseLRM_Full); 748 break; 749 case XGBE_SFP_BASE_10000_ER: 750 XGBE_SET_SUP(lks, 10000baseER_Full); 751 break; 752 case XGBE_SFP_BASE_10000_CR: 753 XGBE_SET_SUP(lks, 10000baseCR_Full); 754 break; 755 default: 756 break; 757 } 758 } 759 break; 760 default: 761 pdata->phy.speed = SPEED_UNKNOWN; 762 pdata->phy.duplex = DUPLEX_UNKNOWN; 763 pdata->phy.autoneg = AUTONEG_DISABLE; 764 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 765 break; 766 } 767 768 switch (phy_data->sfp_base) { 769 case XGBE_SFP_BASE_1000_T: 770 case XGBE_SFP_BASE_1000_CX: 771 case XGBE_SFP_BASE_10000_CR: 772 XGBE_SET_SUP(lks, TP); 773 break; 774 default: 775 XGBE_SET_SUP(lks, FIBRE); 776 break; 777 } 778 779 XGBE_LM_COPY(lks, advertising, lks, supported); 780} 781 782static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 783 enum xgbe_sfp_speed sfp_speed) 784{ 785 u8 *sfp_base, min; 786 787 sfp_base = sfp_eeprom->base; 788 789 switch (sfp_speed) { 790 case XGBE_SFP_SPEED_1000: 791 min = XGBE_SFP_BASE_BR_1GBE_MIN; 792 break; 793 case XGBE_SFP_SPEED_10000: 794 min = XGBE_SFP_BASE_BR_10GBE_MIN; 795 break; 796 default: 797 return false; 798 } 799 800 return sfp_base[XGBE_SFP_BASE_BR] >= min; 801} 802 803static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 804{ 805 struct xgbe_phy_data *phy_data = pdata->phy_data; 806 807 if (phy_data->phydev) { 808 phy_detach(phy_data->phydev); 809 phy_device_remove(phy_data->phydev); 810 phy_device_free(phy_data->phydev); 811 phy_data->phydev = NULL; 812 } 813} 814 815static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 816{ 817 struct xgbe_phy_data *phy_data = pdata->phy_data; 818 unsigned int phy_id = phy_data->phydev->phy_id; 819 820 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 821 return false; 822 823 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 824 return false; 825 826 /* Enable Base-T AN */ 827 phy_write(phy_data->phydev, 0x16, 0x0001); 828 phy_write(phy_data->phydev, 0x00, 0x9140); 829 phy_write(phy_data->phydev, 0x16, 0x0000); 830 831 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 832 phy_write(phy_data->phydev, 0x1b, 0x9084); 833 phy_write(phy_data->phydev, 0x09, 0x0e00); 834 phy_write(phy_data->phydev, 0x00, 0x8140); 835 phy_write(phy_data->phydev, 0x04, 0x0d01); 836 phy_write(phy_data->phydev, 0x00, 0x9140); 837 838 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES); 839 840 phy_support_asym_pause(phy_data->phydev); 841 842 netif_dbg(pdata, drv, pdata->netdev, 843 "Finisar PHY quirk in place\n"); 844 845 return true; 846} 847 848static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) 849{ 850 struct xgbe_phy_data *phy_data = pdata->phy_data; 851 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 852 unsigned int phy_id = phy_data->phydev->phy_id; 853 int reg; 854 855 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 856 return false; 857 858 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 859 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 860 return false; 861 862 /* For Bel-Fuse, use the extra AN flag */ 863 pdata->an_again = 1; 864 865 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 866 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) 867 return false; 868 869 if ((phy_id & 0xfffffff0) != 0x03625d10) 870 return false; 871 872 /* Reset PHY - wait for self-clearing reset bit to clear */ 873 genphy_soft_reset(phy_data->phydev); 874 875 /* Disable RGMII mode */ 876 phy_write(phy_data->phydev, 0x18, 0x7007); 877 reg = phy_read(phy_data->phydev, 0x18); 878 phy_write(phy_data->phydev, 0x18, reg & ~0x0080); 879 880 /* Enable fiber register bank */ 881 phy_write(phy_data->phydev, 0x1c, 0x7c00); 882 reg = phy_read(phy_data->phydev, 0x1c); 883 reg &= 0x03ff; 884 reg &= ~0x0001; 885 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001); 886 887 /* Power down SerDes */ 888 reg = phy_read(phy_data->phydev, 0x00); 889 phy_write(phy_data->phydev, 0x00, reg | 0x00800); 890 891 /* Configure SGMII-to-Copper mode */ 892 phy_write(phy_data->phydev, 0x1c, 0x7c00); 893 reg = phy_read(phy_data->phydev, 0x1c); 894 reg &= 0x03ff; 895 reg &= ~0x0006; 896 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004); 897 898 /* Power up SerDes */ 899 reg = phy_read(phy_data->phydev, 0x00); 900 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 901 902 /* Enable copper register bank */ 903 phy_write(phy_data->phydev, 0x1c, 0x7c00); 904 reg = phy_read(phy_data->phydev, 0x1c); 905 reg &= 0x03ff; 906 reg &= ~0x0001; 907 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg); 908 909 /* Power up SerDes */ 910 reg = phy_read(phy_data->phydev, 0x00); 911 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 912 913 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES); 914 phy_support_asym_pause(phy_data->phydev); 915 916 netif_dbg(pdata, drv, pdata->netdev, 917 "BelFuse PHY quirk in place\n"); 918 919 return true; 920} 921 922static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 923{ 924 if (xgbe_phy_belfuse_phy_quirks(pdata)) 925 return; 926 927 if (xgbe_phy_finisar_phy_quirks(pdata)) 928 return; 929} 930 931static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 932{ 933 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 934 struct xgbe_phy_data *phy_data = pdata->phy_data; 935 struct phy_device *phydev; 936 int ret; 937 938 /* If we already have a PHY, just return */ 939 if (phy_data->phydev) 940 return 0; 941 942 /* Clear the extra AN flag */ 943 pdata->an_again = 0; 944 945 /* Check for the use of an external PHY */ 946 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 947 return 0; 948 949 /* For SFP, only use an external PHY if available */ 950 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 951 !phy_data->sfp_phy_avail) 952 return 0; 953 954 /* Set the proper MDIO mode for the PHY */ 955 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 956 phy_data->phydev_mode); 957 if (ret) { 958 netdev_err(pdata->netdev, 959 "mdio port/clause not compatible (%u/%u)\n", 960 phy_data->mdio_addr, phy_data->phydev_mode); 961 return ret; 962 } 963 964 /* Create and connect to the PHY device */ 965 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 966 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 967 if (IS_ERR(phydev)) { 968 netdev_err(pdata->netdev, "get_phy_device failed\n"); 969 return -ENODEV; 970 } 971 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 972 phydev->phy_id); 973 974 /*TODO: If c45, add request_module based on one of the MMD ids? */ 975 976 ret = phy_device_register(phydev); 977 if (ret) { 978 netdev_err(pdata->netdev, "phy_device_register failed\n"); 979 phy_device_free(phydev); 980 return ret; 981 } 982 983 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 984 PHY_INTERFACE_MODE_SGMII); 985 if (ret) { 986 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 987 phy_device_remove(phydev); 988 phy_device_free(phydev); 989 return ret; 990 } 991 phy_data->phydev = phydev; 992 phy_data->phydev->mac_managed_pm = true; 993 994 xgbe_phy_external_phy_quirks(pdata); 995 996 linkmode_and(phydev->advertising, phydev->advertising, 997 lks->link_modes.advertising); 998 999 phy_start_aneg(phy_data->phydev); 1000 1001 return 0; 1002} 1003 1004static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 1005{ 1006 struct xgbe_phy_data *phy_data = pdata->phy_data; 1007 int ret; 1008 1009 if (!phy_data->sfp_changed) 1010 return; 1011 1012 phy_data->sfp_phy_avail = 0; 1013 1014 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 1015 return; 1016 1017 /* Check access to the PHY by reading CTRL1 */ 1018 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 1019 if (ret < 0) 1020 return; 1021 1022 /* Successfully accessed the PHY */ 1023 phy_data->sfp_phy_avail = 1; 1024} 1025 1026static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 1027{ 1028 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1029 1030 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 1031 return false; 1032 1033 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1034 return false; 1035 1036 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1037 return true; 1038 1039 return false; 1040} 1041 1042static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1043{ 1044 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1045 1046 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1047 return false; 1048 1049 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1050 return false; 1051 1052 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1053 return true; 1054 1055 return false; 1056} 1057 1058static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1059{ 1060 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1061 return false; 1062 1063 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1064 return true; 1065 1066 return false; 1067} 1068 1069static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1070{ 1071 struct xgbe_phy_data *phy_data = pdata->phy_data; 1072 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1073 u8 *sfp_base; 1074 1075 sfp_base = sfp_eeprom->base; 1076 1077 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1078 return; 1079 1080 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1081 return; 1082 1083 /* Update transceiver signals (eeprom extd/options) */ 1084 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1085 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1086 1087 /* Assume FIBER cable unless told otherwise */ 1088 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1089 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1090 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1091 } else if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_ACTIVE) { 1092 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1093 } else { 1094 phy_data->sfp_cable = XGBE_SFP_CABLE_FIBER; 1095 } 1096 1097 /* Determine the type of SFP */ 1098 if (phy_data->sfp_cable != XGBE_SFP_CABLE_FIBER && 1099 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1100 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1101 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1102 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1103 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1104 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1105 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1106 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1107 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1108 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1109 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1110 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1111 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1112 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1113 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1114 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1115 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1116 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1117 1118 switch (phy_data->sfp_base) { 1119 case XGBE_SFP_BASE_1000_T: 1120 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1121 break; 1122 case XGBE_SFP_BASE_1000_SX: 1123 case XGBE_SFP_BASE_1000_LX: 1124 case XGBE_SFP_BASE_1000_CX: 1125 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1126 break; 1127 case XGBE_SFP_BASE_10000_SR: 1128 case XGBE_SFP_BASE_10000_LR: 1129 case XGBE_SFP_BASE_10000_LRM: 1130 case XGBE_SFP_BASE_10000_ER: 1131 case XGBE_SFP_BASE_10000_CR: 1132 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1133 break; 1134 default: 1135 break; 1136 } 1137} 1138 1139static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1140 struct xgbe_sfp_eeprom *sfp_eeprom) 1141{ 1142 struct xgbe_sfp_ascii sfp_ascii; 1143 char *sfp_data = (char *)&sfp_ascii; 1144 1145 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1146 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1147 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1148 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1149 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1150 sfp_data); 1151 1152 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1153 XGBE_SFP_BASE_VENDOR_PN_LEN); 1154 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1155 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1156 sfp_data); 1157 1158 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1159 XGBE_SFP_BASE_VENDOR_REV_LEN); 1160 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1161 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1162 sfp_data); 1163 1164 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1165 XGBE_SFP_BASE_VENDOR_SN_LEN); 1166 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1167 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1168 sfp_data); 1169} 1170 1171static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1172{ 1173 u8 cc; 1174 1175 for (cc = 0; len; buf++, len--) 1176 cc += *buf; 1177 1178 return cc == cc_in; 1179} 1180 1181static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1182{ 1183 struct xgbe_phy_data *phy_data = pdata->phy_data; 1184 struct xgbe_sfp_eeprom sfp_eeprom; 1185 u8 eeprom_addr; 1186 int ret; 1187 1188 ret = xgbe_phy_sfp_get_mux(pdata); 1189 if (ret) { 1190 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1191 netdev_name(pdata->netdev)); 1192 return ret; 1193 } 1194 1195 /* Read the SFP serial ID eeprom */ 1196 eeprom_addr = 0; 1197 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1198 &eeprom_addr, sizeof(eeprom_addr), 1199 &sfp_eeprom, sizeof(sfp_eeprom)); 1200 if (ret) { 1201 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1202 netdev_name(pdata->netdev)); 1203 goto put; 1204 } 1205 1206 /* Validate the contents read */ 1207 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1208 sfp_eeprom.base, 1209 sizeof(sfp_eeprom.base) - 1)) { 1210 ret = -EINVAL; 1211 goto put; 1212 } 1213 1214 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1215 sfp_eeprom.extd, 1216 sizeof(sfp_eeprom.extd) - 1)) { 1217 ret = -EINVAL; 1218 goto put; 1219 } 1220 1221 /* Check for an added or changed SFP */ 1222 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1223 phy_data->sfp_changed = 1; 1224 1225 if (netif_msg_drv(pdata)) 1226 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1227 1228 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1229 1230 xgbe_phy_free_phy_device(pdata); 1231 } else { 1232 phy_data->sfp_changed = 0; 1233 } 1234 1235put: 1236 xgbe_phy_sfp_put_mux(pdata); 1237 1238 return ret; 1239} 1240 1241static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1242{ 1243 struct xgbe_phy_data *phy_data = pdata->phy_data; 1244 u8 gpio_reg, gpio_ports[2]; 1245 int ret; 1246 1247 /* Read the input port registers */ 1248 gpio_reg = 0; 1249 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1250 &gpio_reg, sizeof(gpio_reg), 1251 gpio_ports, sizeof(gpio_ports)); 1252 if (ret) { 1253 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1254 netdev_name(pdata->netdev)); 1255 return; 1256 } 1257 1258 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1259 1260 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1261} 1262 1263static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1264{ 1265 struct xgbe_phy_data *phy_data = pdata->phy_data; 1266 1267 xgbe_phy_free_phy_device(pdata); 1268 1269 phy_data->sfp_mod_absent = 1; 1270 phy_data->sfp_phy_avail = 0; 1271 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1272} 1273 1274static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1275{ 1276 phy_data->sfp_rx_los = 0; 1277 phy_data->sfp_tx_fault = 0; 1278 phy_data->sfp_mod_absent = 1; 1279 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1280 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1281 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1282} 1283 1284static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1285{ 1286 struct xgbe_phy_data *phy_data = pdata->phy_data; 1287 int ret; 1288 1289 /* Reset the SFP signals and info */ 1290 xgbe_phy_sfp_reset(phy_data); 1291 1292 ret = xgbe_phy_get_comm_ownership(pdata); 1293 if (ret) 1294 return; 1295 1296 /* Read the SFP signals and check for module presence */ 1297 xgbe_phy_sfp_signals(pdata); 1298 if (phy_data->sfp_mod_absent) { 1299 xgbe_phy_sfp_mod_absent(pdata); 1300 goto put; 1301 } 1302 1303 ret = xgbe_phy_sfp_read_eeprom(pdata); 1304 if (ret) { 1305 /* Treat any error as if there isn't an SFP plugged in */ 1306 xgbe_phy_sfp_reset(phy_data); 1307 xgbe_phy_sfp_mod_absent(pdata); 1308 goto put; 1309 } 1310 1311 xgbe_phy_sfp_parse_eeprom(pdata); 1312 1313 xgbe_phy_sfp_external_phy(pdata); 1314 1315put: 1316 xgbe_phy_sfp_phy_settings(pdata); 1317 1318 xgbe_phy_put_comm_ownership(pdata); 1319} 1320 1321static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata, 1322 struct ethtool_eeprom *eeprom, u8 *data) 1323{ 1324 struct xgbe_phy_data *phy_data = pdata->phy_data; 1325 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX]; 1326 struct xgbe_sfp_eeprom *sfp_eeprom; 1327 unsigned int i, j, rem; 1328 int ret; 1329 1330 rem = eeprom->len; 1331 1332 if (!eeprom->len) { 1333 ret = -EINVAL; 1334 goto done; 1335 } 1336 1337 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) { 1338 ret = -EINVAL; 1339 goto done; 1340 } 1341 1342 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 1343 ret = -ENXIO; 1344 goto done; 1345 } 1346 1347 if (!netif_running(pdata->netdev)) { 1348 ret = -EIO; 1349 goto done; 1350 } 1351 1352 if (phy_data->sfp_mod_absent) { 1353 ret = -EIO; 1354 goto done; 1355 } 1356 1357 ret = xgbe_phy_get_comm_ownership(pdata); 1358 if (ret) { 1359 ret = -EIO; 1360 goto done; 1361 } 1362 1363 ret = xgbe_phy_sfp_get_mux(pdata); 1364 if (ret) { 1365 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n"); 1366 ret = -EIO; 1367 goto put_own; 1368 } 1369 1370 /* Read the SFP serial ID eeprom */ 1371 eeprom_addr = 0; 1372 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1373 &eeprom_addr, sizeof(eeprom_addr), 1374 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN); 1375 if (ret) { 1376 netdev_err(pdata->netdev, 1377 "I2C error reading SFP EEPROM\n"); 1378 ret = -EIO; 1379 goto put_mux; 1380 } 1381 1382 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data; 1383 1384 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) { 1385 /* Read the SFP diagnostic eeprom */ 1386 eeprom_addr = 0; 1387 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS, 1388 &eeprom_addr, sizeof(eeprom_addr), 1389 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN, 1390 XGBE_SFP_EEPROM_DIAG_LEN); 1391 if (ret) { 1392 netdev_err(pdata->netdev, 1393 "I2C error reading SFP DIAGS\n"); 1394 ret = -EIO; 1395 goto put_mux; 1396 } 1397 } 1398 1399 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) { 1400 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) && 1401 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) 1402 break; 1403 1404 data[i] = eeprom_data[j]; 1405 rem--; 1406 } 1407 1408put_mux: 1409 xgbe_phy_sfp_put_mux(pdata); 1410 1411put_own: 1412 xgbe_phy_put_comm_ownership(pdata); 1413 1414done: 1415 eeprom->len -= rem; 1416 1417 return ret; 1418} 1419 1420static int xgbe_phy_module_info(struct xgbe_prv_data *pdata, 1421 struct ethtool_modinfo *modinfo) 1422{ 1423 struct xgbe_phy_data *phy_data = pdata->phy_data; 1424 1425 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 1426 return -ENXIO; 1427 1428 if (!netif_running(pdata->netdev)) 1429 return -EIO; 1430 1431 if (phy_data->sfp_mod_absent) 1432 return -EIO; 1433 1434 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) { 1435 modinfo->type = ETH_MODULE_SFF_8472; 1436 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1437 } else { 1438 modinfo->type = ETH_MODULE_SFF_8079; 1439 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1440 } 1441 1442 return 0; 1443} 1444 1445static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1446{ 1447 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1448 struct xgbe_phy_data *phy_data = pdata->phy_data; 1449 u16 lcl_adv = 0, rmt_adv = 0; 1450 u8 fc; 1451 1452 pdata->phy.tx_pause = 0; 1453 pdata->phy.rx_pause = 0; 1454 1455 if (!phy_data->phydev) 1456 return; 1457 1458 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising); 1459 1460 if (phy_data->phydev->pause) { 1461 XGBE_SET_LP_ADV(lks, Pause); 1462 rmt_adv |= LPA_PAUSE_CAP; 1463 } 1464 if (phy_data->phydev->asym_pause) { 1465 XGBE_SET_LP_ADV(lks, Asym_Pause); 1466 rmt_adv |= LPA_PAUSE_ASYM; 1467 } 1468 1469 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1470 if (fc & FLOW_CTRL_TX) 1471 pdata->phy.tx_pause = 1; 1472 if (fc & FLOW_CTRL_RX) 1473 pdata->phy.rx_pause = 1; 1474} 1475 1476static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1477{ 1478 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1479 enum xgbe_mode mode; 1480 1481 XGBE_SET_LP_ADV(lks, Autoneg); 1482 XGBE_SET_LP_ADV(lks, TP); 1483 1484 /* Use external PHY to determine flow control */ 1485 if (pdata->phy.pause_autoneg) 1486 xgbe_phy_phydev_flowctrl(pdata); 1487 1488 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1489 case XGBE_SGMII_AN_LINK_SPEED_10: 1490 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1491 XGBE_SET_LP_ADV(lks, 10baseT_Full); 1492 mode = XGBE_MODE_SGMII_10; 1493 } else { 1494 /* Half-duplex not supported */ 1495 XGBE_SET_LP_ADV(lks, 10baseT_Half); 1496 mode = XGBE_MODE_UNKNOWN; 1497 } 1498 break; 1499 case XGBE_SGMII_AN_LINK_SPEED_100: 1500 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1501 XGBE_SET_LP_ADV(lks, 100baseT_Full); 1502 mode = XGBE_MODE_SGMII_100; 1503 } else { 1504 /* Half-duplex not supported */ 1505 XGBE_SET_LP_ADV(lks, 100baseT_Half); 1506 mode = XGBE_MODE_UNKNOWN; 1507 } 1508 break; 1509 case XGBE_SGMII_AN_LINK_SPEED_1000: 1510 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1511 XGBE_SET_LP_ADV(lks, 1000baseT_Full); 1512 mode = XGBE_MODE_SGMII_1000; 1513 } else { 1514 /* Half-duplex not supported */ 1515 XGBE_SET_LP_ADV(lks, 1000baseT_Half); 1516 mode = XGBE_MODE_UNKNOWN; 1517 } 1518 break; 1519 default: 1520 mode = XGBE_MODE_UNKNOWN; 1521 } 1522 1523 return mode; 1524} 1525 1526static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1527{ 1528 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1529 enum xgbe_mode mode; 1530 unsigned int ad_reg, lp_reg; 1531 1532 XGBE_SET_LP_ADV(lks, Autoneg); 1533 XGBE_SET_LP_ADV(lks, FIBRE); 1534 1535 /* Compare Advertisement and Link Partner register */ 1536 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1537 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1538 if (lp_reg & 0x100) 1539 XGBE_SET_LP_ADV(lks, Pause); 1540 if (lp_reg & 0x80) 1541 XGBE_SET_LP_ADV(lks, Asym_Pause); 1542 1543 if (pdata->phy.pause_autoneg) { 1544 /* Set flow control based on auto-negotiation result */ 1545 pdata->phy.tx_pause = 0; 1546 pdata->phy.rx_pause = 0; 1547 1548 if (ad_reg & lp_reg & 0x100) { 1549 pdata->phy.tx_pause = 1; 1550 pdata->phy.rx_pause = 1; 1551 } else if (ad_reg & lp_reg & 0x80) { 1552 if (ad_reg & 0x100) 1553 pdata->phy.rx_pause = 1; 1554 else if (lp_reg & 0x100) 1555 pdata->phy.tx_pause = 1; 1556 } 1557 } 1558 1559 if (lp_reg & 0x20) 1560 XGBE_SET_LP_ADV(lks, 1000baseX_Full); 1561 1562 /* Half duplex is not supported */ 1563 ad_reg &= lp_reg; 1564 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1565 1566 return mode; 1567} 1568 1569static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1570{ 1571 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1572 struct xgbe_phy_data *phy_data = pdata->phy_data; 1573 enum xgbe_mode mode; 1574 unsigned int ad_reg, lp_reg; 1575 1576 XGBE_SET_LP_ADV(lks, Autoneg); 1577 XGBE_SET_LP_ADV(lks, Backplane); 1578 1579 /* Use external PHY to determine flow control */ 1580 if (pdata->phy.pause_autoneg) 1581 xgbe_phy_phydev_flowctrl(pdata); 1582 1583 /* Compare Advertisement and Link Partner register 2 */ 1584 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1585 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1586 if (lp_reg & 0x80) 1587 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1588 if (lp_reg & 0x20) 1589 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1590 1591 ad_reg &= lp_reg; 1592 if (ad_reg & 0x80) { 1593 switch (phy_data->port_mode) { 1594 case XGBE_PORT_MODE_BACKPLANE: 1595 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1596 mode = XGBE_MODE_KR; 1597 break; 1598 default: 1599 mode = XGBE_MODE_SFI; 1600 break; 1601 } 1602 } else if (ad_reg & 0x20) { 1603 switch (phy_data->port_mode) { 1604 case XGBE_PORT_MODE_BACKPLANE: 1605 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1606 mode = XGBE_MODE_KX_1000; 1607 break; 1608 case XGBE_PORT_MODE_1000BASE_X: 1609 mode = XGBE_MODE_X; 1610 break; 1611 case XGBE_PORT_MODE_SFP: 1612 switch (phy_data->sfp_base) { 1613 case XGBE_SFP_BASE_1000_T: 1614 if (phy_data->phydev && 1615 (phy_data->phydev->speed == SPEED_10)) 1616 mode = XGBE_MODE_SGMII_10; 1617 else if (phy_data->phydev && 1618 (phy_data->phydev->speed == SPEED_100)) 1619 mode = XGBE_MODE_SGMII_100; 1620 else 1621 mode = XGBE_MODE_SGMII_1000; 1622 break; 1623 case XGBE_SFP_BASE_1000_SX: 1624 case XGBE_SFP_BASE_1000_LX: 1625 case XGBE_SFP_BASE_1000_CX: 1626 default: 1627 mode = XGBE_MODE_X; 1628 break; 1629 } 1630 break; 1631 default: 1632 if (phy_data->phydev && 1633 (phy_data->phydev->speed == SPEED_10)) 1634 mode = XGBE_MODE_SGMII_10; 1635 else if (phy_data->phydev && 1636 (phy_data->phydev->speed == SPEED_100)) 1637 mode = XGBE_MODE_SGMII_100; 1638 else 1639 mode = XGBE_MODE_SGMII_1000; 1640 break; 1641 } 1642 } else { 1643 mode = XGBE_MODE_UNKNOWN; 1644 } 1645 1646 /* Compare Advertisement and Link Partner register 3 */ 1647 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1648 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1649 if (lp_reg & 0xc000) 1650 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1651 1652 return mode; 1653} 1654 1655static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1656{ 1657 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1658 enum xgbe_mode mode; 1659 unsigned int ad_reg, lp_reg; 1660 1661 XGBE_SET_LP_ADV(lks, Autoneg); 1662 XGBE_SET_LP_ADV(lks, Backplane); 1663 1664 /* Compare Advertisement and Link Partner register 1 */ 1665 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1666 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1667 if (lp_reg & 0x400) 1668 XGBE_SET_LP_ADV(lks, Pause); 1669 if (lp_reg & 0x800) 1670 XGBE_SET_LP_ADV(lks, Asym_Pause); 1671 1672 if (pdata->phy.pause_autoneg) { 1673 /* Set flow control based on auto-negotiation result */ 1674 pdata->phy.tx_pause = 0; 1675 pdata->phy.rx_pause = 0; 1676 1677 if (ad_reg & lp_reg & 0x400) { 1678 pdata->phy.tx_pause = 1; 1679 pdata->phy.rx_pause = 1; 1680 } else if (ad_reg & lp_reg & 0x800) { 1681 if (ad_reg & 0x400) 1682 pdata->phy.rx_pause = 1; 1683 else if (lp_reg & 0x400) 1684 pdata->phy.tx_pause = 1; 1685 } 1686 } 1687 1688 /* Compare Advertisement and Link Partner register 2 */ 1689 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1690 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1691 if (lp_reg & 0x80) 1692 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1693 if (lp_reg & 0x20) 1694 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1695 1696 ad_reg &= lp_reg; 1697 if (ad_reg & 0x80) 1698 mode = XGBE_MODE_KR; 1699 else if (ad_reg & 0x20) 1700 mode = XGBE_MODE_KX_1000; 1701 else 1702 mode = XGBE_MODE_UNKNOWN; 1703 1704 /* Compare Advertisement and Link Partner register 3 */ 1705 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1706 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1707 if (lp_reg & 0xc000) 1708 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1709 1710 return mode; 1711} 1712 1713static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1714{ 1715 switch (pdata->an_mode) { 1716 case XGBE_AN_MODE_CL73: 1717 return xgbe_phy_an73_outcome(pdata); 1718 case XGBE_AN_MODE_CL73_REDRV: 1719 return xgbe_phy_an73_redrv_outcome(pdata); 1720 case XGBE_AN_MODE_CL37: 1721 return xgbe_phy_an37_outcome(pdata); 1722 case XGBE_AN_MODE_CL37_SGMII: 1723 return xgbe_phy_an37_sgmii_outcome(pdata); 1724 default: 1725 return XGBE_MODE_UNKNOWN; 1726 } 1727} 1728 1729static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, 1730 struct ethtool_link_ksettings *dlks) 1731{ 1732 struct ethtool_link_ksettings *slks = &pdata->phy.lks; 1733 struct xgbe_phy_data *phy_data = pdata->phy_data; 1734 1735 XGBE_LM_COPY(dlks, advertising, slks, advertising); 1736 1737 /* Without a re-driver, just return current advertising */ 1738 if (!phy_data->redrv) 1739 return; 1740 1741 /* With the KR re-driver we need to advertise a single speed */ 1742 XGBE_CLR_ADV(dlks, 1000baseKX_Full); 1743 XGBE_CLR_ADV(dlks, 10000baseKR_Full); 1744 1745 /* Advertise FEC support is present */ 1746 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1747 XGBE_SET_ADV(dlks, 10000baseR_FEC); 1748 1749 switch (phy_data->port_mode) { 1750 case XGBE_PORT_MODE_BACKPLANE: 1751 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1752 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1753 break; 1754 case XGBE_PORT_MODE_BACKPLANE_2500: 1755 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1756 break; 1757 case XGBE_PORT_MODE_1000BASE_T: 1758 case XGBE_PORT_MODE_1000BASE_X: 1759 case XGBE_PORT_MODE_NBASE_T: 1760 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1761 break; 1762 case XGBE_PORT_MODE_10GBASE_T: 1763 if (phy_data->phydev && 1764 (phy_data->phydev->speed == SPEED_10000)) 1765 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1766 else if (phy_data->phydev && 1767 (phy_data->phydev->speed == SPEED_2500)) 1768 XGBE_SET_ADV(dlks, 2500baseX_Full); 1769 else 1770 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1771 break; 1772 case XGBE_PORT_MODE_10GBASE_R: 1773 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1774 break; 1775 case XGBE_PORT_MODE_SFP: 1776 switch (phy_data->sfp_base) { 1777 case XGBE_SFP_BASE_1000_T: 1778 case XGBE_SFP_BASE_1000_SX: 1779 case XGBE_SFP_BASE_1000_LX: 1780 case XGBE_SFP_BASE_1000_CX: 1781 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1782 break; 1783 default: 1784 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1785 break; 1786 } 1787 break; 1788 default: 1789 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1790 break; 1791 } 1792} 1793 1794static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1795{ 1796 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1797 struct xgbe_phy_data *phy_data = pdata->phy_data; 1798 int ret; 1799 1800 ret = xgbe_phy_find_phy_device(pdata); 1801 if (ret) 1802 return ret; 1803 1804 if (!phy_data->phydev) 1805 return 0; 1806 1807 phy_data->phydev->autoneg = pdata->phy.autoneg; 1808 linkmode_and(phy_data->phydev->advertising, 1809 phy_data->phydev->supported, 1810 lks->link_modes.advertising); 1811 1812 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1813 phy_data->phydev->speed = pdata->phy.speed; 1814 phy_data->phydev->duplex = pdata->phy.duplex; 1815 } 1816 1817 ret = phy_start_aneg(phy_data->phydev); 1818 1819 return ret; 1820} 1821 1822static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1823{ 1824 switch (phy_data->sfp_base) { 1825 case XGBE_SFP_BASE_1000_T: 1826 return XGBE_AN_MODE_CL37_SGMII; 1827 case XGBE_SFP_BASE_1000_SX: 1828 case XGBE_SFP_BASE_1000_LX: 1829 case XGBE_SFP_BASE_1000_CX: 1830 return XGBE_AN_MODE_CL37; 1831 default: 1832 return XGBE_AN_MODE_NONE; 1833 } 1834} 1835 1836static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1837{ 1838 struct xgbe_phy_data *phy_data = pdata->phy_data; 1839 1840 /* A KR re-driver will always require CL73 AN */ 1841 if (phy_data->redrv) 1842 return XGBE_AN_MODE_CL73_REDRV; 1843 1844 switch (phy_data->port_mode) { 1845 case XGBE_PORT_MODE_BACKPLANE: 1846 return XGBE_AN_MODE_CL73; 1847 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1848 case XGBE_PORT_MODE_BACKPLANE_2500: 1849 return XGBE_AN_MODE_NONE; 1850 case XGBE_PORT_MODE_1000BASE_T: 1851 return XGBE_AN_MODE_CL37_SGMII; 1852 case XGBE_PORT_MODE_1000BASE_X: 1853 return XGBE_AN_MODE_CL37; 1854 case XGBE_PORT_MODE_NBASE_T: 1855 return XGBE_AN_MODE_CL37_SGMII; 1856 case XGBE_PORT_MODE_10GBASE_T: 1857 return XGBE_AN_MODE_CL73; 1858 case XGBE_PORT_MODE_10GBASE_R: 1859 return XGBE_AN_MODE_NONE; 1860 case XGBE_PORT_MODE_SFP: 1861 return xgbe_phy_an_sfp_mode(phy_data); 1862 default: 1863 return XGBE_AN_MODE_NONE; 1864 } 1865} 1866 1867static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1868 enum xgbe_phy_redrv_mode mode) 1869{ 1870 struct xgbe_phy_data *phy_data = pdata->phy_data; 1871 u16 redrv_reg, redrv_val; 1872 1873 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1874 redrv_val = (u16)mode; 1875 1876 return pdata->hw_if.write_ext_mii_regs_c22(pdata, phy_data->redrv_addr, 1877 redrv_reg, redrv_val); 1878} 1879 1880static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1881 enum xgbe_phy_redrv_mode mode) 1882{ 1883 struct xgbe_phy_data *phy_data = pdata->phy_data; 1884 unsigned int redrv_reg; 1885 int ret; 1886 1887 /* Calculate the register to write */ 1888 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1889 1890 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1891 1892 return ret; 1893} 1894 1895static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1896{ 1897 struct xgbe_phy_data *phy_data = pdata->phy_data; 1898 enum xgbe_phy_redrv_mode mode; 1899 int ret; 1900 1901 if (!phy_data->redrv) 1902 return; 1903 1904 mode = XGBE_PHY_REDRV_MODE_CX; 1905 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1906 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1907 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1908 mode = XGBE_PHY_REDRV_MODE_SR; 1909 1910 ret = xgbe_phy_get_comm_ownership(pdata); 1911 if (ret) 1912 return; 1913 1914 if (phy_data->redrv_if) 1915 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1916 else 1917 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1918 1919 xgbe_phy_put_comm_ownership(pdata); 1920} 1921 1922#define MAX_RX_ADAPT_RETRIES 1 1923#define XGBE_PMA_RX_VAL_SIG_MASK (XGBE_PMA_RX_SIG_DET_0_MASK | \ 1924 XGBE_PMA_RX_VALID_0_MASK) 1925 1926static void xgbe_set_rx_adap_mode(struct xgbe_prv_data *pdata, 1927 enum xgbe_mode mode) 1928{ 1929 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) { 1930 pdata->rx_adapt_retries = 0; 1931 pdata->mode_set = false; 1932 return; 1933 } 1934 1935 xgbe_phy_perform_ratechange(pdata, 1936 mode == XGBE_MODE_KR ? 1937 XGBE_MB_CMD_SET_10G_KR : 1938 XGBE_MB_CMD_SET_10G_SFI, 1939 XGBE_MB_SUBCMD_RX_ADAP); 1940} 1941 1942static void xgbe_rx_adaptation(struct xgbe_prv_data *pdata) 1943{ 1944 struct xgbe_phy_data *phy_data = pdata->phy_data; 1945 int reg; 1946 1947 /* step 2: force PCS to send RX_ADAPT Req to PHY */ 1948 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4, 1949 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_ENABLE); 1950 1951 /* Step 3: Wait for RX_ADAPT ACK from the PHY */ 1952 msleep(200); 1953 1954 /* Software polls for coefficient update command (given by local PHY) */ 1955 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_PHY_RX_EQ_CEU); 1956 1957 /* Clear the RX_AD_REQ bit */ 1958 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4, 1959 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_DISABLE); 1960 1961 /* Check if coefficient update command is set */ 1962 if ((reg & XGBE_PMA_CFF_UPDT_MASK) != XGBE_PMA_CFF_UPDT_MASK) 1963 goto set_mode; 1964 1965 /* Step 4: Check for Block lock */ 1966 1967 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1968 if (reg < 0) 1969 goto set_mode; 1970 1971 /* Link status is latched low so that momentary link drops 1972 * can be detected. If link was already down read again 1973 * to get the latest state. 1974 */ 1975 if (!pdata->phy.link && !(reg & MDIO_STAT1_LSTATUS)) { 1976 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1977 if (reg < 0) 1978 goto set_mode; 1979 } 1980 1981 if (reg & MDIO_STAT1_LSTATUS) { 1982 /* If the block lock is found, update the helpers 1983 * and declare the link up 1984 */ 1985 netif_dbg(pdata, link, pdata->netdev, "Block_lock done"); 1986 pdata->rx_adapt_done = true; 1987 pdata->rx_adapt_retries = 0; 1988 pdata->mode_set = false; 1989 return; 1990 } 1991 1992set_mode: 1993 xgbe_set_rx_adap_mode(pdata, phy_data->cur_mode); 1994} 1995 1996static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata) 1997{ 1998 unsigned int reg; 1999 2000rx_adapt_reinit: 2001 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_LSTS, 2002 XGBE_PMA_RX_VAL_SIG_MASK); 2003 2004 /* step 1: Check for RX_VALID && LF_SIGDET */ 2005 if ((reg & XGBE_PMA_RX_VAL_SIG_MASK) != XGBE_PMA_RX_VAL_SIG_MASK) { 2006 netif_dbg(pdata, link, pdata->netdev, 2007 "RX_VALID or LF_SIGDET is unset, issue rrc"); 2008 xgbe_phy_rrc(pdata); 2009 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) { 2010 pdata->rx_adapt_retries = 0; 2011 return; 2012 } 2013 goto rx_adapt_reinit; 2014 } 2015 2016 /* perform rx adaptation */ 2017 xgbe_rx_adaptation(pdata); 2018} 2019 2020/* 2021 * xgbe_phy_stop_data_path - Stop TX/RX to prevent packet corruption 2022 * @pdata: driver private data 2023 * 2024 * This function stops the data path (TX and RX) to prevent packet 2025 * corruption during critical PHY operations like RX adaptation. 2026 * Must be called before initiating RX adaptation when link goes down. 2027 */ 2028static void xgbe_phy_stop_data_path(struct xgbe_prv_data *pdata) 2029{ 2030 if (pdata->data_path_stopped) 2031 return; 2032 2033 /* Stop TX/RX to prevent packet corruption during RX adaptation */ 2034 pdata->hw_if.disable_tx(pdata); 2035 pdata->hw_if.disable_rx(pdata); 2036 pdata->data_path_stopped = true; 2037 2038 netif_dbg(pdata, link, pdata->netdev, 2039 "stopping data path for RX adaptation\n"); 2040} 2041 2042/* 2043 * xgbe_phy_start_data_path - Re-enable TX/RX after RX adaptation 2044 * @pdata: driver private data 2045 * 2046 * This function re-enables the data path (TX and RX) after RX adaptation 2047 * has completed successfully. Only called when link is confirmed up. 2048 */ 2049static void xgbe_phy_start_data_path(struct xgbe_prv_data *pdata) 2050{ 2051 if (!pdata->data_path_stopped) 2052 return; 2053 2054 pdata->hw_if.enable_rx(pdata); 2055 pdata->hw_if.enable_tx(pdata); 2056 pdata->data_path_stopped = false; 2057 2058 netif_dbg(pdata, link, pdata->netdev, 2059 "restarting data path after RX adaptation\n"); 2060} 2061 2062static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata) 2063{ 2064 int reg; 2065 2066 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT, 2067 XGBE_PCS_PSEQ_STATE_MASK); 2068 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) { 2069 /* Mailbox command timed out, reset of RX block is required. 2070 * This can be done by asseting the reset bit and wait for 2071 * its compeletion. 2072 */ 2073 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 2074 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON); 2075 ndelay(20); 2076 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 2077 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF); 2078 usleep_range(40, 50); 2079 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n"); 2080 } 2081} 2082 2083static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable) 2084{ 2085 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */ 2086 if (pdata->phy.autoneg != AUTONEG_DISABLE) 2087 return; 2088 2089 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 2090 XGBE_PMA_PLL_CTRL_MASK, 2091 enable ? XGBE_PMA_PLL_CTRL_ENABLE 2092 : XGBE_PMA_PLL_CTRL_DISABLE); 2093 2094 /* Wait for command to complete */ 2095 usleep_range(100, 200); 2096} 2097 2098static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 2099 enum xgbe_mb_cmd cmd, enum xgbe_mb_subcmd sub_cmd) 2100{ 2101 unsigned int s0 = 0; 2102 unsigned int wait; 2103 2104 /* Disable PLL re-initialization during FW command processing */ 2105 xgbe_phy_pll_ctrl(pdata, false); 2106 2107 /* Log if a previous command did not complete */ 2108 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 2109 netif_dbg(pdata, link, pdata->netdev, 2110 "firmware mailbox not ready for command\n"); 2111 xgbe_phy_rx_reset(pdata); 2112 } 2113 2114 /* Construct the command */ 2115 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 2116 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 2117 2118 /* Issue the command */ 2119 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 2120 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 2121 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 2122 2123 /* Wait for command to complete */ 2124 wait = XGBE_RATECHANGE_COUNT; 2125 while (wait--) { 2126 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 2127 goto do_rx_adaptation; 2128 2129 usleep_range(1000, 2000); 2130 } 2131 2132 netif_dbg(pdata, link, pdata->netdev, 2133 "firmware mailbox command did not complete\n"); 2134 2135 /* Reset on error */ 2136 xgbe_phy_rx_reset(pdata); 2137 goto reenable_pll; 2138 2139do_rx_adaptation: 2140 if (pdata->en_rx_adap && sub_cmd == XGBE_MB_SUBCMD_RX_ADAP && 2141 (cmd == XGBE_MB_CMD_SET_10G_KR || cmd == XGBE_MB_CMD_SET_10G_SFI)) { 2142 netif_dbg(pdata, link, pdata->netdev, 2143 "Enabling RX adaptation\n"); 2144 pdata->mode_set = true; 2145 xgbe_phy_rx_adaptation(pdata); 2146 /* return from here to avoid enabling PLL ctrl 2147 * during adaptation phase 2148 */ 2149 return; 2150 } 2151 2152reenable_pll: 2153 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */ 2154 if (cmd != XGBE_MB_CMD_POWER_OFF && 2155 cmd != XGBE_MB_CMD_RRC) 2156 xgbe_phy_pll_ctrl(pdata, true); 2157} 2158 2159static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 2160{ 2161 /* Receiver Reset Cycle */ 2162 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_RRC, XGBE_MB_SUBCMD_NONE); 2163 2164 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 2165} 2166 2167static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 2168{ 2169 struct xgbe_phy_data *phy_data = pdata->phy_data; 2170 2171 /* Power off */ 2172 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_POWER_OFF, XGBE_MB_SUBCMD_NONE); 2173 2174 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2175 2176 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 2177} 2178 2179static bool enable_rx_adap(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2180{ 2181 struct xgbe_phy_data *phy_data = pdata->phy_data; 2182 unsigned int ver; 2183 2184 /* Rx-Adaptation is not supported on older platforms(< 0x30H) */ 2185 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2186 if (ver < 0x30) 2187 return false; 2188 2189 /* Re-driver models 4223 && 4227 do not support Rx-Adaptation */ 2190 if (phy_data->redrv && 2191 (phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4223 || 2192 phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4227)) 2193 return false; 2194 2195 /* 10G KR mode with AN does not support Rx-Adaptation */ 2196 if (mode == XGBE_MODE_KR && 2197 phy_data->port_mode != XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG) 2198 return false; 2199 2200 pdata->en_rx_adap = 1; 2201 return true; 2202} 2203 2204static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 2205{ 2206 struct xgbe_phy_data *phy_data = pdata->phy_data; 2207 2208 xgbe_phy_set_redrv_mode(pdata); 2209 2210 /* 10G/SFI */ 2211 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 2212 pdata->en_rx_adap = 0; 2213 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, XGBE_MB_SUBCMD_ACTIVE); 2214 } else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 2215 (enable_rx_adap(pdata, XGBE_MODE_SFI))) { 2216 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2217 XGBE_MB_SUBCMD_RX_ADAP); 2218 } else { 2219 if (phy_data->sfp_cable_len <= 1) 2220 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2221 XGBE_MB_SUBCMD_PASSIVE_1M); 2222 else if (phy_data->sfp_cable_len <= 3) 2223 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2224 XGBE_MB_SUBCMD_PASSIVE_3M); 2225 else 2226 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2227 XGBE_MB_SUBCMD_PASSIVE_OTHER); 2228 } 2229 2230 phy_data->cur_mode = XGBE_MODE_SFI; 2231 2232 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 2233} 2234 2235static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 2236{ 2237 struct xgbe_phy_data *phy_data = pdata->phy_data; 2238 2239 xgbe_phy_set_redrv_mode(pdata); 2240 2241 /* 1G/X */ 2242 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX); 2243 2244 phy_data->cur_mode = XGBE_MODE_X; 2245 2246 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 2247} 2248 2249static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 2250{ 2251 struct xgbe_phy_data *phy_data = pdata->phy_data; 2252 2253 xgbe_phy_set_redrv_mode(pdata); 2254 2255 /* 1G/SGMII */ 2256 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_SGMII); 2257 2258 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 2259 2260 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 2261} 2262 2263static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 2264{ 2265 struct xgbe_phy_data *phy_data = pdata->phy_data; 2266 2267 xgbe_phy_set_redrv_mode(pdata); 2268 2269 /* 100M/SGMII */ 2270 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_100MBITS); 2271 2272 phy_data->cur_mode = XGBE_MODE_SGMII_100; 2273 2274 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 2275} 2276 2277static void xgbe_phy_sgmii_10_mode(struct xgbe_prv_data *pdata) 2278{ 2279 struct xgbe_phy_data *phy_data = pdata->phy_data; 2280 2281 xgbe_phy_set_redrv_mode(pdata); 2282 2283 /* 10M/SGMII */ 2284 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_10MBITS); 2285 2286 phy_data->cur_mode = XGBE_MODE_SGMII_10; 2287 2288 netif_dbg(pdata, link, pdata->netdev, "10MbE SGMII mode set\n"); 2289} 2290 2291static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2292{ 2293 struct xgbe_phy_data *phy_data = pdata->phy_data; 2294 2295 xgbe_phy_set_redrv_mode(pdata); 2296 2297 /* 10G/KR */ 2298 if (enable_rx_adap(pdata, XGBE_MODE_KR)) 2299 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR, 2300 XGBE_MB_SUBCMD_RX_ADAP); 2301 else 2302 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR, 2303 XGBE_MB_SUBCMD_NONE); 2304 2305 phy_data->cur_mode = XGBE_MODE_KR; 2306 2307 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 2308} 2309 2310static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 2311{ 2312 struct xgbe_phy_data *phy_data = pdata->phy_data; 2313 2314 xgbe_phy_set_redrv_mode(pdata); 2315 2316 /* 2.5G/KX */ 2317 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G, XGBE_MB_SUBCMD_NONE); 2318 2319 phy_data->cur_mode = XGBE_MODE_KX_2500; 2320 2321 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 2322} 2323 2324static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 2325{ 2326 struct xgbe_phy_data *phy_data = pdata->phy_data; 2327 2328 xgbe_phy_set_redrv_mode(pdata); 2329 2330 /* 1G/KX */ 2331 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX); 2332 2333 phy_data->cur_mode = XGBE_MODE_KX_1000; 2334 2335 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 2336} 2337 2338static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 2339{ 2340 struct xgbe_phy_data *phy_data = pdata->phy_data; 2341 2342 return phy_data->cur_mode; 2343} 2344 2345static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 2346{ 2347 struct xgbe_phy_data *phy_data = pdata->phy_data; 2348 2349 /* No switching if not 10GBase-T */ 2350 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 2351 return xgbe_phy_cur_mode(pdata); 2352 2353 switch (xgbe_phy_cur_mode(pdata)) { 2354 case XGBE_MODE_SGMII_10: 2355 case XGBE_MODE_SGMII_100: 2356 case XGBE_MODE_SGMII_1000: 2357 return XGBE_MODE_KR; 2358 case XGBE_MODE_KX_2500: 2359 return XGBE_MODE_SGMII_1000; 2360 case XGBE_MODE_KR: 2361 default: 2362 return XGBE_MODE_KX_2500; 2363 } 2364} 2365 2366static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 2367{ 2368 return XGBE_MODE_KX_2500; 2369} 2370 2371static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 2372{ 2373 /* If we are in KR switch to KX, and vice-versa */ 2374 switch (xgbe_phy_cur_mode(pdata)) { 2375 case XGBE_MODE_KX_1000: 2376 return XGBE_MODE_KR; 2377 case XGBE_MODE_KR: 2378 default: 2379 return XGBE_MODE_KX_1000; 2380 } 2381} 2382 2383static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 2384{ 2385 struct xgbe_phy_data *phy_data = pdata->phy_data; 2386 2387 switch (phy_data->port_mode) { 2388 case XGBE_PORT_MODE_BACKPLANE: 2389 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2390 return xgbe_phy_switch_bp_mode(pdata); 2391 case XGBE_PORT_MODE_BACKPLANE_2500: 2392 return xgbe_phy_switch_bp_2500_mode(pdata); 2393 case XGBE_PORT_MODE_1000BASE_T: 2394 case XGBE_PORT_MODE_NBASE_T: 2395 case XGBE_PORT_MODE_10GBASE_T: 2396 return xgbe_phy_switch_baset_mode(pdata); 2397 case XGBE_PORT_MODE_1000BASE_X: 2398 case XGBE_PORT_MODE_10GBASE_R: 2399 case XGBE_PORT_MODE_SFP: 2400 /* No switching, so just return current mode */ 2401 return xgbe_phy_cur_mode(pdata); 2402 default: 2403 return XGBE_MODE_UNKNOWN; 2404 } 2405} 2406 2407static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 2408 int speed) 2409{ 2410 switch (speed) { 2411 case SPEED_1000: 2412 return XGBE_MODE_X; 2413 case SPEED_10000: 2414 return XGBE_MODE_KR; 2415 default: 2416 return XGBE_MODE_UNKNOWN; 2417 } 2418} 2419 2420static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 2421 int speed) 2422{ 2423 switch (speed) { 2424 case SPEED_10: 2425 return XGBE_MODE_SGMII_10; 2426 case SPEED_100: 2427 return XGBE_MODE_SGMII_100; 2428 case SPEED_1000: 2429 return XGBE_MODE_SGMII_1000; 2430 case SPEED_2500: 2431 return XGBE_MODE_KX_2500; 2432 case SPEED_10000: 2433 return XGBE_MODE_KR; 2434 default: 2435 return XGBE_MODE_UNKNOWN; 2436 } 2437} 2438 2439static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 2440 int speed) 2441{ 2442 switch (speed) { 2443 case SPEED_10: 2444 return XGBE_MODE_SGMII_10; 2445 case SPEED_100: 2446 return XGBE_MODE_SGMII_100; 2447 case SPEED_1000: 2448 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2449 return XGBE_MODE_SGMII_1000; 2450 else 2451 return XGBE_MODE_X; 2452 case SPEED_10000: 2453 case SPEED_UNKNOWN: 2454 return XGBE_MODE_SFI; 2455 default: 2456 return XGBE_MODE_UNKNOWN; 2457 } 2458} 2459 2460static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2461{ 2462 switch (speed) { 2463 case SPEED_2500: 2464 return XGBE_MODE_KX_2500; 2465 default: 2466 return XGBE_MODE_UNKNOWN; 2467 } 2468} 2469 2470static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2471{ 2472 switch (speed) { 2473 case SPEED_1000: 2474 return XGBE_MODE_KX_1000; 2475 case SPEED_10000: 2476 return XGBE_MODE_KR; 2477 default: 2478 return XGBE_MODE_UNKNOWN; 2479 } 2480} 2481 2482static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2483 int speed) 2484{ 2485 struct xgbe_phy_data *phy_data = pdata->phy_data; 2486 2487 switch (phy_data->port_mode) { 2488 case XGBE_PORT_MODE_BACKPLANE: 2489 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2490 return xgbe_phy_get_bp_mode(speed); 2491 case XGBE_PORT_MODE_BACKPLANE_2500: 2492 return xgbe_phy_get_bp_2500_mode(speed); 2493 case XGBE_PORT_MODE_1000BASE_T: 2494 case XGBE_PORT_MODE_NBASE_T: 2495 case XGBE_PORT_MODE_10GBASE_T: 2496 return xgbe_phy_get_baset_mode(phy_data, speed); 2497 case XGBE_PORT_MODE_1000BASE_X: 2498 case XGBE_PORT_MODE_10GBASE_R: 2499 return xgbe_phy_get_basex_mode(phy_data, speed); 2500 case XGBE_PORT_MODE_SFP: 2501 return xgbe_phy_get_sfp_mode(phy_data, speed); 2502 default: 2503 return XGBE_MODE_UNKNOWN; 2504 } 2505} 2506 2507static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2508{ 2509 switch (mode) { 2510 case XGBE_MODE_KX_1000: 2511 xgbe_phy_kx_1000_mode(pdata); 2512 break; 2513 case XGBE_MODE_KX_2500: 2514 xgbe_phy_kx_2500_mode(pdata); 2515 break; 2516 case XGBE_MODE_KR: 2517 xgbe_phy_kr_mode(pdata); 2518 break; 2519 case XGBE_MODE_SGMII_10: 2520 xgbe_phy_sgmii_10_mode(pdata); 2521 break; 2522 case XGBE_MODE_SGMII_100: 2523 xgbe_phy_sgmii_100_mode(pdata); 2524 break; 2525 case XGBE_MODE_SGMII_1000: 2526 xgbe_phy_sgmii_1000_mode(pdata); 2527 break; 2528 case XGBE_MODE_X: 2529 xgbe_phy_x_mode(pdata); 2530 break; 2531 case XGBE_MODE_SFI: 2532 xgbe_phy_sfi_mode(pdata); 2533 break; 2534 default: 2535 break; 2536 } 2537} 2538 2539static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2540 enum xgbe_mode mode, bool advert) 2541{ 2542 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2543 return advert; 2544 } else { 2545 enum xgbe_mode cur_mode; 2546 2547 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2548 if (cur_mode == mode) 2549 return true; 2550 } 2551 2552 return false; 2553} 2554 2555static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2556 enum xgbe_mode mode) 2557{ 2558 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2559 2560 switch (mode) { 2561 case XGBE_MODE_X: 2562 return xgbe_phy_check_mode(pdata, mode, 2563 XGBE_ADV(lks, 1000baseX_Full)); 2564 case XGBE_MODE_KR: 2565 return xgbe_phy_check_mode(pdata, mode, 2566 XGBE_ADV(lks, 10000baseKR_Full)); 2567 default: 2568 return false; 2569 } 2570} 2571 2572static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2573 enum xgbe_mode mode) 2574{ 2575 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2576 2577 switch (mode) { 2578 case XGBE_MODE_SGMII_10: 2579 return xgbe_phy_check_mode(pdata, mode, 2580 XGBE_ADV(lks, 10baseT_Full)); 2581 case XGBE_MODE_SGMII_100: 2582 return xgbe_phy_check_mode(pdata, mode, 2583 XGBE_ADV(lks, 100baseT_Full)); 2584 case XGBE_MODE_SGMII_1000: 2585 return xgbe_phy_check_mode(pdata, mode, 2586 XGBE_ADV(lks, 1000baseT_Full)); 2587 case XGBE_MODE_KX_2500: 2588 return xgbe_phy_check_mode(pdata, mode, 2589 XGBE_ADV(lks, 2500baseT_Full)); 2590 case XGBE_MODE_KR: 2591 return xgbe_phy_check_mode(pdata, mode, 2592 XGBE_ADV(lks, 10000baseT_Full)); 2593 default: 2594 return false; 2595 } 2596} 2597 2598static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2599 enum xgbe_mode mode) 2600{ 2601 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2602 struct xgbe_phy_data *phy_data = pdata->phy_data; 2603 2604 switch (mode) { 2605 case XGBE_MODE_X: 2606 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2607 return false; 2608 return xgbe_phy_check_mode(pdata, mode, 2609 XGBE_ADV(lks, 1000baseX_Full)); 2610 case XGBE_MODE_SGMII_10: 2611 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2612 return false; 2613 return xgbe_phy_check_mode(pdata, mode, 2614 XGBE_ADV(lks, 10baseT_Full)); 2615 case XGBE_MODE_SGMII_100: 2616 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2617 return false; 2618 return xgbe_phy_check_mode(pdata, mode, 2619 XGBE_ADV(lks, 100baseT_Full)); 2620 case XGBE_MODE_SGMII_1000: 2621 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2622 return false; 2623 return xgbe_phy_check_mode(pdata, mode, 2624 XGBE_ADV(lks, 1000baseT_Full)); 2625 case XGBE_MODE_SFI: 2626 if (phy_data->sfp_mod_absent) 2627 return true; 2628 return xgbe_phy_check_mode(pdata, mode, 2629 XGBE_ADV(lks, 10000baseSR_Full) || 2630 XGBE_ADV(lks, 10000baseLR_Full) || 2631 XGBE_ADV(lks, 10000baseLRM_Full) || 2632 XGBE_ADV(lks, 10000baseER_Full) || 2633 XGBE_ADV(lks, 10000baseCR_Full)); 2634 default: 2635 return false; 2636 } 2637} 2638 2639static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2640 enum xgbe_mode mode) 2641{ 2642 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2643 2644 switch (mode) { 2645 case XGBE_MODE_KX_2500: 2646 return xgbe_phy_check_mode(pdata, mode, 2647 XGBE_ADV(lks, 2500baseX_Full)); 2648 default: 2649 return false; 2650 } 2651} 2652 2653static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2654 enum xgbe_mode mode) 2655{ 2656 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2657 2658 switch (mode) { 2659 case XGBE_MODE_KX_1000: 2660 return xgbe_phy_check_mode(pdata, mode, 2661 XGBE_ADV(lks, 1000baseKX_Full)); 2662 case XGBE_MODE_KR: 2663 return xgbe_phy_check_mode(pdata, mode, 2664 XGBE_ADV(lks, 10000baseKR_Full)); 2665 default: 2666 return false; 2667 } 2668} 2669 2670static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2671{ 2672 struct xgbe_phy_data *phy_data = pdata->phy_data; 2673 2674 switch (phy_data->port_mode) { 2675 case XGBE_PORT_MODE_BACKPLANE: 2676 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2677 return xgbe_phy_use_bp_mode(pdata, mode); 2678 case XGBE_PORT_MODE_BACKPLANE_2500: 2679 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2680 case XGBE_PORT_MODE_1000BASE_T: 2681 case XGBE_PORT_MODE_NBASE_T: 2682 case XGBE_PORT_MODE_10GBASE_T: 2683 return xgbe_phy_use_baset_mode(pdata, mode); 2684 case XGBE_PORT_MODE_1000BASE_X: 2685 case XGBE_PORT_MODE_10GBASE_R: 2686 return xgbe_phy_use_basex_mode(pdata, mode); 2687 case XGBE_PORT_MODE_SFP: 2688 return xgbe_phy_use_sfp_mode(pdata, mode); 2689 default: 2690 return false; 2691 } 2692} 2693 2694static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2695 int speed) 2696{ 2697 switch (speed) { 2698 case SPEED_1000: 2699 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2700 case SPEED_10000: 2701 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2702 default: 2703 return false; 2704 } 2705} 2706 2707static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data *pdata, 2708 int speed) 2709{ 2710 struct xgbe_phy_data *phy_data = pdata->phy_data; 2711 unsigned int ver; 2712 2713 switch (speed) { 2714 case SPEED_10: 2715 /* Supported in ver 21H and ver >= 30H */ 2716 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2717 return (ver == 0x21 || ver >= 0x30); 2718 case SPEED_100: 2719 case SPEED_1000: 2720 return true; 2721 case SPEED_2500: 2722 return ((phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T) || 2723 (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T)); 2724 case SPEED_10000: 2725 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2726 default: 2727 return false; 2728 } 2729} 2730 2731static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data *pdata, 2732 int speed) 2733{ 2734 struct xgbe_phy_data *phy_data = pdata->phy_data; 2735 unsigned int ver; 2736 2737 switch (speed) { 2738 case SPEED_10: 2739 /* Supported in ver 21H and ver >= 30H */ 2740 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2741 return ((ver == 0x21 || ver >= 0x30) && 2742 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000)); 2743 case SPEED_100: 2744 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2745 case SPEED_1000: 2746 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2747 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2748 case SPEED_10000: 2749 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2750 default: 2751 return false; 2752 } 2753} 2754 2755static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2756{ 2757 switch (speed) { 2758 case SPEED_2500: 2759 return true; 2760 default: 2761 return false; 2762 } 2763} 2764 2765static bool xgbe_phy_valid_speed_bp_mode(int speed) 2766{ 2767 switch (speed) { 2768 case SPEED_1000: 2769 case SPEED_10000: 2770 return true; 2771 default: 2772 return false; 2773 } 2774} 2775 2776static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2777{ 2778 struct xgbe_phy_data *phy_data = pdata->phy_data; 2779 2780 switch (phy_data->port_mode) { 2781 case XGBE_PORT_MODE_BACKPLANE: 2782 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2783 return xgbe_phy_valid_speed_bp_mode(speed); 2784 case XGBE_PORT_MODE_BACKPLANE_2500: 2785 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2786 case XGBE_PORT_MODE_1000BASE_T: 2787 case XGBE_PORT_MODE_NBASE_T: 2788 case XGBE_PORT_MODE_10GBASE_T: 2789 return xgbe_phy_valid_speed_baset_mode(pdata, speed); 2790 case XGBE_PORT_MODE_1000BASE_X: 2791 case XGBE_PORT_MODE_10GBASE_R: 2792 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2793 case XGBE_PORT_MODE_SFP: 2794 return xgbe_phy_valid_speed_sfp_mode(pdata, speed); 2795 default: 2796 return false; 2797 } 2798} 2799 2800static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2801{ 2802 struct xgbe_phy_data *phy_data = pdata->phy_data; 2803 int reg, ret; 2804 2805 *an_restart = 0; 2806 2807 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2808 /* Check SFP signals */ 2809 xgbe_phy_sfp_detect(pdata); 2810 2811 if (phy_data->sfp_changed) { 2812 *an_restart = 1; 2813 return 0; 2814 } 2815 2816 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) { 2817 if (pdata->en_rx_adap) 2818 pdata->rx_adapt_done = false; 2819 return 0; 2820 } 2821 } 2822 2823 if (phy_data->phydev) { 2824 /* Check external PHY */ 2825 ret = phy_read_status(phy_data->phydev); 2826 if (ret < 0) 2827 return 0; 2828 2829 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2830 !phy_aneg_done(phy_data->phydev)) 2831 return 0; 2832 2833 if (!phy_data->phydev->link) 2834 return 0; 2835 } 2836 2837 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2838 if (reg < 0) 2839 return reg; 2840 2841 /* Link status is latched low so that momentary link drops 2842 * can be detected. If link was already down read again 2843 * to get the latest state. 2844 */ 2845 2846 if (!pdata->phy.link && !(reg & MDIO_STAT1_LSTATUS)) { 2847 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2848 if (reg < 0) 2849 return reg; 2850 } 2851 2852 if (pdata->en_rx_adap) { 2853 /* if the link is available and adaptation is done, 2854 * declare link up 2855 * 2856 * Note: When link is up and adaptation is done, we can 2857 * safely re-enable the data path if it was stopped 2858 * for adaptation. 2859 */ 2860 if ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done) { 2861 xgbe_phy_start_data_path(pdata); 2862 return 1; 2863 } 2864 /* If either link is not available or adaptation is not done, 2865 * retrigger the adaptation logic. (if the mode is not set, 2866 * then issue mailbox command first) 2867 */ 2868 2869 /* CRITICAL: Stop data path BEFORE triggering RX adaptation 2870 * to prevent CRC errors from packets corrupted during 2871 * the adaptation process. This is especially important 2872 * when AN is OFF in 10G KR mode. 2873 */ 2874 xgbe_phy_stop_data_path(pdata); 2875 2876 if (pdata->mode_set) { 2877 xgbe_phy_rx_adaptation(pdata); 2878 } else { 2879 pdata->rx_adapt_done = false; 2880 xgbe_phy_set_mode(pdata, phy_data->cur_mode); 2881 } 2882 2883 if (pdata->rx_adapt_done) { 2884 /* Adaptation complete, safe to re-enable data path */ 2885 xgbe_phy_start_data_path(pdata); 2886 return 1; 2887 } 2888 } else if (reg & MDIO_STAT1_LSTATUS) 2889 return 1; 2890 2891 if (pdata->phy.autoneg == AUTONEG_ENABLE && 2892 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) { 2893 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { 2894 netif_carrier_off(pdata->netdev); 2895 *an_restart = 1; 2896 } 2897 } 2898 2899 /* No link, attempt a receiver reset cycle */ 2900 if (pdata->vdata->enable_rrc && phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2901 phy_data->rrc_count = 0; 2902 xgbe_phy_rrc(pdata); 2903 } 2904 2905 return 0; 2906} 2907 2908static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2909{ 2910 struct xgbe_phy_data *phy_data = pdata->phy_data; 2911 2912 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2913 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2914 GPIO_ADDR); 2915 2916 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2917 GPIO_MASK); 2918 2919 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2920 GPIO_RX_LOS); 2921 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2922 GPIO_TX_FAULT); 2923 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2924 GPIO_MOD_ABS); 2925 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2926 GPIO_RATE_SELECT); 2927 2928 if (netif_msg_probe(pdata)) { 2929 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2930 phy_data->sfp_gpio_address); 2931 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2932 phy_data->sfp_gpio_mask); 2933 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2934 phy_data->sfp_gpio_rx_los); 2935 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2936 phy_data->sfp_gpio_tx_fault); 2937 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2938 phy_data->sfp_gpio_mod_absent); 2939 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2940 phy_data->sfp_gpio_rate_select); 2941 } 2942} 2943 2944static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2945{ 2946 struct xgbe_phy_data *phy_data = pdata->phy_data; 2947 unsigned int mux_addr_hi, mux_addr_lo; 2948 2949 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 2950 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 2951 if (mux_addr_lo == XGBE_SFP_DIRECT) 2952 return; 2953 2954 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2955 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2956 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, 2957 MUX_CHAN); 2958 2959 if (netif_msg_probe(pdata)) { 2960 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2961 phy_data->sfp_mux_address); 2962 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2963 phy_data->sfp_mux_channel); 2964 } 2965} 2966 2967static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2968{ 2969 xgbe_phy_sfp_comm_setup(pdata); 2970 xgbe_phy_sfp_gpio_setup(pdata); 2971} 2972 2973static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2974{ 2975 struct xgbe_phy_data *phy_data = pdata->phy_data; 2976 int ret; 2977 2978 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2979 if (ret) 2980 return ret; 2981 2982 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2983 2984 return ret; 2985} 2986 2987static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2988{ 2989 struct xgbe_phy_data *phy_data = pdata->phy_data; 2990 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2991 int ret; 2992 2993 /* Read the output port registers */ 2994 gpio_reg = 2; 2995 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2996 &gpio_reg, sizeof(gpio_reg), 2997 gpio_ports, sizeof(gpio_ports)); 2998 if (ret) 2999 return ret; 3000 3001 /* Prepare to write the GPIO data */ 3002 gpio_data[0] = 2; 3003 gpio_data[1] = gpio_ports[0]; 3004 gpio_data[2] = gpio_ports[1]; 3005 3006 /* Set the GPIO pin */ 3007 if (phy_data->mdio_reset_gpio < 8) 3008 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 3009 else 3010 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 3011 3012 /* Write the output port registers */ 3013 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 3014 gpio_data, sizeof(gpio_data)); 3015 if (ret) 3016 return ret; 3017 3018 /* Clear the GPIO pin */ 3019 if (phy_data->mdio_reset_gpio < 8) 3020 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 3021 else 3022 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 3023 3024 /* Write the output port registers */ 3025 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 3026 gpio_data, sizeof(gpio_data)); 3027 3028 return ret; 3029} 3030 3031static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 3032{ 3033 struct xgbe_phy_data *phy_data = pdata->phy_data; 3034 int ret; 3035 3036 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 3037 return 0; 3038 3039 ret = xgbe_phy_get_comm_ownership(pdata); 3040 if (ret) 3041 return ret; 3042 3043 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 3044 ret = xgbe_phy_i2c_mdio_reset(pdata); 3045 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 3046 ret = xgbe_phy_int_mdio_reset(pdata); 3047 3048 xgbe_phy_put_comm_ownership(pdata); 3049 3050 return ret; 3051} 3052 3053static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 3054{ 3055 if (!phy_data->redrv) 3056 return false; 3057 3058 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 3059 return true; 3060 3061 switch (phy_data->redrv_model) { 3062 case XGBE_PHY_REDRV_MODEL_4223: 3063 if (phy_data->redrv_lane > 3) 3064 return true; 3065 break; 3066 case XGBE_PHY_REDRV_MODEL_4227: 3067 if (phy_data->redrv_lane > 1) 3068 return true; 3069 break; 3070 default: 3071 return true; 3072 } 3073 3074 return false; 3075} 3076 3077static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 3078{ 3079 struct xgbe_phy_data *phy_data = pdata->phy_data; 3080 3081 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 3082 return 0; 3083 3084 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 3085 switch (phy_data->mdio_reset) { 3086 case XGBE_MDIO_RESET_NONE: 3087 case XGBE_MDIO_RESET_I2C_GPIO: 3088 case XGBE_MDIO_RESET_INT_GPIO: 3089 break; 3090 default: 3091 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 3092 phy_data->mdio_reset); 3093 return -EINVAL; 3094 } 3095 3096 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 3097 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 3098 XP_GET_BITS(pdata->pp3, XP_PROP_3, 3099 MDIO_RESET_I2C_ADDR); 3100 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3101 MDIO_RESET_I2C_GPIO); 3102 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 3103 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3104 MDIO_RESET_INT_GPIO); 3105 } 3106 3107 return 0; 3108} 3109 3110static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 3111{ 3112 struct xgbe_phy_data *phy_data = pdata->phy_data; 3113 unsigned int ver; 3114 3115 /* 10 Mbps speed is supported in ver 21H and ver >= 30H */ 3116 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 3117 if ((ver < 0x30 && ver != 0x21) && (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)) 3118 return true; 3119 3120 switch (phy_data->port_mode) { 3121 case XGBE_PORT_MODE_BACKPLANE: 3122 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 3123 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3124 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3125 return false; 3126 break; 3127 case XGBE_PORT_MODE_BACKPLANE_2500: 3128 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 3129 return false; 3130 break; 3131 case XGBE_PORT_MODE_1000BASE_T: 3132 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 3133 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3134 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 3135 return false; 3136 break; 3137 case XGBE_PORT_MODE_1000BASE_X: 3138 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3139 return false; 3140 break; 3141 case XGBE_PORT_MODE_NBASE_T: 3142 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 3143 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3144 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3145 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 3146 return false; 3147 break; 3148 case XGBE_PORT_MODE_10GBASE_T: 3149 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 3150 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3151 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3152 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) || 3153 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3154 return false; 3155 break; 3156 case XGBE_PORT_MODE_10GBASE_R: 3157 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3158 return false; 3159 break; 3160 case XGBE_PORT_MODE_SFP: 3161 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 3162 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3163 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3164 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3165 return false; 3166 break; 3167 default: 3168 break; 3169 } 3170 3171 return true; 3172} 3173 3174static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 3175{ 3176 struct xgbe_phy_data *phy_data = pdata->phy_data; 3177 3178 switch (phy_data->port_mode) { 3179 case XGBE_PORT_MODE_BACKPLANE: 3180 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 3181 case XGBE_PORT_MODE_BACKPLANE_2500: 3182 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 3183 return false; 3184 break; 3185 case XGBE_PORT_MODE_1000BASE_T: 3186 case XGBE_PORT_MODE_1000BASE_X: 3187 case XGBE_PORT_MODE_NBASE_T: 3188 case XGBE_PORT_MODE_10GBASE_T: 3189 case XGBE_PORT_MODE_10GBASE_R: 3190 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 3191 return false; 3192 break; 3193 case XGBE_PORT_MODE_SFP: 3194 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 3195 return false; 3196 break; 3197 default: 3198 break; 3199 } 3200 3201 return true; 3202} 3203 3204static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 3205{ 3206 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 3207 return false; 3208 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 3209 return false; 3210 3211 return true; 3212} 3213 3214static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 3215{ 3216 struct xgbe_phy_data *phy_data = pdata->phy_data; 3217 3218 if (!pdata->debugfs_an_cdr_workaround) 3219 return; 3220 3221 if (!phy_data->phy_cdr_notrack) 3222 return; 3223 3224 usleep_range(phy_data->phy_cdr_delay, 3225 phy_data->phy_cdr_delay + 500); 3226 3227 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 3228 XGBE_PMA_CDR_TRACK_EN_MASK, 3229 XGBE_PMA_CDR_TRACK_EN_ON); 3230 3231 phy_data->phy_cdr_notrack = 0; 3232} 3233 3234static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 3235{ 3236 struct xgbe_phy_data *phy_data = pdata->phy_data; 3237 3238 if (!pdata->debugfs_an_cdr_workaround) 3239 return; 3240 3241 if (phy_data->phy_cdr_notrack) 3242 return; 3243 3244 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 3245 XGBE_PMA_CDR_TRACK_EN_MASK, 3246 XGBE_PMA_CDR_TRACK_EN_OFF); 3247 3248 xgbe_phy_rrc(pdata); 3249 3250 phy_data->phy_cdr_notrack = 1; 3251} 3252 3253static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 3254{ 3255 if (!pdata->debugfs_an_cdr_track_early) 3256 xgbe_phy_cdr_track(pdata); 3257} 3258 3259static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 3260{ 3261 if (pdata->debugfs_an_cdr_track_early) 3262 xgbe_phy_cdr_track(pdata); 3263} 3264 3265static void xgbe_phy_an_post(struct xgbe_prv_data *pdata) 3266{ 3267 struct xgbe_phy_data *phy_data = pdata->phy_data; 3268 3269 switch (pdata->an_mode) { 3270 case XGBE_AN_MODE_CL73: 3271 case XGBE_AN_MODE_CL73_REDRV: 3272 if (phy_data->cur_mode != XGBE_MODE_KR) 3273 break; 3274 3275 xgbe_phy_cdr_track(pdata); 3276 3277 switch (pdata->an_result) { 3278 case XGBE_AN_READY: 3279 case XGBE_AN_COMPLETE: 3280 break; 3281 default: 3282 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 3283 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 3284 else 3285 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3286 break; 3287 } 3288 break; 3289 default: 3290 break; 3291 } 3292} 3293 3294static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 3295{ 3296 struct xgbe_phy_data *phy_data = pdata->phy_data; 3297 3298 switch (pdata->an_mode) { 3299 case XGBE_AN_MODE_CL73: 3300 case XGBE_AN_MODE_CL73_REDRV: 3301 if (phy_data->cur_mode != XGBE_MODE_KR) 3302 break; 3303 3304 xgbe_phy_cdr_notrack(pdata); 3305 break; 3306 default: 3307 break; 3308 } 3309} 3310 3311static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 3312{ 3313 struct xgbe_phy_data *phy_data = pdata->phy_data; 3314 3315 /* If we have an external PHY, free it */ 3316 xgbe_phy_free_phy_device(pdata); 3317 3318 /* Reset SFP data */ 3319 xgbe_phy_sfp_reset(phy_data); 3320 xgbe_phy_sfp_mod_absent(pdata); 3321 3322 /* Reset CDR support */ 3323 xgbe_phy_cdr_track(pdata); 3324 3325 /* Power off the PHY */ 3326 xgbe_phy_power_off(pdata); 3327 3328 /* Stop the I2C controller */ 3329 pdata->i2c_if.i2c_stop(pdata); 3330} 3331 3332static int xgbe_phy_start(struct xgbe_prv_data *pdata) 3333{ 3334 struct xgbe_phy_data *phy_data = pdata->phy_data; 3335 int ret; 3336 3337 /* Start the I2C controller */ 3338 ret = pdata->i2c_if.i2c_start(pdata); 3339 if (ret) 3340 return ret; 3341 3342 /* Set the proper MDIO mode for the re-driver */ 3343 if (phy_data->redrv && !phy_data->redrv_if) { 3344 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3345 XGBE_MDIO_MODE_CL22); 3346 if (ret) { 3347 netdev_err(pdata->netdev, 3348 "redriver mdio port not compatible (%u)\n", 3349 phy_data->redrv_addr); 3350 return ret; 3351 } 3352 } 3353 3354 /* Start in highest supported mode */ 3355 xgbe_phy_set_mode(pdata, phy_data->start_mode); 3356 3357 /* Reset CDR support */ 3358 xgbe_phy_cdr_track(pdata); 3359 3360 /* After starting the I2C controller, we can check for an SFP */ 3361 switch (phy_data->port_mode) { 3362 case XGBE_PORT_MODE_SFP: 3363 xgbe_phy_sfp_detect(pdata); 3364 break; 3365 default: 3366 break; 3367 } 3368 3369 /* If we have an external PHY, start it */ 3370 ret = xgbe_phy_find_phy_device(pdata); 3371 if (ret) 3372 goto err_i2c; 3373 3374 return 0; 3375 3376err_i2c: 3377 pdata->i2c_if.i2c_stop(pdata); 3378 3379 return ret; 3380} 3381 3382static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 3383{ 3384 struct xgbe_phy_data *phy_data = pdata->phy_data; 3385 enum xgbe_mode cur_mode; 3386 int ret; 3387 3388 /* Reset by power cycling the PHY */ 3389 cur_mode = phy_data->cur_mode; 3390 xgbe_phy_power_off(pdata); 3391 xgbe_phy_set_mode(pdata, cur_mode); 3392 3393 if (!phy_data->phydev) 3394 return 0; 3395 3396 /* Reset the external PHY */ 3397 ret = xgbe_phy_mdio_reset(pdata); 3398 if (ret) 3399 return ret; 3400 3401 return phy_init_hw(phy_data->phydev); 3402} 3403 3404static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 3405{ 3406 struct xgbe_phy_data *phy_data = pdata->phy_data; 3407 3408 /* Unregister for driving external PHYs */ 3409 mdiobus_unregister(phy_data->mii); 3410} 3411 3412static int xgbe_phy_init(struct xgbe_prv_data *pdata) 3413{ 3414 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 3415 struct xgbe_phy_data *phy_data; 3416 struct mii_bus *mii; 3417 int ret; 3418 3419 /* Check if enabled */ 3420 if (!xgbe_phy_port_enabled(pdata)) { 3421 dev_info(pdata->dev, "device is not enabled\n"); 3422 return -ENODEV; 3423 } 3424 3425 /* Initialize the I2C controller */ 3426 ret = pdata->i2c_if.i2c_init(pdata); 3427 if (ret) 3428 return ret; 3429 3430 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 3431 if (!phy_data) 3432 return -ENOMEM; 3433 pdata->phy_data = phy_data; 3434 3435 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 3436 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 3437 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 3438 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 3439 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 3440 if (netif_msg_probe(pdata)) { 3441 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 3442 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 3443 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 3444 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 3445 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 3446 } 3447 3448 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 3449 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 3450 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 3451 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 3452 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 3453 if (phy_data->redrv && netif_msg_probe(pdata)) { 3454 dev_dbg(pdata->dev, "redrv present\n"); 3455 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 3456 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 3457 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 3458 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 3459 } 3460 3461 /* Validate the connection requested */ 3462 if (xgbe_phy_conn_type_mismatch(pdata)) { 3463 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 3464 phy_data->port_mode, phy_data->conn_type); 3465 return -EINVAL; 3466 } 3467 3468 /* Validate the mode requested */ 3469 if (xgbe_phy_port_mode_mismatch(pdata)) { 3470 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 3471 phy_data->port_mode, phy_data->port_speeds); 3472 return -EINVAL; 3473 } 3474 3475 /* Check for and validate MDIO reset support */ 3476 ret = xgbe_phy_mdio_reset_setup(pdata); 3477 if (ret) 3478 return ret; 3479 3480 /* Validate the re-driver information */ 3481 if (xgbe_phy_redrv_error(phy_data)) { 3482 dev_err(pdata->dev, "phy re-driver settings error\n"); 3483 return -EINVAL; 3484 } 3485 pdata->kr_redrv = phy_data->redrv; 3486 3487 /* Indicate current mode is unknown */ 3488 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 3489 3490 /* Initialize supported features */ 3491 XGBE_ZERO_SUP(lks); 3492 3493 switch (phy_data->port_mode) { 3494 /* Backplane support */ 3495 case XGBE_PORT_MODE_BACKPLANE: 3496 XGBE_SET_SUP(lks, Autoneg); 3497 fallthrough; 3498 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 3499 XGBE_SET_SUP(lks, Pause); 3500 XGBE_SET_SUP(lks, Asym_Pause); 3501 XGBE_SET_SUP(lks, Backplane); 3502 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3503 XGBE_SET_SUP(lks, 1000baseKX_Full); 3504 phy_data->start_mode = XGBE_MODE_KX_1000; 3505 } 3506 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3507 XGBE_SET_SUP(lks, 10000baseKR_Full); 3508 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3509 XGBE_SET_SUP(lks, 10000baseR_FEC); 3510 phy_data->start_mode = XGBE_MODE_KR; 3511 } 3512 3513 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3514 break; 3515 case XGBE_PORT_MODE_BACKPLANE_2500: 3516 XGBE_SET_SUP(lks, Pause); 3517 XGBE_SET_SUP(lks, Asym_Pause); 3518 XGBE_SET_SUP(lks, Backplane); 3519 XGBE_SET_SUP(lks, 2500baseX_Full); 3520 phy_data->start_mode = XGBE_MODE_KX_2500; 3521 3522 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3523 break; 3524 3525 /* MDIO 1GBase-T support */ 3526 case XGBE_PORT_MODE_1000BASE_T: 3527 XGBE_SET_SUP(lks, Autoneg); 3528 XGBE_SET_SUP(lks, Pause); 3529 XGBE_SET_SUP(lks, Asym_Pause); 3530 XGBE_SET_SUP(lks, TP); 3531 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3532 XGBE_SET_SUP(lks, 10baseT_Full); 3533 phy_data->start_mode = XGBE_MODE_SGMII_10; 3534 } 3535 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3536 XGBE_SET_SUP(lks, 100baseT_Full); 3537 phy_data->start_mode = XGBE_MODE_SGMII_100; 3538 } 3539 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3540 XGBE_SET_SUP(lks, 1000baseT_Full); 3541 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3542 } 3543 3544 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3545 break; 3546 3547 /* MDIO Base-X support */ 3548 case XGBE_PORT_MODE_1000BASE_X: 3549 XGBE_SET_SUP(lks, Autoneg); 3550 XGBE_SET_SUP(lks, Pause); 3551 XGBE_SET_SUP(lks, Asym_Pause); 3552 XGBE_SET_SUP(lks, FIBRE); 3553 XGBE_SET_SUP(lks, 1000baseX_Full); 3554 phy_data->start_mode = XGBE_MODE_X; 3555 3556 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3557 break; 3558 3559 /* MDIO NBase-T support */ 3560 case XGBE_PORT_MODE_NBASE_T: 3561 XGBE_SET_SUP(lks, Autoneg); 3562 XGBE_SET_SUP(lks, Pause); 3563 XGBE_SET_SUP(lks, Asym_Pause); 3564 XGBE_SET_SUP(lks, TP); 3565 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3566 XGBE_SET_SUP(lks, 10baseT_Full); 3567 phy_data->start_mode = XGBE_MODE_SGMII_10; 3568 } 3569 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3570 XGBE_SET_SUP(lks, 100baseT_Full); 3571 phy_data->start_mode = XGBE_MODE_SGMII_100; 3572 } 3573 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3574 XGBE_SET_SUP(lks, 1000baseT_Full); 3575 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3576 } 3577 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3578 XGBE_SET_SUP(lks, 2500baseT_Full); 3579 phy_data->start_mode = XGBE_MODE_KX_2500; 3580 } 3581 3582 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3583 break; 3584 3585 /* 10GBase-T support */ 3586 case XGBE_PORT_MODE_10GBASE_T: 3587 XGBE_SET_SUP(lks, Autoneg); 3588 XGBE_SET_SUP(lks, Pause); 3589 XGBE_SET_SUP(lks, Asym_Pause); 3590 XGBE_SET_SUP(lks, TP); 3591 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3592 XGBE_SET_SUP(lks, 10baseT_Full); 3593 phy_data->start_mode = XGBE_MODE_SGMII_10; 3594 } 3595 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3596 XGBE_SET_SUP(lks, 100baseT_Full); 3597 phy_data->start_mode = XGBE_MODE_SGMII_100; 3598 } 3599 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3600 XGBE_SET_SUP(lks, 1000baseT_Full); 3601 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3602 } 3603 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3604 XGBE_SET_SUP(lks, 2500baseT_Full); 3605 phy_data->start_mode = XGBE_MODE_KX_2500; 3606 } 3607 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3608 XGBE_SET_SUP(lks, 10000baseT_Full); 3609 phy_data->start_mode = XGBE_MODE_KR; 3610 } 3611 3612 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3613 break; 3614 3615 /* 10GBase-R support */ 3616 case XGBE_PORT_MODE_10GBASE_R: 3617 XGBE_SET_SUP(lks, Autoneg); 3618 XGBE_SET_SUP(lks, Pause); 3619 XGBE_SET_SUP(lks, Asym_Pause); 3620 XGBE_SET_SUP(lks, FIBRE); 3621 XGBE_SET_SUP(lks, 10000baseSR_Full); 3622 XGBE_SET_SUP(lks, 10000baseLR_Full); 3623 XGBE_SET_SUP(lks, 10000baseLRM_Full); 3624 XGBE_SET_SUP(lks, 10000baseER_Full); 3625 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3626 XGBE_SET_SUP(lks, 10000baseR_FEC); 3627 phy_data->start_mode = XGBE_MODE_SFI; 3628 3629 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3630 break; 3631 3632 /* SFP support */ 3633 case XGBE_PORT_MODE_SFP: 3634 XGBE_SET_SUP(lks, Autoneg); 3635 XGBE_SET_SUP(lks, Pause); 3636 XGBE_SET_SUP(lks, Asym_Pause); 3637 XGBE_SET_SUP(lks, TP); 3638 XGBE_SET_SUP(lks, FIBRE); 3639 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) 3640 phy_data->start_mode = XGBE_MODE_SGMII_10; 3641 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3642 phy_data->start_mode = XGBE_MODE_SGMII_100; 3643 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3644 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3645 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3646 phy_data->start_mode = XGBE_MODE_SFI; 3647 3648 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3649 3650 xgbe_phy_sfp_setup(pdata); 3651 break; 3652 default: 3653 return -EINVAL; 3654 } 3655 3656 if (netif_msg_probe(pdata)) 3657 dev_dbg(pdata->dev, "phy supported=0x%*pb\n", 3658 __ETHTOOL_LINK_MODE_MASK_NBITS, 3659 lks->link_modes.supported); 3660 3661 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3662 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3663 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3664 phy_data->phydev_mode); 3665 if (ret) { 3666 dev_err(pdata->dev, 3667 "mdio port/clause not compatible (%d/%u)\n", 3668 phy_data->mdio_addr, phy_data->phydev_mode); 3669 return -EINVAL; 3670 } 3671 } 3672 3673 if (phy_data->redrv && !phy_data->redrv_if) { 3674 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3675 XGBE_MDIO_MODE_CL22); 3676 if (ret) { 3677 dev_err(pdata->dev, 3678 "redriver mdio port not compatible (%u)\n", 3679 phy_data->redrv_addr); 3680 return -EINVAL; 3681 } 3682 } 3683 3684 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3685 3686 /* Register for driving external PHYs */ 3687 mii = devm_mdiobus_alloc(pdata->dev); 3688 if (!mii) { 3689 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3690 return -ENOMEM; 3691 } 3692 3693 mii->priv = pdata; 3694 mii->name = "amd-xgbe-mii"; 3695 mii->read = xgbe_phy_mii_read_c22; 3696 mii->write = xgbe_phy_mii_write_c22; 3697 mii->read_c45 = xgbe_phy_mii_read_c45; 3698 mii->write_c45 = xgbe_phy_mii_write_c45; 3699 mii->parent = pdata->dev; 3700 mii->phy_mask = ~0; 3701 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3702 ret = mdiobus_register(mii); 3703 if (ret) { 3704 dev_err(pdata->dev, "mdiobus_register failed\n"); 3705 return ret; 3706 } 3707 phy_data->mii = mii; 3708 3709 return 0; 3710} 3711 3712void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3713{ 3714 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3715 3716 phy_impl->init = xgbe_phy_init; 3717 phy_impl->exit = xgbe_phy_exit; 3718 3719 phy_impl->reset = xgbe_phy_reset; 3720 phy_impl->start = xgbe_phy_start; 3721 phy_impl->stop = xgbe_phy_stop; 3722 3723 phy_impl->link_status = xgbe_phy_link_status; 3724 3725 phy_impl->valid_speed = xgbe_phy_valid_speed; 3726 3727 phy_impl->use_mode = xgbe_phy_use_mode; 3728 phy_impl->set_mode = xgbe_phy_set_mode; 3729 phy_impl->get_mode = xgbe_phy_get_mode; 3730 phy_impl->switch_mode = xgbe_phy_switch_mode; 3731 phy_impl->cur_mode = xgbe_phy_cur_mode; 3732 3733 phy_impl->an_mode = xgbe_phy_an_mode; 3734 3735 phy_impl->an_config = xgbe_phy_an_config; 3736 3737 phy_impl->an_advertising = xgbe_phy_an_advertising; 3738 3739 phy_impl->an_outcome = xgbe_phy_an_outcome; 3740 3741 phy_impl->an_pre = xgbe_phy_an_pre; 3742 phy_impl->an_post = xgbe_phy_an_post; 3743 3744 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3745 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3746 3747 phy_impl->module_info = xgbe_phy_module_info; 3748 phy_impl->module_eeprom = xgbe_phy_module_eeprom; 3749}
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