xgbe-common.h

   1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
   2/*
   3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
   4 * Copyright (c) 2014, Synopsys, Inc.
   5 * All rights reserved
   6 */
   7
   8#ifndef __XGBE_COMMON_H__
   9#define __XGBE_COMMON_H__
  10
  11/* DMA register offsets */
  12#define DMA_MR				0x3000
  13#define DMA_SBMR			0x3004
  14#define DMA_ISR				0x3008
  15#define DMA_AXIARCR			0x3010
  16#define DMA_AXIAWCR			0x3018
  17#define DMA_AXIAWARCR			0x301c
  18#define DMA_DSR0			0x3020
  19#define DMA_DSR1			0x3024
  20#define DMA_TXEDMACR			0x3040
  21#define DMA_RXEDMACR			0x3044
  22
  23/* DMA register entry bit positions and sizes */
  24#define DMA_ISR_MACIS_INDEX		17
  25#define DMA_ISR_MACIS_WIDTH		1
  26#define DMA_ISR_MTLIS_INDEX		16
  27#define DMA_ISR_MTLIS_WIDTH		1
  28#define DMA_MR_INTM_INDEX		12
  29#define DMA_MR_INTM_WIDTH		2
  30#define DMA_MR_SWR_INDEX		0
  31#define DMA_MR_SWR_WIDTH		1
  32#define DMA_RXEDMACR_RDPS_INDEX		0
  33#define DMA_RXEDMACR_RDPS_WIDTH		3
  34#define DMA_SBMR_AAL_INDEX		12
  35#define DMA_SBMR_AAL_WIDTH		1
  36#define DMA_SBMR_EAME_INDEX		11
  37#define DMA_SBMR_EAME_WIDTH		1
  38#define DMA_SBMR_BLEN_INDEX		1
  39#define DMA_SBMR_BLEN_WIDTH		7
  40#define DMA_SBMR_RD_OSR_LMT_INDEX	16
  41#define DMA_SBMR_RD_OSR_LMT_WIDTH	6
  42#define DMA_SBMR_UNDEF_INDEX		0
  43#define DMA_SBMR_UNDEF_WIDTH		1
  44#define DMA_SBMR_WR_OSR_LMT_INDEX	24
  45#define DMA_SBMR_WR_OSR_LMT_WIDTH	6
  46#define DMA_TXEDMACR_TDPS_INDEX		0
  47#define DMA_TXEDMACR_TDPS_WIDTH		3
  48
  49/* DMA register values */
  50#define DMA_SBMR_BLEN_256		256
  51#define DMA_SBMR_BLEN_128		128
  52#define DMA_SBMR_BLEN_64		64
  53#define DMA_SBMR_BLEN_32		32
  54#define DMA_SBMR_BLEN_16		16
  55#define DMA_SBMR_BLEN_8			8
  56#define DMA_SBMR_BLEN_4			4
  57#define DMA_DSR_RPS_WIDTH		4
  58#define DMA_DSR_TPS_WIDTH		4
  59#define DMA_DSR_Q_WIDTH			(DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
  60#define DMA_DSR0_RPS_START		8
  61#define DMA_DSR0_TPS_START		12
  62#define DMA_DSRX_FIRST_QUEUE		3
  63#define DMA_DSRX_INC			4
  64#define DMA_DSRX_QPR			4
  65#define DMA_DSRX_RPS_START		0
  66#define DMA_DSRX_TPS_START		4
  67#define DMA_TPS_STOPPED			0x00
  68#define DMA_TPS_SUSPENDED		0x06
  69
  70/* DMA channel register offsets
  71 *   Multiple channels can be active.  The first channel has registers
  72 *   that begin at 0x3100.  Each subsequent channel has registers that
  73 *   are accessed using an offset of 0x80 from the previous channel.
  74 */
  75#define DMA_CH_BASE			0x3100
  76#define DMA_CH_INC			0x80
  77
  78#define DMA_CH_CR			0x00
  79#define DMA_CH_TCR			0x04
  80#define DMA_CH_RCR			0x08
  81#define DMA_CH_TDLR_HI			0x10
  82#define DMA_CH_TDLR_LO			0x14
  83#define DMA_CH_RDLR_HI			0x18
  84#define DMA_CH_RDLR_LO			0x1c
  85#define DMA_CH_TDTR_LO			0x24
  86#define DMA_CH_RDTR_LO			0x2c
  87#define DMA_CH_TDRLR			0x30
  88#define DMA_CH_RDRLR			0x34
  89#define DMA_CH_IER			0x38
  90#define DMA_CH_RIWT			0x3c
  91#define DMA_CH_CATDR_LO			0x44
  92#define DMA_CH_CARDR_LO			0x4c
  93#define DMA_CH_CATBR_HI			0x50
  94#define DMA_CH_CATBR_LO			0x54
  95#define DMA_CH_CARBR_HI			0x58
  96#define DMA_CH_CARBR_LO			0x5c
  97#define DMA_CH_SR			0x60
  98
  99/* DMA channel register entry bit positions and sizes */
 100#define DMA_CH_CR_PBLX8_INDEX		16
 101#define DMA_CH_CR_PBLX8_WIDTH		1
 102#define DMA_CH_CR_SPH_INDEX		24
 103#define DMA_CH_CR_SPH_WIDTH		1
 104#define DMA_CH_IER_AIE20_INDEX		15
 105#define DMA_CH_IER_AIE20_WIDTH		1
 106#define DMA_CH_IER_AIE_INDEX		14
 107#define DMA_CH_IER_AIE_WIDTH		1
 108#define DMA_CH_IER_FBEE_INDEX		12
 109#define DMA_CH_IER_FBEE_WIDTH		1
 110#define DMA_CH_IER_NIE20_INDEX		16
 111#define DMA_CH_IER_NIE20_WIDTH		1
 112#define DMA_CH_IER_NIE_INDEX		15
 113#define DMA_CH_IER_NIE_WIDTH		1
 114#define DMA_CH_IER_RBUE_INDEX		7
 115#define DMA_CH_IER_RBUE_WIDTH		1
 116#define DMA_CH_IER_RIE_INDEX		6
 117#define DMA_CH_IER_RIE_WIDTH		1
 118#define DMA_CH_IER_RSE_INDEX		8
 119#define DMA_CH_IER_RSE_WIDTH		1
 120#define DMA_CH_IER_TBUE_INDEX		2
 121#define DMA_CH_IER_TBUE_WIDTH		1
 122#define DMA_CH_IER_TIE_INDEX		0
 123#define DMA_CH_IER_TIE_WIDTH		1
 124#define DMA_CH_IER_TXSE_INDEX		1
 125#define DMA_CH_IER_TXSE_WIDTH		1
 126#define DMA_CH_RCR_PBL_INDEX		16
 127#define DMA_CH_RCR_PBL_WIDTH		6
 128#define DMA_CH_RCR_RBSZ_INDEX		1
 129#define DMA_CH_RCR_RBSZ_WIDTH		14
 130#define DMA_CH_RCR_SR_INDEX		0
 131#define DMA_CH_RCR_SR_WIDTH		1
 132#define DMA_CH_RIWT_RWT_INDEX		0
 133#define DMA_CH_RIWT_RWT_WIDTH		8
 134#define DMA_CH_SR_FBE_INDEX		12
 135#define DMA_CH_SR_FBE_WIDTH		1
 136#define DMA_CH_SR_RBU_INDEX		7
 137#define DMA_CH_SR_RBU_WIDTH		1
 138#define DMA_CH_SR_RI_INDEX		6
 139#define DMA_CH_SR_RI_WIDTH		1
 140#define DMA_CH_SR_RPS_INDEX		8
 141#define DMA_CH_SR_RPS_WIDTH		1
 142#define DMA_CH_SR_TBU_INDEX		2
 143#define DMA_CH_SR_TBU_WIDTH		1
 144#define DMA_CH_SR_TI_INDEX		0
 145#define DMA_CH_SR_TI_WIDTH		1
 146#define DMA_CH_SR_TPS_INDEX		1
 147#define DMA_CH_SR_TPS_WIDTH		1
 148#define DMA_CH_TCR_OSP_INDEX		4
 149#define DMA_CH_TCR_OSP_WIDTH		1
 150#define DMA_CH_TCR_PBL_INDEX		16
 151#define DMA_CH_TCR_PBL_WIDTH		6
 152#define DMA_CH_TCR_ST_INDEX		0
 153#define DMA_CH_TCR_ST_WIDTH		1
 154#define DMA_CH_TCR_TSE_INDEX		12
 155#define DMA_CH_TCR_TSE_WIDTH		1
 156
 157/* DMA channel register values */
 158#define DMA_OSP_DISABLE			0x00
 159#define DMA_OSP_ENABLE			0x01
 160#define DMA_PBL_1			1
 161#define DMA_PBL_2			2
 162#define DMA_PBL_4			4
 163#define DMA_PBL_8			8
 164#define DMA_PBL_16			16
 165#define DMA_PBL_32			32
 166#define DMA_PBL_64			64      /* 8 x 8 */
 167#define DMA_PBL_128			128     /* 8 x 16 */
 168#define DMA_PBL_256			256     /* 8 x 32 */
 169#define DMA_PBL_X8_DISABLE		0x00
 170#define DMA_PBL_X8_ENABLE		0x01
 171
 172/* MAC register offsets */
 173#define MAC_TCR				0x0000
 174#define MAC_RCR				0x0004
 175#define MAC_PFR				0x0008
 176#define MAC_WTR				0x000c
 177#define MAC_HTR0			0x0010
 178#define MAC_VLANTR			0x0050
 179#define MAC_VLANHTR			0x0058
 180#define MAC_VLANIR			0x0060
 181#define MAC_IVLANIR			0x0064
 182#define MAC_RETMR			0x006c
 183#define MAC_Q0TFCR			0x0070
 184#define MAC_RFCR			0x0090
 185#define MAC_RQC0R			0x00a0
 186#define MAC_RQC1R			0x00a4
 187#define MAC_RQC2R			0x00a8
 188#define MAC_RQC3R			0x00ac
 189#define MAC_ISR				0x00b0
 190#define MAC_IER				0x00b4
 191#define MAC_RTSR			0x00b8
 192#define MAC_PMTCSR			0x00c0
 193#define MAC_RWKPFR			0x00c4
 194#define MAC_LPICSR			0x00d0
 195#define MAC_LPITCR			0x00d4
 196#define MAC_TIR				0x00e0
 197#define MAC_VR				0x0110
 198#define MAC_DR				0x0114
 199#define MAC_HWF0R			0x011c
 200#define MAC_HWF1R			0x0120
 201#define MAC_HWF2R			0x0124
 202#define MAC_MDIOSCAR			0x0200
 203#define MAC_MDIOSCCDR			0x0204
 204#define MAC_MDIOISR			0x0214
 205#define MAC_MDIOIER			0x0218
 206#define MAC_MDIOCL22R			0x0220
 207#define MAC_GPIOCR			0x0278
 208#define MAC_GPIOSR			0x027c
 209#define MAC_MACA0HR			0x0300
 210#define MAC_MACA0LR			0x0304
 211#define MAC_MACA1HR			0x0308
 212#define MAC_MACA1LR			0x030c
 213#define MAC_RSSCR			0x0c80
 214#define MAC_RSSAR			0x0c88
 215#define MAC_RSSDR			0x0c8c
 216#define MAC_TSCR			0x0d00
 217#define MAC_SSIR			0x0d04
 218#define MAC_STSR			0x0d08
 219#define MAC_STNR			0x0d0c
 220#define MAC_STSUR			0x0d10
 221#define MAC_STNUR			0x0d14
 222#define MAC_TSAR			0x0d18
 223#define MAC_TSSR			0x0d20
 224#define MAC_TXSNR			0x0d30
 225#define MAC_TXSSR			0x0d34
 226#define MAC_TICNR                       0x0d58
 227#define MAC_TICSNR                      0x0d5C
 228#define MAC_TECNR                       0x0d60
 229#define MAC_TECSNR                      0x0d64
 230#define MAC_PPSCR			0x0d70
 231#define MAC_PPS0_TTSR			0x0d80
 232#define MAC_PPS0_TTNSR			0x0d84
 233#define MAC_PPS0_INTERVAL		0x0d88
 234#define MAC_PPS0_WIDTH			0x0d8C
 235#define MAC_QTFCR_INC			4
 236#define MAC_MACA_INC			4
 237#define MAC_HTR_INC			4
 238
 239#define MAC_RQC2_INC			4
 240#define MAC_RQC2_Q_PER_REG		4
 241
 242/* PPS helpers */
 243#define PPSEN0				BIT(4)
 244#define MAC_PPSx_TTSR(x)		((MAC_PPS0_TTSR) + ((x) * 0x10))
 245#define MAC_PPSx_TTNSR(x)		((MAC_PPS0_TTNSR) + ((x) * 0x10))
 246#define MAC_PPSx_INTERVAL(x)		((MAC_PPS0_INTERVAL) + ((x) * 0x10))
 247#define MAC_PPSx_WIDTH(x)		((MAC_PPS0_WIDTH) + ((x) * 0x10))
 248#define PPS_MAXIDX(x)			((((x) + 1) * 8) - 1)
 249#define PPS_MINIDX(x)			((x) * 8)
 250#define XGBE_PPSCMD_STOP		0x5
 251#define XGBE_PPSCMD_START		0x2
 252#define XGBE_PPSTARGET_PULSE		0x2
 253
 254/* MAC register entry bit positions and sizes */
 255#define MAC_HWF0R_ADDMACADRSEL_INDEX	18
 256#define MAC_HWF0R_ADDMACADRSEL_WIDTH	5
 257#define MAC_HWF0R_ARPOFFSEL_INDEX	9
 258#define MAC_HWF0R_ARPOFFSEL_WIDTH	1
 259#define MAC_HWF0R_EEESEL_INDEX		13
 260#define MAC_HWF0R_EEESEL_WIDTH		1
 261#define MAC_HWF0R_GMIISEL_INDEX		1
 262#define MAC_HWF0R_GMIISEL_WIDTH		1
 263#define MAC_HWF0R_MGKSEL_INDEX		7
 264#define MAC_HWF0R_MGKSEL_WIDTH		1
 265#define MAC_HWF0R_MMCSEL_INDEX		8
 266#define MAC_HWF0R_MMCSEL_WIDTH		1
 267#define MAC_HWF0R_RWKSEL_INDEX		6
 268#define MAC_HWF0R_RWKSEL_WIDTH		1
 269#define MAC_HWF0R_RXCOESEL_INDEX	16
 270#define MAC_HWF0R_RXCOESEL_WIDTH	1
 271#define MAC_HWF0R_SAVLANINS_INDEX	27
 272#define MAC_HWF0R_SAVLANINS_WIDTH	1
 273#define MAC_HWF0R_SMASEL_INDEX		5
 274#define MAC_HWF0R_SMASEL_WIDTH		1
 275#define MAC_HWF0R_TSSEL_INDEX		12
 276#define MAC_HWF0R_TSSEL_WIDTH		1
 277#define MAC_HWF0R_TSSTSSEL_INDEX	25
 278#define MAC_HWF0R_TSSTSSEL_WIDTH	2
 279#define MAC_HWF0R_TXCOESEL_INDEX	14
 280#define MAC_HWF0R_TXCOESEL_WIDTH	1
 281#define MAC_HWF0R_VLHASH_INDEX		4
 282#define MAC_HWF0R_VLHASH_WIDTH		1
 283#define MAC_HWF0R_VXN_INDEX		29
 284#define MAC_HWF0R_VXN_WIDTH		1
 285#define MAC_HWF1R_ADDR64_INDEX		14
 286#define MAC_HWF1R_ADDR64_WIDTH		2
 287#define MAC_HWF1R_ADVTHWORD_INDEX	13
 288#define MAC_HWF1R_ADVTHWORD_WIDTH	1
 289#define MAC_HWF1R_DBGMEMA_INDEX		19
 290#define MAC_HWF1R_DBGMEMA_WIDTH		1
 291#define MAC_HWF1R_DCBEN_INDEX		16
 292#define MAC_HWF1R_DCBEN_WIDTH		1
 293#define MAC_HWF1R_HASHTBLSZ_INDEX	24
 294#define MAC_HWF1R_HASHTBLSZ_WIDTH	3
 295#define MAC_HWF1R_L3L4FNUM_INDEX	27
 296#define MAC_HWF1R_L3L4FNUM_WIDTH	4
 297#define MAC_HWF1R_NUMTC_INDEX		21
 298#define MAC_HWF1R_NUMTC_WIDTH		3
 299#define MAC_HWF1R_RSSEN_INDEX		20
 300#define MAC_HWF1R_RSSEN_WIDTH		1
 301#define MAC_HWF1R_RXFIFOSIZE_INDEX	0
 302#define MAC_HWF1R_RXFIFOSIZE_WIDTH	5
 303#define MAC_HWF1R_SPHEN_INDEX		17
 304#define MAC_HWF1R_SPHEN_WIDTH		1
 305#define MAC_HWF1R_TSOEN_INDEX		18
 306#define MAC_HWF1R_TSOEN_WIDTH		1
 307#define MAC_HWF1R_TXFIFOSIZE_INDEX	6
 308#define MAC_HWF1R_TXFIFOSIZE_WIDTH	5
 309#define MAC_HWF2R_AUXSNAPNUM_INDEX	28
 310#define MAC_HWF2R_AUXSNAPNUM_WIDTH	3
 311#define MAC_HWF2R_PPSOUTNUM_INDEX	24
 312#define MAC_HWF2R_PPSOUTNUM_WIDTH	3
 313#define MAC_HWF2R_RXCHCNT_INDEX		12
 314#define MAC_HWF2R_RXCHCNT_WIDTH		4
 315#define MAC_HWF2R_RXQCNT_INDEX		0
 316#define MAC_HWF2R_RXQCNT_WIDTH		4
 317#define MAC_HWF2R_TXCHCNT_INDEX		18
 318#define MAC_HWF2R_TXCHCNT_WIDTH		4
 319#define MAC_HWF2R_TXQCNT_INDEX		6
 320#define MAC_HWF2R_TXQCNT_WIDTH		4
 321#define MAC_IER_TSIE_INDEX		12
 322#define MAC_IER_TSIE_WIDTH		1
 323#define MAC_ISR_MMCRXIS_INDEX		9
 324#define MAC_ISR_MMCRXIS_WIDTH		1
 325#define MAC_ISR_MMCTXIS_INDEX		10
 326#define MAC_ISR_MMCTXIS_WIDTH		1
 327#define MAC_ISR_PMTIS_INDEX		4
 328#define MAC_ISR_PMTIS_WIDTH		1
 329#define MAC_ISR_SMI_INDEX		1
 330#define MAC_ISR_SMI_WIDTH		1
 331#define MAC_ISR_TSIS_INDEX		12
 332#define MAC_ISR_TSIS_WIDTH		1
 333#define MAC_MACA1HR_AE_INDEX		31
 334#define MAC_MACA1HR_AE_WIDTH		1
 335#define MAC_MDIOIER_SNGLCOMPIE_INDEX	12
 336#define MAC_MDIOIER_SNGLCOMPIE_WIDTH	1
 337#define MAC_MDIOISR_SNGLCOMPINT_INDEX	12
 338#define MAC_MDIOISR_SNGLCOMPINT_WIDTH	1
 339#define MAC_MDIOSCAR_DA_INDEX		21
 340#define MAC_MDIOSCAR_DA_WIDTH		5
 341#define MAC_MDIOSCAR_PA_INDEX		16
 342#define MAC_MDIOSCAR_PA_WIDTH		5
 343#define MAC_MDIOSCAR_RA_INDEX		0
 344#define MAC_MDIOSCAR_RA_WIDTH		16
 345#define MAC_MDIOSCCDR_BUSY_INDEX	22
 346#define MAC_MDIOSCCDR_BUSY_WIDTH	1
 347#define MAC_MDIOSCCDR_CMD_INDEX		16
 348#define MAC_MDIOSCCDR_CMD_WIDTH		2
 349#define MAC_MDIOSCCDR_CR_INDEX		19
 350#define MAC_MDIOSCCDR_CR_WIDTH		3
 351#define MAC_MDIOSCCDR_DATA_INDEX	0
 352#define MAC_MDIOSCCDR_DATA_WIDTH	16
 353#define MAC_MDIOSCCDR_SADDR_INDEX	18
 354#define MAC_MDIOSCCDR_SADDR_WIDTH	1
 355#define MAC_PFR_HMC_INDEX		2
 356#define MAC_PFR_HMC_WIDTH		1
 357#define MAC_PFR_HPF_INDEX		10
 358#define MAC_PFR_HPF_WIDTH		1
 359#define MAC_PFR_HUC_INDEX		1
 360#define MAC_PFR_HUC_WIDTH		1
 361#define MAC_PFR_PM_INDEX		4
 362#define MAC_PFR_PM_WIDTH		1
 363#define MAC_PFR_PR_INDEX		0
 364#define MAC_PFR_PR_WIDTH		1
 365#define MAC_PFR_VTFE_INDEX		16
 366#define MAC_PFR_VTFE_WIDTH		1
 367#define MAC_PFR_VUCC_INDEX		22
 368#define MAC_PFR_VUCC_WIDTH		1
 369#define MAC_PMTCSR_MGKPKTEN_INDEX	1
 370#define MAC_PMTCSR_MGKPKTEN_WIDTH	1
 371#define MAC_PMTCSR_PWRDWN_INDEX		0
 372#define MAC_PMTCSR_PWRDWN_WIDTH		1
 373#define MAC_PMTCSR_RWKFILTRST_INDEX	31
 374#define MAC_PMTCSR_RWKFILTRST_WIDTH	1
 375#define MAC_PMTCSR_RWKPKTEN_INDEX	2
 376#define MAC_PMTCSR_RWKPKTEN_WIDTH	1
 377#define MAC_Q0TFCR_PT_INDEX		16
 378#define MAC_Q0TFCR_PT_WIDTH		16
 379#define MAC_Q0TFCR_TFE_INDEX		1
 380#define MAC_Q0TFCR_TFE_WIDTH		1
 381#define MAC_RCR_ACS_INDEX		1
 382#define MAC_RCR_ACS_WIDTH		1
 383#define MAC_RCR_CST_INDEX		2
 384#define MAC_RCR_CST_WIDTH		1
 385#define MAC_RCR_DCRCC_INDEX		3
 386#define MAC_RCR_DCRCC_WIDTH		1
 387#define MAC_RCR_GPSLCE_INDEX		6
 388#define MAC_RCR_GPSLCE_WIDTH		1
 389#define MAC_RCR_WD_INDEX		7
 390#define MAC_RCR_WD_WIDTH		1
 391#define MAC_RCR_HDSMS_INDEX		12
 392#define MAC_RCR_HDSMS_WIDTH		3
 393#define MAC_RCR_IPC_INDEX		9
 394#define MAC_RCR_IPC_WIDTH		1
 395#define MAC_RCR_JE_INDEX		8
 396#define MAC_RCR_JE_WIDTH		1
 397#define MAC_RCR_LM_INDEX		10
 398#define MAC_RCR_LM_WIDTH		1
 399#define MAC_RCR_RE_INDEX		0
 400#define MAC_RCR_RE_WIDTH		1
 401#define MAC_RCR_GPSL_INDEX		16
 402#define MAC_RCR_GPSL_WIDTH		14
 403#define MAC_RFCR_PFCE_INDEX		8
 404#define MAC_RFCR_PFCE_WIDTH		1
 405#define MAC_RFCR_RFE_INDEX		0
 406#define MAC_RFCR_RFE_WIDTH		1
 407#define MAC_RFCR_UP_INDEX		1
 408#define MAC_RFCR_UP_WIDTH		1
 409#define MAC_RQC0R_RXQ0EN_INDEX		0
 410#define MAC_RQC0R_RXQ0EN_WIDTH		2
 411#define MAC_RSSAR_ADDRT_INDEX		2
 412#define MAC_RSSAR_ADDRT_WIDTH		1
 413#define MAC_RSSAR_CT_INDEX		1
 414#define MAC_RSSAR_CT_WIDTH		1
 415#define MAC_RSSAR_OB_INDEX		0
 416#define MAC_RSSAR_OB_WIDTH		1
 417#define MAC_RSSAR_RSSIA_INDEX		8
 418#define MAC_RSSAR_RSSIA_WIDTH		8
 419#define MAC_RSSCR_IP2TE_INDEX		1
 420#define MAC_RSSCR_IP2TE_WIDTH		1
 421#define MAC_RSSCR_RSSE_INDEX		0
 422#define MAC_RSSCR_RSSE_WIDTH		1
 423#define MAC_RSSCR_TCP4TE_INDEX		2
 424#define MAC_RSSCR_TCP4TE_WIDTH		1
 425#define MAC_RSSCR_UDP4TE_INDEX		3
 426#define MAC_RSSCR_UDP4TE_WIDTH		1
 427#define MAC_RSSDR_DMCH_INDEX		0
 428#define MAC_RSSDR_DMCH_WIDTH		4
 429#define MAC_SSIR_SNSINC_INDEX		8
 430#define MAC_SSIR_SNSINC_WIDTH		8
 431#define MAC_SSIR_SSINC_INDEX		16
 432#define MAC_SSIR_SSINC_WIDTH		8
 433#define MAC_TCR_SS_INDEX		29
 434#define MAC_TCR_SS_WIDTH		3
 435#define MAC_TCR_TE_INDEX		0
 436#define MAC_TCR_TE_WIDTH		1
 437#define MAC_TCR_VNE_INDEX		24
 438#define MAC_TCR_VNE_WIDTH		1
 439#define MAC_TCR_VNM_INDEX		25
 440#define MAC_TCR_VNM_WIDTH		1
 441#define MAC_TCR_JD_INDEX		16
 442#define MAC_TCR_JD_WIDTH		1
 443#define MAC_TIR_TNID_INDEX		0
 444#define MAC_TIR_TNID_WIDTH		16
 445#define MAC_TSCR_AV8021ASMEN_INDEX	28
 446#define MAC_TSCR_AV8021ASMEN_WIDTH	1
 447#define MAC_TSCR_SNAPTYPSEL_INDEX	16
 448#define MAC_TSCR_SNAPTYPSEL_WIDTH	2
 449#define MAC_TSCR_TSADDREG_INDEX		5
 450#define MAC_TSCR_TSADDREG_WIDTH		1
 451#define MAC_TSCR_TSUPDT_INDEX		3
 452#define MAC_TSCR_TSUPDT_WIDTH		1
 453#define MAC_TSCR_TSCFUPDT_INDEX		1
 454#define MAC_TSCR_TSCFUPDT_WIDTH		1
 455#define MAC_TSCR_TSCTRLSSR_INDEX	9
 456#define MAC_TSCR_TSCTRLSSR_WIDTH	1
 457#define MAC_TSCR_TSENA_INDEX		0
 458#define MAC_TSCR_TSENA_WIDTH		1
 459#define MAC_TSCR_TSENALL_INDEX		8
 460#define MAC_TSCR_TSENALL_WIDTH		1
 461#define MAC_TSCR_TSEVNTENA_INDEX	14
 462#define MAC_TSCR_TSEVNTENA_WIDTH	1
 463#define MAC_TSCR_TSINIT_INDEX		2
 464#define MAC_TSCR_TSINIT_WIDTH		1
 465#define MAC_TSCR_TSIPENA_INDEX		11
 466#define MAC_TSCR_TSIPENA_WIDTH		1
 467#define MAC_TSCR_TSIPV4ENA_INDEX	13
 468#define MAC_TSCR_TSIPV4ENA_WIDTH	1
 469#define MAC_TSCR_TSIPV6ENA_INDEX	12
 470#define MAC_TSCR_TSIPV6ENA_WIDTH	1
 471#define MAC_TSCR_TSMSTRENA_INDEX	15
 472#define MAC_TSCR_TSMSTRENA_WIDTH	1
 473#define MAC_TSCR_TSVER2ENA_INDEX	10
 474#define MAC_TSCR_TSVER2ENA_WIDTH	1
 475#define MAC_TSCR_TXTSSTSM_INDEX		24
 476#define MAC_TSCR_TXTSSTSM_WIDTH		1
 477#define MAC_TSSR_TXTSC_INDEX		15
 478#define MAC_TSSR_TXTSC_WIDTH		1
 479#define MAC_TXSNR_TXTSSTSMIS_INDEX	31
 480#define MAC_TXSNR_TXTSSTSMIS_WIDTH	1
 481#define MAC_TICSNR_TSICSNS_INDEX	8
 482#define MAC_TICSNR_TSICSNS_WIDTH	8
 483#define MAC_TECSNR_TSECSNS_INDEX	8
 484#define MAC_TECSNR_TSECSNS_WIDTH	8
 485#define MAC_VLANHTR_VLHT_INDEX		0
 486#define MAC_VLANHTR_VLHT_WIDTH		16
 487#define MAC_VLANIR_VLTI_INDEX		20
 488#define MAC_VLANIR_VLTI_WIDTH		1
 489#define MAC_VLANIR_CSVL_INDEX		19
 490#define MAC_VLANIR_CSVL_WIDTH		1
 491#define MAC_VLANTR_DOVLTC_INDEX		20
 492#define MAC_VLANTR_DOVLTC_WIDTH		1
 493#define MAC_VLANTR_ERSVLM_INDEX		19
 494#define MAC_VLANTR_ERSVLM_WIDTH		1
 495#define MAC_VLANTR_ESVL_INDEX		18
 496#define MAC_VLANTR_ESVL_WIDTH		1
 497#define MAC_VLANTR_ETV_INDEX		16
 498#define MAC_VLANTR_ETV_WIDTH		1
 499#define MAC_VLANTR_EVLS_INDEX		21
 500#define MAC_VLANTR_EVLS_WIDTH		2
 501#define MAC_VLANTR_EVLRXS_INDEX		24
 502#define MAC_VLANTR_EVLRXS_WIDTH		1
 503#define MAC_VLANTR_VL_INDEX		0
 504#define MAC_VLANTR_VL_WIDTH		16
 505#define MAC_VLANTR_VTHM_INDEX		25
 506#define MAC_VLANTR_VTHM_WIDTH		1
 507#define MAC_VLANTR_VTIM_INDEX		17
 508#define MAC_VLANTR_VTIM_WIDTH		1
 509#define MAC_VR_DEVID_INDEX		8
 510#define MAC_VR_DEVID_WIDTH		8
 511#define MAC_VR_SNPSVER_INDEX		0
 512#define MAC_VR_SNPSVER_WIDTH		8
 513#define MAC_VR_USERVER_INDEX		16
 514#define MAC_VR_USERVER_WIDTH		8
 515#define MAC_PPSx_TTNSR_TRGTBUSY0_INDEX	31
 516#define MAC_PPSx_TTNSR_TRGTBUSY0_WIDTH	1
 517
 518 /* MMC register offsets */
 519#define MMC_CR				0x0800
 520#define MMC_RISR			0x0804
 521#define MMC_TISR			0x0808
 522#define MMC_RIER			0x080c
 523#define MMC_TIER			0x0810
 524#define MMC_TXOCTETCOUNT_GB_LO		0x0814
 525#define MMC_TXOCTETCOUNT_GB_HI		0x0818
 526#define MMC_TXFRAMECOUNT_GB_LO		0x081c
 527#define MMC_TXFRAMECOUNT_GB_HI		0x0820
 528#define MMC_TXBROADCASTFRAMES_G_LO	0x0824
 529#define MMC_TXBROADCASTFRAMES_G_HI	0x0828
 530#define MMC_TXMULTICASTFRAMES_G_LO	0x082c
 531#define MMC_TXMULTICASTFRAMES_G_HI	0x0830
 532#define MMC_TX64OCTETS_GB_LO		0x0834
 533#define MMC_TX64OCTETS_GB_HI		0x0838
 534#define MMC_TX65TO127OCTETS_GB_LO	0x083c
 535#define MMC_TX65TO127OCTETS_GB_HI	0x0840
 536#define MMC_TX128TO255OCTETS_GB_LO	0x0844
 537#define MMC_TX128TO255OCTETS_GB_HI	0x0848
 538#define MMC_TX256TO511OCTETS_GB_LO	0x084c
 539#define MMC_TX256TO511OCTETS_GB_HI	0x0850
 540#define MMC_TX512TO1023OCTETS_GB_LO	0x0854
 541#define MMC_TX512TO1023OCTETS_GB_HI	0x0858
 542#define MMC_TX1024TOMAXOCTETS_GB_LO	0x085c
 543#define MMC_TX1024TOMAXOCTETS_GB_HI	0x0860
 544#define MMC_TXUNICASTFRAMES_GB_LO	0x0864
 545#define MMC_TXUNICASTFRAMES_GB_HI	0x0868
 546#define MMC_TXMULTICASTFRAMES_GB_LO	0x086c
 547#define MMC_TXMULTICASTFRAMES_GB_HI	0x0870
 548#define MMC_TXBROADCASTFRAMES_GB_LO	0x0874
 549#define MMC_TXBROADCASTFRAMES_GB_HI	0x0878
 550#define MMC_TXUNDERFLOWERROR_LO		0x087c
 551#define MMC_TXUNDERFLOWERROR_HI		0x0880
 552#define MMC_TXOCTETCOUNT_G_LO		0x0884
 553#define MMC_TXOCTETCOUNT_G_HI		0x0888
 554#define MMC_TXFRAMECOUNT_G_LO		0x088c
 555#define MMC_TXFRAMECOUNT_G_HI		0x0890
 556#define MMC_TXPAUSEFRAMES_LO		0x0894
 557#define MMC_TXPAUSEFRAMES_HI		0x0898
 558#define MMC_TXVLANFRAMES_G_LO		0x089c
 559#define MMC_TXVLANFRAMES_G_HI		0x08a0
 560#define MMC_RXFRAMECOUNT_GB_LO		0x0900
 561#define MMC_RXFRAMECOUNT_GB_HI		0x0904
 562#define MMC_RXOCTETCOUNT_GB_LO		0x0908
 563#define MMC_RXOCTETCOUNT_GB_HI		0x090c
 564#define MMC_RXOCTETCOUNT_G_LO		0x0910
 565#define MMC_RXOCTETCOUNT_G_HI		0x0914
 566#define MMC_RXBROADCASTFRAMES_G_LO	0x0918
 567#define MMC_RXBROADCASTFRAMES_G_HI	0x091c
 568#define MMC_RXMULTICASTFRAMES_G_LO	0x0920
 569#define MMC_RXMULTICASTFRAMES_G_HI	0x0924
 570#define MMC_RXCRCERROR_LO		0x0928
 571#define MMC_RXCRCERROR_HI		0x092c
 572#define MMC_RXRUNTERROR			0x0930
 573#define MMC_RXJABBERERROR		0x0934
 574#define MMC_RXUNDERSIZE_G		0x0938
 575#define MMC_RXOVERSIZE_G		0x093c
 576#define MMC_RX64OCTETS_GB_LO		0x0940
 577#define MMC_RX64OCTETS_GB_HI		0x0944
 578#define MMC_RX65TO127OCTETS_GB_LO	0x0948
 579#define MMC_RX65TO127OCTETS_GB_HI	0x094c
 580#define MMC_RX128TO255OCTETS_GB_LO	0x0950
 581#define MMC_RX128TO255OCTETS_GB_HI	0x0954
 582#define MMC_RX256TO511OCTETS_GB_LO	0x0958
 583#define MMC_RX256TO511OCTETS_GB_HI	0x095c
 584#define MMC_RX512TO1023OCTETS_GB_LO	0x0960
 585#define MMC_RX512TO1023OCTETS_GB_HI	0x0964
 586#define MMC_RX1024TOMAXOCTETS_GB_LO	0x0968
 587#define MMC_RX1024TOMAXOCTETS_GB_HI	0x096c
 588#define MMC_RXUNICASTFRAMES_G_LO	0x0970
 589#define MMC_RXUNICASTFRAMES_G_HI	0x0974
 590#define MMC_RXLENGTHERROR_LO		0x0978
 591#define MMC_RXLENGTHERROR_HI		0x097c
 592#define MMC_RXOUTOFRANGETYPE_LO		0x0980
 593#define MMC_RXOUTOFRANGETYPE_HI		0x0984
 594#define MMC_RXPAUSEFRAMES_LO		0x0988
 595#define MMC_RXPAUSEFRAMES_HI		0x098c
 596#define MMC_RXFIFOOVERFLOW_LO		0x0990
 597#define MMC_RXFIFOOVERFLOW_HI		0x0994
 598#define MMC_RXVLANFRAMES_GB_LO		0x0998
 599#define MMC_RXVLANFRAMES_GB_HI		0x099c
 600#define MMC_RXWATCHDOGERROR		0x09a0
 601
 602/* MMC register entry bit positions and sizes */
 603#define MMC_CR_CR_INDEX				0
 604#define MMC_CR_CR_WIDTH				1
 605#define MMC_CR_CSR_INDEX			1
 606#define MMC_CR_CSR_WIDTH			1
 607#define MMC_CR_ROR_INDEX			2
 608#define MMC_CR_ROR_WIDTH			1
 609#define MMC_CR_MCF_INDEX			3
 610#define MMC_CR_MCF_WIDTH			1
 611#define MMC_CR_MCT_INDEX			4
 612#define MMC_CR_MCT_WIDTH			2
 613#define MMC_RIER_ALL_INTERRUPTS_INDEX		0
 614#define MMC_RIER_ALL_INTERRUPTS_WIDTH		23
 615#define MMC_RISR_RXFRAMECOUNT_GB_INDEX		0
 616#define MMC_RISR_RXFRAMECOUNT_GB_WIDTH		1
 617#define MMC_RISR_RXOCTETCOUNT_GB_INDEX		1
 618#define MMC_RISR_RXOCTETCOUNT_GB_WIDTH		1
 619#define MMC_RISR_RXOCTETCOUNT_G_INDEX		2
 620#define MMC_RISR_RXOCTETCOUNT_G_WIDTH		1
 621#define MMC_RISR_RXBROADCASTFRAMES_G_INDEX	3
 622#define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH	1
 623#define MMC_RISR_RXMULTICASTFRAMES_G_INDEX	4
 624#define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH	1
 625#define MMC_RISR_RXCRCERROR_INDEX		5
 626#define MMC_RISR_RXCRCERROR_WIDTH		1
 627#define MMC_RISR_RXRUNTERROR_INDEX		6
 628#define MMC_RISR_RXRUNTERROR_WIDTH		1
 629#define MMC_RISR_RXJABBERERROR_INDEX		7
 630#define MMC_RISR_RXJABBERERROR_WIDTH		1
 631#define MMC_RISR_RXUNDERSIZE_G_INDEX		8
 632#define MMC_RISR_RXUNDERSIZE_G_WIDTH		1
 633#define MMC_RISR_RXOVERSIZE_G_INDEX		9
 634#define MMC_RISR_RXOVERSIZE_G_WIDTH		1
 635#define MMC_RISR_RX64OCTETS_GB_INDEX		10
 636#define MMC_RISR_RX64OCTETS_GB_WIDTH		1
 637#define MMC_RISR_RX65TO127OCTETS_GB_INDEX	11
 638#define MMC_RISR_RX65TO127OCTETS_GB_WIDTH	1
 639#define MMC_RISR_RX128TO255OCTETS_GB_INDEX	12
 640#define MMC_RISR_RX128TO255OCTETS_GB_WIDTH	1
 641#define MMC_RISR_RX256TO511OCTETS_GB_INDEX	13
 642#define MMC_RISR_RX256TO511OCTETS_GB_WIDTH	1
 643#define MMC_RISR_RX512TO1023OCTETS_GB_INDEX	14
 644#define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH	1
 645#define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX	15
 646#define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH	1
 647#define MMC_RISR_RXUNICASTFRAMES_G_INDEX	16
 648#define MMC_RISR_RXUNICASTFRAMES_G_WIDTH	1
 649#define MMC_RISR_RXLENGTHERROR_INDEX		17
 650#define MMC_RISR_RXLENGTHERROR_WIDTH		1
 651#define MMC_RISR_RXOUTOFRANGETYPE_INDEX		18
 652#define MMC_RISR_RXOUTOFRANGETYPE_WIDTH		1
 653#define MMC_RISR_RXPAUSEFRAMES_INDEX		19
 654#define MMC_RISR_RXPAUSEFRAMES_WIDTH		1
 655#define MMC_RISR_RXFIFOOVERFLOW_INDEX		20
 656#define MMC_RISR_RXFIFOOVERFLOW_WIDTH		1
 657#define MMC_RISR_RXVLANFRAMES_GB_INDEX		21
 658#define MMC_RISR_RXVLANFRAMES_GB_WIDTH		1
 659#define MMC_RISR_RXWATCHDOGERROR_INDEX		22
 660#define MMC_RISR_RXWATCHDOGERROR_WIDTH		1
 661#define MMC_TIER_ALL_INTERRUPTS_INDEX		0
 662#define MMC_TIER_ALL_INTERRUPTS_WIDTH		18
 663#define MMC_TISR_TXOCTETCOUNT_GB_INDEX		0
 664#define MMC_TISR_TXOCTETCOUNT_GB_WIDTH		1
 665#define MMC_TISR_TXFRAMECOUNT_GB_INDEX		1
 666#define MMC_TISR_TXFRAMECOUNT_GB_WIDTH		1
 667#define MMC_TISR_TXBROADCASTFRAMES_G_INDEX	2
 668#define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH	1
 669#define MMC_TISR_TXMULTICASTFRAMES_G_INDEX	3
 670#define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH	1
 671#define MMC_TISR_TX64OCTETS_GB_INDEX		4
 672#define MMC_TISR_TX64OCTETS_GB_WIDTH		1
 673#define MMC_TISR_TX65TO127OCTETS_GB_INDEX	5
 674#define MMC_TISR_TX65TO127OCTETS_GB_WIDTH	1
 675#define MMC_TISR_TX128TO255OCTETS_GB_INDEX	6
 676#define MMC_TISR_TX128TO255OCTETS_GB_WIDTH	1
 677#define MMC_TISR_TX256TO511OCTETS_GB_INDEX	7
 678#define MMC_TISR_TX256TO511OCTETS_GB_WIDTH	1
 679#define MMC_TISR_TX512TO1023OCTETS_GB_INDEX	8
 680#define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH	1
 681#define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX	9
 682#define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH	1
 683#define MMC_TISR_TXUNICASTFRAMES_GB_INDEX	10
 684#define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH	1
 685#define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX	11
 686#define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH	1
 687#define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX	12
 688#define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH	1
 689#define MMC_TISR_TXUNDERFLOWERROR_INDEX		13
 690#define MMC_TISR_TXUNDERFLOWERROR_WIDTH		1
 691#define MMC_TISR_TXOCTETCOUNT_G_INDEX		14
 692#define MMC_TISR_TXOCTETCOUNT_G_WIDTH		1
 693#define MMC_TISR_TXFRAMECOUNT_G_INDEX		15
 694#define MMC_TISR_TXFRAMECOUNT_G_WIDTH		1
 695#define MMC_TISR_TXPAUSEFRAMES_INDEX		16
 696#define MMC_TISR_TXPAUSEFRAMES_WIDTH		1
 697#define MMC_TISR_TXVLANFRAMES_G_INDEX		17
 698#define MMC_TISR_TXVLANFRAMES_G_WIDTH		1
 699
 700/* MTL register offsets */
 701#define MTL_OMR				0x1000
 702#define MTL_FDCR			0x1008
 703#define MTL_FDSR			0x100c
 704#define MTL_FDDR			0x1010
 705#define MTL_ISR				0x1020
 706#define MTL_RQDCM0R			0x1030
 707#define MTL_TCPM0R			0x1040
 708#define MTL_TCPM1R			0x1044
 709
 710#define MTL_RQDCM_INC			4
 711#define MTL_RQDCM_Q_PER_REG		4
 712#define MTL_TCPM_INC			4
 713#define MTL_TCPM_TC_PER_REG		4
 714
 715/* MTL register entry bit positions and sizes */
 716#define MTL_OMR_ETSALG_INDEX		5
 717#define MTL_OMR_ETSALG_WIDTH		2
 718#define MTL_OMR_RAA_INDEX		2
 719#define MTL_OMR_RAA_WIDTH		1
 720
 721/* MTL queue register offsets
 722 *   Multiple queues can be active.  The first queue has registers
 723 *   that begin at 0x1100.  Each subsequent queue has registers that
 724 *   are accessed using an offset of 0x80 from the previous queue.
 725 */
 726#define MTL_Q_BASE			0x1100
 727#define MTL_Q_INC			0x80
 728
 729#define MTL_Q_TQOMR			0x00
 730#define MTL_Q_TQUR			0x04
 731#define MTL_Q_TQDR			0x08
 732#define MTL_Q_RQOMR			0x40
 733#define MTL_Q_RQMPOCR			0x44
 734#define MTL_Q_RQDR			0x48
 735#define MTL_Q_RQFCR			0x50
 736#define MTL_Q_IER			0x70
 737#define MTL_Q_ISR			0x74
 738
 739/* MTL queue register entry bit positions and sizes */
 740#define MTL_Q_RQDR_PRXQ_INDEX		16
 741#define MTL_Q_RQDR_PRXQ_WIDTH		14
 742#define MTL_Q_RQDR_RXQSTS_INDEX		4
 743#define MTL_Q_RQDR_RXQSTS_WIDTH		2
 744#define MTL_Q_RQFCR_RFA_INDEX		1
 745#define MTL_Q_RQFCR_RFA_WIDTH		6
 746#define MTL_Q_RQFCR_RFD_INDEX		17
 747#define MTL_Q_RQFCR_RFD_WIDTH		6
 748#define MTL_Q_RQOMR_EHFC_INDEX		7
 749#define MTL_Q_RQOMR_EHFC_WIDTH		1
 750#define MTL_Q_RQOMR_RQS_INDEX		16
 751#define MTL_Q_RQOMR_RQS_WIDTH		9
 752#define MTL_Q_RQOMR_RSF_INDEX		5
 753#define MTL_Q_RQOMR_RSF_WIDTH		1
 754#define MTL_Q_RQOMR_RTC_INDEX		0
 755#define MTL_Q_RQOMR_RTC_WIDTH		2
 756#define MTL_Q_TQDR_TRCSTS_INDEX		1
 757#define MTL_Q_TQDR_TRCSTS_WIDTH		2
 758#define MTL_Q_TQDR_TXQSTS_INDEX		4
 759#define MTL_Q_TQDR_TXQSTS_WIDTH		1
 760#define MTL_Q_TQOMR_FTQ_INDEX		0
 761#define MTL_Q_TQOMR_FTQ_WIDTH		1
 762#define MTL_Q_TQOMR_Q2TCMAP_INDEX	8
 763#define MTL_Q_TQOMR_Q2TCMAP_WIDTH	3
 764#define MTL_Q_TQOMR_TQS_INDEX		16
 765#define MTL_Q_TQOMR_TQS_WIDTH		10
 766#define MTL_Q_TQOMR_TSF_INDEX		1
 767#define MTL_Q_TQOMR_TSF_WIDTH		1
 768#define MTL_Q_TQOMR_TTC_INDEX		4
 769#define MTL_Q_TQOMR_TTC_WIDTH		3
 770#define MTL_Q_TQOMR_TXQEN_INDEX		2
 771#define MTL_Q_TQOMR_TXQEN_WIDTH		2
 772
 773/* MTL queue register value */
 774#define MTL_RSF_DISABLE			0x00
 775#define MTL_RSF_ENABLE			0x01
 776#define MTL_TSF_DISABLE			0x00
 777#define MTL_TSF_ENABLE			0x01
 778
 779#define MTL_RX_THRESHOLD_64		0x00
 780#define MTL_RX_THRESHOLD_96		0x02
 781#define MTL_RX_THRESHOLD_128		0x03
 782#define MTL_TX_THRESHOLD_32		0x01
 783#define MTL_TX_THRESHOLD_64		0x00
 784#define MTL_TX_THRESHOLD_96		0x02
 785#define MTL_TX_THRESHOLD_128		0x03
 786#define MTL_TX_THRESHOLD_192		0x04
 787#define MTL_TX_THRESHOLD_256		0x05
 788#define MTL_TX_THRESHOLD_384		0x06
 789#define MTL_TX_THRESHOLD_512		0x07
 790
 791#define MTL_ETSALG_WRR			0x00
 792#define MTL_ETSALG_WFQ			0x01
 793#define MTL_ETSALG_DWRR			0x02
 794#define MTL_RAA_SP			0x00
 795#define MTL_RAA_WSP			0x01
 796
 797#define MTL_Q_DISABLED			0x00
 798#define MTL_Q_ENABLED			0x02
 799
 800/* MTL traffic class register offsets
 801 *   Multiple traffic classes can be active.  The first class has registers
 802 *   that begin at 0x1100.  Each subsequent queue has registers that
 803 *   are accessed using an offset of 0x80 from the previous queue.
 804 */
 805#define MTL_TC_BASE			MTL_Q_BASE
 806#define MTL_TC_INC			MTL_Q_INC
 807
 808#define MTL_TC_ETSCR			0x10
 809#define MTL_TC_ETSSR			0x14
 810#define MTL_TC_QWR			0x18
 811
 812/* MTL traffic class register entry bit positions and sizes */
 813#define MTL_TC_ETSCR_TSA_INDEX		0
 814#define MTL_TC_ETSCR_TSA_WIDTH		2
 815#define MTL_TC_QWR_QW_INDEX		0
 816#define MTL_TC_QWR_QW_WIDTH		21
 817
 818/* MTL traffic class register value */
 819#define MTL_TSA_SP			0x00
 820#define MTL_TSA_ETS			0x02
 821
 822/* PCS register offsets */
 823#define PCS_V1_WINDOW_SELECT		0x03fc
 824#define PCS_V2_WINDOW_DEF		0x9060
 825#define PCS_V2_WINDOW_SELECT		0x9064
 826#define PCS_V2_RV_WINDOW_DEF		0x1060
 827#define PCS_V2_RV_WINDOW_SELECT		0x1064
 828#define PCS_V2_YC_WINDOW_DEF		0x18060
 829#define PCS_V2_YC_WINDOW_SELECT		0x18064
 830#define PCS_V3_RN_WINDOW_DEF		0xf8078
 831#define PCS_V3_RN_WINDOW_SELECT		0xf807c
 832
 833#define PCS_RN_SMN_BASE_ADDR		0x11e00000
 834#define PCS_RN_PORT_ADDR_SIZE		0x100000
 835
 836/* PCS register entry bit positions and sizes */
 837#define PCS_V2_WINDOW_DEF_OFFSET_INDEX	6
 838#define PCS_V2_WINDOW_DEF_OFFSET_WIDTH	14
 839#define PCS_V2_WINDOW_DEF_SIZE_INDEX	2
 840#define PCS_V2_WINDOW_DEF_SIZE_WIDTH	4
 841
 842/* SerDes integration register offsets */
 843#define SIR0_KR_RT_1			0x002c
 844#define SIR0_STATUS			0x0040
 845#define SIR1_SPEED			0x0000
 846
 847/* SerDes integration register entry bit positions and sizes */
 848#define SIR0_KR_RT_1_RESET_INDEX	11
 849#define SIR0_KR_RT_1_RESET_WIDTH	1
 850#define SIR0_STATUS_RX_READY_INDEX	0
 851#define SIR0_STATUS_RX_READY_WIDTH	1
 852#define SIR0_STATUS_TX_READY_INDEX	8
 853#define SIR0_STATUS_TX_READY_WIDTH	1
 854#define SIR1_SPEED_CDR_RATE_INDEX	12
 855#define SIR1_SPEED_CDR_RATE_WIDTH	4
 856#define SIR1_SPEED_DATARATE_INDEX	4
 857#define SIR1_SPEED_DATARATE_WIDTH	2
 858#define SIR1_SPEED_PLLSEL_INDEX		3
 859#define SIR1_SPEED_PLLSEL_WIDTH		1
 860#define SIR1_SPEED_RATECHANGE_INDEX	6
 861#define SIR1_SPEED_RATECHANGE_WIDTH	1
 862#define SIR1_SPEED_TXAMP_INDEX		8
 863#define SIR1_SPEED_TXAMP_WIDTH		4
 864#define SIR1_SPEED_WORDMODE_INDEX	0
 865#define SIR1_SPEED_WORDMODE_WIDTH	3
 866
 867/* SerDes RxTx register offsets */
 868#define RXTX_REG6			0x0018
 869#define RXTX_REG20			0x0050
 870#define RXTX_REG22			0x0058
 871#define RXTX_REG114			0x01c8
 872#define RXTX_REG129			0x0204
 873
 874/* SerDes RxTx register entry bit positions and sizes */
 875#define RXTX_REG6_RESETB_RXD_INDEX	8
 876#define RXTX_REG6_RESETB_RXD_WIDTH	1
 877#define RXTX_REG20_BLWC_ENA_INDEX	2
 878#define RXTX_REG20_BLWC_ENA_WIDTH	1
 879#define RXTX_REG114_PQ_REG_INDEX	9
 880#define RXTX_REG114_PQ_REG_WIDTH	7
 881#define RXTX_REG129_RXDFE_CONFIG_INDEX	14
 882#define RXTX_REG129_RXDFE_CONFIG_WIDTH	2
 883
 884/* MAC Control register offsets */
 885#define XP_PROP_0			0x0000
 886#define XP_PROP_1			0x0004
 887#define XP_PROP_2			0x0008
 888#define XP_PROP_3			0x000c
 889#define XP_PROP_4			0x0010
 890#define XP_PROP_5			0x0014
 891#define XP_MAC_ADDR_LO			0x0020
 892#define XP_MAC_ADDR_HI			0x0024
 893#define XP_ECC_ISR			0x0030
 894#define XP_ECC_IER			0x0034
 895#define XP_ECC_CNT0			0x003c
 896#define XP_ECC_CNT1			0x0040
 897#define XP_DRIVER_INT_REQ		0x0060
 898#define XP_DRIVER_INT_RO		0x0064
 899#define XP_DRIVER_SCRATCH_0		0x0068
 900#define XP_DRIVER_SCRATCH_1		0x006c
 901#define XP_INT_REISSUE_EN		0x0074
 902#define XP_INT_EN			0x0078
 903#define XP_I2C_MUTEX			0x0080
 904#define XP_MDIO_MUTEX			0x0084
 905
 906/* MAC Control register entry bit positions and sizes */
 907#define XP_DRIVER_INT_REQ_REQUEST_INDEX		0
 908#define XP_DRIVER_INT_REQ_REQUEST_WIDTH		1
 909#define XP_DRIVER_INT_RO_STATUS_INDEX		0
 910#define XP_DRIVER_INT_RO_STATUS_WIDTH		1
 911#define XP_DRIVER_SCRATCH_0_COMMAND_INDEX	0
 912#define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH	8
 913#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX	8
 914#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH	8
 915#define XP_ECC_CNT0_RX_DED_INDEX		24
 916#define XP_ECC_CNT0_RX_DED_WIDTH		8
 917#define XP_ECC_CNT0_RX_SEC_INDEX		16
 918#define XP_ECC_CNT0_RX_SEC_WIDTH		8
 919#define XP_ECC_CNT0_TX_DED_INDEX		8
 920#define XP_ECC_CNT0_TX_DED_WIDTH		8
 921#define XP_ECC_CNT0_TX_SEC_INDEX		0
 922#define XP_ECC_CNT0_TX_SEC_WIDTH		8
 923#define XP_ECC_CNT1_DESC_DED_INDEX		8
 924#define XP_ECC_CNT1_DESC_DED_WIDTH		8
 925#define XP_ECC_CNT1_DESC_SEC_INDEX		0
 926#define XP_ECC_CNT1_DESC_SEC_WIDTH		8
 927#define XP_ECC_IER_DESC_DED_INDEX		5
 928#define XP_ECC_IER_DESC_DED_WIDTH		1
 929#define XP_ECC_IER_DESC_SEC_INDEX		4
 930#define XP_ECC_IER_DESC_SEC_WIDTH		1
 931#define XP_ECC_IER_RX_DED_INDEX			3
 932#define XP_ECC_IER_RX_DED_WIDTH			1
 933#define XP_ECC_IER_RX_SEC_INDEX			2
 934#define XP_ECC_IER_RX_SEC_WIDTH			1
 935#define XP_ECC_IER_TX_DED_INDEX			1
 936#define XP_ECC_IER_TX_DED_WIDTH			1
 937#define XP_ECC_IER_TX_SEC_INDEX			0
 938#define XP_ECC_IER_TX_SEC_WIDTH			1
 939#define XP_ECC_ISR_DESC_DED_INDEX		5
 940#define XP_ECC_ISR_DESC_DED_WIDTH		1
 941#define XP_ECC_ISR_DESC_SEC_INDEX		4
 942#define XP_ECC_ISR_DESC_SEC_WIDTH		1
 943#define XP_ECC_ISR_RX_DED_INDEX			3
 944#define XP_ECC_ISR_RX_DED_WIDTH			1
 945#define XP_ECC_ISR_RX_SEC_INDEX			2
 946#define XP_ECC_ISR_RX_SEC_WIDTH			1
 947#define XP_ECC_ISR_TX_DED_INDEX			1
 948#define XP_ECC_ISR_TX_DED_WIDTH			1
 949#define XP_ECC_ISR_TX_SEC_INDEX			0
 950#define XP_ECC_ISR_TX_SEC_WIDTH			1
 951#define XP_I2C_MUTEX_BUSY_INDEX			31
 952#define XP_I2C_MUTEX_BUSY_WIDTH			1
 953#define XP_I2C_MUTEX_ID_INDEX			29
 954#define XP_I2C_MUTEX_ID_WIDTH			2
 955#define XP_I2C_MUTEX_ACTIVE_INDEX		0
 956#define XP_I2C_MUTEX_ACTIVE_WIDTH		1
 957#define XP_MAC_ADDR_HI_VALID_INDEX		31
 958#define XP_MAC_ADDR_HI_VALID_WIDTH		1
 959#define XP_PROP_0_CONN_TYPE_INDEX		28
 960#define XP_PROP_0_CONN_TYPE_WIDTH		3
 961#define XP_PROP_0_MDIO_ADDR_INDEX		16
 962#define XP_PROP_0_MDIO_ADDR_WIDTH		5
 963#define XP_PROP_0_PORT_ID_INDEX			0
 964#define XP_PROP_0_PORT_ID_WIDTH			8
 965#define XP_PROP_0_PORT_MODE_INDEX		8
 966#define XP_PROP_0_PORT_MODE_WIDTH		4
 967#define XP_PROP_0_PORT_SPEEDS_INDEX		22
 968#define XP_PROP_0_PORT_SPEEDS_WIDTH		5
 969#define XP_PROP_1_MAX_RX_DMA_INDEX		24
 970#define XP_PROP_1_MAX_RX_DMA_WIDTH		5
 971#define XP_PROP_1_MAX_RX_QUEUES_INDEX		8
 972#define XP_PROP_1_MAX_RX_QUEUES_WIDTH		5
 973#define XP_PROP_1_MAX_TX_DMA_INDEX		16
 974#define XP_PROP_1_MAX_TX_DMA_WIDTH		5
 975#define XP_PROP_1_MAX_TX_QUEUES_INDEX		0
 976#define XP_PROP_1_MAX_TX_QUEUES_WIDTH		5
 977#define XP_PROP_2_RX_FIFO_SIZE_INDEX		16
 978#define XP_PROP_2_RX_FIFO_SIZE_WIDTH		16
 979#define XP_PROP_2_TX_FIFO_SIZE_INDEX		0
 980#define XP_PROP_2_TX_FIFO_SIZE_WIDTH		16
 981#define XP_PROP_3_GPIO_MASK_INDEX		28
 982#define XP_PROP_3_GPIO_MASK_WIDTH		4
 983#define XP_PROP_3_GPIO_MOD_ABS_INDEX		20
 984#define XP_PROP_3_GPIO_MOD_ABS_WIDTH		4
 985#define XP_PROP_3_GPIO_RATE_SELECT_INDEX	16
 986#define XP_PROP_3_GPIO_RATE_SELECT_WIDTH	4
 987#define XP_PROP_3_GPIO_RX_LOS_INDEX		24
 988#define XP_PROP_3_GPIO_RX_LOS_WIDTH		4
 989#define XP_PROP_3_GPIO_TX_FAULT_INDEX		12
 990#define XP_PROP_3_GPIO_TX_FAULT_WIDTH		4
 991#define XP_PROP_3_GPIO_ADDR_INDEX		8
 992#define XP_PROP_3_GPIO_ADDR_WIDTH		3
 993#define XP_PROP_3_MDIO_RESET_INDEX		0
 994#define XP_PROP_3_MDIO_RESET_WIDTH		2
 995#define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX	8
 996#define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH	3
 997#define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX	12
 998#define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH	4
 999#define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX	4
1000#define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH	2
1001#define XP_PROP_4_MUX_ADDR_HI_INDEX		8
1002#define XP_PROP_4_MUX_ADDR_HI_WIDTH		5
1003#define XP_PROP_4_MUX_ADDR_LO_INDEX		0
1004#define XP_PROP_4_MUX_ADDR_LO_WIDTH		3
1005#define XP_PROP_4_MUX_CHAN_INDEX		4
1006#define XP_PROP_4_MUX_CHAN_WIDTH		3
1007#define XP_PROP_4_REDRV_ADDR_INDEX		16
1008#define XP_PROP_4_REDRV_ADDR_WIDTH		7
1009#define XP_PROP_4_REDRV_IF_INDEX		23
1010#define XP_PROP_4_REDRV_IF_WIDTH		1
1011#define XP_PROP_4_REDRV_LANE_INDEX		24
1012#define XP_PROP_4_REDRV_LANE_WIDTH		3
1013#define XP_PROP_4_REDRV_MODEL_INDEX		28
1014#define XP_PROP_4_REDRV_MODEL_WIDTH		3
1015#define XP_PROP_4_REDRV_PRESENT_INDEX		31
1016#define XP_PROP_4_REDRV_PRESENT_WIDTH		1
1017
1018/* I2C Control register offsets */
1019#define IC_CON					0x0000
1020#define IC_TAR					0x0004
1021#define IC_DATA_CMD				0x0010
1022#define IC_INTR_STAT				0x002c
1023#define IC_INTR_MASK				0x0030
1024#define IC_RAW_INTR_STAT			0x0034
1025#define IC_CLR_INTR				0x0040
1026#define IC_CLR_TX_ABRT				0x0054
1027#define IC_CLR_STOP_DET				0x0060
1028#define IC_ENABLE				0x006c
1029#define IC_TXFLR				0x0074
1030#define IC_RXFLR				0x0078
1031#define IC_TX_ABRT_SOURCE			0x0080
1032#define IC_ENABLE_STATUS			0x009c
1033#define IC_COMP_PARAM_1				0x00f4
1034
1035/* I2C Control register entry bit positions and sizes */
1036#define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX	2
1037#define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH	2
1038#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX	8
1039#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH	8
1040#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX	16
1041#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH	8
1042#define IC_CON_MASTER_MODE_INDEX		0
1043#define IC_CON_MASTER_MODE_WIDTH		1
1044#define IC_CON_RESTART_EN_INDEX			5
1045#define IC_CON_RESTART_EN_WIDTH			1
1046#define IC_CON_RX_FIFO_FULL_HOLD_INDEX		9
1047#define IC_CON_RX_FIFO_FULL_HOLD_WIDTH		1
1048#define IC_CON_SLAVE_DISABLE_INDEX		6
1049#define IC_CON_SLAVE_DISABLE_WIDTH		1
1050#define IC_CON_SPEED_INDEX			1
1051#define IC_CON_SPEED_WIDTH			2
1052#define IC_DATA_CMD_CMD_INDEX			8
1053#define IC_DATA_CMD_CMD_WIDTH			1
1054#define IC_DATA_CMD_STOP_INDEX			9
1055#define IC_DATA_CMD_STOP_WIDTH			1
1056#define IC_ENABLE_ABORT_INDEX			1
1057#define IC_ENABLE_ABORT_WIDTH			1
1058#define IC_ENABLE_EN_INDEX			0
1059#define IC_ENABLE_EN_WIDTH			1
1060#define IC_ENABLE_STATUS_EN_INDEX		0
1061#define IC_ENABLE_STATUS_EN_WIDTH		1
1062#define IC_INTR_MASK_TX_EMPTY_INDEX		4
1063#define IC_INTR_MASK_TX_EMPTY_WIDTH		1
1064#define IC_RAW_INTR_STAT_RX_FULL_INDEX		2
1065#define IC_RAW_INTR_STAT_RX_FULL_WIDTH		1
1066#define IC_RAW_INTR_STAT_STOP_DET_INDEX		9
1067#define IC_RAW_INTR_STAT_STOP_DET_WIDTH		1
1068#define IC_RAW_INTR_STAT_TX_ABRT_INDEX		6
1069#define IC_RAW_INTR_STAT_TX_ABRT_WIDTH		1
1070#define IC_RAW_INTR_STAT_TX_EMPTY_INDEX		4
1071#define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH		1
1072
1073/* I2C Control register value */
1074#define IC_TX_ABRT_7B_ADDR_NOACK		0x0001
1075#define IC_TX_ABRT_ARB_LOST			0x1000
1076
1077/* Descriptor/Packet entry bit positions and sizes */
1078#define RX_PACKET_ERRORS_CRC_INDEX		2
1079#define RX_PACKET_ERRORS_CRC_WIDTH		1
1080#define RX_PACKET_ERRORS_FRAME_INDEX		3
1081#define RX_PACKET_ERRORS_FRAME_WIDTH		1
1082#define RX_PACKET_ERRORS_LENGTH_INDEX		0
1083#define RX_PACKET_ERRORS_LENGTH_WIDTH		1
1084#define RX_PACKET_ERRORS_OVERRUN_INDEX		1
1085#define RX_PACKET_ERRORS_OVERRUN_WIDTH		1
1086
1087#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX	0
1088#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH	1
1089#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX	1
1090#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH	1
1091#define RX_PACKET_ATTRIBUTES_LAST_INDEX		2
1092#define RX_PACKET_ATTRIBUTES_LAST_WIDTH		1
1093#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX	3
1094#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH	1
1095#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX	4
1096#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH	1
1097#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX	5
1098#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH	1
1099#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX	6
1100#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH	1
1101#define RX_PACKET_ATTRIBUTES_FIRST_INDEX	7
1102#define RX_PACKET_ATTRIBUTES_FIRST_WIDTH	1
1103#define RX_PACKET_ATTRIBUTES_TNP_INDEX		8
1104#define RX_PACKET_ATTRIBUTES_TNP_WIDTH		1
1105#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX	9
1106#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH	1
1107
1108#define RX_NORMAL_DESC0_OVT_INDEX		0
1109#define RX_NORMAL_DESC0_OVT_WIDTH		16
1110#define RX_NORMAL_DESC2_HL_INDEX		0
1111#define RX_NORMAL_DESC2_HL_WIDTH		10
1112#define RX_NORMAL_DESC2_TNP_INDEX		11
1113#define RX_NORMAL_DESC2_TNP_WIDTH		1
1114#define RX_NORMAL_DESC3_CDA_INDEX		27
1115#define RX_NORMAL_DESC3_CDA_WIDTH		1
1116#define RX_NORMAL_DESC3_CTXT_INDEX		30
1117#define RX_NORMAL_DESC3_CTXT_WIDTH		1
1118#define RX_NORMAL_DESC3_ES_INDEX		15
1119#define RX_NORMAL_DESC3_ES_WIDTH		1
1120#define RX_NORMAL_DESC3_ETLT_INDEX		16
1121#define RX_NORMAL_DESC3_ETLT_WIDTH		4
1122#define RX_NORMAL_DESC3_FD_INDEX		29
1123#define RX_NORMAL_DESC3_FD_WIDTH		1
1124#define RX_NORMAL_DESC3_INTE_INDEX		30
1125#define RX_NORMAL_DESC3_INTE_WIDTH		1
1126#define RX_NORMAL_DESC3_L34T_INDEX		20
1127#define RX_NORMAL_DESC3_L34T_WIDTH		4
1128#define RX_NORMAL_DESC3_LD_INDEX		28
1129#define RX_NORMAL_DESC3_LD_WIDTH		1
1130#define RX_NORMAL_DESC3_OWN_INDEX		31
1131#define RX_NORMAL_DESC3_OWN_WIDTH		1
1132#define RX_NORMAL_DESC3_PL_INDEX		0
1133#define RX_NORMAL_DESC3_PL_WIDTH		14
1134#define RX_NORMAL_DESC3_RSV_INDEX		26
1135#define RX_NORMAL_DESC3_RSV_WIDTH		1
1136
1137#define RX_DESC3_L34T_IPV4_TCP			1
1138#define RX_DESC3_L34T_IPV4_UDP			2
1139#define RX_DESC3_L34T_IPV4_ICMP			3
1140#define RX_DESC3_L34T_IPV4_UNKNOWN		7
1141#define RX_DESC3_L34T_IPV6_TCP			9
1142#define RX_DESC3_L34T_IPV6_UDP			10
1143#define RX_DESC3_L34T_IPV6_ICMP			11
1144#define RX_DESC3_L34T_IPV6_UNKNOWN		15
1145
1146#define RX_CONTEXT_DESC3_TSA_INDEX		4
1147#define RX_CONTEXT_DESC3_TSA_WIDTH		1
1148#define RX_CONTEXT_DESC3_TSD_INDEX		6
1149#define RX_CONTEXT_DESC3_TSD_WIDTH		1
1150
1151#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX	0
1152#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH	1
1153#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX	1
1154#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH	1
1155#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX	2
1156#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH	1
1157#define TX_PACKET_ATTRIBUTES_PTP_INDEX		3
1158#define TX_PACKET_ATTRIBUTES_PTP_WIDTH		1
1159#define TX_PACKET_ATTRIBUTES_VXLAN_INDEX	4
1160#define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH	1
1161
1162#define TX_CONTEXT_DESC2_MSS_INDEX		0
1163#define TX_CONTEXT_DESC2_MSS_WIDTH		15
1164#define TX_CONTEXT_DESC3_CTXT_INDEX		30
1165#define TX_CONTEXT_DESC3_CTXT_WIDTH		1
1166#define TX_CONTEXT_DESC3_TCMSSV_INDEX		26
1167#define TX_CONTEXT_DESC3_TCMSSV_WIDTH		1
1168#define TX_CONTEXT_DESC3_VLTV_INDEX		16
1169#define TX_CONTEXT_DESC3_VLTV_WIDTH		1
1170#define TX_CONTEXT_DESC3_VT_INDEX		0
1171#define TX_CONTEXT_DESC3_VT_WIDTH		16
1172
1173#define TX_NORMAL_DESC2_HL_B1L_INDEX		0
1174#define TX_NORMAL_DESC2_HL_B1L_WIDTH		14
1175#define TX_NORMAL_DESC2_IC_INDEX		31
1176#define TX_NORMAL_DESC2_IC_WIDTH		1
1177#define TX_NORMAL_DESC2_TTSE_INDEX		30
1178#define TX_NORMAL_DESC2_TTSE_WIDTH		1
1179#define TX_NORMAL_DESC2_VTIR_INDEX		14
1180#define TX_NORMAL_DESC2_VTIR_WIDTH		2
1181#define TX_NORMAL_DESC3_CIC_INDEX		16
1182#define TX_NORMAL_DESC3_CIC_WIDTH		2
1183#define TX_NORMAL_DESC3_CPC_INDEX		26
1184#define TX_NORMAL_DESC3_CPC_WIDTH		2
1185#define TX_NORMAL_DESC3_CTXT_INDEX		30
1186#define TX_NORMAL_DESC3_CTXT_WIDTH		1
1187#define TX_NORMAL_DESC3_FD_INDEX		29
1188#define TX_NORMAL_DESC3_FD_WIDTH		1
1189#define TX_NORMAL_DESC3_FL_INDEX		0
1190#define TX_NORMAL_DESC3_FL_WIDTH		15
1191#define TX_NORMAL_DESC3_LD_INDEX		28
1192#define TX_NORMAL_DESC3_LD_WIDTH		1
1193#define TX_NORMAL_DESC3_OWN_INDEX		31
1194#define TX_NORMAL_DESC3_OWN_WIDTH		1
1195#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX		19
1196#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH		4
1197#define TX_NORMAL_DESC3_TCPPL_INDEX		0
1198#define TX_NORMAL_DESC3_TCPPL_WIDTH		18
1199#define TX_NORMAL_DESC3_TSE_INDEX		18
1200#define TX_NORMAL_DESC3_TSE_WIDTH		1
1201#define TX_NORMAL_DESC3_VNP_INDEX		23
1202#define TX_NORMAL_DESC3_VNP_WIDTH		3
1203
1204#define TX_NORMAL_DESC2_VLAN_INSERT		0x2
1205#define TX_NORMAL_DESC3_VXLAN_PACKET		0x3
1206
1207/* MDIO undefined or vendor specific registers */
1208#ifndef MDIO_PMA_10GBR_PMD_CTRL
1209#define MDIO_PMA_10GBR_PMD_CTRL		0x0096
1210#endif
1211
1212#ifndef MDIO_PMA_10GBR_FECCTRL
1213#define MDIO_PMA_10GBR_FECCTRL		0x00ab
1214#endif
1215
1216#ifndef MDIO_PMA_RX_CTRL1
1217#define MDIO_PMA_RX_CTRL1		0x8051
1218#endif
1219
1220#ifndef MDIO_PMA_RX_LSTS
1221#define MDIO_PMA_RX_LSTS		0x018020
1222#endif
1223
1224#ifndef MDIO_PMA_RX_EQ_CTRL4
1225#define MDIO_PMA_RX_EQ_CTRL4		0x0001805C
1226#endif
1227
1228#ifndef MDIO_PMA_MP_MISC_STS
1229#define MDIO_PMA_MP_MISC_STS		0x0078
1230#endif
1231
1232#ifndef MDIO_PMA_PHY_RX_EQ_CEU
1233#define MDIO_PMA_PHY_RX_EQ_CEU		0x1800E
1234#endif
1235
1236#ifndef MDIO_PCS_DIG_CTRL
1237#define MDIO_PCS_DIG_CTRL		0x8000
1238#endif
1239
1240#ifndef MDIO_PCS_DIGITAL_STAT
1241#define MDIO_PCS_DIGITAL_STAT		0x8010
1242#endif
1243
1244#ifndef MDIO_AN_XNP
1245#define MDIO_AN_XNP			0x0016
1246#endif
1247
1248#ifndef MDIO_AN_LPX
1249#define MDIO_AN_LPX			0x0019
1250#endif
1251
1252#ifndef MDIO_AN_COMP_STAT
1253#define MDIO_AN_COMP_STAT		0x0030
1254#endif
1255
1256#ifndef MDIO_AN_INTMASK
1257#define MDIO_AN_INTMASK			0x8001
1258#endif
1259
1260#ifndef MDIO_AN_INT
1261#define MDIO_AN_INT			0x8002
1262#endif
1263
1264#ifndef MDIO_VEND2_AN_ADVERTISE
1265#define MDIO_VEND2_AN_ADVERTISE		0x0004
1266#endif
1267
1268#ifndef MDIO_VEND2_AN_LP_ABILITY
1269#define MDIO_VEND2_AN_LP_ABILITY	0x0005
1270#endif
1271
1272#ifndef MDIO_VEND2_AN_CTRL
1273#define MDIO_VEND2_AN_CTRL		0x8001
1274#endif
1275
1276#ifndef MDIO_VEND2_AN_STAT
1277#define MDIO_VEND2_AN_STAT		0x8002
1278#endif
1279
1280#ifndef MDIO_VEND2_PMA_CDR_CONTROL
1281#define MDIO_VEND2_PMA_CDR_CONTROL	0x8056
1282#endif
1283
1284#ifndef MDIO_VEND2_PMA_MISC_CTRL0
1285#define MDIO_VEND2_PMA_MISC_CTRL0	0x8090
1286#endif
1287
1288#ifndef MDIO_CTRL1_SPEED1G
1289#define MDIO_CTRL1_SPEED1G		(MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
1290#endif
1291
1292#ifndef MDIO_VEND2_CTRL1_AN_ENABLE
1293#define MDIO_VEND2_CTRL1_AN_ENABLE	BIT(12)
1294#endif
1295
1296#ifndef MDIO_VEND2_CTRL1_AN_RESTART
1297#define MDIO_VEND2_CTRL1_AN_RESTART	BIT(9)
1298#endif
1299
1300#ifndef MDIO_VEND2_CTRL1_SS6
1301#define MDIO_VEND2_CTRL1_SS6		BIT(6)
1302#endif
1303
1304#ifndef MDIO_VEND2_CTRL1_SS13
1305#define MDIO_VEND2_CTRL1_SS13		BIT(13)
1306#endif
1307
1308#define XGBE_VEND2_MAC_AUTO_SW		BIT(9)
1309
1310/* MDIO mask values */
1311#define XGBE_AN_CL73_INT_CMPLT		BIT(0)
1312#define XGBE_AN_CL73_INC_LINK		BIT(1)
1313#define XGBE_AN_CL73_PG_RCV		BIT(2)
1314#define XGBE_AN_CL73_INT_MASK		0x07
1315
1316#define XGBE_XNP_MCF_NULL_MESSAGE	0x001
1317#define XGBE_XNP_ACK_PROCESSED		BIT(12)
1318#define XGBE_XNP_MP_FORMATTED		BIT(13)
1319#define XGBE_XNP_NP_EXCHANGE		BIT(15)
1320
1321#define XGBE_KR_TRAINING_START		BIT(0)
1322#define XGBE_KR_TRAINING_ENABLE		BIT(1)
1323
1324#define XGBE_PCS_CL37_BP		BIT(12)
1325#define XGBE_PCS_PSEQ_STATE_MASK	0x1c
1326#define XGBE_PCS_PSEQ_STATE_POWER_GOOD	0x10
1327
1328#define XGBE_AN_CL37_INT_CMPLT		BIT(0)
1329#define XGBE_AN_CL37_INT_MASK		0x01
1330
1331#define XGBE_AN_CL37_HD_MASK		0x40
1332#define XGBE_AN_CL37_FD_MASK		0x20
1333
1334#define XGBE_AN_CL37_PCS_MODE_MASK	0x06
1335#define XGBE_AN_CL37_PCS_MODE_BASEX	0x00
1336#define XGBE_AN_CL37_PCS_MODE_SGMII	0x04
1337#define XGBE_AN_CL37_TX_CONFIG_MASK	0x08
1338#define XGBE_AN_CL37_MII_CTRL_8BIT	0x0100
1339
1340#define XGBE_PMA_CDR_TRACK_EN_MASK	0x01
1341#define XGBE_PMA_CDR_TRACK_EN_OFF	0x00
1342#define XGBE_PMA_CDR_TRACK_EN_ON	0x01
1343
1344#define XGBE_PMA_RX_RST_0_MASK		BIT(4)
1345#define XGBE_PMA_RX_RST_0_RESET_ON	0x10
1346#define XGBE_PMA_RX_RST_0_RESET_OFF	0x00
1347
1348#define XGBE_PMA_RX_SIG_DET_0_MASK	BIT(4)
1349#define XGBE_PMA_RX_SIG_DET_0_ENABLE	BIT(4)
1350#define XGBE_PMA_RX_SIG_DET_0_DISABLE	0x0000
1351
1352#define XGBE_PMA_RX_VALID_0_MASK	BIT(12)
1353#define XGBE_PMA_RX_VALID_0_ENABLE	BIT(12)
1354#define XGBE_PMA_RX_VALID_0_DISABLE	0x0000
1355
1356#define XGBE_PMA_RX_AD_REQ_MASK		BIT(12)
1357#define XGBE_PMA_RX_AD_REQ_ENABLE	BIT(12)
1358#define XGBE_PMA_RX_AD_REQ_DISABLE	0x0000
1359
1360#define XGBE_PMA_RX_ADPT_ACK_MASK	BIT(12)
1361#define XGBE_PMA_RX_ADPT_ACK		BIT(12)
1362
1363#define XGBE_PMA_CFF_UPDTM1_VLD		BIT(8)
1364#define XGBE_PMA_CFF_UPDT0_VLD		BIT(9)
1365#define XGBE_PMA_CFF_UPDT1_VLD		BIT(10)
1366#define XGBE_PMA_CFF_UPDT_MASK		(XGBE_PMA_CFF_UPDTM1_VLD |\
1367					 XGBE_PMA_CFF_UPDT0_VLD | \
1368					 XGBE_PMA_CFF_UPDT1_VLD)
1369
1370#define XGBE_PMA_PLL_CTRL_MASK		BIT(15)
1371#define XGBE_PMA_PLL_CTRL_ENABLE	BIT(15)
1372#define XGBE_PMA_PLL_CTRL_DISABLE	0x0000
1373
1374/* Bit setting and getting macros
1375 *  The get macro will extract the current bit field value from within
1376 *  the variable
1377 *
1378 *  The set macro will clear the current bit field value within the
1379 *  variable and then set the bit field of the variable to the
1380 *  specified value
1381 */
1382#define GET_BITS(_var, _index, _width)					\
1383	(((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1384
1385#define SET_BITS(_var, _index, _width, _val)				\
1386do {									\
1387	(_var) &= ~(((0x1 << (_width)) - 1) << (_index));		\
1388	(_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index));	\
1389} while (0)
1390
1391#define GET_BITS_LE(_var, _index, _width)				\
1392	((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1393
1394#define SET_BITS_LE(_var, _index, _width, _val)				\
1395do {									\
1396	(_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index)));	\
1397	(_var) |= cpu_to_le32((((_val) &				\
1398			      ((0x1 << (_width)) - 1)) << (_index)));	\
1399} while (0)
1400
1401/* Bit setting and getting macros based on register fields
1402 *  The get macro uses the bit field definitions formed using the input
1403 *  names to extract the current bit field value from within the
1404 *  variable
1405 *
1406 *  The set macro uses the bit field definitions formed using the input
1407 *  names to set the bit field of the variable to the specified value
1408 */
1409#define XGMAC_GET_BITS(_var, _prefix, _field)				\
1410	GET_BITS((_var),						\
1411		 _prefix##_##_field##_INDEX,				\
1412		 _prefix##_##_field##_WIDTH)
1413
1414#define XGMAC_SET_BITS(_var, _prefix, _field, _val)			\
1415	SET_BITS((_var),						\
1416		 _prefix##_##_field##_INDEX,				\
1417		 _prefix##_##_field##_WIDTH, (_val))
1418
1419#define XGMAC_GET_BITS_LE(_var, _prefix, _field)			\
1420	GET_BITS_LE((_var),						\
1421		 _prefix##_##_field##_INDEX,				\
1422		 _prefix##_##_field##_WIDTH)
1423
1424#define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val)			\
1425	SET_BITS_LE((_var),						\
1426		 _prefix##_##_field##_INDEX,				\
1427		 _prefix##_##_field##_WIDTH, (_val))
1428
1429/* Macros for reading or writing registers
1430 *  The ioread macros will get bit fields or full values using the
1431 *  register definitions formed using the input names
1432 *
1433 *  The iowrite macros will set bit fields or full values using the
1434 *  register definitions formed using the input names
1435 */
1436#define XGMAC_IOREAD(_pdata, _reg)					\
1437	ioread32((_pdata)->xgmac_regs + _reg)
1438
1439#define XGMAC_IOREAD_BITS(_pdata, _reg, _field)				\
1440	GET_BITS(XGMAC_IOREAD((_pdata), _reg),				\
1441		 _reg##_##_field##_INDEX,				\
1442		 _reg##_##_field##_WIDTH)
1443
1444#define XGMAC_IOWRITE(_pdata, _reg, _val)				\
1445	iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1446
1447#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val)			\
1448do {									\
1449	u32 reg_val = XGMAC_IOREAD((_pdata), _reg);			\
1450	SET_BITS(reg_val,						\
1451		 _reg##_##_field##_INDEX,				\
1452		 _reg##_##_field##_WIDTH, (_val));			\
1453	XGMAC_IOWRITE((_pdata), _reg, reg_val);				\
1454} while (0)
1455
1456/* Macros for reading or writing MTL queue or traffic class registers
1457 *  Similar to the standard read and write macros except that the
1458 *  base register value is calculated by the queue or traffic class number
1459 */
1460#define XGMAC_MTL_IOREAD(_pdata, _n, _reg)				\
1461	ioread32((_pdata)->xgmac_regs +					\
1462		 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
1463
1464#define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field)			\
1465	GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg),		\
1466		 _reg##_##_field##_INDEX,				\
1467		 _reg##_##_field##_WIDTH)
1468
1469#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val)			\
1470	iowrite32((_val), (_pdata)->xgmac_regs +			\
1471		  MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
1472
1473#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val)		\
1474do {									\
1475	u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg);		\
1476	SET_BITS(reg_val,						\
1477		 _reg##_##_field##_INDEX,				\
1478		 _reg##_##_field##_WIDTH, (_val));			\
1479	XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val);		\
1480} while (0)
1481
1482/* Macros for reading or writing DMA channel registers
1483 *  Similar to the standard read and write macros except that the
1484 *  base register value is obtained from the ring
1485 */
1486#define XGMAC_DMA_IOREAD(_channel, _reg)				\
1487	ioread32((_channel)->dma_regs + _reg)
1488
1489#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field)			\
1490	GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg),			\
1491		 _reg##_##_field##_INDEX,				\
1492		 _reg##_##_field##_WIDTH)
1493
1494#define XGMAC_DMA_IOWRITE(_channel, _reg, _val)				\
1495	iowrite32((_val), (_channel)->dma_regs + _reg)
1496
1497#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val)		\
1498do {									\
1499	u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg);		\
1500	SET_BITS(reg_val,						\
1501		 _reg##_##_field##_INDEX,				\
1502		 _reg##_##_field##_WIDTH, (_val));			\
1503	XGMAC_DMA_IOWRITE((_channel), _reg, reg_val);			\
1504} while (0)
1505
1506/* Macros for building, reading or writing register values or bits
1507 * within the register values of XPCS registers.
1508 */
1509#define XPCS_GET_BITS(_var, _prefix, _field)				\
1510	GET_BITS((_var),                                                \
1511		 _prefix##_##_field##_INDEX,                            \
1512		 _prefix##_##_field##_WIDTH)
1513
1514#define XPCS_SET_BITS(_var, _prefix, _field, _val)                      \
1515	SET_BITS((_var),                                                \
1516		 _prefix##_##_field##_INDEX,                            \
1517		 _prefix##_##_field##_WIDTH, (_val))
1518
1519#define XPCS32_IOWRITE(_pdata, _off, _val)				\
1520	iowrite32(_val, (_pdata)->xpcs_regs + (_off))
1521
1522#define XPCS32_IOREAD(_pdata, _off)					\
1523	ioread32((_pdata)->xpcs_regs + (_off))
1524
1525#define XPCS16_IOWRITE(_pdata, _off, _val)				\
1526	iowrite16(_val, (_pdata)->xpcs_regs + (_off))
1527
1528#define XPCS16_IOREAD(_pdata, _off)					\
1529	ioread16((_pdata)->xpcs_regs + (_off))
1530
1531/* Macros for building, reading or writing register values or bits
1532 * within the register values of SerDes integration registers.
1533 */
1534#define XSIR_GET_BITS(_var, _prefix, _field)                            \
1535	GET_BITS((_var),                                                \
1536		 _prefix##_##_field##_INDEX,                            \
1537		 _prefix##_##_field##_WIDTH)
1538
1539#define XSIR_SET_BITS(_var, _prefix, _field, _val)                      \
1540	SET_BITS((_var),                                                \
1541		 _prefix##_##_field##_INDEX,                            \
1542		 _prefix##_##_field##_WIDTH, (_val))
1543
1544#define XSIR0_IOREAD(_pdata, _reg)					\
1545	ioread16((_pdata)->sir0_regs + _reg)
1546
1547#define XSIR0_IOREAD_BITS(_pdata, _reg, _field)				\
1548	GET_BITS(XSIR0_IOREAD((_pdata), _reg),				\
1549		 _reg##_##_field##_INDEX,				\
1550		 _reg##_##_field##_WIDTH)
1551
1552#define XSIR0_IOWRITE(_pdata, _reg, _val)				\
1553	iowrite16((_val), (_pdata)->sir0_regs + _reg)
1554
1555#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val)			\
1556do {									\
1557	u16 reg_val = XSIR0_IOREAD((_pdata), _reg);			\
1558	SET_BITS(reg_val,						\
1559		 _reg##_##_field##_INDEX,				\
1560		 _reg##_##_field##_WIDTH, (_val));			\
1561	XSIR0_IOWRITE((_pdata), _reg, reg_val);				\
1562} while (0)
1563
1564#define XSIR1_IOREAD(_pdata, _reg)					\
1565	ioread16((_pdata)->sir1_regs + _reg)
1566
1567#define XSIR1_IOREAD_BITS(_pdata, _reg, _field)				\
1568	GET_BITS(XSIR1_IOREAD((_pdata), _reg),				\
1569		 _reg##_##_field##_INDEX,				\
1570		 _reg##_##_field##_WIDTH)
1571
1572#define XSIR1_IOWRITE(_pdata, _reg, _val)				\
1573	iowrite16((_val), (_pdata)->sir1_regs + _reg)
1574
1575#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val)			\
1576do {									\
1577	u16 reg_val = XSIR1_IOREAD((_pdata), _reg);			\
1578	SET_BITS(reg_val,						\
1579		 _reg##_##_field##_INDEX,				\
1580		 _reg##_##_field##_WIDTH, (_val));			\
1581	XSIR1_IOWRITE((_pdata), _reg, reg_val);				\
1582} while (0)
1583
1584/* Macros for building, reading or writing register values or bits
1585 * within the register values of SerDes RxTx registers.
1586 */
1587#define XRXTX_IOREAD(_pdata, _reg)					\
1588	ioread16((_pdata)->rxtx_regs + _reg)
1589
1590#define XRXTX_IOREAD_BITS(_pdata, _reg, _field)				\
1591	GET_BITS(XRXTX_IOREAD((_pdata), _reg),				\
1592		 _reg##_##_field##_INDEX,				\
1593		 _reg##_##_field##_WIDTH)
1594
1595#define XRXTX_IOWRITE(_pdata, _reg, _val)				\
1596	iowrite16((_val), (_pdata)->rxtx_regs + _reg)
1597
1598#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val)			\
1599do {									\
1600	u16 reg_val = XRXTX_IOREAD((_pdata), _reg);			\
1601	SET_BITS(reg_val,						\
1602		 _reg##_##_field##_INDEX,				\
1603		 _reg##_##_field##_WIDTH, (_val));			\
1604	XRXTX_IOWRITE((_pdata), _reg, reg_val);				\
1605} while (0)
1606
1607/* Macros for building, reading or writing register values or bits
1608 * within the register values of MAC Control registers.
1609 */
1610#define XP_GET_BITS(_var, _prefix, _field)				\
1611	GET_BITS((_var),						\
1612		 _prefix##_##_field##_INDEX,				\
1613		 _prefix##_##_field##_WIDTH)
1614
1615#define XP_SET_BITS(_var, _prefix, _field, _val)			\
1616	SET_BITS((_var),						\
1617		 _prefix##_##_field##_INDEX,				\
1618		 _prefix##_##_field##_WIDTH, (_val))
1619
1620#define XP_IOREAD(_pdata, _reg)						\
1621	ioread32((_pdata)->xprop_regs + (_reg))
1622
1623#define XP_IOREAD_BITS(_pdata, _reg, _field)				\
1624	GET_BITS(XP_IOREAD((_pdata), (_reg)),				\
1625		 _reg##_##_field##_INDEX,				\
1626		 _reg##_##_field##_WIDTH)
1627
1628#define XP_IOWRITE(_pdata, _reg, _val)					\
1629	iowrite32((_val), (_pdata)->xprop_regs + (_reg))
1630
1631#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val)			\
1632do {									\
1633	u32 reg_val = XP_IOREAD((_pdata), (_reg));			\
1634	SET_BITS(reg_val,						\
1635		 _reg##_##_field##_INDEX,				\
1636		 _reg##_##_field##_WIDTH, (_val));			\
1637	XP_IOWRITE((_pdata), (_reg), reg_val);				\
1638} while (0)
1639
1640/* Macros for building, reading or writing register values or bits
1641 * within the register values of I2C Control registers.
1642 */
1643#define XI2C_GET_BITS(_var, _prefix, _field)				\
1644	GET_BITS((_var),						\
1645		 _prefix##_##_field##_INDEX,				\
1646		 _prefix##_##_field##_WIDTH)
1647
1648#define XI2C_SET_BITS(_var, _prefix, _field, _val)			\
1649	SET_BITS((_var),						\
1650		 _prefix##_##_field##_INDEX,				\
1651		 _prefix##_##_field##_WIDTH, (_val))
1652
1653#define XI2C_IOREAD(_pdata, _reg)					\
1654	ioread32((_pdata)->xi2c_regs + (_reg))
1655
1656#define XI2C_IOREAD_BITS(_pdata, _reg, _field)				\
1657	GET_BITS(XI2C_IOREAD((_pdata), (_reg)),				\
1658		 _reg##_##_field##_INDEX,				\
1659		 _reg##_##_field##_WIDTH)
1660
1661#define XI2C_IOWRITE(_pdata, _reg, _val)				\
1662	iowrite32((_val), (_pdata)->xi2c_regs + (_reg))
1663
1664#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val)			\
1665do {									\
1666	u32 reg_val = XI2C_IOREAD((_pdata), (_reg));			\
1667	SET_BITS(reg_val,						\
1668		 _reg##_##_field##_INDEX,				\
1669		 _reg##_##_field##_WIDTH, (_val));			\
1670	XI2C_IOWRITE((_pdata), (_reg), reg_val);			\
1671} while (0)
1672
1673/* Macros for building, reading or writing register values or bits
1674 * using MDIO.
1675 */
1676
1677#define XGBE_ADDR_C45 BIT(30)
1678
1679#define XMDIO_READ(_pdata, _mmd, _reg)					\
1680	((_pdata)->hw_if.read_mmd_regs((_pdata), 0,			\
1681		XGBE_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))
1682
1683#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask)			\
1684	(XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1685
1686#define XMDIO_WRITE(_pdata, _mmd, _reg, _val)				\
1687	((_pdata)->hw_if.write_mmd_regs((_pdata), 0,			\
1688		XGBE_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
1689
1690#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val)		\
1691do {									\
1692	u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg);			\
1693	mmd_val &= ~_mask;						\
1694	mmd_val |= (_val);						\
1695	XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val);			\
1696} while (0)
1697
1698#endif