ena_regs_defs.h

  1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
  2/*
  3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
  4 */
  5#ifndef _ENA_REGS_H_
  6#define _ENA_REGS_H_
  7
  8enum ena_regs_reset_reason_types {
  9	ENA_REGS_RESET_NORMAL                       = 0,
 10	ENA_REGS_RESET_KEEP_ALIVE_TO                = 1,
 11	ENA_REGS_RESET_ADMIN_TO                     = 2,
 12	ENA_REGS_RESET_MISS_TX_CMPL                 = 3,
 13	ENA_REGS_RESET_INV_RX_REQ_ID                = 4,
 14	ENA_REGS_RESET_INV_TX_REQ_ID                = 5,
 15	ENA_REGS_RESET_TOO_MANY_RX_DESCS            = 6,
 16	ENA_REGS_RESET_INIT_ERR                     = 7,
 17	ENA_REGS_RESET_DRIVER_INVALID_STATE         = 8,
 18	ENA_REGS_RESET_OS_TRIGGER                   = 9,
 19	ENA_REGS_RESET_OS_NETDEV_WD                 = 10,
 20	ENA_REGS_RESET_SHUTDOWN                     = 11,
 21	ENA_REGS_RESET_USER_TRIGGER                 = 12,
 22	ENA_REGS_RESET_GENERIC                      = 13,
 23	ENA_REGS_RESET_MISS_INTERRUPT               = 14,
 24	ENA_REGS_RESET_SUSPECTED_POLL_STARVATION    = 15,
 25	ENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED	    = 16,
 26};
 27
 28/* ena_registers offsets */
 29
 30/* 0 base */
 31#define ENA_REGS_VERSION_OFF                                0x0
 32#define ENA_REGS_CONTROLLER_VERSION_OFF                     0x4
 33#define ENA_REGS_CAPS_OFF                                   0x8
 34#define ENA_REGS_CAPS_EXT_OFF                               0xc
 35#define ENA_REGS_AQ_BASE_LO_OFF                             0x10
 36#define ENA_REGS_AQ_BASE_HI_OFF                             0x14
 37#define ENA_REGS_AQ_CAPS_OFF                                0x18
 38#define ENA_REGS_ACQ_BASE_LO_OFF                            0x20
 39#define ENA_REGS_ACQ_BASE_HI_OFF                            0x24
 40#define ENA_REGS_ACQ_CAPS_OFF                               0x28
 41#define ENA_REGS_AQ_DB_OFF                                  0x2c
 42#define ENA_REGS_ACQ_TAIL_OFF                               0x30
 43#define ENA_REGS_AENQ_CAPS_OFF                              0x34
 44#define ENA_REGS_AENQ_BASE_LO_OFF                           0x38
 45#define ENA_REGS_AENQ_BASE_HI_OFF                           0x3c
 46#define ENA_REGS_AENQ_HEAD_DB_OFF                           0x40
 47#define ENA_REGS_AENQ_TAIL_OFF                              0x44
 48#define ENA_REGS_INTR_MASK_OFF                              0x4c
 49#define ENA_REGS_DEV_CTL_OFF                                0x54
 50#define ENA_REGS_DEV_STS_OFF                                0x58
 51#define ENA_REGS_MMIO_REG_READ_OFF                          0x5c
 52#define ENA_REGS_MMIO_RESP_LO_OFF                           0x60
 53#define ENA_REGS_MMIO_RESP_HI_OFF                           0x64
 54#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF                   0x68
 55
 56/* phc_registers offsets */
 57
 58/* 100 base */
 59#define ENA_REGS_PHC_DB_OFF                                 0x100
 60
 61/* version register */
 62#define ENA_REGS_VERSION_MINOR_VERSION_MASK                 0xff
 63#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT                8
 64#define ENA_REGS_VERSION_MAJOR_VERSION_MASK                 0xff00
 65
 66/* controller_version register */
 67#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK   0xff
 68#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT     8
 69#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK      0xff00
 70#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT     16
 71#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK      0xff0000
 72#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT           24
 73#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK            0xff000000
 74
 75/* caps register */
 76#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK        0x1
 77#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT                   1
 78#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK                    0x3e
 79#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT                  8
 80#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK                   0xff00
 81#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT                    16
 82#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK                     0xf0000
 83
 84/* aq_caps register */
 85#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK                      0xffff
 86#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT                16
 87#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK                 0xffff0000
 88
 89/* acq_caps register */
 90#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK                    0xffff
 91#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT              16
 92#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK               0xffff0000
 93
 94/* aenq_caps register */
 95#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK                  0xffff
 96#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT            16
 97#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK             0xffff0000
 98
 99/* dev_ctl register */
100#define ENA_REGS_DEV_CTL_DEV_RESET_MASK                     0x1
101#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT                   1
102#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK                    0x2
103#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT                    2
104#define ENA_REGS_DEV_CTL_QUIESCENT_MASK                     0x4
105#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT                    3
106#define ENA_REGS_DEV_CTL_IO_RESUME_MASK                     0x8
107#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT                 28
108#define ENA_REGS_DEV_CTL_RESET_REASON_MASK                  0xf0000000
109
110/* dev_sts register */
111#define ENA_REGS_DEV_STS_READY_MASK                         0x1
112#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT       1
113#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK        0x2
114#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT          2
115#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK           0x4
116#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT            3
117#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK             0x8
118#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT               4
119#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK                0x10
120#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT                  5
121#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK                   0x20
122#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT  6
123#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK   0x40
124#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT     7
125#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK      0x80
126
127/* mmio_reg_read register */
128#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK                  0xffff
129#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT                16
130#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK                 0xffff0000
131
132/* rss_ind_entry_update register */
133#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK            0xffff
134#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT          16
135#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK           0xffff0000
136
137/* phc_db_req_id register */
138#define ENA_REGS_PHC_DB_REQ_ID_MASK                         0xffff
139
140#endif /* _ENA_REGS_H_ */