FILE
ena_com.c
File preview with syntax highlighting.
linux-6.19.14/drivers/net/ethernet/amazon/ena/ena_com.c
1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2/* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6#include "ena_com.h" 7 8/*****************************************************************************/ 9/*****************************************************************************/ 10 11/* Timeout in micro-sec */ 12#define ADMIN_CMD_TIMEOUT_US (3000000) 13 14#define ENA_ASYNC_QUEUE_DEPTH 16 15#define ENA_ADMIN_QUEUE_DEPTH 32 16 17 18#define ENA_CTRL_MAJOR 0 19#define ENA_CTRL_MINOR 0 20#define ENA_CTRL_SUB_MINOR 1 21 22#define MIN_ENA_CTRL_VER \ 23 (((ENA_CTRL_MAJOR) << \ 24 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \ 25 ((ENA_CTRL_MINOR) << \ 26 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \ 27 (ENA_CTRL_SUB_MINOR)) 28 29#define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x))) 30#define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32)) 31 32#define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF 33 34#define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4 35 36#define ENA_REGS_ADMIN_INTR_MASK 1 37 38#define ENA_MAX_BACKOFF_DELAY_EXP 16U 39 40#define ENA_MIN_ADMIN_POLL_US 100 41 42#define ENA_MAX_ADMIN_POLL_US 5000 43 44/* PHC definitions */ 45#define ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC 10 46#define ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC 1000 47#define ENA_PHC_REQ_ID_OFFSET 0xDEAD 48#define ENA_PHC_ERROR_FLAGS (ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP) 49 50/*****************************************************************************/ 51/*****************************************************************************/ 52/*****************************************************************************/ 53 54enum ena_cmd_status { 55 ENA_CMD_SUBMITTED, 56 ENA_CMD_COMPLETED, 57 /* Abort - canceled by the driver */ 58 ENA_CMD_ABORTED, 59}; 60 61struct ena_comp_ctx { 62 struct completion wait_event; 63 struct ena_admin_acq_entry *user_cqe; 64 u32 comp_size; 65 enum ena_cmd_status status; 66 /* status from the device */ 67 u8 comp_status; 68 u8 cmd_opcode; 69 bool occupied; 70}; 71 72struct ena_com_stats_ctx { 73 struct ena_admin_aq_get_stats_cmd get_cmd; 74 struct ena_admin_acq_get_stats_resp get_resp; 75}; 76 77static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, 78 struct ena_common_mem_addr *ena_addr, 79 dma_addr_t addr) 80{ 81 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { 82 netdev_err(ena_dev->net_device, 83 "DMA address has more bits that the device supports\n"); 84 return -EINVAL; 85 } 86 87 ena_addr->mem_addr_low = lower_32_bits(addr); 88 ena_addr->mem_addr_high = (u16)upper_32_bits(addr); 89 90 return 0; 91} 92 93static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) 94{ 95 struct ena_com_dev *ena_dev = admin_queue->ena_dev; 96 struct ena_com_admin_sq *sq = &admin_queue->sq; 97 u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 98 99 sq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &sq->dma_addr, GFP_KERNEL); 100 101 if (!sq->entries) { 102 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 103 return -ENOMEM; 104 } 105 106 sq->head = 0; 107 sq->tail = 0; 108 sq->phase = 1; 109 110 sq->db_addr = NULL; 111 112 return 0; 113} 114 115static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) 116{ 117 struct ena_com_dev *ena_dev = admin_queue->ena_dev; 118 struct ena_com_admin_cq *cq = &admin_queue->cq; 119 u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 120 121 cq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &cq->dma_addr, GFP_KERNEL); 122 123 if (!cq->entries) { 124 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 125 return -ENOMEM; 126 } 127 128 cq->head = 0; 129 cq->phase = 1; 130 131 return 0; 132} 133 134static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, 135 struct ena_aenq_handlers *aenq_handlers) 136{ 137 struct ena_com_aenq *aenq = &ena_dev->aenq; 138 u32 addr_low, addr_high, aenq_caps; 139 u16 size; 140 141 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; 142 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); 143 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL); 144 145 if (!aenq->entries) { 146 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 147 return -ENOMEM; 148 } 149 150 aenq->head = aenq->q_depth; 151 aenq->phase = 1; 152 153 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); 154 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); 155 156 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); 157 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); 158 159 aenq_caps = 0; 160 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; 161 aenq_caps |= 162 (sizeof(struct ena_admin_aenq_entry) << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & 163 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; 164 writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); 165 166 if (unlikely(!aenq_handlers)) { 167 netdev_err(ena_dev->net_device, "AENQ handlers pointer is NULL\n"); 168 return -EINVAL; 169 } 170 171 aenq->aenq_handlers = aenq_handlers; 172 173 return 0; 174} 175 176static void comp_ctxt_release(struct ena_com_admin_queue *queue, 177 struct ena_comp_ctx *comp_ctx) 178{ 179 comp_ctx->occupied = false; 180 atomic_dec(&queue->outstanding_cmds); 181} 182 183static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue, 184 u16 command_id, bool capture) 185{ 186 if (unlikely(command_id >= admin_queue->q_depth)) { 187 netdev_err(admin_queue->ena_dev->net_device, 188 "Command id is larger than the queue size. cmd_id: %u queue size %d\n", 189 command_id, admin_queue->q_depth); 190 return NULL; 191 } 192 193 if (unlikely(!admin_queue->comp_ctx)) { 194 netdev_err(admin_queue->ena_dev->net_device, "Completion context is NULL\n"); 195 return NULL; 196 } 197 198 if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) { 199 netdev_err(admin_queue->ena_dev->net_device, "Completion context is occupied\n"); 200 return NULL; 201 } 202 203 if (capture) { 204 atomic_inc(&admin_queue->outstanding_cmds); 205 admin_queue->comp_ctx[command_id].occupied = true; 206 } 207 208 return &admin_queue->comp_ctx[command_id]; 209} 210 211static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 212 struct ena_admin_aq_entry *cmd, 213 size_t cmd_size_in_bytes, 214 struct ena_admin_acq_entry *comp, 215 size_t comp_size_in_bytes) 216{ 217 struct ena_comp_ctx *comp_ctx; 218 u16 tail_masked, cmd_id; 219 u16 queue_size_mask; 220 u16 cnt; 221 222 queue_size_mask = admin_queue->q_depth - 1; 223 224 tail_masked = admin_queue->sq.tail & queue_size_mask; 225 226 /* In case of queue FULL */ 227 cnt = (u16)atomic_read(&admin_queue->outstanding_cmds); 228 if (cnt >= admin_queue->q_depth) { 229 netdev_dbg(admin_queue->ena_dev->net_device, "Admin queue is full.\n"); 230 admin_queue->stats.out_of_space++; 231 return ERR_PTR(-ENOSPC); 232 } 233 234 cmd_id = admin_queue->curr_cmd_id; 235 236 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase & 237 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 238 239 cmd->aq_common_descriptor.command_id |= cmd_id & 240 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 241 242 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true); 243 if (unlikely(!comp_ctx)) 244 return ERR_PTR(-EINVAL); 245 246 comp_ctx->status = ENA_CMD_SUBMITTED; 247 comp_ctx->comp_size = (u32)comp_size_in_bytes; 248 comp_ctx->user_cqe = comp; 249 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 250 251 reinit_completion(&comp_ctx->wait_event); 252 253 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes); 254 255 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) & 256 queue_size_mask; 257 258 admin_queue->sq.tail++; 259 admin_queue->stats.submitted_cmd++; 260 261 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0)) 262 admin_queue->sq.phase = !admin_queue->sq.phase; 263 264 writel(admin_queue->sq.tail, admin_queue->sq.db_addr); 265 266 return comp_ctx; 267} 268 269static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue) 270{ 271 struct ena_com_dev *ena_dev = admin_queue->ena_dev; 272 size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx); 273 struct ena_comp_ctx *comp_ctx; 274 u16 i; 275 276 admin_queue->comp_ctx = devm_kzalloc(admin_queue->q_dmadev, size, GFP_KERNEL); 277 if (unlikely(!admin_queue->comp_ctx)) { 278 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 279 return -ENOMEM; 280 } 281 282 for (i = 0; i < admin_queue->q_depth; i++) { 283 comp_ctx = get_comp_ctxt(admin_queue, i, false); 284 if (comp_ctx) 285 init_completion(&comp_ctx->wait_event); 286 } 287 288 return 0; 289} 290 291static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 292 struct ena_admin_aq_entry *cmd, 293 size_t cmd_size_in_bytes, 294 struct ena_admin_acq_entry *comp, 295 size_t comp_size_in_bytes) 296{ 297 unsigned long flags = 0; 298 struct ena_comp_ctx *comp_ctx; 299 300 spin_lock_irqsave(&admin_queue->q_lock, flags); 301 if (unlikely(!admin_queue->running_state)) { 302 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 303 return ERR_PTR(-ENODEV); 304 } 305 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd, 306 cmd_size_in_bytes, 307 comp, 308 comp_size_in_bytes); 309 if (IS_ERR(comp_ctx)) 310 admin_queue->running_state = false; 311 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 312 313 return comp_ctx; 314} 315 316static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 317 struct ena_com_create_io_ctx *ctx, 318 struct ena_com_io_sq *io_sq) 319{ 320 size_t size; 321 322 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr)); 323 324 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits; 325 io_sq->desc_entry_size = 326 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 327 sizeof(struct ena_eth_io_tx_desc) : 328 sizeof(struct ena_eth_io_rx_desc); 329 330 size = io_sq->desc_entry_size * io_sq->q_depth; 331 332 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 333 io_sq->desc_addr.virt_addr = 334 dma_alloc_coherent(ena_dev->dmadev, size, &io_sq->desc_addr.phys_addr, 335 GFP_KERNEL); 336 if (!io_sq->desc_addr.virt_addr) { 337 io_sq->desc_addr.virt_addr = 338 dma_alloc_coherent(ena_dev->dmadev, size, 339 &io_sq->desc_addr.phys_addr, GFP_KERNEL); 340 } 341 342 if (!io_sq->desc_addr.virt_addr) { 343 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 344 return -ENOMEM; 345 } 346 } 347 348 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 349 /* Allocate bounce buffers */ 350 io_sq->bounce_buf_ctrl.buffer_size = 351 ena_dev->llq_info.desc_list_entry_size; 352 io_sq->bounce_buf_ctrl.buffers_num = 353 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT; 354 io_sq->bounce_buf_ctrl.next_to_use = 0; 355 356 size = (size_t)io_sq->bounce_buf_ctrl.buffer_size * 357 io_sq->bounce_buf_ctrl.buffers_num; 358 359 io_sq->bounce_buf_ctrl.base_buffer = devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 360 if (!io_sq->bounce_buf_ctrl.base_buffer) 361 io_sq->bounce_buf_ctrl.base_buffer = 362 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 363 364 if (!io_sq->bounce_buf_ctrl.base_buffer) { 365 netdev_err(ena_dev->net_device, "Bounce buffer memory allocation failed\n"); 366 return -ENOMEM; 367 } 368 369 memcpy(&io_sq->llq_info, &ena_dev->llq_info, 370 sizeof(io_sq->llq_info)); 371 372 /* Initiate the first bounce buffer */ 373 io_sq->llq_buf_ctrl.curr_bounce_buf = 374 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl); 375 memset(io_sq->llq_buf_ctrl.curr_bounce_buf, 376 0x0, io_sq->llq_info.desc_list_entry_size); 377 io_sq->llq_buf_ctrl.descs_left_in_line = 378 io_sq->llq_info.descs_num_before_header; 379 io_sq->disable_meta_caching = 380 io_sq->llq_info.disable_meta_caching; 381 382 if (io_sq->llq_info.max_entries_in_tx_burst > 0) 383 io_sq->entries_in_tx_burst_left = 384 io_sq->llq_info.max_entries_in_tx_burst; 385 } 386 387 io_sq->tail = 0; 388 io_sq->next_to_comp = 0; 389 io_sq->phase = 1; 390 391 return 0; 392} 393 394static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, 395 struct ena_com_create_io_ctx *ctx, 396 struct ena_com_io_cq *io_cq) 397{ 398 size_t size; 399 400 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr)); 401 402 /* Use the basic completion descriptor for Rx */ 403 io_cq->cdesc_entry_size_in_bytes = 404 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 405 sizeof(struct ena_eth_io_tx_cdesc) : 406 sizeof(struct ena_eth_io_rx_cdesc_base); 407 408 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 409 410 io_cq->cdesc_addr.virt_addr = 411 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr, GFP_KERNEL); 412 if (!io_cq->cdesc_addr.virt_addr) { 413 io_cq->cdesc_addr.virt_addr = 414 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr, 415 GFP_KERNEL); 416 } 417 418 if (!io_cq->cdesc_addr.virt_addr) { 419 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 420 return -ENOMEM; 421 } 422 423 io_cq->phase = 1; 424 io_cq->head = 0; 425 426 return 0; 427} 428 429static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, 430 struct ena_admin_acq_entry *cqe) 431{ 432 struct ena_comp_ctx *comp_ctx; 433 u16 cmd_id; 434 435 cmd_id = cqe->acq_common_descriptor.command & 436 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 437 438 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); 439 if (unlikely(!comp_ctx)) { 440 netdev_err(admin_queue->ena_dev->net_device, 441 "comp_ctx is NULL. Changing the admin queue running state\n"); 442 admin_queue->running_state = false; 443 return; 444 } 445 446 comp_ctx->status = ENA_CMD_COMPLETED; 447 comp_ctx->comp_status = cqe->acq_common_descriptor.status; 448 449 if (comp_ctx->user_cqe) 450 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); 451 452 if (!admin_queue->polling) 453 complete(&comp_ctx->wait_event); 454} 455 456static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue) 457{ 458 struct ena_admin_acq_entry *cqe = NULL; 459 u16 comp_num = 0; 460 u16 head_masked; 461 u8 phase; 462 463 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1); 464 phase = admin_queue->cq.phase; 465 466 cqe = &admin_queue->cq.entries[head_masked]; 467 468 /* Go over all the completions */ 469 while ((READ_ONCE(cqe->acq_common_descriptor.flags) & 470 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 471 /* Do not read the rest of the completion entry before the 472 * phase bit was validated 473 */ 474 dma_rmb(); 475 ena_com_handle_single_admin_completion(admin_queue, cqe); 476 477 head_masked++; 478 comp_num++; 479 if (unlikely(head_masked == admin_queue->q_depth)) { 480 head_masked = 0; 481 phase = !phase; 482 } 483 484 cqe = &admin_queue->cq.entries[head_masked]; 485 } 486 487 admin_queue->cq.head += comp_num; 488 admin_queue->cq.phase = phase; 489 admin_queue->sq.head += comp_num; 490 admin_queue->stats.completed_cmd += comp_num; 491} 492 493static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue, 494 u8 comp_status) 495{ 496 if (unlikely(comp_status != 0)) 497 netdev_err(admin_queue->ena_dev->net_device, "Admin command failed[%u]\n", 498 comp_status); 499 500 switch (comp_status) { 501 case ENA_ADMIN_SUCCESS: 502 return 0; 503 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 504 return -ENOMEM; 505 case ENA_ADMIN_UNSUPPORTED_OPCODE: 506 return -EOPNOTSUPP; 507 case ENA_ADMIN_BAD_OPCODE: 508 case ENA_ADMIN_MALFORMED_REQUEST: 509 case ENA_ADMIN_ILLEGAL_PARAMETER: 510 case ENA_ADMIN_UNKNOWN_ERROR: 511 return -EINVAL; 512 case ENA_ADMIN_RESOURCE_BUSY: 513 return -EAGAIN; 514 } 515 516 return -EINVAL; 517} 518 519static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us) 520{ 521 exp = min_t(u32, exp, ENA_MAX_BACKOFF_DELAY_EXP); 522 delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us); 523 delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US); 524 usleep_range(delay_us, 2 * delay_us); 525} 526 527static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx, 528 struct ena_com_admin_queue *admin_queue) 529{ 530 unsigned long flags = 0; 531 unsigned long timeout; 532 int ret; 533 u32 exp = 0; 534 535 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout); 536 537 while (1) { 538 spin_lock_irqsave(&admin_queue->q_lock, flags); 539 ena_com_handle_admin_completion(admin_queue); 540 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 541 542 if (comp_ctx->status != ENA_CMD_SUBMITTED) 543 break; 544 545 if (time_is_before_jiffies(timeout)) { 546 netdev_err(admin_queue->ena_dev->net_device, 547 "Wait for completion (polling) timeout\n"); 548 /* ENA didn't have any completion */ 549 spin_lock_irqsave(&admin_queue->q_lock, flags); 550 admin_queue->stats.no_completion++; 551 admin_queue->running_state = false; 552 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 553 554 ret = -ETIME; 555 goto err; 556 } 557 558 ena_delay_exponential_backoff_us(exp++, 559 admin_queue->ena_dev->ena_min_poll_delay_us); 560 } 561 562 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { 563 netdev_err(admin_queue->ena_dev->net_device, "Command was aborted\n"); 564 spin_lock_irqsave(&admin_queue->q_lock, flags); 565 admin_queue->stats.aborted_cmd++; 566 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 567 ret = -ENODEV; 568 goto err; 569 } 570 571 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", comp_ctx->status); 572 573 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); 574err: 575 comp_ctxt_release(admin_queue, comp_ctx); 576 return ret; 577} 578 579/* 580 * Set the LLQ configurations of the firmware 581 * 582 * The driver provides only the enabled feature values to the device, 583 * which in turn, checks if they are supported. 584 */ 585static int ena_com_set_llq(struct ena_com_dev *ena_dev) 586{ 587 struct ena_com_admin_queue *admin_queue; 588 struct ena_admin_set_feat_cmd cmd; 589 struct ena_admin_set_feat_resp resp; 590 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 591 int ret; 592 593 memset(&cmd, 0x0, sizeof(cmd)); 594 admin_queue = &ena_dev->admin_queue; 595 596 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 597 cmd.feat_common.feature_id = ENA_ADMIN_LLQ; 598 599 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl; 600 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl; 601 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header; 602 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl; 603 604 cmd.u.llq.accel_mode.u.set.enabled_flags = 605 BIT(ENA_ADMIN_DISABLE_META_CACHING) | 606 BIT(ENA_ADMIN_LIMIT_TX_BURST); 607 608 ret = ena_com_execute_admin_command(admin_queue, 609 (struct ena_admin_aq_entry *)&cmd, 610 sizeof(cmd), 611 (struct ena_admin_acq_entry *)&resp, 612 sizeof(resp)); 613 614 if (unlikely(ret)) 615 netdev_err(ena_dev->net_device, "Failed to set LLQ configurations: %d\n", ret); 616 617 return ret; 618} 619 620static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, 621 struct ena_admin_feature_llq_desc *llq_features, 622 struct ena_llq_configurations *llq_default_cfg) 623{ 624 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 625 struct ena_admin_accel_mode_get llq_accel_mode_get; 626 u16 supported_feat; 627 int rc; 628 629 memset(llq_info, 0, sizeof(*llq_info)); 630 631 supported_feat = llq_features->header_location_ctrl_supported; 632 633 if (likely(supported_feat & llq_default_cfg->llq_header_location)) { 634 llq_info->header_location_ctrl = 635 llq_default_cfg->llq_header_location; 636 } else { 637 netdev_err(ena_dev->net_device, 638 "Invalid header location control, supported: 0x%x\n", supported_feat); 639 return -EINVAL; 640 } 641 642 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) { 643 supported_feat = llq_features->descriptors_stride_ctrl_supported; 644 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) { 645 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl; 646 } else { 647 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) { 648 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 649 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) { 650 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY; 651 } else { 652 netdev_err(ena_dev->net_device, 653 "Invalid desc_stride_ctrl, supported: 0x%x\n", 654 supported_feat); 655 return -EINVAL; 656 } 657 658 netdev_err(ena_dev->net_device, 659 "Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 660 llq_default_cfg->llq_stride_ctrl, supported_feat, 661 llq_info->desc_stride_ctrl); 662 } 663 } else { 664 llq_info->desc_stride_ctrl = 0; 665 } 666 667 supported_feat = llq_features->entry_size_ctrl_supported; 668 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) { 669 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size; 670 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value; 671 } else { 672 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) { 673 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 674 llq_info->desc_list_entry_size = 128; 675 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) { 676 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B; 677 llq_info->desc_list_entry_size = 192; 678 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) { 679 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B; 680 llq_info->desc_list_entry_size = 256; 681 } else { 682 netdev_err(ena_dev->net_device, 683 "Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat); 684 return -EINVAL; 685 } 686 687 netdev_err(ena_dev->net_device, 688 "Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 689 llq_default_cfg->llq_ring_entry_size, supported_feat, 690 llq_info->desc_list_entry_size); 691 } 692 if (unlikely(llq_info->desc_list_entry_size & 0x7)) { 693 /* The desc list entry size should be whole multiply of 8 694 * This requirement comes from __iowrite64_copy() 695 */ 696 netdev_err(ena_dev->net_device, "Illegal entry size %d\n", 697 llq_info->desc_list_entry_size); 698 return -EINVAL; 699 } 700 701 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) 702 llq_info->descs_per_entry = llq_info->desc_list_entry_size / 703 sizeof(struct ena_eth_io_tx_desc); 704 else 705 llq_info->descs_per_entry = 1; 706 707 supported_feat = llq_features->desc_num_before_header_supported; 708 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) { 709 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header; 710 } else { 711 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) { 712 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 713 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) { 714 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1; 715 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) { 716 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4; 717 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) { 718 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8; 719 } else { 720 netdev_err(ena_dev->net_device, 721 "Invalid descs_num_before_header, supported: 0x%x\n", 722 supported_feat); 723 return -EINVAL; 724 } 725 726 netdev_err(ena_dev->net_device, 727 "Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 728 llq_default_cfg->llq_num_decs_before_header, supported_feat, 729 llq_info->descs_num_before_header); 730 } 731 /* Check for accelerated queue supported */ 732 llq_accel_mode_get = llq_features->accel_mode.u.get; 733 734 llq_info->disable_meta_caching = 735 !!(llq_accel_mode_get.supported_flags & 736 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 737 738 if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST)) 739 llq_info->max_entries_in_tx_burst = 740 llq_accel_mode_get.max_tx_burst_size / 741 llq_default_cfg->llq_ring_entry_size_value; 742 743 rc = ena_com_set_llq(ena_dev); 744 if (rc) 745 netdev_err(ena_dev->net_device, "Cannot set LLQ configuration: %d\n", rc); 746 747 return rc; 748} 749 750static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx, 751 struct ena_com_admin_queue *admin_queue) 752{ 753 unsigned long flags = 0; 754 int ret; 755 756 wait_for_completion_timeout(&comp_ctx->wait_event, 757 usecs_to_jiffies(admin_queue->completion_timeout)); 758 759 /* In case the command wasn't completed find out the root cause. 760 * There might be 2 kinds of errors 761 * 1) No completion (timeout reached) 762 * 2) There is completion but the device didn't get any msi-x interrupt. 763 */ 764 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) { 765 spin_lock_irqsave(&admin_queue->q_lock, flags); 766 ena_com_handle_admin_completion(admin_queue); 767 admin_queue->stats.no_completion++; 768 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 769 770 if (comp_ctx->status == ENA_CMD_COMPLETED) { 771 netdev_err(admin_queue->ena_dev->net_device, 772 "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d)\n", 773 comp_ctx->cmd_opcode); 774 } else { 775 netdev_err(admin_queue->ena_dev->net_device, 776 "The ena device didn't send a completion for the admin cmd %d status %d\n", 777 comp_ctx->cmd_opcode, comp_ctx->status); 778 } 779 admin_queue->running_state = false; 780 ret = -ETIME; 781 goto err; 782 } 783 784 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); 785err: 786 comp_ctxt_release(admin_queue, comp_ctx); 787 return ret; 788} 789 790/* This method read the hardware device register through posting writes 791 * and waiting for response 792 * On timeout the function will return ENA_MMIO_READ_TIMEOUT 793 */ 794static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) 795{ 796 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 797 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp = 798 mmio_read->read_resp; 799 u32 mmio_read_reg, ret, i; 800 unsigned long flags = 0; 801 u32 timeout = mmio_read->reg_read_to; 802 803 might_sleep(); 804 805 if (timeout == 0) 806 timeout = ENA_REG_READ_TIMEOUT; 807 808 /* If readless is disabled, perform regular read */ 809 if (!mmio_read->readless_supported) 810 return readl(ena_dev->reg_bar + offset); 811 812 spin_lock_irqsave(&mmio_read->lock, flags); 813 mmio_read->seq_num++; 814 815 read_resp->req_id = mmio_read->seq_num + 0xDEAD; 816 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & 817 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; 818 mmio_read_reg |= mmio_read->seq_num & 819 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; 820 821 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); 822 823 for (i = 0; i < timeout; i++) { 824 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num) 825 break; 826 827 udelay(1); 828 } 829 830 if (unlikely(i == timeout)) { 831 netdev_err(ena_dev->net_device, 832 "Reading reg failed for timeout. expected: req id[%u] offset[%u] actual: req id[%u] offset[%u]\n", 833 mmio_read->seq_num, offset, read_resp->req_id, read_resp->reg_off); 834 ret = ENA_MMIO_READ_TIMEOUT; 835 goto err; 836 } 837 838 if (read_resp->reg_off != offset) { 839 netdev_err(ena_dev->net_device, "Read failure: wrong offset provided\n"); 840 ret = ENA_MMIO_READ_TIMEOUT; 841 } else { 842 ret = read_resp->reg_val; 843 } 844err: 845 spin_unlock_irqrestore(&mmio_read->lock, flags); 846 847 return ret; 848} 849 850/* There are two types to wait for completion. 851 * Polling mode - wait until the completion is available. 852 * Async mode - wait on wait queue until the completion is ready 853 * (or the timeout expired). 854 * It is expected that the IRQ called ena_com_handle_admin_completion 855 * to mark the completions. 856 */ 857static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx, 858 struct ena_com_admin_queue *admin_queue) 859{ 860 if (admin_queue->polling) 861 return ena_com_wait_and_process_admin_cq_polling(comp_ctx, 862 admin_queue); 863 864 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx, 865 admin_queue); 866} 867 868static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, 869 struct ena_com_io_sq *io_sq) 870{ 871 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 872 struct ena_admin_aq_destroy_sq_cmd destroy_cmd; 873 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp; 874 u8 direction; 875 int ret; 876 877 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 878 879 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 880 direction = ENA_ADMIN_SQ_DIRECTION_TX; 881 else 882 direction = ENA_ADMIN_SQ_DIRECTION_RX; 883 884 destroy_cmd.sq.sq_identity |= (direction << 885 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & 886 ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 887 888 destroy_cmd.sq.sq_idx = io_sq->idx; 889 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; 890 891 ret = ena_com_execute_admin_command(admin_queue, 892 (struct ena_admin_aq_entry *)&destroy_cmd, 893 sizeof(destroy_cmd), 894 (struct ena_admin_acq_entry *)&destroy_resp, 895 sizeof(destroy_resp)); 896 897 if (unlikely(ret && (ret != -ENODEV))) 898 netdev_err(ena_dev->net_device, "Failed to destroy io sq error: %d\n", ret); 899 900 return ret; 901} 902 903static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, 904 struct ena_com_io_sq *io_sq, 905 struct ena_com_io_cq *io_cq) 906{ 907 size_t size; 908 909 if (io_cq->cdesc_addr.virt_addr) { 910 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 911 912 dma_free_coherent(ena_dev->dmadev, size, io_cq->cdesc_addr.virt_addr, 913 io_cq->cdesc_addr.phys_addr); 914 915 io_cq->cdesc_addr.virt_addr = NULL; 916 } 917 918 if (io_sq->desc_addr.virt_addr) { 919 size = io_sq->desc_entry_size * io_sq->q_depth; 920 921 dma_free_coherent(ena_dev->dmadev, size, io_sq->desc_addr.virt_addr, 922 io_sq->desc_addr.phys_addr); 923 924 io_sq->desc_addr.virt_addr = NULL; 925 } 926 927 if (io_sq->bounce_buf_ctrl.base_buffer) { 928 devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer); 929 io_sq->bounce_buf_ctrl.base_buffer = NULL; 930 } 931} 932 933static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, 934 u16 exp_state) 935{ 936 u32 val, exp = 0; 937 unsigned long timeout_stamp; 938 939 /* Convert timeout from resolution of 100ms to us resolution. */ 940 timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout); 941 942 while (1) { 943 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 944 945 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { 946 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n"); 947 return -ETIME; 948 } 949 950 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == 951 exp_state) 952 return 0; 953 954 if (time_is_before_jiffies(timeout_stamp)) 955 return -ETIME; 956 957 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); 958 } 959} 960 961static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, 962 enum ena_admin_aq_feature_id feature_id) 963{ 964 u32 feature_mask = 1 << feature_id; 965 966 /* Device attributes is always supported */ 967 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) && 968 !(ena_dev->supported_features & feature_mask)) 969 return false; 970 971 return true; 972} 973 974static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, 975 struct ena_admin_get_feat_resp *get_resp, 976 enum ena_admin_aq_feature_id feature_id, 977 dma_addr_t control_buf_dma_addr, 978 u32 control_buff_size, 979 u8 feature_ver) 980{ 981 struct ena_com_admin_queue *admin_queue; 982 struct ena_admin_get_feat_cmd get_cmd; 983 int ret; 984 985 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { 986 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", feature_id); 987 return -EOPNOTSUPP; 988 } 989 990 memset(&get_cmd, 0x0, sizeof(get_cmd)); 991 admin_queue = &ena_dev->admin_queue; 992 993 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE; 994 995 if (control_buff_size) 996 get_cmd.aq_common_descriptor.flags = 997 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 998 else 999 get_cmd.aq_common_descriptor.flags = 0; 1000 1001 ret = ena_com_mem_addr_set(ena_dev, 1002 &get_cmd.control_buffer.address, 1003 control_buf_dma_addr); 1004 if (unlikely(ret)) { 1005 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 1006 return ret; 1007 } 1008 1009 get_cmd.control_buffer.length = control_buff_size; 1010 get_cmd.feat_common.feature_version = feature_ver; 1011 get_cmd.feat_common.feature_id = feature_id; 1012 1013 ret = ena_com_execute_admin_command(admin_queue, 1014 (struct ena_admin_aq_entry *) 1015 &get_cmd, 1016 sizeof(get_cmd), 1017 (struct ena_admin_acq_entry *) 1018 get_resp, 1019 sizeof(*get_resp)); 1020 1021 if (unlikely(ret)) 1022 netdev_err(ena_dev->net_device, 1023 "Failed to submit get_feature command %d error: %d\n", feature_id, ret); 1024 1025 return ret; 1026} 1027 1028static int ena_com_get_feature(struct ena_com_dev *ena_dev, 1029 struct ena_admin_get_feat_resp *get_resp, 1030 enum ena_admin_aq_feature_id feature_id, 1031 u8 feature_ver) 1032{ 1033 return ena_com_get_feature_ex(ena_dev, 1034 get_resp, 1035 feature_id, 1036 0, 1037 0, 1038 feature_ver); 1039} 1040 1041int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev) 1042{ 1043 return ena_dev->rss.hash_func; 1044} 1045 1046static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev) 1047{ 1048 struct ena_admin_feature_rss_flow_hash_control *hash_key = 1049 (ena_dev->rss).hash_key; 1050 1051 netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key)); 1052 /* The key buffer is stored in the device in an array of 1053 * uint32 elements. 1054 */ 1055 hash_key->key_parts = ENA_ADMIN_RSS_KEY_PARTS; 1056} 1057 1058static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) 1059{ 1060 struct ena_rss *rss = &ena_dev->rss; 1061 1062 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) 1063 return -EOPNOTSUPP; 1064 1065 rss->hash_key = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 1066 &rss->hash_key_dma_addr, GFP_KERNEL); 1067 1068 if (unlikely(!rss->hash_key)) 1069 return -ENOMEM; 1070 1071 return 0; 1072} 1073 1074static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) 1075{ 1076 struct ena_rss *rss = &ena_dev->rss; 1077 1078 if (rss->hash_key) 1079 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), rss->hash_key, 1080 rss->hash_key_dma_addr); 1081 rss->hash_key = NULL; 1082} 1083 1084static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) 1085{ 1086 struct ena_rss *rss = &ena_dev->rss; 1087 1088 rss->hash_ctrl = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 1089 &rss->hash_ctrl_dma_addr, GFP_KERNEL); 1090 1091 if (unlikely(!rss->hash_ctrl)) 1092 return -ENOMEM; 1093 1094 return 0; 1095} 1096 1097static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) 1098{ 1099 struct ena_rss *rss = &ena_dev->rss; 1100 1101 if (rss->hash_ctrl) 1102 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), rss->hash_ctrl, 1103 rss->hash_ctrl_dma_addr); 1104 rss->hash_ctrl = NULL; 1105} 1106 1107static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, 1108 u16 log_size) 1109{ 1110 struct ena_rss *rss = &ena_dev->rss; 1111 struct ena_admin_get_feat_resp get_resp; 1112 size_t tbl_size; 1113 int ret; 1114 1115 ret = ena_com_get_feature(ena_dev, &get_resp, 1116 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0); 1117 if (unlikely(ret)) 1118 return ret; 1119 1120 if ((get_resp.u.ind_table.min_size > log_size) || 1121 (get_resp.u.ind_table.max_size < log_size)) { 1122 netdev_err(ena_dev->net_device, 1123 "Indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 1124 1 << log_size, 1 << get_resp.u.ind_table.min_size, 1125 1 << get_resp.u.ind_table.max_size); 1126 return -EINVAL; 1127 } 1128 1129 tbl_size = (1ULL << log_size) * 1130 sizeof(struct ena_admin_rss_ind_table_entry); 1131 1132 rss->rss_ind_tbl = dma_alloc_coherent(ena_dev->dmadev, tbl_size, &rss->rss_ind_tbl_dma_addr, 1133 GFP_KERNEL); 1134 if (unlikely(!rss->rss_ind_tbl)) 1135 goto mem_err1; 1136 1137 tbl_size = (1ULL << log_size) * sizeof(u16); 1138 rss->host_rss_ind_tbl = devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL); 1139 if (unlikely(!rss->host_rss_ind_tbl)) 1140 goto mem_err2; 1141 1142 rss->tbl_log_size = log_size; 1143 1144 return 0; 1145 1146mem_err2: 1147 tbl_size = (1ULL << log_size) * 1148 sizeof(struct ena_admin_rss_ind_table_entry); 1149 1150 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, rss->rss_ind_tbl_dma_addr); 1151 rss->rss_ind_tbl = NULL; 1152mem_err1: 1153 rss->tbl_log_size = 0; 1154 return -ENOMEM; 1155} 1156 1157static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) 1158{ 1159 struct ena_rss *rss = &ena_dev->rss; 1160 size_t tbl_size = (1ULL << rss->tbl_log_size) * 1161 sizeof(struct ena_admin_rss_ind_table_entry); 1162 1163 if (rss->rss_ind_tbl) 1164 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 1165 rss->rss_ind_tbl_dma_addr); 1166 rss->rss_ind_tbl = NULL; 1167 1168 if (rss->host_rss_ind_tbl) 1169 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl); 1170 rss->host_rss_ind_tbl = NULL; 1171} 1172 1173static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, 1174 struct ena_com_io_sq *io_sq, u16 cq_idx) 1175{ 1176 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1177 struct ena_admin_aq_create_sq_cmd create_cmd; 1178 struct ena_admin_acq_create_sq_resp_desc cmd_completion; 1179 u8 direction; 1180 int ret; 1181 1182 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1183 1184 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ; 1185 1186 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1187 direction = ENA_ADMIN_SQ_DIRECTION_TX; 1188 else 1189 direction = ENA_ADMIN_SQ_DIRECTION_RX; 1190 1191 create_cmd.sq_identity |= (direction << 1192 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & 1193 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1194 1195 create_cmd.sq_caps_2 |= io_sq->mem_queue_type & 1196 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1197 1198 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << 1199 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & 1200 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1201 1202 create_cmd.sq_caps_3 |= 1203 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1204 1205 create_cmd.cq_idx = cq_idx; 1206 create_cmd.sq_depth = io_sq->q_depth; 1207 1208 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 1209 ret = ena_com_mem_addr_set(ena_dev, 1210 &create_cmd.sq_ba, 1211 io_sq->desc_addr.phys_addr); 1212 if (unlikely(ret)) { 1213 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 1214 return ret; 1215 } 1216 } 1217 1218 ret = ena_com_execute_admin_command(admin_queue, 1219 (struct ena_admin_aq_entry *)&create_cmd, 1220 sizeof(create_cmd), 1221 (struct ena_admin_acq_entry *)&cmd_completion, 1222 sizeof(cmd_completion)); 1223 if (unlikely(ret)) { 1224 netdev_err(ena_dev->net_device, "Failed to create IO SQ. error: %d\n", ret); 1225 return ret; 1226 } 1227 1228 io_sq->idx = cmd_completion.sq_idx; 1229 1230 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1231 (uintptr_t)cmd_completion.sq_doorbell_offset); 1232 1233 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1234 io_sq->desc_addr.pbuf_dev_addr = 1235 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + 1236 cmd_completion.llq_descriptors_offset); 1237 } 1238 1239 netdev_dbg(ena_dev->net_device, "Created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); 1240 1241 return ret; 1242} 1243 1244static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) 1245{ 1246 struct ena_rss *rss = &ena_dev->rss; 1247 struct ena_com_io_sq *io_sq; 1248 u16 qid; 1249 int i; 1250 1251 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1252 qid = rss->host_rss_ind_tbl[i]; 1253 if (qid >= ENA_TOTAL_NUM_QUEUES) 1254 return -EINVAL; 1255 1256 io_sq = &ena_dev->io_sq_queues[qid]; 1257 1258 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX) 1259 return -EINVAL; 1260 1261 rss->rss_ind_tbl[i].cq_idx = io_sq->idx; 1262 } 1263 1264 return 0; 1265} 1266 1267static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, 1268 u16 intr_delay_resolution) 1269{ 1270 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution; 1271 1272 if (unlikely(!intr_delay_resolution)) { 1273 netdev_err(ena_dev->net_device, 1274 "Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); 1275 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION; 1276 } 1277 1278 /* update Rx */ 1279 ena_dev->intr_moder_rx_interval = 1280 ena_dev->intr_moder_rx_interval * 1281 prev_intr_delay_resolution / 1282 intr_delay_resolution; 1283 1284 /* update Tx */ 1285 ena_dev->intr_moder_tx_interval = 1286 ena_dev->intr_moder_tx_interval * 1287 prev_intr_delay_resolution / 1288 intr_delay_resolution; 1289 1290 ena_dev->intr_delay_resolution = intr_delay_resolution; 1291} 1292 1293/*****************************************************************************/ 1294/******************************* API ******************************/ 1295/*****************************************************************************/ 1296 1297int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 1298 struct ena_admin_aq_entry *cmd, 1299 size_t cmd_size, 1300 struct ena_admin_acq_entry *comp, 1301 size_t comp_size) 1302{ 1303 struct ena_comp_ctx *comp_ctx; 1304 int ret; 1305 1306 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size, 1307 comp, comp_size); 1308 if (IS_ERR(comp_ctx)) { 1309 ret = PTR_ERR(comp_ctx); 1310 if (ret == -ENODEV) 1311 netdev_dbg(admin_queue->ena_dev->net_device, 1312 "Failed to submit command [%d]\n", ret); 1313 else 1314 netdev_err(admin_queue->ena_dev->net_device, 1315 "Failed to submit command [%d]\n", ret); 1316 1317 return ret; 1318 } 1319 1320 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); 1321 if (unlikely(ret)) { 1322 if (admin_queue->running_state) 1323 netdev_err(admin_queue->ena_dev->net_device, 1324 "Failed to process command. ret = %d\n", ret); 1325 else 1326 netdev_dbg(admin_queue->ena_dev->net_device, 1327 "Failed to process command. ret = %d\n", ret); 1328 } 1329 return ret; 1330} 1331 1332int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 1333 struct ena_com_io_cq *io_cq) 1334{ 1335 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1336 struct ena_admin_aq_create_cq_cmd create_cmd; 1337 struct ena_admin_acq_create_cq_resp_desc cmd_completion; 1338 int ret; 1339 1340 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1341 1342 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ; 1343 1344 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) & 1345 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1346 create_cmd.cq_caps_1 |= 1347 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1348 1349 create_cmd.msix_vector = io_cq->msix_vector; 1350 create_cmd.cq_depth = io_cq->q_depth; 1351 1352 ret = ena_com_mem_addr_set(ena_dev, 1353 &create_cmd.cq_ba, 1354 io_cq->cdesc_addr.phys_addr); 1355 if (unlikely(ret)) { 1356 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 1357 return ret; 1358 } 1359 1360 ret = ena_com_execute_admin_command(admin_queue, 1361 (struct ena_admin_aq_entry *)&create_cmd, 1362 sizeof(create_cmd), 1363 (struct ena_admin_acq_entry *)&cmd_completion, 1364 sizeof(cmd_completion)); 1365 if (unlikely(ret)) { 1366 netdev_err(ena_dev->net_device, "Failed to create IO CQ. error: %d\n", ret); 1367 return ret; 1368 } 1369 1370 io_cq->idx = cmd_completion.cq_idx; 1371 1372 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1373 cmd_completion.cq_interrupt_unmask_register_offset); 1374 1375 if (cmd_completion.numa_node_register_offset) 1376 io_cq->numa_node_cfg_reg = 1377 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1378 cmd_completion.numa_node_register_offset); 1379 1380 netdev_dbg(ena_dev->net_device, "Created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); 1381 1382 return ret; 1383} 1384 1385int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 1386 struct ena_com_io_sq **io_sq, 1387 struct ena_com_io_cq **io_cq) 1388{ 1389 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1390 netdev_err(ena_dev->net_device, "Invalid queue number %d but the max is %d\n", qid, 1391 ENA_TOTAL_NUM_QUEUES); 1392 return -EINVAL; 1393 } 1394 1395 *io_sq = &ena_dev->io_sq_queues[qid]; 1396 *io_cq = &ena_dev->io_cq_queues[qid]; 1397 1398 return 0; 1399} 1400 1401void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) 1402{ 1403 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1404 struct ena_comp_ctx *comp_ctx; 1405 u16 i; 1406 1407 if (!admin_queue->comp_ctx) 1408 return; 1409 1410 for (i = 0; i < admin_queue->q_depth; i++) { 1411 comp_ctx = get_comp_ctxt(admin_queue, i, false); 1412 if (unlikely(!comp_ctx)) 1413 break; 1414 1415 comp_ctx->status = ENA_CMD_ABORTED; 1416 1417 complete(&comp_ctx->wait_event); 1418 } 1419} 1420 1421void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) 1422{ 1423 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1424 unsigned long flags = 0; 1425 u32 exp = 0; 1426 1427 spin_lock_irqsave(&admin_queue->q_lock, flags); 1428 while (atomic_read(&admin_queue->outstanding_cmds) != 0) { 1429 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1430 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); 1431 spin_lock_irqsave(&admin_queue->q_lock, flags); 1432 } 1433 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1434} 1435 1436int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 1437 struct ena_com_io_cq *io_cq) 1438{ 1439 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1440 struct ena_admin_aq_destroy_cq_cmd destroy_cmd; 1441 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp; 1442 int ret; 1443 1444 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 1445 1446 destroy_cmd.cq_idx = io_cq->idx; 1447 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ; 1448 1449 ret = ena_com_execute_admin_command(admin_queue, 1450 (struct ena_admin_aq_entry *)&destroy_cmd, 1451 sizeof(destroy_cmd), 1452 (struct ena_admin_acq_entry *)&destroy_resp, 1453 sizeof(destroy_resp)); 1454 1455 if (unlikely(ret && (ret != -ENODEV))) 1456 netdev_err(ena_dev->net_device, "Failed to destroy IO CQ. error: %d\n", ret); 1457 1458 return ret; 1459} 1460 1461bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) 1462{ 1463 return ena_dev->admin_queue.running_state; 1464} 1465 1466void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) 1467{ 1468 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1469 unsigned long flags = 0; 1470 1471 spin_lock_irqsave(&admin_queue->q_lock, flags); 1472 ena_dev->admin_queue.running_state = state; 1473 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1474} 1475 1476void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) 1477{ 1478 u16 depth = ena_dev->aenq.q_depth; 1479 1480 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); 1481 1482 /* Init head_db to mark that all entries in the queue 1483 * are initially available 1484 */ 1485 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1486} 1487 1488int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) 1489{ 1490 struct ena_com_admin_queue *admin_queue; 1491 struct ena_admin_set_feat_cmd cmd; 1492 struct ena_admin_set_feat_resp resp; 1493 struct ena_admin_get_feat_resp get_resp; 1494 int ret; 1495 1496 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0); 1497 if (ret) { 1498 dev_info(ena_dev->dmadev, "Can't get aenq configuration\n"); 1499 return ret; 1500 } 1501 1502 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { 1503 netdev_warn(ena_dev->net_device, 1504 "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n", 1505 get_resp.u.aenq.supported_groups, groups_flag); 1506 return -EOPNOTSUPP; 1507 } 1508 1509 memset(&cmd, 0x0, sizeof(cmd)); 1510 admin_queue = &ena_dev->admin_queue; 1511 1512 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1513 cmd.aq_common_descriptor.flags = 0; 1514 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG; 1515 cmd.u.aenq.enabled_groups = groups_flag; 1516 1517 ret = ena_com_execute_admin_command(admin_queue, 1518 (struct ena_admin_aq_entry *)&cmd, 1519 sizeof(cmd), 1520 (struct ena_admin_acq_entry *)&resp, 1521 sizeof(resp)); 1522 1523 if (unlikely(ret)) 1524 netdev_err(ena_dev->net_device, "Failed to config AENQ ret: %d\n", ret); 1525 1526 return ret; 1527} 1528 1529int ena_com_get_dma_width(struct ena_com_dev *ena_dev) 1530{ 1531 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1532 u32 width; 1533 1534 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { 1535 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n"); 1536 return -ETIME; 1537 } 1538 1539 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> 1540 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; 1541 1542 netdev_dbg(ena_dev->net_device, "ENA dma width: %d\n", width); 1543 1544 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { 1545 netdev_err(ena_dev->net_device, "DMA width illegal value: %d\n", width); 1546 return -EINVAL; 1547 } 1548 1549 ena_dev->dma_addr_bits = width; 1550 1551 return width; 1552} 1553 1554int ena_com_validate_version(struct ena_com_dev *ena_dev) 1555{ 1556 u32 ver; 1557 u32 ctrl_ver; 1558 u32 ctrl_ver_masked; 1559 1560 /* Make sure the ENA version and the controller version are at least 1561 * as the driver expects 1562 */ 1563 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); 1564 ctrl_ver = ena_com_reg_bar_read32(ena_dev, 1565 ENA_REGS_CONTROLLER_VERSION_OFF); 1566 1567 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { 1568 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n"); 1569 return -ETIME; 1570 } 1571 1572 dev_info(ena_dev->dmadev, "ENA device version: %d.%d\n", 1573 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, 1574 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); 1575 1576 dev_info(ena_dev->dmadev, "ENA controller version: %d.%d.%d implementation version %d\n", 1577 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >> 1578 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, 1579 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >> 1580 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, 1581 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), 1582 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> 1583 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); 1584 1585 ctrl_ver_masked = 1586 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | 1587 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) | 1588 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK); 1589 1590 /* Validate the ctrl version without the implementation ID */ 1591 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { 1592 netdev_err(ena_dev->net_device, 1593 "ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1594 return -1; 1595 } 1596 1597 return 0; 1598} 1599 1600static void 1601ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev *ena_dev, 1602 struct ena_com_admin_queue *admin_queue) 1603 1604{ 1605 if (!admin_queue->comp_ctx) 1606 return; 1607 1608 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx); 1609 1610 admin_queue->comp_ctx = NULL; 1611} 1612 1613void ena_com_admin_destroy(struct ena_com_dev *ena_dev) 1614{ 1615 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1616 struct ena_com_admin_cq *cq = &admin_queue->cq; 1617 struct ena_com_admin_sq *sq = &admin_queue->sq; 1618 struct ena_com_aenq *aenq = &ena_dev->aenq; 1619 u16 size; 1620 1621 ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue); 1622 1623 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 1624 if (sq->entries) 1625 dma_free_coherent(ena_dev->dmadev, size, sq->entries, sq->dma_addr); 1626 sq->entries = NULL; 1627 1628 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 1629 if (cq->entries) 1630 dma_free_coherent(ena_dev->dmadev, size, cq->entries, cq->dma_addr); 1631 cq->entries = NULL; 1632 1633 size = ADMIN_AENQ_SIZE(aenq->q_depth); 1634 if (ena_dev->aenq.entries) 1635 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr); 1636 aenq->entries = NULL; 1637} 1638 1639void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) 1640{ 1641 u32 mask_value = 0; 1642 1643 if (polling) 1644 mask_value = ENA_REGS_ADMIN_INTR_MASK; 1645 1646 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); 1647 ena_dev->admin_queue.polling = polling; 1648} 1649 1650bool ena_com_phc_supported(struct ena_com_dev *ena_dev) 1651{ 1652 return ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_PHC_CONFIG); 1653} 1654 1655int ena_com_phc_init(struct ena_com_dev *ena_dev) 1656{ 1657 struct ena_com_phc_info *phc = &ena_dev->phc; 1658 1659 memset(phc, 0x0, sizeof(*phc)); 1660 1661 /* Allocate shared mem used PHC timestamp retrieved from device */ 1662 phc->virt_addr = dma_alloc_coherent(ena_dev->dmadev, 1663 sizeof(*phc->virt_addr), 1664 &phc->phys_addr, 1665 GFP_KERNEL); 1666 if (unlikely(!phc->virt_addr)) 1667 return -ENOMEM; 1668 1669 spin_lock_init(&phc->lock); 1670 1671 phc->virt_addr->req_id = 0; 1672 phc->virt_addr->timestamp = 0; 1673 1674 return 0; 1675} 1676 1677int ena_com_phc_config(struct ena_com_dev *ena_dev) 1678{ 1679 struct ena_com_phc_info *phc = &ena_dev->phc; 1680 struct ena_admin_get_feat_resp get_feat_resp; 1681 struct ena_admin_set_feat_resp set_feat_resp; 1682 struct ena_admin_set_feat_cmd set_feat_cmd; 1683 int ret = 0; 1684 1685 /* Get device PHC default configuration */ 1686 ret = ena_com_get_feature(ena_dev, 1687 &get_feat_resp, 1688 ENA_ADMIN_PHC_CONFIG, 1689 0); 1690 if (unlikely(ret)) { 1691 netdev_err(ena_dev->net_device, 1692 "Failed to get PHC feature configuration, error: %d\n", 1693 ret); 1694 return ret; 1695 } 1696 1697 /* Supporting only readless PHC retrieval */ 1698 if (get_feat_resp.u.phc.type != ENA_ADMIN_PHC_TYPE_READLESS) { 1699 netdev_err(ena_dev->net_device, 1700 "Unsupported PHC type, error: %d\n", 1701 -EOPNOTSUPP); 1702 return -EOPNOTSUPP; 1703 } 1704 1705 /* Update PHC doorbell offset according to device value, 1706 * used to write req_id to PHC bar 1707 */ 1708 phc->doorbell_offset = get_feat_resp.u.phc.doorbell_offset; 1709 1710 /* Update PHC expire timeout according to device 1711 * or default driver value 1712 */ 1713 phc->expire_timeout_usec = (get_feat_resp.u.phc.expire_timeout_usec) ? 1714 get_feat_resp.u.phc.expire_timeout_usec : 1715 ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC; 1716 1717 /* Update PHC block timeout according to device 1718 * or default driver value 1719 */ 1720 phc->block_timeout_usec = (get_feat_resp.u.phc.block_timeout_usec) ? 1721 get_feat_resp.u.phc.block_timeout_usec : 1722 ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC; 1723 1724 /* Sanity check - expire timeout must not exceed block timeout */ 1725 if (phc->expire_timeout_usec > phc->block_timeout_usec) 1726 phc->expire_timeout_usec = phc->block_timeout_usec; 1727 1728 /* Prepare PHC feature command */ 1729 memset(&set_feat_cmd, 0x0, sizeof(set_feat_cmd)); 1730 set_feat_cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1731 set_feat_cmd.feat_common.feature_id = ENA_ADMIN_PHC_CONFIG; 1732 set_feat_cmd.u.phc.output_length = sizeof(*phc->virt_addr); 1733 ret = ena_com_mem_addr_set(ena_dev, 1734 &set_feat_cmd.u.phc.output_address, 1735 phc->phys_addr); 1736 if (unlikely(ret)) { 1737 netdev_err(ena_dev->net_device, 1738 "Failed setting PHC output address, error: %d\n", 1739 ret); 1740 return ret; 1741 } 1742 1743 /* Send PHC feature command to the device */ 1744 ret = ena_com_execute_admin_command(&ena_dev->admin_queue, 1745 (struct ena_admin_aq_entry *)&set_feat_cmd, 1746 sizeof(set_feat_cmd), 1747 (struct ena_admin_acq_entry *)&set_feat_resp, 1748 sizeof(set_feat_resp)); 1749 1750 if (unlikely(ret)) { 1751 netdev_err(ena_dev->net_device, 1752 "Failed to enable PHC, error: %d\n", 1753 ret); 1754 return ret; 1755 } 1756 1757 phc->active = true; 1758 netdev_dbg(ena_dev->net_device, "PHC is active in the device\n"); 1759 1760 return ret; 1761} 1762 1763void ena_com_phc_destroy(struct ena_com_dev *ena_dev) 1764{ 1765 struct ena_com_phc_info *phc = &ena_dev->phc; 1766 unsigned long flags = 0; 1767 1768 /* In case PHC is not supported by the device, silently exiting */ 1769 if (!phc->virt_addr) 1770 return; 1771 1772 spin_lock_irqsave(&phc->lock, flags); 1773 phc->active = false; 1774 spin_unlock_irqrestore(&phc->lock, flags); 1775 1776 dma_free_coherent(ena_dev->dmadev, 1777 sizeof(*phc->virt_addr), 1778 phc->virt_addr, 1779 phc->phys_addr); 1780 phc->virt_addr = NULL; 1781} 1782 1783int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp) 1784{ 1785 volatile struct ena_admin_phc_resp *resp = ena_dev->phc.virt_addr; 1786 const ktime_t zero_system_time = ktime_set(0, 0); 1787 struct ena_com_phc_info *phc = &ena_dev->phc; 1788 ktime_t expire_time; 1789 ktime_t block_time; 1790 unsigned long flags = 0; 1791 int ret = 0; 1792 1793 if (!phc->active) { 1794 netdev_err(ena_dev->net_device, "PHC feature is not active in the device\n"); 1795 return -EOPNOTSUPP; 1796 } 1797 1798 spin_lock_irqsave(&phc->lock, flags); 1799 1800 /* Check if PHC is in blocked state */ 1801 if (unlikely(ktime_compare(phc->system_time, zero_system_time))) { 1802 /* Check if blocking time expired */ 1803 block_time = ktime_add_us(phc->system_time, phc->block_timeout_usec); 1804 if (!ktime_after(ktime_get(), block_time)) { 1805 /* PHC is still in blocked state, skip PHC request */ 1806 phc->stats.phc_skp++; 1807 ret = -EBUSY; 1808 goto skip; 1809 } 1810 1811 /* PHC is in active state, update statistics according 1812 * to req_id and error_flags 1813 */ 1814 if (READ_ONCE(resp->req_id) != phc->req_id) { 1815 /* Device didn't update req_id during blocking time, 1816 * this indicates on a device error 1817 */ 1818 netdev_err(ena_dev->net_device, 1819 "PHC get time request 0x%x failed (device error)\n", 1820 phc->req_id); 1821 phc->stats.phc_err_dv++; 1822 } else if (resp->error_flags & ENA_PHC_ERROR_FLAGS) { 1823 /* Device updated req_id during blocking time but got 1824 * a PHC error, this occurs if device: 1825 * - exceeded the get time request limit 1826 * - received an invalid timestamp 1827 */ 1828 netdev_err(ena_dev->net_device, 1829 "PHC get time request 0x%x failed (error 0x%x)\n", 1830 phc->req_id, 1831 resp->error_flags); 1832 phc->stats.phc_err_ts += !!(resp->error_flags & 1833 ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP); 1834 } else { 1835 /* Device updated req_id during blocking time 1836 * with valid timestamp 1837 */ 1838 phc->stats.phc_exp++; 1839 } 1840 } 1841 1842 /* Setting relative timeouts */ 1843 phc->system_time = ktime_get(); 1844 block_time = ktime_add_us(phc->system_time, phc->block_timeout_usec); 1845 expire_time = ktime_add_us(phc->system_time, phc->expire_timeout_usec); 1846 1847 /* We expect the device to return this req_id once 1848 * the new PHC timestamp is updated 1849 */ 1850 phc->req_id++; 1851 1852 /* Initialize PHC shared memory with different req_id value 1853 * to be able to identify once the device changes it to req_id 1854 */ 1855 resp->req_id = phc->req_id + ENA_PHC_REQ_ID_OFFSET; 1856 1857 /* Writing req_id to PHC bar */ 1858 writel(phc->req_id, ena_dev->reg_bar + phc->doorbell_offset); 1859 1860 /* Stalling until the device updates req_id */ 1861 while (1) { 1862 if (unlikely(ktime_after(ktime_get(), expire_time))) { 1863 /* Gave up waiting for updated req_id, PHC enters into 1864 * blocked state until passing blocking time, 1865 * during this time any get PHC timestamp will fail with 1866 * device busy error 1867 */ 1868 ret = -EBUSY; 1869 break; 1870 } 1871 1872 /* Check if req_id was updated by the device */ 1873 if (READ_ONCE(resp->req_id) != phc->req_id) { 1874 /* req_id was not updated by the device yet, 1875 * check again on next loop 1876 */ 1877 continue; 1878 } 1879 1880 /* req_id was updated by the device which indicates that 1881 * PHC timestamp and error_flags are updated too, 1882 * checking errors before retrieving timestamp 1883 */ 1884 if (unlikely(resp->error_flags & ENA_PHC_ERROR_FLAGS)) { 1885 /* Retrieved invalid PHC timestamp, PHC enters into 1886 * blocked state until passing blocking time, 1887 * during this time any get PHC timestamp requests 1888 * will fail with device busy error 1889 */ 1890 ret = -EBUSY; 1891 break; 1892 } 1893 1894 /* PHC timestamp value is returned to the caller */ 1895 *timestamp = resp->timestamp; 1896 1897 /* Update statistic on valid PHC timestamp retrieval */ 1898 phc->stats.phc_cnt++; 1899 1900 /* This indicates PHC state is active */ 1901 phc->system_time = zero_system_time; 1902 break; 1903 } 1904 1905skip: 1906 spin_unlock_irqrestore(&phc->lock, flags); 1907 1908 return ret; 1909} 1910 1911int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) 1912{ 1913 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1914 1915 spin_lock_init(&mmio_read->lock); 1916 mmio_read->read_resp = dma_alloc_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), 1917 &mmio_read->read_resp_dma_addr, GFP_KERNEL); 1918 if (unlikely(!mmio_read->read_resp)) 1919 goto err; 1920 1921 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1922 1923 mmio_read->read_resp->req_id = 0x0; 1924 mmio_read->seq_num = 0x0; 1925 mmio_read->readless_supported = true; 1926 1927 return 0; 1928 1929err: 1930 1931 return -ENOMEM; 1932} 1933 1934void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) 1935{ 1936 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1937 1938 mmio_read->readless_supported = readless_supported; 1939} 1940 1941void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) 1942{ 1943 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1944 1945 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1946 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1947 1948 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), mmio_read->read_resp, 1949 mmio_read->read_resp_dma_addr); 1950 1951 mmio_read->read_resp = NULL; 1952} 1953 1954void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) 1955{ 1956 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1957 u32 addr_low, addr_high; 1958 1959 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr); 1960 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr); 1961 1962 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1963 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1964} 1965 1966int ena_com_admin_init(struct ena_com_dev *ena_dev, 1967 struct ena_aenq_handlers *aenq_handlers) 1968{ 1969 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1970 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; 1971 int ret; 1972 1973 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1974 1975 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { 1976 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n"); 1977 return -ETIME; 1978 } 1979 1980 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { 1981 netdev_err(ena_dev->net_device, "Device isn't ready, abort com init\n"); 1982 return -ENODEV; 1983 } 1984 1985 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; 1986 1987 admin_queue->q_dmadev = ena_dev->dmadev; 1988 admin_queue->polling = false; 1989 admin_queue->curr_cmd_id = 0; 1990 1991 atomic_set(&admin_queue->outstanding_cmds, 0); 1992 1993 spin_lock_init(&admin_queue->q_lock); 1994 1995 ret = ena_com_init_comp_ctxt(admin_queue); 1996 if (ret) 1997 goto error; 1998 1999 ret = ena_com_admin_init_sq(admin_queue); 2000 if (ret) 2001 goto error; 2002 2003 ret = ena_com_admin_init_cq(admin_queue); 2004 if (ret) 2005 goto error; 2006 2007 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 2008 ENA_REGS_AQ_DB_OFF); 2009 2010 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); 2011 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); 2012 2013 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); 2014 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); 2015 2016 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); 2017 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); 2018 2019 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); 2020 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); 2021 2022 aq_caps = 0; 2023 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; 2024 aq_caps |= (sizeof(struct ena_admin_aq_entry) << 2025 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & 2026 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; 2027 2028 acq_caps = 0; 2029 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; 2030 acq_caps |= (sizeof(struct ena_admin_acq_entry) << 2031 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & 2032 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; 2033 2034 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); 2035 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); 2036 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); 2037 if (ret) 2038 goto error; 2039 2040 admin_queue->ena_dev = ena_dev; 2041 admin_queue->running_state = true; 2042 2043 return 0; 2044error: 2045 ena_com_admin_destroy(ena_dev); 2046 2047 return ret; 2048} 2049 2050int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 2051 struct ena_com_create_io_ctx *ctx) 2052{ 2053 struct ena_com_io_sq *io_sq; 2054 struct ena_com_io_cq *io_cq; 2055 int ret; 2056 2057 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { 2058 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n", 2059 ctx->qid, ENA_TOTAL_NUM_QUEUES); 2060 return -EINVAL; 2061 } 2062 2063 io_sq = &ena_dev->io_sq_queues[ctx->qid]; 2064 io_cq = &ena_dev->io_cq_queues[ctx->qid]; 2065 2066 memset(io_sq, 0x0, sizeof(*io_sq)); 2067 memset(io_cq, 0x0, sizeof(*io_cq)); 2068 2069 /* Init CQ */ 2070 io_cq->q_depth = ctx->queue_size; 2071 io_cq->direction = ctx->direction; 2072 io_cq->qid = ctx->qid; 2073 2074 io_cq->msix_vector = ctx->msix_vector; 2075 2076 io_sq->q_depth = ctx->queue_size; 2077 io_sq->direction = ctx->direction; 2078 io_sq->qid = ctx->qid; 2079 2080 io_sq->mem_queue_type = ctx->mem_queue_type; 2081 2082 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 2083 /* header length is limited to 8 bits */ 2084 io_sq->tx_max_header_size = min_t(u32, ena_dev->tx_max_header_size, SZ_256); 2085 2086 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); 2087 if (ret) 2088 goto error; 2089 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); 2090 if (ret) 2091 goto error; 2092 2093 ret = ena_com_create_io_cq(ena_dev, io_cq); 2094 if (ret) 2095 goto error; 2096 2097 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); 2098 if (ret) 2099 goto destroy_io_cq; 2100 2101 return 0; 2102 2103destroy_io_cq: 2104 ena_com_destroy_io_cq(ena_dev, io_cq); 2105error: 2106 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 2107 return ret; 2108} 2109 2110void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) 2111{ 2112 struct ena_com_io_sq *io_sq; 2113 struct ena_com_io_cq *io_cq; 2114 2115 if (qid >= ENA_TOTAL_NUM_QUEUES) { 2116 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n", 2117 qid, ENA_TOTAL_NUM_QUEUES); 2118 return; 2119 } 2120 2121 io_sq = &ena_dev->io_sq_queues[qid]; 2122 io_cq = &ena_dev->io_cq_queues[qid]; 2123 2124 ena_com_destroy_io_sq(ena_dev, io_sq); 2125 ena_com_destroy_io_cq(ena_dev, io_cq); 2126 2127 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 2128} 2129 2130int ena_com_get_link_params(struct ena_com_dev *ena_dev, 2131 struct ena_admin_get_feat_resp *resp) 2132{ 2133 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0); 2134} 2135 2136static int ena_get_dev_stats(struct ena_com_dev *ena_dev, 2137 struct ena_com_stats_ctx *ctx, 2138 enum ena_admin_get_stats_type type) 2139{ 2140 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp; 2141 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd; 2142 struct ena_com_admin_queue *admin_queue; 2143 int ret; 2144 2145 admin_queue = &ena_dev->admin_queue; 2146 2147 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS; 2148 get_cmd->aq_common_descriptor.flags = 0; 2149 get_cmd->type = type; 2150 2151 ret = ena_com_execute_admin_command(admin_queue, 2152 (struct ena_admin_aq_entry *)get_cmd, 2153 sizeof(*get_cmd), 2154 (struct ena_admin_acq_entry *)get_resp, 2155 sizeof(*get_resp)); 2156 2157 if (unlikely(ret)) 2158 netdev_err(ena_dev->net_device, "Failed to get stats. error: %d\n", ret); 2159 2160 return ret; 2161} 2162 2163static void ena_com_set_supported_customer_metrics(struct ena_com_dev *ena_dev) 2164{ 2165 struct ena_customer_metrics *customer_metrics; 2166 struct ena_com_stats_ctx ctx; 2167 int ret; 2168 2169 customer_metrics = &ena_dev->customer_metrics; 2170 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) { 2171 customer_metrics->supported_metrics = ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK; 2172 return; 2173 } 2174 2175 memset(&ctx, 0x0, sizeof(ctx)); 2176 ctx.get_cmd.requested_metrics = ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK; 2177 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS); 2178 if (likely(ret == 0)) 2179 customer_metrics->supported_metrics = 2180 ctx.get_resp.u.customer_metrics.reported_metrics; 2181 else 2182 netdev_err(ena_dev->net_device, 2183 "Failed to query customer metrics support. error: %d\n", ret); 2184} 2185 2186int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 2187 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2188{ 2189 struct ena_admin_get_feat_resp get_resp; 2190 int rc; 2191 2192 rc = ena_com_get_feature(ena_dev, &get_resp, 2193 ENA_ADMIN_DEVICE_ATTRIBUTES, 0); 2194 if (rc) 2195 return rc; 2196 2197 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, 2198 sizeof(get_resp.u.dev_attr)); 2199 2200 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; 2201 ena_dev->capabilities = get_resp.u.dev_attr.capabilities; 2202 2203 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 2204 rc = ena_com_get_feature(ena_dev, &get_resp, 2205 ENA_ADMIN_MAX_QUEUES_EXT, 2206 ENA_FEATURE_MAX_QUEUE_EXT_VER); 2207 if (rc) 2208 return rc; 2209 2210 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER) 2211 return -EINVAL; 2212 2213 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext, 2214 sizeof(get_resp.u.max_queue_ext)); 2215 ena_dev->tx_max_header_size = 2216 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size; 2217 } else { 2218 rc = ena_com_get_feature(ena_dev, &get_resp, 2219 ENA_ADMIN_MAX_QUEUES_NUM, 0); 2220 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue, 2221 sizeof(get_resp.u.max_queue)); 2222 ena_dev->tx_max_header_size = 2223 get_resp.u.max_queue.max_header_size; 2224 2225 if (rc) 2226 return rc; 2227 } 2228 2229 rc = ena_com_get_feature(ena_dev, &get_resp, 2230 ENA_ADMIN_AENQ_CONFIG, 0); 2231 if (rc) 2232 return rc; 2233 2234 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, 2235 sizeof(get_resp.u.aenq)); 2236 2237 rc = ena_com_get_feature(ena_dev, &get_resp, 2238 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); 2239 if (rc) 2240 return rc; 2241 2242 memcpy(&get_feat_ctx->offload, &get_resp.u.offload, 2243 sizeof(get_resp.u.offload)); 2244 2245 /* Driver hints isn't mandatory admin command. So in case the 2246 * command isn't supported set driver hints to 0 2247 */ 2248 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0); 2249 2250 if (!rc) 2251 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, sizeof(get_resp.u.hw_hints)); 2252 else if (rc == -EOPNOTSUPP) 2253 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints)); 2254 else 2255 return rc; 2256 2257 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0); 2258 if (!rc) 2259 memcpy(&get_feat_ctx->llq, &get_resp.u.llq, sizeof(get_resp.u.llq)); 2260 else if (rc == -EOPNOTSUPP) 2261 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq)); 2262 else 2263 return rc; 2264 2265 ena_com_set_supported_customer_metrics(ena_dev); 2266 2267 return 0; 2268} 2269 2270void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) 2271{ 2272 ena_com_handle_admin_completion(&ena_dev->admin_queue); 2273} 2274 2275/* ena_handle_specific_aenq_event: 2276 * return the handler that is relevant to the specific event group 2277 */ 2278static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev, 2279 u16 group) 2280{ 2281 struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers; 2282 2283 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) 2284 return aenq_handlers->handlers[group]; 2285 2286 return aenq_handlers->unimplemented_handler; 2287} 2288 2289/* ena_aenq_intr_handler: 2290 * handles the aenq incoming events. 2291 * pop events from the queue and apply the specific handler 2292 */ 2293void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) 2294{ 2295 struct ena_admin_aenq_entry *aenq_e; 2296 struct ena_admin_aenq_common_desc *aenq_common; 2297 struct ena_com_aenq *aenq = &ena_dev->aenq; 2298 u64 timestamp; 2299 ena_aenq_handler handler_cb; 2300 u16 masked_head, processed = 0; 2301 u8 phase; 2302 2303 masked_head = aenq->head & (aenq->q_depth - 1); 2304 phase = aenq->phase; 2305 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ 2306 aenq_common = &aenq_e->aenq_common_desc; 2307 2308 /* Go over all the events */ 2309 while ((READ_ONCE(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { 2310 /* Make sure the phase bit (ownership) is as expected before 2311 * reading the rest of the descriptor. 2312 */ 2313 dma_rmb(); 2314 2315 timestamp = (u64)aenq_common->timestamp_low | 2316 ((u64)aenq_common->timestamp_high << 32); 2317 2318 netdev_dbg(ena_dev->net_device, "AENQ! Group[%x] Syndrome[%x] timestamp: [%llus]\n", 2319 aenq_common->group, aenq_common->syndrome, timestamp); 2320 2321 /* Handle specific event*/ 2322 handler_cb = ena_com_get_specific_aenq_cb(ena_dev, 2323 aenq_common->group); 2324 handler_cb(data, aenq_e); /* call the actual event handler*/ 2325 2326 /* Get next event entry */ 2327 masked_head++; 2328 processed++; 2329 2330 if (unlikely(masked_head == aenq->q_depth)) { 2331 masked_head = 0; 2332 phase = !phase; 2333 } 2334 aenq_e = &aenq->entries[masked_head]; 2335 aenq_common = &aenq_e->aenq_common_desc; 2336 } 2337 2338 aenq->head += processed; 2339 aenq->phase = phase; 2340 2341 /* Don't update aenq doorbell if there weren't any processed events */ 2342 if (!processed) 2343 return; 2344 2345 /* write the aenq doorbell after all AENQ descriptors were read */ 2346 mb(); 2347 writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 2348} 2349 2350int ena_com_dev_reset(struct ena_com_dev *ena_dev, 2351 enum ena_regs_reset_reason_types reset_reason) 2352{ 2353 u32 stat, timeout, cap, reset_val; 2354 int rc; 2355 2356 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 2357 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 2358 2359 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || (cap == ENA_MMIO_READ_TIMEOUT))) { 2360 netdev_err(ena_dev->net_device, "Reg read32 timeout occurred\n"); 2361 return -ETIME; 2362 } 2363 2364 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { 2365 netdev_err(ena_dev->net_device, "Device isn't ready, can't reset device\n"); 2366 return -EINVAL; 2367 } 2368 2369 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> 2370 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; 2371 if (timeout == 0) { 2372 netdev_err(ena_dev->net_device, "Invalid timeout value\n"); 2373 return -EINVAL; 2374 } 2375 2376 /* start reset */ 2377 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 2378 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & 2379 ENA_REGS_DEV_CTL_RESET_REASON_MASK; 2380 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 2381 2382 /* Write again the MMIO read request address */ 2383 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 2384 2385 rc = wait_for_reset_state(ena_dev, timeout, 2386 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); 2387 if (rc != 0) { 2388 netdev_err(ena_dev->net_device, "Reset indication didn't turn on\n"); 2389 return rc; 2390 } 2391 2392 /* reset done */ 2393 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 2394 rc = wait_for_reset_state(ena_dev, timeout, 0); 2395 if (rc != 0) { 2396 netdev_err(ena_dev->net_device, "Reset indication didn't turn off\n"); 2397 return rc; 2398 } 2399 2400 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >> 2401 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT; 2402 if (timeout) 2403 /* the resolution of timeout reg is 100ms */ 2404 ena_dev->admin_queue.completion_timeout = timeout * 100000; 2405 else 2406 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; 2407 2408 return 0; 2409} 2410 2411int ena_com_get_eni_stats(struct ena_com_dev *ena_dev, 2412 struct ena_admin_eni_stats *stats) 2413{ 2414 struct ena_com_stats_ctx ctx; 2415 int ret; 2416 2417 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) { 2418 netdev_err(ena_dev->net_device, "Capability %d isn't supported\n", 2419 ENA_ADMIN_ENI_STATS); 2420 return -EOPNOTSUPP; 2421 } 2422 2423 memset(&ctx, 0x0, sizeof(ctx)); 2424 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI); 2425 if (likely(ret == 0)) 2426 memcpy(stats, &ctx.get_resp.u.eni_stats, 2427 sizeof(ctx.get_resp.u.eni_stats)); 2428 2429 return ret; 2430} 2431 2432int ena_com_get_ena_srd_info(struct ena_com_dev *ena_dev, 2433 struct ena_admin_ena_srd_info *info) 2434{ 2435 struct ena_com_stats_ctx ctx; 2436 int ret; 2437 2438 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENA_SRD_INFO)) { 2439 netdev_err(ena_dev->net_device, "Capability %d isn't supported\n", 2440 ENA_ADMIN_ENA_SRD_INFO); 2441 return -EOPNOTSUPP; 2442 } 2443 2444 memset(&ctx, 0x0, sizeof(ctx)); 2445 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENA_SRD); 2446 if (likely(ret == 0)) 2447 memcpy(info, &ctx.get_resp.u.ena_srd_info, 2448 sizeof(ctx.get_resp.u.ena_srd_info)); 2449 2450 return ret; 2451} 2452 2453int ena_com_get_customer_metrics(struct ena_com_dev *ena_dev, char *buffer, u32 len) 2454{ 2455 struct ena_admin_aq_get_stats_cmd *get_cmd; 2456 struct ena_com_stats_ctx ctx; 2457 int ret; 2458 2459 if (unlikely(len > ena_dev->customer_metrics.buffer_len)) { 2460 netdev_err(ena_dev->net_device, 2461 "Invalid buffer size %u. The given buffer is too big.\n", len); 2462 return -EINVAL; 2463 } 2464 2465 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) { 2466 netdev_err(ena_dev->net_device, "Capability %d not supported.\n", 2467 ENA_ADMIN_CUSTOMER_METRICS); 2468 return -EOPNOTSUPP; 2469 } 2470 2471 if (!ena_dev->customer_metrics.supported_metrics) { 2472 netdev_err(ena_dev->net_device, "No supported customer metrics.\n"); 2473 return -EOPNOTSUPP; 2474 } 2475 2476 get_cmd = &ctx.get_cmd; 2477 memset(&ctx, 0x0, sizeof(ctx)); 2478 ret = ena_com_mem_addr_set(ena_dev, 2479 &get_cmd->u.control_buffer.address, 2480 ena_dev->customer_metrics.buffer_dma_addr); 2481 if (unlikely(ret)) { 2482 netdev_err(ena_dev->net_device, "Memory address set failed.\n"); 2483 return ret; 2484 } 2485 2486 get_cmd->u.control_buffer.length = ena_dev->customer_metrics.buffer_len; 2487 get_cmd->requested_metrics = ena_dev->customer_metrics.supported_metrics; 2488 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS); 2489 if (likely(ret == 0)) 2490 memcpy(buffer, ena_dev->customer_metrics.buffer_virt_addr, len); 2491 else 2492 netdev_err(ena_dev->net_device, "Failed to get customer metrics. error: %d\n", ret); 2493 2494 return ret; 2495} 2496 2497int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu) 2498{ 2499 struct ena_com_admin_queue *admin_queue; 2500 struct ena_admin_set_feat_cmd cmd; 2501 struct ena_admin_set_feat_resp resp; 2502 int ret; 2503 2504 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { 2505 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", ENA_ADMIN_MTU); 2506 return -EOPNOTSUPP; 2507 } 2508 2509 memset(&cmd, 0x0, sizeof(cmd)); 2510 admin_queue = &ena_dev->admin_queue; 2511 2512 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2513 cmd.aq_common_descriptor.flags = 0; 2514 cmd.feat_common.feature_id = ENA_ADMIN_MTU; 2515 cmd.u.mtu.mtu = mtu; 2516 2517 ret = ena_com_execute_admin_command(admin_queue, 2518 (struct ena_admin_aq_entry *)&cmd, 2519 sizeof(cmd), 2520 (struct ena_admin_acq_entry *)&resp, 2521 sizeof(resp)); 2522 2523 if (unlikely(ret)) 2524 netdev_err(ena_dev->net_device, "Failed to set mtu %d. error: %d\n", mtu, ret); 2525 2526 return ret; 2527} 2528 2529int ena_com_set_hash_function(struct ena_com_dev *ena_dev) 2530{ 2531 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2532 struct ena_rss *rss = &ena_dev->rss; 2533 struct ena_admin_set_feat_cmd cmd; 2534 struct ena_admin_set_feat_resp resp; 2535 struct ena_admin_get_feat_resp get_resp; 2536 int ret; 2537 2538 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) { 2539 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", 2540 ENA_ADMIN_RSS_HASH_FUNCTION); 2541 return -EOPNOTSUPP; 2542 } 2543 2544 /* Validate hash function is supported */ 2545 ret = ena_com_get_feature(ena_dev, &get_resp, 2546 ENA_ADMIN_RSS_HASH_FUNCTION, 0); 2547 if (unlikely(ret)) 2548 return ret; 2549 2550 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) { 2551 netdev_err(ena_dev->net_device, "Func hash %d isn't supported by device, abort\n", 2552 rss->hash_func); 2553 return -EOPNOTSUPP; 2554 } 2555 2556 memset(&cmd, 0x0, sizeof(cmd)); 2557 2558 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2559 cmd.aq_common_descriptor.flags = 2560 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2561 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION; 2562 cmd.u.flow_hash_func.init_val = rss->hash_init_val; 2563 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func; 2564 2565 ret = ena_com_mem_addr_set(ena_dev, 2566 &cmd.control_buffer.address, 2567 rss->hash_key_dma_addr); 2568 if (unlikely(ret)) { 2569 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 2570 return ret; 2571 } 2572 2573 cmd.control_buffer.length = sizeof(*rss->hash_key); 2574 2575 ret = ena_com_execute_admin_command(admin_queue, 2576 (struct ena_admin_aq_entry *)&cmd, 2577 sizeof(cmd), 2578 (struct ena_admin_acq_entry *)&resp, 2579 sizeof(resp)); 2580 if (unlikely(ret)) { 2581 netdev_err(ena_dev->net_device, "Failed to set hash function %d. error: %d\n", 2582 rss->hash_func, ret); 2583 return -EINVAL; 2584 } 2585 2586 return 0; 2587} 2588 2589int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 2590 enum ena_admin_hash_functions func, 2591 const u8 *key, u16 key_len, u32 init_val) 2592{ 2593 struct ena_admin_feature_rss_flow_hash_control *hash_key; 2594 struct ena_admin_get_feat_resp get_resp; 2595 enum ena_admin_hash_functions old_func; 2596 struct ena_rss *rss = &ena_dev->rss; 2597 int rc; 2598 2599 hash_key = rss->hash_key; 2600 2601 /* Make sure size is a mult of DWs */ 2602 if (unlikely(key_len & 0x3)) 2603 return -EINVAL; 2604 2605 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2606 ENA_ADMIN_RSS_HASH_FUNCTION, 2607 rss->hash_key_dma_addr, 2608 sizeof(*rss->hash_key), 0); 2609 if (unlikely(rc)) 2610 return rc; 2611 2612 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) { 2613 netdev_err(ena_dev->net_device, "Flow hash function %d isn't supported\n", func); 2614 return -EOPNOTSUPP; 2615 } 2616 2617 if ((func == ENA_ADMIN_TOEPLITZ) && key) { 2618 if (key_len != sizeof(hash_key->key)) { 2619 netdev_err(ena_dev->net_device, 2620 "key len (%u) doesn't equal the supported size (%zu)\n", key_len, 2621 sizeof(hash_key->key)); 2622 return -EINVAL; 2623 } 2624 memcpy(hash_key->key, key, key_len); 2625 hash_key->key_parts = key_len / sizeof(hash_key->key[0]); 2626 } 2627 2628 rss->hash_init_val = init_val; 2629 old_func = rss->hash_func; 2630 rss->hash_func = func; 2631 rc = ena_com_set_hash_function(ena_dev); 2632 2633 /* Restore the old function */ 2634 if (unlikely(rc)) 2635 rss->hash_func = old_func; 2636 2637 return rc; 2638} 2639 2640int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 2641 enum ena_admin_hash_functions *func) 2642{ 2643 struct ena_rss *rss = &ena_dev->rss; 2644 struct ena_admin_get_feat_resp get_resp; 2645 int rc; 2646 2647 if (unlikely(!func)) 2648 return -EINVAL; 2649 2650 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2651 ENA_ADMIN_RSS_HASH_FUNCTION, 2652 rss->hash_key_dma_addr, 2653 sizeof(*rss->hash_key), 0); 2654 if (unlikely(rc)) 2655 return rc; 2656 2657 /* ffs() returns 1 in case the lsb is set */ 2658 rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func); 2659 if (rss->hash_func) 2660 rss->hash_func--; 2661 2662 *func = rss->hash_func; 2663 2664 return 0; 2665} 2666 2667int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key) 2668{ 2669 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2670 ena_dev->rss.hash_key; 2671 2672 if (key) 2673 memcpy(key, hash_key->key, 2674 (size_t)(hash_key->key_parts) * sizeof(hash_key->key[0])); 2675 2676 return 0; 2677} 2678 2679int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 2680 enum ena_admin_flow_hash_proto proto, 2681 u16 *fields) 2682{ 2683 struct ena_rss *rss = &ena_dev->rss; 2684 struct ena_admin_get_feat_resp get_resp; 2685 int rc; 2686 2687 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2688 ENA_ADMIN_RSS_HASH_INPUT, 2689 rss->hash_ctrl_dma_addr, 2690 sizeof(*rss->hash_ctrl), 0); 2691 if (unlikely(rc)) 2692 return rc; 2693 2694 if (fields) 2695 *fields = rss->hash_ctrl->selected_fields[proto].fields; 2696 2697 return 0; 2698} 2699 2700int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) 2701{ 2702 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2703 struct ena_rss *rss = &ena_dev->rss; 2704 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2705 struct ena_admin_set_feat_cmd cmd; 2706 struct ena_admin_set_feat_resp resp; 2707 int ret; 2708 2709 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_INPUT)) { 2710 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", 2711 ENA_ADMIN_RSS_HASH_INPUT); 2712 return -EOPNOTSUPP; 2713 } 2714 2715 memset(&cmd, 0x0, sizeof(cmd)); 2716 2717 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2718 cmd.aq_common_descriptor.flags = 2719 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2720 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; 2721 cmd.u.flow_hash_input.enabled_input_sort = 2722 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | 2723 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 2724 2725 ret = ena_com_mem_addr_set(ena_dev, 2726 &cmd.control_buffer.address, 2727 rss->hash_ctrl_dma_addr); 2728 if (unlikely(ret)) { 2729 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 2730 return ret; 2731 } 2732 cmd.control_buffer.length = sizeof(*hash_ctrl); 2733 2734 ret = ena_com_execute_admin_command(admin_queue, 2735 (struct ena_admin_aq_entry *)&cmd, 2736 sizeof(cmd), 2737 (struct ena_admin_acq_entry *)&resp, 2738 sizeof(resp)); 2739 if (unlikely(ret)) 2740 netdev_err(ena_dev->net_device, "Failed to set hash input. error: %d\n", ret); 2741 2742 return ret; 2743} 2744 2745int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) 2746{ 2747 struct ena_rss *rss = &ena_dev->rss; 2748 struct ena_admin_feature_rss_hash_control *hash_ctrl = 2749 rss->hash_ctrl; 2750 u16 available_fields = 0; 2751 int rc, i; 2752 2753 /* Get the supported hash input */ 2754 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2755 if (unlikely(rc)) 2756 return rc; 2757 2758 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields = 2759 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2760 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2761 2762 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields = 2763 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2764 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2765 2766 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields = 2767 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2768 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2769 2770 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields = 2771 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2772 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2773 2774 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields = 2775 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2776 2777 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields = 2778 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2779 2780 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields = 2781 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2782 2783 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields = 2784 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA; 2785 2786 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) { 2787 available_fields = hash_ctrl->selected_fields[i].fields & 2788 hash_ctrl->supported_fields[i].fields; 2789 if (available_fields != hash_ctrl->selected_fields[i].fields) { 2790 netdev_err(ena_dev->net_device, 2791 "Hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", 2792 i, hash_ctrl->supported_fields[i].fields, 2793 hash_ctrl->selected_fields[i].fields); 2794 return -EOPNOTSUPP; 2795 } 2796 } 2797 2798 rc = ena_com_set_hash_ctrl(ena_dev); 2799 2800 /* In case of failure, restore the old hash ctrl */ 2801 if (unlikely(rc)) 2802 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2803 2804 return rc; 2805} 2806 2807int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 2808 enum ena_admin_flow_hash_proto proto, 2809 u16 hash_fields) 2810{ 2811 struct ena_rss *rss = &ena_dev->rss; 2812 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2813 u16 supported_fields; 2814 int rc; 2815 2816 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { 2817 netdev_err(ena_dev->net_device, "Invalid proto num (%u)\n", proto); 2818 return -EINVAL; 2819 } 2820 2821 /* Get the ctrl table */ 2822 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); 2823 if (unlikely(rc)) 2824 return rc; 2825 2826 /* Make sure all the fields are supported */ 2827 supported_fields = hash_ctrl->supported_fields[proto].fields; 2828 if ((hash_fields & supported_fields) != hash_fields) { 2829 netdev_err(ena_dev->net_device, 2830 "Proto %d doesn't support the required fields %x. supports only: %x\n", 2831 proto, hash_fields, supported_fields); 2832 } 2833 2834 hash_ctrl->selected_fields[proto].fields = hash_fields; 2835 2836 rc = ena_com_set_hash_ctrl(ena_dev); 2837 2838 /* In case of failure, restore the old hash ctrl */ 2839 if (unlikely(rc)) 2840 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2841 2842 return 0; 2843} 2844 2845int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 2846 u16 entry_idx, u16 entry_value) 2847{ 2848 struct ena_rss *rss = &ena_dev->rss; 2849 2850 if (unlikely(entry_idx >= (1 << rss->tbl_log_size))) 2851 return -EINVAL; 2852 2853 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES))) 2854 return -EINVAL; 2855 2856 rss->host_rss_ind_tbl[entry_idx] = entry_value; 2857 2858 return 0; 2859} 2860 2861int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) 2862{ 2863 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2864 struct ena_rss *rss = &ena_dev->rss; 2865 struct ena_admin_set_feat_cmd cmd; 2866 struct ena_admin_set_feat_resp resp; 2867 int ret; 2868 2869 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG)) { 2870 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", 2871 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG); 2872 return -EOPNOTSUPP; 2873 } 2874 2875 ret = ena_com_ind_tbl_convert_to_device(ena_dev); 2876 if (ret) { 2877 netdev_err(ena_dev->net_device, 2878 "Failed to convert host indirection table to device table\n"); 2879 return ret; 2880 } 2881 2882 memset(&cmd, 0x0, sizeof(cmd)); 2883 2884 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2885 cmd.aq_common_descriptor.flags = 2886 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2887 cmd.feat_common.feature_id = ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG; 2888 cmd.u.ind_table.size = rss->tbl_log_size; 2889 cmd.u.ind_table.inline_index = 0xFFFFFFFF; 2890 2891 ret = ena_com_mem_addr_set(ena_dev, 2892 &cmd.control_buffer.address, 2893 rss->rss_ind_tbl_dma_addr); 2894 if (unlikely(ret)) { 2895 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 2896 return ret; 2897 } 2898 2899 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * 2900 sizeof(struct ena_admin_rss_ind_table_entry); 2901 2902 ret = ena_com_execute_admin_command(admin_queue, 2903 (struct ena_admin_aq_entry *)&cmd, 2904 sizeof(cmd), 2905 (struct ena_admin_acq_entry *)&resp, 2906 sizeof(resp)); 2907 2908 if (unlikely(ret)) 2909 netdev_err(ena_dev->net_device, "Failed to set indirect table. error: %d\n", ret); 2910 2911 return ret; 2912} 2913 2914int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) 2915{ 2916 struct ena_rss *rss = &ena_dev->rss; 2917 struct ena_admin_get_feat_resp get_resp; 2918 u32 tbl_size; 2919 int i, rc; 2920 2921 tbl_size = (1ULL << rss->tbl_log_size) * 2922 sizeof(struct ena_admin_rss_ind_table_entry); 2923 2924 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2925 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 2926 rss->rss_ind_tbl_dma_addr, 2927 tbl_size, 0); 2928 if (unlikely(rc)) 2929 return rc; 2930 2931 if (!ind_tbl) 2932 return 0; 2933 2934 for (i = 0; i < (1 << rss->tbl_log_size); i++) 2935 ind_tbl[i] = rss->host_rss_ind_tbl[i]; 2936 2937 return 0; 2938} 2939 2940int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) 2941{ 2942 int rc; 2943 2944 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2945 2946 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); 2947 if (unlikely(rc)) 2948 goto err_indr_tbl; 2949 2950 /* The following function might return unsupported in case the 2951 * device doesn't support setting the key / hash function. We can safely 2952 * ignore this error and have indirection table support only. 2953 */ 2954 rc = ena_com_hash_key_allocate(ena_dev); 2955 if (likely(!rc)) 2956 ena_com_hash_key_fill_default_key(ena_dev); 2957 else if (rc != -EOPNOTSUPP) 2958 goto err_hash_key; 2959 2960 rc = ena_com_hash_ctrl_init(ena_dev); 2961 if (unlikely(rc)) 2962 goto err_hash_ctrl; 2963 2964 return 0; 2965 2966err_hash_ctrl: 2967 ena_com_hash_key_destroy(ena_dev); 2968err_hash_key: 2969 ena_com_indirect_table_destroy(ena_dev); 2970err_indr_tbl: 2971 2972 return rc; 2973} 2974 2975void ena_com_rss_destroy(struct ena_com_dev *ena_dev) 2976{ 2977 ena_com_indirect_table_destroy(ena_dev); 2978 ena_com_hash_key_destroy(ena_dev); 2979 ena_com_hash_ctrl_destroy(ena_dev); 2980 2981 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2982} 2983 2984int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) 2985{ 2986 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2987 2988 host_attr->host_info = dma_alloc_coherent(ena_dev->dmadev, SZ_4K, 2989 &host_attr->host_info_dma_addr, GFP_KERNEL); 2990 if (unlikely(!host_attr->host_info)) 2991 return -ENOMEM; 2992 2993 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR << 2994 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) | 2995 (ENA_COMMON_SPEC_VERSION_MINOR)); 2996 2997 return 0; 2998} 2999 3000int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 3001 u32 debug_area_size) 3002{ 3003 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 3004 3005 host_attr->debug_area_virt_addr = 3006 dma_alloc_coherent(ena_dev->dmadev, debug_area_size, 3007 &host_attr->debug_area_dma_addr, GFP_KERNEL); 3008 if (unlikely(!host_attr->debug_area_virt_addr)) { 3009 host_attr->debug_area_size = 0; 3010 return -ENOMEM; 3011 } 3012 3013 host_attr->debug_area_size = debug_area_size; 3014 3015 return 0; 3016} 3017 3018int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev) 3019{ 3020 struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics; 3021 3022 customer_metrics->buffer_len = ENA_CUSTOMER_METRICS_BUFFER_SIZE; 3023 customer_metrics->buffer_virt_addr = NULL; 3024 3025 customer_metrics->buffer_virt_addr = 3026 dma_alloc_coherent(ena_dev->dmadev, customer_metrics->buffer_len, 3027 &customer_metrics->buffer_dma_addr, GFP_KERNEL); 3028 if (!customer_metrics->buffer_virt_addr) { 3029 customer_metrics->buffer_len = 0; 3030 return -ENOMEM; 3031 } 3032 3033 return 0; 3034} 3035 3036void ena_com_delete_host_info(struct ena_com_dev *ena_dev) 3037{ 3038 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 3039 3040 if (host_attr->host_info) { 3041 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info, 3042 host_attr->host_info_dma_addr); 3043 host_attr->host_info = NULL; 3044 } 3045} 3046 3047void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) 3048{ 3049 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 3050 3051 if (host_attr->debug_area_virt_addr) { 3052 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size, 3053 host_attr->debug_area_virt_addr, host_attr->debug_area_dma_addr); 3054 host_attr->debug_area_virt_addr = NULL; 3055 } 3056} 3057 3058void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev) 3059{ 3060 struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics; 3061 3062 if (customer_metrics->buffer_virt_addr) { 3063 dma_free_coherent(ena_dev->dmadev, customer_metrics->buffer_len, 3064 customer_metrics->buffer_virt_addr, 3065 customer_metrics->buffer_dma_addr); 3066 customer_metrics->buffer_virt_addr = NULL; 3067 customer_metrics->buffer_len = 0; 3068 } 3069} 3070 3071int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) 3072{ 3073 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 3074 struct ena_com_admin_queue *admin_queue; 3075 struct ena_admin_set_feat_cmd cmd; 3076 struct ena_admin_set_feat_resp resp; 3077 3078 int ret; 3079 3080 /* Host attribute config is called before ena_com_get_dev_attr_feat 3081 * so ena_com can't check if the feature is supported. 3082 */ 3083 3084 memset(&cmd, 0x0, sizeof(cmd)); 3085 admin_queue = &ena_dev->admin_queue; 3086 3087 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 3088 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG; 3089 3090 ret = ena_com_mem_addr_set(ena_dev, 3091 &cmd.u.host_attr.debug_ba, 3092 host_attr->debug_area_dma_addr); 3093 if (unlikely(ret)) { 3094 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 3095 return ret; 3096 } 3097 3098 ret = ena_com_mem_addr_set(ena_dev, 3099 &cmd.u.host_attr.os_info_ba, 3100 host_attr->host_info_dma_addr); 3101 if (unlikely(ret)) { 3102 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 3103 return ret; 3104 } 3105 3106 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size; 3107 3108 ret = ena_com_execute_admin_command(admin_queue, 3109 (struct ena_admin_aq_entry *)&cmd, 3110 sizeof(cmd), 3111 (struct ena_admin_acq_entry *)&resp, 3112 sizeof(resp)); 3113 3114 if (unlikely(ret)) 3115 netdev_err(ena_dev->net_device, "Failed to set host attributes: %d\n", ret); 3116 3117 return ret; 3118} 3119 3120/* Interrupt moderation */ 3121bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) 3122{ 3123 return ena_com_check_supported_feature_id(ena_dev, 3124 ENA_ADMIN_INTERRUPT_MODERATION); 3125} 3126 3127static int ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev *ena_dev, 3128 u32 coalesce_usecs, 3129 u32 intr_delay_resolution, 3130 u32 *intr_moder_interval) 3131{ 3132 if (!intr_delay_resolution) { 3133 netdev_err(ena_dev->net_device, "Illegal interrupt delay granularity value\n"); 3134 return -EFAULT; 3135 } 3136 3137 *intr_moder_interval = coalesce_usecs / intr_delay_resolution; 3138 3139 return 0; 3140} 3141 3142int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 3143 u32 tx_coalesce_usecs) 3144{ 3145 return ena_com_update_nonadaptive_moderation_interval(ena_dev, 3146 tx_coalesce_usecs, 3147 ena_dev->intr_delay_resolution, 3148 &ena_dev->intr_moder_tx_interval); 3149} 3150 3151int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 3152 u32 rx_coalesce_usecs) 3153{ 3154 return ena_com_update_nonadaptive_moderation_interval(ena_dev, 3155 rx_coalesce_usecs, 3156 ena_dev->intr_delay_resolution, 3157 &ena_dev->intr_moder_rx_interval); 3158} 3159 3160int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) 3161{ 3162 struct ena_admin_get_feat_resp get_resp; 3163 u16 delay_resolution; 3164 int rc; 3165 3166 rc = ena_com_get_feature(ena_dev, &get_resp, 3167 ENA_ADMIN_INTERRUPT_MODERATION, 0); 3168 3169 if (rc) { 3170 if (rc == -EOPNOTSUPP) { 3171 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", 3172 ENA_ADMIN_INTERRUPT_MODERATION); 3173 rc = 0; 3174 } else { 3175 netdev_err(ena_dev->net_device, 3176 "Failed to get interrupt moderation admin cmd. rc: %d\n", rc); 3177 } 3178 3179 /* no moderation supported, disable adaptive support */ 3180 ena_com_disable_adaptive_moderation(ena_dev); 3181 return rc; 3182 } 3183 3184 /* if moderation is supported by device we set adaptive moderation */ 3185 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; 3186 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); 3187 3188 /* Disable adaptive moderation by default - can be enabled later */ 3189 ena_com_disable_adaptive_moderation(ena_dev); 3190 3191 return 0; 3192} 3193 3194unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) 3195{ 3196 return ena_dev->intr_moder_tx_interval; 3197} 3198 3199unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) 3200{ 3201 return ena_dev->intr_moder_rx_interval; 3202} 3203 3204int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, 3205 struct ena_admin_feature_llq_desc *llq_features, 3206 struct ena_llq_configurations *llq_default_cfg) 3207{ 3208 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 3209 int rc; 3210 3211 if (!llq_features->max_llq_num) { 3212 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3213 return 0; 3214 } 3215 3216 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg); 3217 if (rc) 3218 return rc; 3219 3220 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size - 3221 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc)); 3222 3223 if (unlikely(ena_dev->tx_max_header_size == 0)) { 3224 netdev_err(ena_dev->net_device, "The size of the LLQ entry is smaller than needed\n"); 3225 return -EINVAL; 3226 } 3227 3228 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV; 3229 3230 return 0; 3231}
~/
Read-only file preview.