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ena_admin_defs.h
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linux-6.19.14/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2/* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5#ifndef _ENA_ADMIN_H_ 6#define _ENA_ADMIN_H_ 7 8#define ENA_ADMIN_RSS_KEY_PARTS 10 9 10#define ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK 0x3F 11#define ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK 0x1F 12 13 /* customer metrics - in correlation with 14 * ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK 15 */ 16enum ena_admin_customer_metrics_id { 17 ENA_ADMIN_BW_IN_ALLOWANCE_EXCEEDED = 0, 18 ENA_ADMIN_BW_OUT_ALLOWANCE_EXCEEDED = 1, 19 ENA_ADMIN_PPS_ALLOWANCE_EXCEEDED = 2, 20 ENA_ADMIN_CONNTRACK_ALLOWANCE_EXCEEDED = 3, 21 ENA_ADMIN_LINKLOCAL_ALLOWANCE_EXCEEDED = 4, 22 ENA_ADMIN_CONNTRACK_ALLOWANCE_AVAILABLE = 5, 23}; 24 25enum ena_admin_aq_opcode { 26 ENA_ADMIN_CREATE_SQ = 1, 27 ENA_ADMIN_DESTROY_SQ = 2, 28 ENA_ADMIN_CREATE_CQ = 3, 29 ENA_ADMIN_DESTROY_CQ = 4, 30 ENA_ADMIN_GET_FEATURE = 8, 31 ENA_ADMIN_SET_FEATURE = 9, 32 ENA_ADMIN_GET_STATS = 11, 33}; 34 35enum ena_admin_aq_completion_status { 36 ENA_ADMIN_SUCCESS = 0, 37 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 38 ENA_ADMIN_BAD_OPCODE = 2, 39 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 40 ENA_ADMIN_MALFORMED_REQUEST = 4, 41 /* Additional status is provided in ACQ entry extended_status */ 42 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 43 ENA_ADMIN_UNKNOWN_ERROR = 6, 44 ENA_ADMIN_RESOURCE_BUSY = 7, 45}; 46 47/* subcommands for the set/get feature admin commands */ 48enum ena_admin_aq_feature_id { 49 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 50 ENA_ADMIN_MAX_QUEUES_NUM = 2, 51 ENA_ADMIN_HW_HINTS = 3, 52 ENA_ADMIN_LLQ = 4, 53 ENA_ADMIN_MAX_QUEUES_EXT = 7, 54 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 55 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 56 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12, 57 ENA_ADMIN_MTU = 14, 58 ENA_ADMIN_RSS_HASH_INPUT = 18, 59 ENA_ADMIN_INTERRUPT_MODERATION = 20, 60 ENA_ADMIN_AENQ_CONFIG = 26, 61 ENA_ADMIN_LINK_CONFIG = 27, 62 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 63 ENA_ADMIN_PHC_CONFIG = 29, 64 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 65}; 66 67/* device capabilities */ 68enum ena_admin_aq_caps_id { 69 ENA_ADMIN_ENI_STATS = 0, 70 /* ENA SRD customer metrics */ 71 ENA_ADMIN_ENA_SRD_INFO = 1, 72 ENA_ADMIN_CUSTOMER_METRICS = 2, 73}; 74 75enum ena_admin_placement_policy_type { 76 /* descriptors and headers are in host memory */ 77 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 78 /* descriptors and headers are in device memory (a.k.a Low Latency 79 * Queue) 80 */ 81 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 82}; 83 84enum ena_admin_link_types { 85 ENA_ADMIN_LINK_SPEED_1G = 0x1, 86 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 87 ENA_ADMIN_LINK_SPEED_5G = 0x4, 88 ENA_ADMIN_LINK_SPEED_10G = 0x8, 89 ENA_ADMIN_LINK_SPEED_25G = 0x10, 90 ENA_ADMIN_LINK_SPEED_40G = 0x20, 91 ENA_ADMIN_LINK_SPEED_50G = 0x40, 92 ENA_ADMIN_LINK_SPEED_100G = 0x80, 93 ENA_ADMIN_LINK_SPEED_200G = 0x100, 94 ENA_ADMIN_LINK_SPEED_400G = 0x200, 95}; 96 97enum ena_admin_completion_policy_type { 98 /* completion queue entry for each sq descriptor */ 99 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 100 /* completion queue entry upon request in sq descriptor */ 101 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 102 /* current queue head pointer is updated in OS memory upon sq 103 * descriptor request 104 */ 105 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 106 /* current queue head pointer is updated in OS memory for each sq 107 * descriptor 108 */ 109 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 110}; 111 112/* basic stats return ena_admin_basic_stats while extanded stats return a 113 * buffer (string format) with additional statistics per queue and per 114 * device id 115 */ 116enum ena_admin_get_stats_type { 117 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 118 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 119 /* extra HW stats for specific network interface */ 120 ENA_ADMIN_GET_STATS_TYPE_ENI = 2, 121 /* extra HW stats for ENA SRD */ 122 ENA_ADMIN_GET_STATS_TYPE_ENA_SRD = 3, 123 ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS = 4, 124}; 125 126enum ena_admin_get_stats_scope { 127 ENA_ADMIN_SPECIFIC_QUEUE = 0, 128 ENA_ADMIN_ETH_TRAFFIC = 1, 129}; 130 131enum ena_admin_phc_type { 132 ENA_ADMIN_PHC_TYPE_READLESS = 0, 133}; 134 135enum ena_admin_phc_error_flags { 136 ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP = BIT(0), 137}; 138 139/* ENA SRD configuration for ENI */ 140enum ena_admin_ena_srd_flags { 141 /* Feature enabled */ 142 ENA_ADMIN_ENA_SRD_ENABLED = BIT(0), 143 /* UDP support enabled */ 144 ENA_ADMIN_ENA_SRD_UDP_ENABLED = BIT(1), 145 /* Bypass Rx UDP ordering */ 146 ENA_ADMIN_ENA_SRD_UDP_ORDERING_BYPASS_ENABLED = BIT(2), 147}; 148 149struct ena_admin_aq_common_desc { 150 /* 11:0 : command_id 151 * 15:12 : reserved12 152 */ 153 u16 command_id; 154 155 /* as appears in ena_admin_aq_opcode */ 156 u8 opcode; 157 158 /* 0 : phase 159 * 1 : ctrl_data - control buffer address valid 160 * 2 : ctrl_data_indirect - control buffer address 161 * points to list of pages with addresses of control 162 * buffers 163 * 7:3 : reserved3 164 */ 165 u8 flags; 166}; 167 168/* used in ena_admin_aq_entry. Can point directly to control data, or to a 169 * page list chunk. Used also at the end of indirect mode page list chunks, 170 * for chaining. 171 */ 172struct ena_admin_ctrl_buff_info { 173 u32 length; 174 175 struct ena_common_mem_addr address; 176}; 177 178struct ena_admin_sq { 179 u16 sq_idx; 180 181 /* 4:0 : reserved 182 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 183 */ 184 u8 sq_identity; 185 186 u8 reserved1; 187}; 188 189struct ena_admin_aq_entry { 190 struct ena_admin_aq_common_desc aq_common_descriptor; 191 192 union { 193 u32 inline_data_w1[3]; 194 195 struct ena_admin_ctrl_buff_info control_buffer; 196 } u; 197 198 u32 inline_data_w4[12]; 199}; 200 201struct ena_admin_acq_common_desc { 202 /* command identifier to associate it with the aq descriptor 203 * 11:0 : command_id 204 * 15:12 : reserved12 205 */ 206 u16 command; 207 208 u8 status; 209 210 /* 0 : phase 211 * 7:1 : reserved1 212 */ 213 u8 flags; 214 215 u16 extended_status; 216 217 /* indicates to the driver which AQ entry has been consumed by the 218 * device and could be reused 219 */ 220 u16 sq_head_indx; 221}; 222 223struct ena_admin_acq_entry { 224 struct ena_admin_acq_common_desc acq_common_descriptor; 225 226 u32 response_specific_data[14]; 227}; 228 229struct ena_admin_aq_create_sq_cmd { 230 struct ena_admin_aq_common_desc aq_common_descriptor; 231 232 /* 4:0 : reserved0_w1 233 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 234 */ 235 u8 sq_identity; 236 237 u8 reserved8_w1; 238 239 /* 3:0 : placement_policy - Describing where the SQ 240 * descriptor ring and the SQ packet headers reside: 241 * 0x1 - descriptors and headers are in OS memory, 242 * 0x3 - descriptors and headers in device memory 243 * (a.k.a Low Latency Queue) 244 * 6:4 : completion_policy - Describing what policy 245 * to use for generation completion entry (cqe) in 246 * the CQ associated with this SQ: 0x0 - cqe for each 247 * sq descriptor, 0x1 - cqe upon request in sq 248 * descriptor, 0x2 - current queue head pointer is 249 * updated in OS memory upon sq descriptor request 250 * 0x3 - current queue head pointer is updated in OS 251 * memory for each sq descriptor 252 * 7 : reserved15_w1 253 */ 254 u8 sq_caps_2; 255 256 /* 0 : is_physically_contiguous - Described if the 257 * queue ring memory is allocated in physical 258 * contiguous pages or split. 259 * 7:1 : reserved17_w1 260 */ 261 u8 sq_caps_3; 262 263 /* associated completion queue id. This CQ must be created prior to SQ 264 * creation 265 */ 266 u16 cq_idx; 267 268 /* submission queue depth in entries */ 269 u16 sq_depth; 270 271 /* SQ physical base address in OS memory. This field should not be 272 * used for Low Latency queues. Has to be page aligned. 273 */ 274 struct ena_common_mem_addr sq_ba; 275 276 /* specifies queue head writeback location in OS memory. Valid if 277 * completion_policy is set to completion_policy_head_on_demand or 278 * completion_policy_head. Has to be cache aligned 279 */ 280 struct ena_common_mem_addr sq_head_writeback; 281 282 u32 reserved0_w7; 283 284 u32 reserved0_w8; 285}; 286 287enum ena_admin_sq_direction { 288 ENA_ADMIN_SQ_DIRECTION_TX = 1, 289 ENA_ADMIN_SQ_DIRECTION_RX = 2, 290}; 291 292struct ena_admin_acq_create_sq_resp_desc { 293 struct ena_admin_acq_common_desc acq_common_desc; 294 295 u16 sq_idx; 296 297 u16 reserved; 298 299 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 300 u32 sq_doorbell_offset; 301 302 /* low latency queue ring base address as an offset to PCIe MMIO 303 * LLQ_MEM BAR 304 */ 305 u32 llq_descriptors_offset; 306 307 /* low latency queue headers' memory as an offset to PCIe MMIO 308 * LLQ_MEM BAR 309 */ 310 u32 llq_headers_offset; 311}; 312 313struct ena_admin_aq_destroy_sq_cmd { 314 struct ena_admin_aq_common_desc aq_common_descriptor; 315 316 struct ena_admin_sq sq; 317}; 318 319struct ena_admin_acq_destroy_sq_resp_desc { 320 struct ena_admin_acq_common_desc acq_common_desc; 321}; 322 323struct ena_admin_aq_create_cq_cmd { 324 struct ena_admin_aq_common_desc aq_common_descriptor; 325 326 /* 4:0 : reserved5 327 * 5 : interrupt_mode_enabled - if set, cq operates 328 * in interrupt mode, otherwise - polling 329 * 7:6 : reserved6 330 */ 331 u8 cq_caps_1; 332 333 /* 4:0 : cq_entry_size_words - size of CQ entry in 334 * 32-bit words, valid values: 4, 8. 335 * 7:5 : reserved7 336 */ 337 u8 cq_caps_2; 338 339 /* completion queue depth in # of entries. must be power of 2 */ 340 u16 cq_depth; 341 342 /* msix vector assigned to this cq */ 343 u32 msix_vector; 344 345 /* cq physical base address in OS memory. CQ must be physically 346 * contiguous 347 */ 348 struct ena_common_mem_addr cq_ba; 349}; 350 351struct ena_admin_acq_create_cq_resp_desc { 352 struct ena_admin_acq_common_desc acq_common_desc; 353 354 u16 cq_idx; 355 356 /* actual cq depth in number of entries */ 357 u16 cq_actual_depth; 358 359 u32 numa_node_register_offset; 360 361 u32 cq_head_db_register_offset; 362 363 u32 cq_interrupt_unmask_register_offset; 364}; 365 366struct ena_admin_aq_destroy_cq_cmd { 367 struct ena_admin_aq_common_desc aq_common_descriptor; 368 369 u16 cq_idx; 370 371 u16 reserved1; 372}; 373 374struct ena_admin_acq_destroy_cq_resp_desc { 375 struct ena_admin_acq_common_desc acq_common_desc; 376}; 377 378/* ENA AQ Get Statistics command. Extended statistics are placed in control 379 * buffer pointed by AQ entry 380 */ 381struct ena_admin_aq_get_stats_cmd { 382 struct ena_admin_aq_common_desc aq_common_descriptor; 383 384 union { 385 /* command specific inline data */ 386 u32 inline_data_w1[3]; 387 388 struct ena_admin_ctrl_buff_info control_buffer; 389 } u; 390 391 /* stats type as defined in enum ena_admin_get_stats_type */ 392 u8 type; 393 394 /* stats scope defined in enum ena_admin_get_stats_scope */ 395 u8 scope; 396 397 u16 reserved3; 398 399 /* queue id. used when scope is specific_queue */ 400 u16 queue_idx; 401 402 /* device id, value 0xFFFF means mine. only privileged device can get 403 * stats of other device 404 */ 405 u16 device_id; 406 407 /* a bitmap representing the requested metric values */ 408 u64 requested_metrics; 409}; 410 411/* Basic Statistics Command. */ 412struct ena_admin_basic_stats { 413 u32 tx_bytes_low; 414 415 u32 tx_bytes_high; 416 417 u32 tx_pkts_low; 418 419 u32 tx_pkts_high; 420 421 u32 rx_bytes_low; 422 423 u32 rx_bytes_high; 424 425 u32 rx_pkts_low; 426 427 u32 rx_pkts_high; 428 429 u32 rx_drops_low; 430 431 u32 rx_drops_high; 432 433 u32 tx_drops_low; 434 435 u32 tx_drops_high; 436}; 437 438/* ENI Statistics Command. */ 439struct ena_admin_eni_stats { 440 /* The number of packets shaped due to inbound aggregate BW 441 * allowance being exceeded 442 */ 443 u64 bw_in_allowance_exceeded; 444 445 /* The number of packets shaped due to outbound aggregate BW 446 * allowance being exceeded 447 */ 448 u64 bw_out_allowance_exceeded; 449 450 /* The number of packets shaped due to PPS allowance being exceeded */ 451 u64 pps_allowance_exceeded; 452 453 /* The number of packets shaped due to connection tracking 454 * allowance being exceeded and leading to failure in establishment 455 * of new connections 456 */ 457 u64 conntrack_allowance_exceeded; 458 459 /* The number of packets shaped due to linklocal packet rate 460 * allowance being exceeded 461 */ 462 u64 linklocal_allowance_exceeded; 463}; 464 465struct ena_admin_ena_srd_stats { 466 /* Number of packets transmitted over ENA SRD */ 467 u64 ena_srd_tx_pkts; 468 469 /* Number of packets transmitted or could have been 470 * transmitted over ENA SRD 471 */ 472 u64 ena_srd_eligible_tx_pkts; 473 474 /* Number of packets received over ENA SRD */ 475 u64 ena_srd_rx_pkts; 476 477 /* Percentage of the ENA SRD resources that is in use */ 478 u64 ena_srd_resource_utilization; 479}; 480 481/* ENA SRD Statistics Command */ 482struct ena_admin_ena_srd_info { 483 /* ENA SRD configuration bitmap. See ena_admin_ena_srd_flags for 484 * details 485 */ 486 u64 flags; 487 488 struct ena_admin_ena_srd_stats ena_srd_stats; 489}; 490 491/* Customer Metrics Command. */ 492struct ena_admin_customer_metrics { 493 /* A bitmap representing the reported customer metrics according to 494 * the order they are reported 495 */ 496 u64 reported_metrics; 497}; 498 499struct ena_admin_acq_get_stats_resp { 500 struct ena_admin_acq_common_desc acq_common_desc; 501 502 union { 503 u64 raw[7]; 504 505 struct ena_admin_basic_stats basic_stats; 506 507 struct ena_admin_eni_stats eni_stats; 508 509 struct ena_admin_ena_srd_info ena_srd_info; 510 511 struct ena_admin_customer_metrics customer_metrics; 512 } u; 513}; 514 515struct ena_admin_get_set_feature_common_desc { 516 /* 1:0 : select - 0x1 - current value; 0x3 - default 517 * value 518 * 7:3 : reserved3 519 */ 520 u8 flags; 521 522 /* as appears in ena_admin_aq_feature_id */ 523 u8 feature_id; 524 525 /* The driver specifies the max feature version it supports and the 526 * device responds with the currently supported feature version. The 527 * field is zero based 528 */ 529 u8 feature_version; 530 531 u8 reserved8; 532}; 533 534struct ena_admin_device_attr_feature_desc { 535 u32 impl_id; 536 537 u32 device_version; 538 539 /* bitmap of ena_admin_aq_feature_id, which represents supported 540 * subcommands for the set/get feature admin commands. 541 */ 542 u32 supported_features; 543 544 /* bitmap of ena_admin_aq_caps_id, which represents device 545 * capabilities. 546 */ 547 u32 capabilities; 548 549 /* Indicates how many bits are used physical address access. */ 550 u32 phys_addr_width; 551 552 /* Indicates how many bits are used virtual address access. */ 553 u32 virt_addr_width; 554 555 /* unicast MAC address (in Network byte order) */ 556 u8 mac_addr[6]; 557 558 u8 reserved7[2]; 559 560 u32 max_mtu; 561}; 562 563enum ena_admin_llq_header_location { 564 /* header is in descriptor list */ 565 ENA_ADMIN_INLINE_HEADER = 1, 566 /* header in a separate ring, implies 16B descriptor list entry */ 567 ENA_ADMIN_HEADER_RING = 2, 568}; 569 570enum ena_admin_llq_ring_entry_size { 571 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 572 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 573 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 574}; 575 576enum ena_admin_llq_num_descs_before_header { 577 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 578 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 579 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 580 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 581 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 582}; 583 584/* packet descriptor list entry always starts with one or more descriptors, 585 * followed by a header. The rest of the descriptors are located in the 586 * beginning of the subsequent entry. Stride refers to how the rest of the 587 * descriptors are placed. This field is relevant only for inline header 588 * mode 589 */ 590enum ena_admin_llq_stride_ctrl { 591 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 592 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 593}; 594 595enum ena_admin_accel_mode_feat { 596 ENA_ADMIN_DISABLE_META_CACHING = 0, 597 ENA_ADMIN_LIMIT_TX_BURST = 1, 598}; 599 600struct ena_admin_accel_mode_get { 601 /* bit field of enum ena_admin_accel_mode_feat */ 602 u16 supported_flags; 603 604 /* maximum burst size between two doorbells. The size is in bytes */ 605 u16 max_tx_burst_size; 606}; 607 608struct ena_admin_accel_mode_set { 609 /* bit field of enum ena_admin_accel_mode_feat */ 610 u16 enabled_flags; 611 612 u16 reserved; 613}; 614 615struct ena_admin_accel_mode_req { 616 union { 617 u32 raw[2]; 618 619 struct ena_admin_accel_mode_get get; 620 621 struct ena_admin_accel_mode_set set; 622 } u; 623}; 624 625struct ena_admin_feature_llq_desc { 626 u32 max_llq_num; 627 628 u32 max_llq_depth; 629 630 /* specify the header locations the device supports. bitfield of enum 631 * ena_admin_llq_header_location. 632 */ 633 u16 header_location_ctrl_supported; 634 635 /* the header location the driver selected to use. */ 636 u16 header_location_ctrl_enabled; 637 638 /* if inline header is specified - this is the size of descriptor list 639 * entry. If header in a separate ring is specified - this is the size 640 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size. 641 * specify the entry sizes the device supports 642 */ 643 u16 entry_size_ctrl_supported; 644 645 /* the entry size the driver selected to use. */ 646 u16 entry_size_ctrl_enabled; 647 648 /* valid only if inline header is specified. First entry associated with 649 * the packet includes descriptors and header. Rest of the entries 650 * occupied by descriptors. This parameter defines the max number of 651 * descriptors precedding the header in the first entry. The field is 652 * bitfield of enum ena_admin_llq_num_descs_before_header and specify 653 * the values the device supports 654 */ 655 u16 desc_num_before_header_supported; 656 657 /* the desire field the driver selected to use */ 658 u16 desc_num_before_header_enabled; 659 660 /* valid only if inline was chosen. bitfield of enum 661 * ena_admin_llq_stride_ctrl 662 */ 663 u16 descriptors_stride_ctrl_supported; 664 665 /* the stride control the driver selected to use */ 666 u16 descriptors_stride_ctrl_enabled; 667 668 /* reserved */ 669 u32 reserved1; 670 671 /* accelerated low latency queues requirement. driver needs to 672 * support those requirements in order to use accelerated llq 673 */ 674 struct ena_admin_accel_mode_req accel_mode; 675}; 676 677struct ena_admin_queue_ext_feature_fields { 678 u32 max_tx_sq_num; 679 680 u32 max_tx_cq_num; 681 682 u32 max_rx_sq_num; 683 684 u32 max_rx_cq_num; 685 686 u32 max_tx_sq_depth; 687 688 u32 max_tx_cq_depth; 689 690 u32 max_rx_sq_depth; 691 692 u32 max_rx_cq_depth; 693 694 u32 max_tx_header_size; 695 696 /* Maximum Descriptors number, including meta descriptor, allowed for a 697 * single Tx packet 698 */ 699 u16 max_per_packet_tx_descs; 700 701 /* Maximum Descriptors number allowed for a single Rx packet */ 702 u16 max_per_packet_rx_descs; 703}; 704 705struct ena_admin_queue_feature_desc { 706 u32 max_sq_num; 707 708 u32 max_sq_depth; 709 710 u32 max_cq_num; 711 712 u32 max_cq_depth; 713 714 u32 max_legacy_llq_num; 715 716 u32 max_legacy_llq_depth; 717 718 u32 max_header_size; 719 720 /* Maximum Descriptors number, including meta descriptor, allowed for a 721 * single Tx packet 722 */ 723 u16 max_packet_tx_descs; 724 725 /* Maximum Descriptors number allowed for a single Rx packet */ 726 u16 max_packet_rx_descs; 727}; 728 729struct ena_admin_set_feature_mtu_desc { 730 /* exclude L2 */ 731 u32 mtu; 732}; 733 734struct ena_admin_set_feature_host_attr_desc { 735 /* host OS info base address in OS memory. host info is 4KB of 736 * physically contiguous 737 */ 738 struct ena_common_mem_addr os_info_ba; 739 740 /* host debug area base address in OS memory. debug area must be 741 * physically contiguous 742 */ 743 struct ena_common_mem_addr debug_ba; 744 745 /* debug area size */ 746 u32 debug_area_size; 747}; 748 749struct ena_admin_feature_intr_moder_desc { 750 /* interrupt delay granularity in usec */ 751 u16 intr_delay_resolution; 752 753 u16 reserved; 754}; 755 756struct ena_admin_get_feature_link_desc { 757 /* Link speed in Mb */ 758 u32 speed; 759 760 /* bit field of enum ena_admin_link types */ 761 u32 supported; 762 763 /* 0 : autoneg 764 * 1 : duplex - Full Duplex 765 * 31:2 : reserved2 766 */ 767 u32 flags; 768}; 769 770struct ena_admin_feature_aenq_desc { 771 /* bitmask for AENQ groups the device can report */ 772 u32 supported_groups; 773 774 /* bitmask for AENQ groups to report */ 775 u32 enabled_groups; 776}; 777 778struct ena_admin_feature_offload_desc { 779 /* 0 : TX_L3_csum_ipv4 780 * 1 : TX_L4_ipv4_csum_part - The checksum field 781 * should be initialized with pseudo header checksum 782 * 2 : TX_L4_ipv4_csum_full 783 * 3 : TX_L4_ipv6_csum_part - The checksum field 784 * should be initialized with pseudo header checksum 785 * 4 : TX_L4_ipv6_csum_full 786 * 5 : tso_ipv4 787 * 6 : tso_ipv6 788 * 7 : tso_ecn 789 */ 790 u32 tx; 791 792 /* Receive side supported stateless offload 793 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 794 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 795 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 796 * 3 : RX_hash - Hash calculation 797 */ 798 u32 rx_supported; 799 800 u32 rx_enabled; 801}; 802 803enum ena_admin_hash_functions { 804 ENA_ADMIN_TOEPLITZ = 1, 805 ENA_ADMIN_CRC32 = 2, 806}; 807 808struct ena_admin_feature_rss_flow_hash_control { 809 u32 key_parts; 810 811 u32 reserved; 812 813 u32 key[ENA_ADMIN_RSS_KEY_PARTS]; 814}; 815 816struct ena_admin_feature_rss_flow_hash_function { 817 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 818 u32 supported_func; 819 820 /* 7:0 : selected_func - bitmask of 821 * ena_admin_hash_functions 822 */ 823 u32 selected_func; 824 825 /* initial value */ 826 u32 init_val; 827}; 828 829/* RSS flow hash protocols */ 830enum ena_admin_flow_hash_proto { 831 ENA_ADMIN_RSS_TCP4 = 0, 832 ENA_ADMIN_RSS_UDP4 = 1, 833 ENA_ADMIN_RSS_TCP6 = 2, 834 ENA_ADMIN_RSS_UDP6 = 3, 835 ENA_ADMIN_RSS_IP4 = 4, 836 ENA_ADMIN_RSS_IP6 = 5, 837 ENA_ADMIN_RSS_IP4_FRAG = 6, 838 ENA_ADMIN_RSS_NOT_IP = 7, 839 /* TCPv6 with extension header */ 840 ENA_ADMIN_RSS_TCP6_EX = 8, 841 /* IPv6 with extension header */ 842 ENA_ADMIN_RSS_IP6_EX = 9, 843 ENA_ADMIN_RSS_PROTO_NUM = 16, 844}; 845 846/* RSS flow hash fields */ 847enum ena_admin_flow_hash_fields { 848 /* Ethernet Dest Addr */ 849 ENA_ADMIN_RSS_L2_DA = BIT(0), 850 /* Ethernet Src Addr */ 851 ENA_ADMIN_RSS_L2_SA = BIT(1), 852 /* ipv4/6 Dest Addr */ 853 ENA_ADMIN_RSS_L3_DA = BIT(2), 854 /* ipv4/6 Src Addr */ 855 ENA_ADMIN_RSS_L3_SA = BIT(3), 856 /* tcp/udp Dest Port */ 857 ENA_ADMIN_RSS_L4_DP = BIT(4), 858 /* tcp/udp Src Port */ 859 ENA_ADMIN_RSS_L4_SP = BIT(5), 860}; 861 862struct ena_admin_proto_input { 863 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 864 u16 fields; 865 866 u16 reserved2; 867}; 868 869struct ena_admin_feature_rss_hash_control { 870 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 871 872 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 873 874 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 875 876 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 877}; 878 879struct ena_admin_feature_rss_flow_hash_input { 880 /* supported hash input sorting 881 * 1 : L3_sort - support swap L3 addresses if DA is 882 * smaller than SA 883 * 2 : L4_sort - support swap L4 ports if DP smaller 884 * SP 885 */ 886 u16 supported_input_sort; 887 888 /* enabled hash input sorting 889 * 1 : enable_L3_sort - enable swap L3 addresses if 890 * DA smaller than SA 891 * 2 : enable_L4_sort - enable swap L4 ports if DP 892 * smaller than SP 893 */ 894 u16 enabled_input_sort; 895}; 896 897enum ena_admin_os_type { 898 ENA_ADMIN_OS_LINUX = 1, 899 ENA_ADMIN_OS_WIN = 2, 900 ENA_ADMIN_OS_DPDK = 3, 901 ENA_ADMIN_OS_FREEBSD = 4, 902 ENA_ADMIN_OS_IPXE = 5, 903 ENA_ADMIN_OS_ESXI = 6, 904 ENA_ADMIN_OS_GROUPS_NUM = 6, 905}; 906 907struct ena_admin_host_info { 908 /* defined in enum ena_admin_os_type */ 909 u32 os_type; 910 911 /* os distribution string format */ 912 u8 os_dist_str[128]; 913 914 /* OS distribution numeric format */ 915 u32 os_dist; 916 917 /* kernel version string format */ 918 u8 kernel_ver_str[32]; 919 920 /* Kernel version numeric format */ 921 u32 kernel_ver; 922 923 /* 7:0 : major 924 * 15:8 : minor 925 * 23:16 : sub_minor 926 * 31:24 : module_type 927 */ 928 u32 driver_version; 929 930 /* features bitmap */ 931 u32 supported_network_features[2]; 932 933 /* ENA spec version of driver */ 934 u16 ena_spec_version; 935 936 /* ENA device's Bus, Device and Function 937 * 2:0 : function 938 * 7:3 : device 939 * 15:8 : bus 940 */ 941 u16 bdf; 942 943 /* Number of CPUs */ 944 u16 num_cpus; 945 946 u16 reserved; 947 948 /* 0 : reserved 949 * 1 : rx_offset 950 * 2 : interrupt_moderation 951 * 3 : rx_buf_mirroring 952 * 4 : rss_configurable_function_key 953 * 5 : reserved 954 * 6 : rx_page_reuse 955 * 7 : reserved 956 * 8 : phc 957 * 31:9 : reserved 958 */ 959 u32 driver_supported_features; 960}; 961 962struct ena_admin_rss_ind_table_entry { 963 u16 cq_idx; 964 965 u16 reserved; 966}; 967 968struct ena_admin_feature_rss_ind_table { 969 /* min supported table size (2^min_size) */ 970 u16 min_size; 971 972 /* max supported table size (2^max_size) */ 973 u16 max_size; 974 975 /* table size (2^size) */ 976 u16 size; 977 978 u16 reserved; 979 980 /* index of the inline entry. 0xFFFFFFFF means invalid */ 981 u32 inline_index; 982 983 /* used for updating single entry, ignored when setting the entire 984 * table through the control buffer. 985 */ 986 struct ena_admin_rss_ind_table_entry inline_entry; 987}; 988 989/* When hint value is 0, driver should use its own predefined value */ 990struct ena_admin_ena_hw_hints { 991 /* value in ms */ 992 u16 mmio_read_timeout; 993 994 /* value in ms */ 995 u16 driver_watchdog_timeout; 996 997 /* Per packet tx completion timeout. value in ms */ 998 u16 missing_tx_completion_timeout; 999 1000 u16 missed_tx_completion_count_threshold_to_reset; 1001 1002 /* value in ms */ 1003 u16 admin_completion_tx_timeout; 1004 1005 u16 netdev_wd_timeout; 1006 1007 u16 max_tx_sgl_size; 1008 1009 u16 max_rx_sgl_size; 1010 1011 u16 reserved[8]; 1012}; 1013 1014struct ena_admin_get_feat_cmd { 1015 struct ena_admin_aq_common_desc aq_common_descriptor; 1016 1017 struct ena_admin_ctrl_buff_info control_buffer; 1018 1019 struct ena_admin_get_set_feature_common_desc feat_common; 1020 1021 u32 raw[11]; 1022}; 1023 1024struct ena_admin_queue_ext_feature_desc { 1025 /* version */ 1026 u8 version; 1027 1028 u8 reserved1[3]; 1029 1030 union { 1031 struct ena_admin_queue_ext_feature_fields max_queue_ext; 1032 1033 u32 raw[10]; 1034 }; 1035}; 1036 1037struct ena_admin_feature_phc_desc { 1038 /* PHC type as defined in enum ena_admin_get_phc_type, 1039 * used only for GET command. 1040 */ 1041 u8 type; 1042 1043 /* Reserved - MBZ */ 1044 u8 reserved1[3]; 1045 1046 /* PHC doorbell address as an offset to PCIe MMIO REG BAR, 1047 * used only for GET command. 1048 */ 1049 u32 doorbell_offset; 1050 1051 /* Max time for valid PHC retrieval, passing this threshold will 1052 * fail the get-time request and block PHC requests for 1053 * block_timeout_usec, used only for GET command. 1054 */ 1055 u32 expire_timeout_usec; 1056 1057 /* PHC requests block period, blocking starts if PHC request expired 1058 * in order to prevent floods on busy device, 1059 * used only for GET command. 1060 */ 1061 u32 block_timeout_usec; 1062 1063 /* Shared PHC physical address (ena_admin_phc_resp), 1064 * used only for SET command. 1065 */ 1066 struct ena_common_mem_addr output_address; 1067 1068 /* Shared PHC Size (ena_admin_phc_resp), 1069 * used only for SET command. 1070 */ 1071 u32 output_length; 1072}; 1073 1074struct ena_admin_get_feat_resp { 1075 struct ena_admin_acq_common_desc acq_common_desc; 1076 1077 union { 1078 u32 raw[14]; 1079 1080 struct ena_admin_device_attr_feature_desc dev_attr; 1081 1082 struct ena_admin_feature_llq_desc llq; 1083 1084 struct ena_admin_queue_feature_desc max_queue; 1085 1086 struct ena_admin_queue_ext_feature_desc max_queue_ext; 1087 1088 struct ena_admin_feature_aenq_desc aenq; 1089 1090 struct ena_admin_get_feature_link_desc link; 1091 1092 struct ena_admin_feature_offload_desc offload; 1093 1094 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1095 1096 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1097 1098 struct ena_admin_feature_rss_ind_table ind_table; 1099 1100 struct ena_admin_feature_intr_moder_desc intr_moderation; 1101 1102 struct ena_admin_ena_hw_hints hw_hints; 1103 1104 struct ena_admin_feature_phc_desc phc; 1105 } u; 1106}; 1107 1108struct ena_admin_set_feat_cmd { 1109 struct ena_admin_aq_common_desc aq_common_descriptor; 1110 1111 struct ena_admin_ctrl_buff_info control_buffer; 1112 1113 struct ena_admin_get_set_feature_common_desc feat_common; 1114 1115 union { 1116 u32 raw[11]; 1117 1118 /* mtu size */ 1119 struct ena_admin_set_feature_mtu_desc mtu; 1120 1121 /* host attributes */ 1122 struct ena_admin_set_feature_host_attr_desc host_attr; 1123 1124 /* AENQ configuration */ 1125 struct ena_admin_feature_aenq_desc aenq; 1126 1127 /* rss flow hash function */ 1128 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1129 1130 /* rss flow hash input */ 1131 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1132 1133 /* rss indirection table */ 1134 struct ena_admin_feature_rss_ind_table ind_table; 1135 1136 /* LLQ configuration */ 1137 struct ena_admin_feature_llq_desc llq; 1138 1139 /* PHC configuration */ 1140 struct ena_admin_feature_phc_desc phc; 1141 } u; 1142}; 1143 1144struct ena_admin_set_feat_resp { 1145 struct ena_admin_acq_common_desc acq_common_desc; 1146 1147 union { 1148 u32 raw[14]; 1149 } u; 1150}; 1151 1152struct ena_admin_aenq_common_desc { 1153 u16 group; 1154 1155 u16 syndrome; 1156 1157 /* 0 : phase 1158 * 7:1 : reserved - MBZ 1159 */ 1160 u8 flags; 1161 1162 u8 reserved1[3]; 1163 1164 u32 timestamp_low; 1165 1166 u32 timestamp_high; 1167}; 1168 1169/* asynchronous event notification groups */ 1170enum ena_admin_aenq_group { 1171 ENA_ADMIN_LINK_CHANGE = 0, 1172 ENA_ADMIN_FATAL_ERROR = 1, 1173 ENA_ADMIN_WARNING = 2, 1174 ENA_ADMIN_NOTIFICATION = 3, 1175 ENA_ADMIN_KEEP_ALIVE = 4, 1176 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 1177}; 1178 1179enum ena_admin_aenq_notification_syndrome { 1180 ENA_ADMIN_UPDATE_HINTS = 2, 1181}; 1182 1183struct ena_admin_aenq_entry { 1184 struct ena_admin_aenq_common_desc aenq_common_desc; 1185 1186 /* command specific inline data */ 1187 u32 inline_data_w4[12]; 1188}; 1189 1190struct ena_admin_aenq_link_change_desc { 1191 struct ena_admin_aenq_common_desc aenq_common_desc; 1192 1193 /* 0 : link_status */ 1194 u32 flags; 1195}; 1196 1197struct ena_admin_aenq_keep_alive_desc { 1198 struct ena_admin_aenq_common_desc aenq_common_desc; 1199 1200 u32 rx_drops_low; 1201 1202 u32 rx_drops_high; 1203 1204 u32 tx_drops_low; 1205 1206 u32 tx_drops_high; 1207}; 1208 1209struct ena_admin_ena_mmio_req_read_less_resp { 1210 u16 req_id; 1211 1212 u16 reg_off; 1213 1214 /* value is valid when poll is cleared */ 1215 u32 reg_val; 1216}; 1217 1218struct ena_admin_phc_resp { 1219 /* Request Id, received from DB register */ 1220 u16 req_id; 1221 1222 u8 reserved1[6]; 1223 1224 /* PHC timestamp (nsec) */ 1225 u64 timestamp; 1226 1227 u8 reserved2[12]; 1228 1229 /* Bit field of enum ena_admin_phc_error_flags */ 1230 u32 error_flags; 1231 1232 u8 reserved3[32]; 1233}; 1234 1235/* aq_common_desc */ 1236#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1237#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1238#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1239#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1240#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1241#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1242 1243/* sq */ 1244#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1245#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1246 1247/* acq_common_desc */ 1248#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1249#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1250 1251/* aq_create_sq_cmd */ 1252#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1253#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1254#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1255#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1256#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1257#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1258 1259/* aq_create_cq_cmd */ 1260#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1261#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1262#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1263 1264/* get_set_feature_common_desc */ 1265#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1266 1267/* get_feature_link_desc */ 1268#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1269#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1270#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1271 1272/* feature_offload_desc */ 1273#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1274#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1275#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1276#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1277#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1278#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1279#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1280#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1281#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1282#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1283#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1284#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1285#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1286#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1287#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1288#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1289#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1290#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1291#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1292#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1293#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1294#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1295 1296/* feature_rss_flow_hash_function */ 1297#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1298#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1299 1300/* feature_rss_flow_hash_input */ 1301#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1302#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1303#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1304#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1305#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1306#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1307#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1308#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1309 1310/* host_info */ 1311#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1312#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1313#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1314#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1315#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1316#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1317#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1318#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1319#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1320#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1321#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1322#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1323#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 1324#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) 1325#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 1326#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 1327#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 1328#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) 1329#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 1330#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) 1331#define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6 1332#define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) 1333#define ENA_ADMIN_HOST_INFO_PHC_SHIFT 8 1334#define ENA_ADMIN_HOST_INFO_PHC_MASK BIT(8) 1335 1336/* aenq_common_desc */ 1337#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1338 1339/* aenq_link_change_desc */ 1340#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1341 1342#endif /* _ENA_ADMIN_H_ */
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