altera_tse_main.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/* Altera Triple-Speed Ethernet MAC driver
   3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
   4 *
   5 * Contributors:
   6 *   Dalon Westergreen
   7 *   Thomas Chou
   8 *   Ian Abbott
   9 *   Yuriy Kozlov
  10 *   Tobias Klauser
  11 *   Andriy Smolskyy
  12 *   Roman Bulgakov
  13 *   Dmytro Mytarchuk
  14 *   Matthew Gerlach
  15 *
  16 * Original driver contributed by SLS.
  17 * Major updates contributed by GlobalLogic
  18 */
  19
  20#include <linux/atomic.h>
  21#include <linux/delay.h>
  22#include <linux/etherdevice.h>
  23#include <linux/if_vlan.h>
  24#include <linux/init.h>
  25#include <linux/interrupt.h>
  26#include <linux/io.h>
  27#include <linux/kernel.h>
  28#include <linux/module.h>
  29#include <linux/mii.h>
  30#include <linux/mdio/mdio-regmap.h>
  31#include <linux/netdevice.h>
  32#include <linux/of.h>
  33#include <linux/of_mdio.h>
  34#include <linux/of_net.h>
  35#include <linux/pcs-lynx.h>
  36#include <linux/phy.h>
  37#include <linux/platform_device.h>
  38#include <linux/property.h>
  39#include <linux/regmap.h>
  40#include <linux/skbuff.h>
  41#include <asm/cacheflush.h>
  42
  43#include "altera_utils.h"
  44#include "altera_tse.h"
  45#include "altera_sgdma.h"
  46#include "altera_msgdma.h"
  47
  48static atomic_t instance_count = ATOMIC_INIT(~0);
  49/* Module parameters */
  50static int debug = -1;
  51module_param(debug, int, 0644);
  52MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  53
  54static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  55					NETIF_MSG_LINK | NETIF_MSG_IFUP |
  56					NETIF_MSG_IFDOWN);
  57
  58#define RX_DESCRIPTORS 64
  59static int dma_rx_num = RX_DESCRIPTORS;
  60module_param(dma_rx_num, int, 0644);
  61MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
  62
  63#define TX_DESCRIPTORS 64
  64static int dma_tx_num = TX_DESCRIPTORS;
  65module_param(dma_tx_num, int, 0644);
  66MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
  67
  68
  69#define POLL_PHY (-1)
  70
  71/* Make sure DMA buffer size is larger than the max frame size
  72 * plus some alignment offset and a VLAN header. If the max frame size is
  73 * 1518, a VLAN header would be additional 4 bytes and additional
  74 * headroom for alignment is 2 bytes, 2048 is just fine.
  75 */
  76#define ALTERA_RXDMABUFFER_SIZE	2048
  77
  78/* Allow network stack to resume queuing packets after we've
  79 * finished transmitting at least 1/4 of the packets in the queue.
  80 */
  81#define TSE_TX_THRESH(x)	(x->tx_ring_size / 4)
  82
  83#define TXQUEUESTOP_THRESHHOLD	2
  84
  85static inline u32 tse_tx_avail(struct altera_tse_private *priv)
  86{
  87	return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
  88}
  89
  90/* MDIO specific functions
  91 */
  92static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  93{
  94	struct net_device *ndev = bus->priv;
  95	struct altera_tse_private *priv = netdev_priv(ndev);
  96
  97	/* set MDIO address */
  98	csrwr32((mii_id & 0x1f), priv->mac_dev,
  99		tse_csroffs(mdio_phy1_addr));
 100
 101	/* get the data */
 102	return csrrd32(priv->mac_dev,
 103		       tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
 104}
 105
 106static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
 107				 u16 value)
 108{
 109	struct net_device *ndev = bus->priv;
 110	struct altera_tse_private *priv = netdev_priv(ndev);
 111
 112	/* set MDIO address */
 113	csrwr32((mii_id & 0x1f), priv->mac_dev,
 114		tse_csroffs(mdio_phy1_addr));
 115
 116	/* write the data */
 117	csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
 118	return 0;
 119}
 120
 121static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
 122{
 123	struct altera_tse_private *priv = netdev_priv(dev);
 124	struct device_node *mdio_node = NULL;
 125	struct device_node *child_node = NULL;
 126	struct mii_bus *mdio = NULL;
 127	int ret;
 128
 129	for_each_child_of_node(priv->device->of_node, child_node) {
 130		if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
 131			mdio_node = child_node;
 132			break;
 133		}
 134	}
 135
 136	if (mdio_node) {
 137		netdev_dbg(dev, "FOUND MDIO subnode\n");
 138	} else {
 139		netdev_dbg(dev, "NO MDIO subnode\n");
 140		return 0;
 141	}
 142
 143	mdio = mdiobus_alloc();
 144	if (mdio == NULL) {
 145		netdev_err(dev, "Error allocating MDIO bus\n");
 146		ret = -ENOMEM;
 147		goto put_node;
 148	}
 149
 150	mdio->name = ALTERA_TSE_RESOURCE_NAME;
 151	mdio->read = &altera_tse_mdio_read;
 152	mdio->write = &altera_tse_mdio_write;
 153	snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
 154
 155	mdio->priv = dev;
 156	mdio->parent = priv->device;
 157
 158	ret = of_mdiobus_register(mdio, mdio_node);
 159	if (ret != 0) {
 160		netdev_err(dev, "Cannot register MDIO bus %s\n",
 161			   mdio->id);
 162		goto out_free_mdio;
 163	}
 164	of_node_put(mdio_node);
 165
 166	if (netif_msg_drv(priv))
 167		netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
 168
 169	priv->mdio = mdio;
 170	return 0;
 171out_free_mdio:
 172	mdiobus_free(mdio);
 173	mdio = NULL;
 174put_node:
 175	of_node_put(mdio_node);
 176	return ret;
 177}
 178
 179static void altera_tse_mdio_destroy(struct net_device *dev)
 180{
 181	struct altera_tse_private *priv = netdev_priv(dev);
 182
 183	if (priv->mdio == NULL)
 184		return;
 185
 186	if (netif_msg_drv(priv))
 187		netdev_info(dev, "MDIO bus %s: removed\n",
 188			    priv->mdio->id);
 189
 190	mdiobus_unregister(priv->mdio);
 191	mdiobus_free(priv->mdio);
 192	priv->mdio = NULL;
 193}
 194
 195static int tse_init_rx_buffer(struct altera_tse_private *priv,
 196			      struct tse_buffer *rxbuffer, int len)
 197{
 198	rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
 199	if (!rxbuffer->skb)
 200		return -ENOMEM;
 201
 202	rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
 203						len,
 204						DMA_FROM_DEVICE);
 205
 206	if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
 207		netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
 208		dev_kfree_skb_any(rxbuffer->skb);
 209		return -EINVAL;
 210	}
 211	rxbuffer->dma_addr &= (dma_addr_t)~3;
 212	rxbuffer->len = len;
 213	return 0;
 214}
 215
 216static void tse_free_rx_buffer(struct altera_tse_private *priv,
 217			       struct tse_buffer *rxbuffer)
 218{
 219	dma_addr_t dma_addr = rxbuffer->dma_addr;
 220	struct sk_buff *skb = rxbuffer->skb;
 221
 222	if (skb != NULL) {
 223		if (dma_addr)
 224			dma_unmap_single(priv->device, dma_addr,
 225					 rxbuffer->len,
 226					 DMA_FROM_DEVICE);
 227		dev_kfree_skb_any(skb);
 228		rxbuffer->skb = NULL;
 229		rxbuffer->dma_addr = 0;
 230	}
 231}
 232
 233/* Unmap and free Tx buffer resources
 234 */
 235static void tse_free_tx_buffer(struct altera_tse_private *priv,
 236			       struct tse_buffer *buffer)
 237{
 238	if (buffer->dma_addr) {
 239		if (buffer->mapped_as_page)
 240			dma_unmap_page(priv->device, buffer->dma_addr,
 241				       buffer->len, DMA_TO_DEVICE);
 242		else
 243			dma_unmap_single(priv->device, buffer->dma_addr,
 244					 buffer->len, DMA_TO_DEVICE);
 245		buffer->dma_addr = 0;
 246	}
 247	if (buffer->skb) {
 248		dev_kfree_skb_any(buffer->skb);
 249		buffer->skb = NULL;
 250	}
 251}
 252
 253static int alloc_init_skbufs(struct altera_tse_private *priv)
 254{
 255	unsigned int rx_descs = priv->rx_ring_size;
 256	unsigned int tx_descs = priv->tx_ring_size;
 257	int ret = -ENOMEM;
 258	int i;
 259
 260	/* Create Rx ring buffer */
 261	priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
 262				GFP_KERNEL);
 263	if (!priv->rx_ring)
 264		goto err_rx_ring;
 265
 266	/* Create Tx ring buffer */
 267	priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
 268				GFP_KERNEL);
 269	if (!priv->tx_ring)
 270		goto err_tx_ring;
 271
 272	priv->tx_cons = 0;
 273	priv->tx_prod = 0;
 274
 275	/* Init Rx ring */
 276	for (i = 0; i < rx_descs; i++) {
 277		ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
 278					 priv->rx_dma_buf_sz);
 279		if (ret)
 280			goto err_init_rx_buffers;
 281	}
 282
 283	priv->rx_cons = 0;
 284	priv->rx_prod = 0;
 285
 286	return 0;
 287err_init_rx_buffers:
 288	while (--i >= 0)
 289		tse_free_rx_buffer(priv, &priv->rx_ring[i]);
 290	kfree(priv->tx_ring);
 291err_tx_ring:
 292	kfree(priv->rx_ring);
 293err_rx_ring:
 294	return ret;
 295}
 296
 297static void free_skbufs(struct net_device *dev)
 298{
 299	struct altera_tse_private *priv = netdev_priv(dev);
 300	unsigned int rx_descs = priv->rx_ring_size;
 301	unsigned int tx_descs = priv->tx_ring_size;
 302	int i;
 303
 304	/* Release the DMA TX/RX socket buffers */
 305	for (i = 0; i < rx_descs; i++)
 306		tse_free_rx_buffer(priv, &priv->rx_ring[i]);
 307	for (i = 0; i < tx_descs; i++)
 308		tse_free_tx_buffer(priv, &priv->tx_ring[i]);
 309
 310
 311	kfree(priv->tx_ring);
 312}
 313
 314/* Reallocate the skb for the reception process
 315 */
 316static inline void tse_rx_refill(struct altera_tse_private *priv)
 317{
 318	unsigned int rxsize = priv->rx_ring_size;
 319	unsigned int entry;
 320	int ret;
 321
 322	for (; priv->rx_cons - priv->rx_prod > 0;
 323			priv->rx_prod++) {
 324		entry = priv->rx_prod % rxsize;
 325		if (likely(priv->rx_ring[entry].skb == NULL)) {
 326			ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
 327				priv->rx_dma_buf_sz);
 328			if (unlikely(ret != 0))
 329				break;
 330			priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
 331		}
 332	}
 333}
 334
 335/* Pull out the VLAN tag and fix up the packet
 336 */
 337static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
 338{
 339	struct ethhdr *eth_hdr;
 340	u16 vid;
 341
 342	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
 343	    !__vlan_get_tag(skb, &vid)) {
 344		eth_hdr = (struct ethhdr *)skb->data;
 345		memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
 346		skb_pull(skb, VLAN_HLEN);
 347		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
 348	}
 349}
 350
 351/* Receive a packet: retrieve and pass over to upper levels
 352 */
 353static int tse_rx(struct altera_tse_private *priv, int limit)
 354{
 355	unsigned int entry = priv->rx_cons % priv->rx_ring_size;
 356	unsigned int next_entry;
 357	unsigned int count = 0;
 358	struct sk_buff *skb;
 359	u32 rxstatus;
 360	u16 pktlength;
 361	u16 pktstatus;
 362
 363	/* Check for count < limit first as get_rx_status is changing
 364	* the response-fifo so we must process the next packet
 365	* after calling get_rx_status if a response is pending.
 366	* (reading the last byte of the response pops the value from the fifo.)
 367	*/
 368	while ((count < limit) &&
 369	       ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) {
 370		pktstatus = rxstatus >> 16;
 371		pktlength = rxstatus & 0xffff;
 372
 373		if ((pktstatus & 0xFF) || (pktlength == 0))
 374			netdev_err(priv->dev,
 375				   "RCV pktstatus %08X pktlength %08X\n",
 376				   pktstatus, pktlength);
 377
 378		/* DMA transfer from TSE starts with 2 additional bytes for
 379		 * IP payload alignment. Status returned by get_rx_status()
 380		 * contains DMA transfer length. Packet is 2 bytes shorter.
 381		 */
 382		pktlength -= 2;
 383
 384		count++;
 385		next_entry = (++priv->rx_cons) % priv->rx_ring_size;
 386
 387		skb = priv->rx_ring[entry].skb;
 388		if (unlikely(!skb)) {
 389			netdev_err(priv->dev,
 390				   "%s: Inconsistent Rx descriptor chain\n",
 391				   __func__);
 392			priv->dev->stats.rx_dropped++;
 393			break;
 394		}
 395		priv->rx_ring[entry].skb = NULL;
 396
 397		skb_put(skb, pktlength);
 398
 399		dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
 400				 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
 401
 402		if (netif_msg_pktdata(priv)) {
 403			netdev_info(priv->dev, "frame received %d bytes\n",
 404				    pktlength);
 405			print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
 406				       16, 1, skb->data, pktlength, true);
 407		}
 408
 409		tse_rx_vlan(priv->dev, skb);
 410
 411		skb->protocol = eth_type_trans(skb, priv->dev);
 412		skb_checksum_none_assert(skb);
 413
 414		napi_gro_receive(&priv->napi, skb);
 415
 416		priv->dev->stats.rx_packets++;
 417		priv->dev->stats.rx_bytes += pktlength;
 418
 419		entry = next_entry;
 420
 421		tse_rx_refill(priv);
 422	}
 423
 424	return count;
 425}
 426
 427/* Reclaim resources after transmission completes
 428 */
 429static int tse_tx_complete(struct altera_tse_private *priv)
 430{
 431	unsigned int txsize = priv->tx_ring_size;
 432	struct tse_buffer *tx_buff;
 433	unsigned int entry;
 434	int txcomplete = 0;
 435	u32 ready;
 436
 437	spin_lock(&priv->tx_lock);
 438
 439	ready = priv->dmaops->tx_completions(priv);
 440
 441	/* Free sent buffers */
 442	while (ready && (priv->tx_cons != priv->tx_prod)) {
 443		entry = priv->tx_cons % txsize;
 444		tx_buff = &priv->tx_ring[entry];
 445
 446		if (netif_msg_tx_done(priv))
 447			netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
 448				   __func__, priv->tx_prod, priv->tx_cons);
 449
 450		if (likely(tx_buff->skb))
 451			priv->dev->stats.tx_packets++;
 452
 453		tse_free_tx_buffer(priv, tx_buff);
 454		priv->tx_cons++;
 455
 456		txcomplete++;
 457		ready--;
 458	}
 459
 460	if (unlikely(netif_queue_stopped(priv->dev) &&
 461		     tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
 462		if (netif_queue_stopped(priv->dev) &&
 463		    tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
 464			if (netif_msg_tx_done(priv))
 465				netdev_dbg(priv->dev, "%s: restart transmit\n",
 466					   __func__);
 467			netif_wake_queue(priv->dev);
 468		}
 469	}
 470
 471	spin_unlock(&priv->tx_lock);
 472	return txcomplete;
 473}
 474
 475/* NAPI polling function
 476 */
 477static int tse_poll(struct napi_struct *napi, int budget)
 478{
 479	struct altera_tse_private *priv =
 480			container_of(napi, struct altera_tse_private, napi);
 481	unsigned long int flags;
 482	int rxcomplete = 0;
 483
 484	tse_tx_complete(priv);
 485
 486	rxcomplete = tse_rx(priv, budget);
 487
 488	if (rxcomplete < budget) {
 489
 490		napi_complete_done(napi, rxcomplete);
 491
 492		netdev_dbg(priv->dev,
 493			   "NAPI Complete, did %d packets with budget %d\n",
 494			   rxcomplete, budget);
 495
 496		spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
 497		priv->dmaops->enable_rxirq(priv);
 498		priv->dmaops->enable_txirq(priv);
 499		spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
 500	}
 501	return rxcomplete;
 502}
 503
 504/* DMA TX & RX FIFO interrupt routing
 505 */
 506static irqreturn_t altera_isr(int irq, void *dev_id)
 507{
 508	struct net_device *dev = dev_id;
 509	struct altera_tse_private *priv;
 510
 511	if (unlikely(!dev)) {
 512		pr_err("%s: invalid dev pointer\n", __func__);
 513		return IRQ_NONE;
 514	}
 515	priv = netdev_priv(dev);
 516
 517	spin_lock(&priv->rxdma_irq_lock);
 518	/* reset IRQs */
 519	priv->dmaops->clear_rxirq(priv);
 520	priv->dmaops->clear_txirq(priv);
 521	spin_unlock(&priv->rxdma_irq_lock);
 522
 523	if (likely(napi_schedule_prep(&priv->napi))) {
 524		spin_lock(&priv->rxdma_irq_lock);
 525		priv->dmaops->disable_rxirq(priv);
 526		priv->dmaops->disable_txirq(priv);
 527		spin_unlock(&priv->rxdma_irq_lock);
 528		__napi_schedule(&priv->napi);
 529	}
 530
 531
 532	return IRQ_HANDLED;
 533}
 534
 535/* Transmit a packet (called by the kernel). Dispatches
 536 * either the SGDMA method for transmitting or the
 537 * MSGDMA method, assumes no scatter/gather support,
 538 * implying an assumption that there's only one
 539 * physically contiguous fragment starting at
 540 * skb->data, for length of skb_headlen(skb).
 541 */
 542static netdev_tx_t tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
 543{
 544	struct altera_tse_private *priv = netdev_priv(dev);
 545	unsigned int nopaged_len = skb_headlen(skb);
 546	unsigned int txsize = priv->tx_ring_size;
 547	int nfrags = skb_shinfo(skb)->nr_frags;
 548	struct tse_buffer *buffer = NULL;
 549	netdev_tx_t ret = NETDEV_TX_OK;
 550	dma_addr_t dma_addr;
 551	unsigned int entry;
 552
 553	spin_lock_bh(&priv->tx_lock);
 554
 555	if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
 556		if (!netif_queue_stopped(dev)) {
 557			netif_stop_queue(dev);
 558			/* This is a hard error, log it. */
 559			netdev_err(priv->dev,
 560				   "%s: Tx list full when queue awake\n",
 561				   __func__);
 562		}
 563		ret = NETDEV_TX_BUSY;
 564		goto out;
 565	}
 566
 567	/* Map the first skb fragment */
 568	entry = priv->tx_prod % txsize;
 569	buffer = &priv->tx_ring[entry];
 570
 571	dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
 572				  DMA_TO_DEVICE);
 573	if (dma_mapping_error(priv->device, dma_addr)) {
 574		netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
 575		dev_kfree_skb_any(skb);
 576		ret = NETDEV_TX_OK;
 577		goto out;
 578	}
 579
 580	buffer->skb = skb;
 581	buffer->dma_addr = dma_addr;
 582	buffer->len = nopaged_len;
 583
 584	priv->dmaops->tx_buffer(priv, buffer);
 585
 586	skb_tx_timestamp(skb);
 587
 588	priv->tx_prod++;
 589	dev->stats.tx_bytes += skb->len;
 590
 591	if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
 592		if (netif_msg_hw(priv))
 593			netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
 594				   __func__);
 595		netif_stop_queue(dev);
 596	}
 597
 598out:
 599	spin_unlock_bh(&priv->tx_lock);
 600
 601	return ret;
 602}
 603
 604static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
 605{
 606	struct altera_tse_private *priv = netdev_priv(dev);
 607	struct device_node *np = priv->device->of_node;
 608	int ret;
 609
 610	ret = of_get_phy_mode(np, &priv->phy_iface);
 611
 612	/* Avoid get phy addr and create mdio if no phy is present */
 613	if (ret)
 614		return 0;
 615
 616	/* try to get PHY address from device tree, use PHY autodetection if
 617	 * no valid address is given
 618	 */
 619
 620	if (of_property_read_u32(priv->device->of_node, "phy-addr",
 621			 &priv->phy_addr)) {
 622		priv->phy_addr = POLL_PHY;
 623	}
 624
 625	if (!((priv->phy_addr == POLL_PHY) ||
 626		  ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
 627		netdev_err(dev, "invalid phy-addr specified %d\n",
 628			priv->phy_addr);
 629		return -ENODEV;
 630	}
 631
 632	/* Create/attach to MDIO bus */
 633	ret = altera_tse_mdio_create(dev,
 634					 atomic_add_return(1, &instance_count));
 635
 636	if (ret)
 637		return -ENODEV;
 638
 639	return 0;
 640}
 641
 642static void tse_update_mac_addr(struct altera_tse_private *priv, const u8 *addr)
 643{
 644	u32 msb;
 645	u32 lsb;
 646
 647	msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
 648	lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
 649
 650	/* Set primary MAC address */
 651	csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
 652	csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
 653}
 654
 655/* MAC software reset.
 656 * When reset is triggered, the MAC function completes the current
 657 * transmission or reception, and subsequently disables the transmit and
 658 * receive logic, flushes the receive FIFO buffer, and resets the statistics
 659 * counters.
 660 */
 661static int reset_mac(struct altera_tse_private *priv)
 662{
 663	int counter;
 664	u32 dat;
 665
 666	dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
 667	dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
 668	dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
 669	csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
 670
 671	counter = 0;
 672	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
 673		if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
 674				     MAC_CMDCFG_SW_RESET))
 675			break;
 676		udelay(1);
 677	}
 678
 679	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
 680		dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
 681		dat &= ~MAC_CMDCFG_SW_RESET;
 682		csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
 683		return -1;
 684	}
 685	return 0;
 686}
 687
 688/* Initialize MAC core registers
 689*/
 690static int init_mac(struct altera_tse_private *priv)
 691{
 692	unsigned int cmd = 0;
 693	u32 frm_length;
 694
 695	/* Setup Rx FIFO */
 696	csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
 697		priv->mac_dev, tse_csroffs(rx_section_empty));
 698
 699	csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
 700		tse_csroffs(rx_section_full));
 701
 702	csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
 703		tse_csroffs(rx_almost_empty));
 704
 705	csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
 706		tse_csroffs(rx_almost_full));
 707
 708	/* Setup Tx FIFO */
 709	csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
 710		priv->mac_dev, tse_csroffs(tx_section_empty));
 711
 712	csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
 713		tse_csroffs(tx_section_full));
 714
 715	csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
 716		tse_csroffs(tx_almost_empty));
 717
 718	csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
 719		tse_csroffs(tx_almost_full));
 720
 721	/* MAC Address Configuration */
 722	tse_update_mac_addr(priv, priv->dev->dev_addr);
 723
 724	/* MAC Function Configuration */
 725	frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
 726	csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
 727
 728	csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
 729		tse_csroffs(tx_ipg_length));
 730
 731	/* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
 732	 * start address
 733	 */
 734	tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
 735		    ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
 736
 737	tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
 738		      ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
 739		      ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
 740
 741	/* Set the MAC options */
 742	cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
 743	cmd &= ~MAC_CMDCFG_PAD_EN;	/* No padding Removal on Receive */
 744	cmd &= ~MAC_CMDCFG_CRC_FWD;	/* CRC Removal */
 745	cmd |= MAC_CMDCFG_RX_ERR_DISC;	/* Automatically discard frames
 746					 * with CRC errors
 747					 */
 748	cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
 749	cmd &= ~MAC_CMDCFG_TX_ENA;
 750	cmd &= ~MAC_CMDCFG_RX_ENA;
 751
 752	/* Default speed and duplex setting, full/100 */
 753	cmd &= ~MAC_CMDCFG_HD_ENA;
 754	cmd &= ~MAC_CMDCFG_ETH_SPEED;
 755	cmd &= ~MAC_CMDCFG_ENA_10;
 756
 757	csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
 758
 759	csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
 760		tse_csroffs(pause_quanta));
 761
 762	if (netif_msg_hw(priv))
 763		dev_dbg(priv->device,
 764			"MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
 765
 766	return 0;
 767}
 768
 769/* Start/stop MAC transmission logic
 770 */
 771static void tse_set_mac(struct altera_tse_private *priv, bool enable)
 772{
 773	u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
 774
 775	if (enable)
 776		value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
 777	else
 778		value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
 779
 780	csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
 781}
 782
 783/* Change the MTU
 784 */
 785static int tse_change_mtu(struct net_device *dev, int new_mtu)
 786{
 787	if (netif_running(dev)) {
 788		netdev_err(dev, "must be stopped to change its MTU\n");
 789		return -EBUSY;
 790	}
 791
 792	WRITE_ONCE(dev->mtu, new_mtu);
 793	netdev_update_features(dev);
 794
 795	return 0;
 796}
 797
 798static void altera_tse_set_mcfilter(struct net_device *dev)
 799{
 800	struct altera_tse_private *priv = netdev_priv(dev);
 801	struct netdev_hw_addr *ha;
 802	int i;
 803
 804	/* clear the hash filter */
 805	for (i = 0; i < 64; i++)
 806		csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
 807
 808	netdev_for_each_mc_addr(ha, dev) {
 809		unsigned int hash = 0;
 810		int mac_octet;
 811
 812		for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
 813			unsigned char xor_bit = 0;
 814			unsigned char octet = ha->addr[mac_octet];
 815			unsigned int bitshift;
 816
 817			for (bitshift = 0; bitshift < 8; bitshift++)
 818				xor_bit ^= ((octet >> bitshift) & 0x01);
 819
 820			hash = (hash << 1) | xor_bit;
 821		}
 822		csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
 823	}
 824}
 825
 826
 827static void altera_tse_set_mcfilterall(struct net_device *dev)
 828{
 829	struct altera_tse_private *priv = netdev_priv(dev);
 830	int i;
 831
 832	/* set the hash filter */
 833	for (i = 0; i < 64; i++)
 834		csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
 835}
 836
 837/* Set or clear the multicast filter for this adapter
 838 */
 839static void tse_set_rx_mode_hashfilter(struct net_device *dev)
 840{
 841	struct altera_tse_private *priv = netdev_priv(dev);
 842
 843	spin_lock(&priv->mac_cfg_lock);
 844
 845	if (dev->flags & IFF_PROMISC)
 846		tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
 847			    MAC_CMDCFG_PROMIS_EN);
 848
 849	if (dev->flags & IFF_ALLMULTI)
 850		altera_tse_set_mcfilterall(dev);
 851	else
 852		altera_tse_set_mcfilter(dev);
 853
 854	spin_unlock(&priv->mac_cfg_lock);
 855}
 856
 857/* Set or clear the multicast filter for this adapter
 858 */
 859static void tse_set_rx_mode(struct net_device *dev)
 860{
 861	struct altera_tse_private *priv = netdev_priv(dev);
 862
 863	spin_lock(&priv->mac_cfg_lock);
 864
 865	if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
 866	    !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
 867		tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
 868			    MAC_CMDCFG_PROMIS_EN);
 869	else
 870		tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
 871			      MAC_CMDCFG_PROMIS_EN);
 872
 873	spin_unlock(&priv->mac_cfg_lock);
 874}
 875
 876/* Open and initialize the interface
 877 */
 878static int tse_open(struct net_device *dev)
 879{
 880	struct altera_tse_private *priv = netdev_priv(dev);
 881	unsigned long flags;
 882	int ret = 0;
 883	int i;
 884
 885	/* Reset and configure TSE MAC and probe associated PHY */
 886	ret = priv->dmaops->init_dma(priv);
 887	if (ret != 0) {
 888		netdev_err(dev, "Cannot initialize DMA\n");
 889		goto phy_error;
 890	}
 891
 892	if (netif_msg_ifup(priv))
 893		netdev_warn(dev, "device MAC address %pM\n",
 894			    dev->dev_addr);
 895
 896	spin_lock(&priv->mac_cfg_lock);
 897
 898	ret = reset_mac(priv);
 899	/* Note that reset_mac will fail if the clocks are gated by the PHY
 900	 * due to the PHY being put into isolation or power down mode.
 901	 * This is not an error if reset fails due to no clock.
 902	 */
 903	if (ret)
 904		netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
 905
 906	ret = init_mac(priv);
 907	spin_unlock(&priv->mac_cfg_lock);
 908	if (ret) {
 909		netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
 910		goto alloc_skbuf_error;
 911	}
 912
 913	priv->dmaops->reset_dma(priv);
 914
 915	/* Create and initialize the TX/RX descriptors chains. */
 916	priv->rx_ring_size = dma_rx_num;
 917	priv->tx_ring_size = dma_tx_num;
 918	ret = alloc_init_skbufs(priv);
 919	if (ret) {
 920		netdev_err(dev, "DMA descriptors initialization failed\n");
 921		goto alloc_skbuf_error;
 922	}
 923
 924
 925	/* Register RX interrupt */
 926	ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
 927			  dev->name, dev);
 928	if (ret) {
 929		netdev_err(dev, "Unable to register RX interrupt %d\n",
 930			   priv->rx_irq);
 931		goto init_error;
 932	}
 933
 934	/* Register TX interrupt */
 935	ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
 936			  dev->name, dev);
 937	if (ret) {
 938		netdev_err(dev, "Unable to register TX interrupt %d\n",
 939			   priv->tx_irq);
 940		goto tx_request_irq_error;
 941	}
 942
 943	/* Enable DMA interrupts */
 944	spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
 945	priv->dmaops->enable_rxirq(priv);
 946	priv->dmaops->enable_txirq(priv);
 947
 948	/* Setup RX descriptor chain */
 949	for (i = 0; i < priv->rx_ring_size; i++)
 950		priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
 951
 952	spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
 953
 954	ret = phylink_of_phy_connect(priv->phylink, priv->device->of_node, 0);
 955	if (ret) {
 956		netdev_err(dev, "could not connect phylink (%d)\n", ret);
 957		goto tx_request_irq_error;
 958	}
 959	phylink_start(priv->phylink);
 960
 961	napi_enable(&priv->napi);
 962	netif_start_queue(dev);
 963
 964	priv->dmaops->start_rxdma(priv);
 965
 966	/* Start MAC Rx/Tx */
 967	spin_lock(&priv->mac_cfg_lock);
 968	tse_set_mac(priv, true);
 969	spin_unlock(&priv->mac_cfg_lock);
 970
 971	return 0;
 972
 973tx_request_irq_error:
 974	free_irq(priv->rx_irq, dev);
 975init_error:
 976	free_skbufs(dev);
 977alloc_skbuf_error:
 978phy_error:
 979	return ret;
 980}
 981
 982/* Stop TSE MAC interface and put the device in an inactive state
 983 */
 984static int tse_shutdown(struct net_device *dev)
 985{
 986	struct altera_tse_private *priv = netdev_priv(dev);
 987	unsigned long int flags;
 988	int ret;
 989
 990	phylink_stop(priv->phylink);
 991	phylink_disconnect_phy(priv->phylink);
 992	netif_stop_queue(dev);
 993	napi_disable(&priv->napi);
 994
 995	/* Disable DMA interrupts */
 996	spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
 997	priv->dmaops->disable_rxirq(priv);
 998	priv->dmaops->disable_txirq(priv);
 999	spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1000
1001	/* Free the IRQ lines */
1002	free_irq(priv->rx_irq, dev);
1003	free_irq(priv->tx_irq, dev);
1004
1005	/* disable and reset the MAC, empties fifo */
1006	spin_lock(&priv->mac_cfg_lock);
1007	spin_lock(&priv->tx_lock);
1008
1009	ret = reset_mac(priv);
1010	/* Note that reset_mac will fail if the clocks are gated by the PHY
1011	 * due to the PHY being put into isolation or power down mode.
1012	 * This is not an error if reset fails due to no clock.
1013	 */
1014	if (ret)
1015		netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1016	priv->dmaops->reset_dma(priv);
1017	free_skbufs(dev);
1018
1019	spin_unlock(&priv->tx_lock);
1020	spin_unlock(&priv->mac_cfg_lock);
1021
1022	priv->dmaops->uninit_dma(priv);
1023
1024	return 0;
1025}
1026
1027static struct net_device_ops altera_tse_netdev_ops = {
1028	.ndo_open		= tse_open,
1029	.ndo_stop		= tse_shutdown,
1030	.ndo_start_xmit		= tse_start_xmit,
1031	.ndo_set_mac_address	= eth_mac_addr,
1032	.ndo_set_rx_mode	= tse_set_rx_mode,
1033	.ndo_change_mtu		= tse_change_mtu,
1034	.ndo_validate_addr	= eth_validate_addr,
1035};
1036
1037static void alt_tse_mac_config(struct phylink_config *config, unsigned int mode,
1038			       const struct phylink_link_state *state)
1039{
1040	struct net_device *ndev = to_net_dev(config->dev);
1041	struct altera_tse_private *priv = netdev_priv(ndev);
1042
1043	spin_lock(&priv->mac_cfg_lock);
1044	reset_mac(priv);
1045	tse_set_mac(priv, true);
1046	spin_unlock(&priv->mac_cfg_lock);
1047}
1048
1049static void alt_tse_mac_link_down(struct phylink_config *config,
1050				  unsigned int mode, phy_interface_t interface)
1051{
1052}
1053
1054static void alt_tse_mac_link_up(struct phylink_config *config,
1055				struct phy_device *phy, unsigned int mode,
1056				phy_interface_t interface, int speed,
1057				int duplex, bool tx_pause, bool rx_pause)
1058{
1059	struct net_device *ndev = to_net_dev(config->dev);
1060	struct altera_tse_private *priv = netdev_priv(ndev);
1061	u32 ctrl;
1062
1063	ctrl = csrrd32(priv->mac_dev, tse_csroffs(command_config));
1064	ctrl &= ~(MAC_CMDCFG_ENA_10 | MAC_CMDCFG_ETH_SPEED | MAC_CMDCFG_HD_ENA);
1065
1066	if (duplex == DUPLEX_HALF)
1067		ctrl |= MAC_CMDCFG_HD_ENA;
1068
1069	if (speed == SPEED_1000)
1070		ctrl |= MAC_CMDCFG_ETH_SPEED;
1071	else if (speed == SPEED_10)
1072		ctrl |= MAC_CMDCFG_ENA_10;
1073
1074	spin_lock(&priv->mac_cfg_lock);
1075	csrwr32(ctrl, priv->mac_dev, tse_csroffs(command_config));
1076	spin_unlock(&priv->mac_cfg_lock);
1077}
1078
1079static struct phylink_pcs *alt_tse_select_pcs(struct phylink_config *config,
1080					      phy_interface_t interface)
1081{
1082	struct net_device *ndev = to_net_dev(config->dev);
1083	struct altera_tse_private *priv = netdev_priv(ndev);
1084
1085	if (interface == PHY_INTERFACE_MODE_SGMII ||
1086	    interface == PHY_INTERFACE_MODE_1000BASEX)
1087		return priv->pcs;
1088	else
1089		return NULL;
1090}
1091
1092static const struct phylink_mac_ops alt_tse_phylink_ops = {
1093	.mac_config = alt_tse_mac_config,
1094	.mac_link_down = alt_tse_mac_link_down,
1095	.mac_link_up = alt_tse_mac_link_up,
1096	.mac_select_pcs = alt_tse_select_pcs,
1097};
1098
1099static int request_and_map(struct platform_device *pdev, const char *name,
1100			   struct resource **res, void __iomem **ptr)
1101{
1102	struct device *device = &pdev->dev;
1103	struct resource *region;
1104
1105	*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1106	if (*res == NULL) {
1107		dev_err(device, "resource %s not defined\n", name);
1108		return -ENODEV;
1109	}
1110
1111	region = devm_request_mem_region(device, (*res)->start,
1112					 resource_size(*res), dev_name(device));
1113	if (region == NULL) {
1114		dev_err(device, "unable to request %s\n", name);
1115		return -EBUSY;
1116	}
1117
1118	*ptr = devm_ioremap(device, region->start,
1119				    resource_size(region));
1120	if (*ptr == NULL) {
1121		dev_err(device, "ioremap of %s failed!", name);
1122		return -ENOMEM;
1123	}
1124
1125	return 0;
1126}
1127
1128/* Probe Altera TSE MAC device
1129 */
1130static int altera_tse_probe(struct platform_device *pdev)
1131{
1132	struct regmap_config pcs_regmap_cfg;
1133	struct altera_tse_private *priv;
1134	struct mdio_regmap_config mrc;
1135	struct resource *control_port;
1136	struct regmap *pcs_regmap;
1137	struct resource *dma_res;
1138	struct resource *pcs_res;
1139	struct mii_bus *pcs_bus;
1140	struct net_device *ndev;
1141	void __iomem *descmap;
1142	int ret = -ENODEV;
1143	u32 revision;
1144
1145	ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1146	if (!ndev) {
1147		dev_err(&pdev->dev, "Could not allocate network device\n");
1148		return -ENODEV;
1149	}
1150
1151	SET_NETDEV_DEV(ndev, &pdev->dev);
1152	platform_set_drvdata(pdev, ndev);
1153
1154	priv = netdev_priv(ndev);
1155	priv->device = &pdev->dev;
1156	priv->dev = ndev;
1157	priv->msg_enable = netif_msg_init(debug, default_msg_level);
1158
1159	priv->dmaops = device_get_match_data(&pdev->dev);
1160
1161	if (priv->dmaops &&
1162	    priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1163		/* Get the mapped address to the SGDMA descriptor memory */
1164		ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1165		if (ret)
1166			goto err_free_netdev;
1167
1168		/* Start of that memory is for transmit descriptors */
1169		priv->tx_dma_desc = descmap;
1170
1171		/* First half is for tx descriptors, other half for tx */
1172		priv->txdescmem = resource_size(dma_res)/2;
1173
1174		priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1175
1176		priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1177						     priv->txdescmem));
1178		priv->rxdescmem = resource_size(dma_res)/2;
1179		priv->rxdescmem_busaddr = dma_res->start;
1180		priv->rxdescmem_busaddr += priv->txdescmem;
1181
1182		if (upper_32_bits(priv->rxdescmem_busaddr)) {
1183			dev_dbg(priv->device,
1184				"SGDMA bus addresses greater than 32-bits\n");
1185			ret = -EINVAL;
1186			goto err_free_netdev;
1187		}
1188		if (upper_32_bits(priv->txdescmem_busaddr)) {
1189			dev_dbg(priv->device,
1190				"SGDMA bus addresses greater than 32-bits\n");
1191			ret = -EINVAL;
1192			goto err_free_netdev;
1193		}
1194	} else if (priv->dmaops &&
1195		   priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1196		ret = request_and_map(pdev, "rx_resp", &dma_res,
1197				      &priv->rx_dma_resp);
1198		if (ret)
1199			goto err_free_netdev;
1200
1201		ret = request_and_map(pdev, "tx_desc", &dma_res,
1202				      &priv->tx_dma_desc);
1203		if (ret)
1204			goto err_free_netdev;
1205
1206		priv->txdescmem = resource_size(dma_res);
1207		priv->txdescmem_busaddr = dma_res->start;
1208
1209		ret = request_and_map(pdev, "rx_desc", &dma_res,
1210				      &priv->rx_dma_desc);
1211		if (ret)
1212			goto err_free_netdev;
1213
1214		priv->rxdescmem = resource_size(dma_res);
1215		priv->rxdescmem_busaddr = dma_res->start;
1216
1217	} else {
1218		ret = -ENODEV;
1219		goto err_free_netdev;
1220	}
1221
1222	if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask))) {
1223		dma_set_coherent_mask(priv->device,
1224				      DMA_BIT_MASK(priv->dmaops->dmamask));
1225	} else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32))) {
1226		dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1227	} else {
1228		ret = -EIO;
1229		goto err_free_netdev;
1230	}
1231
1232	/* MAC address space */
1233	ret = request_and_map(pdev, "control_port", &control_port,
1234			      (void __iomem **)&priv->mac_dev);
1235	if (ret)
1236		goto err_free_netdev;
1237
1238	/* xSGDMA Rx Dispatcher address space */
1239	ret = request_and_map(pdev, "rx_csr", &dma_res,
1240			      &priv->rx_dma_csr);
1241	if (ret)
1242		goto err_free_netdev;
1243
1244
1245	/* xSGDMA Tx Dispatcher address space */
1246	ret = request_and_map(pdev, "tx_csr", &dma_res,
1247			      &priv->tx_dma_csr);
1248	if (ret)
1249		goto err_free_netdev;
1250
1251	memset(&pcs_regmap_cfg, 0, sizeof(pcs_regmap_cfg));
1252	memset(&mrc, 0, sizeof(mrc));
1253	/* SGMII PCS address space. The location can vary depending on how the
1254	 * IP is integrated. We can have a resource dedicated to it at a specific
1255	 * address space, but if it's not the case, we fallback to the mdiophy0
1256	 * from the MAC's address space
1257	 */
1258	ret = request_and_map(pdev, "pcs", &pcs_res, &priv->pcs_base);
1259	if (ret) {
1260		/* If we can't find a dedicated resource for the PCS, fallback
1261		 * to the internal PCS, that has a different address stride
1262		 */
1263		priv->pcs_base = priv->mac_dev + tse_csroffs(mdio_phy0);
1264		pcs_regmap_cfg.reg_bits = 32;
1265		/* Values are MDIO-like values, on 16 bits */
1266		pcs_regmap_cfg.val_bits = 16;
1267		pcs_regmap_cfg.reg_shift = REGMAP_UPSHIFT(2);
1268	} else {
1269		pcs_regmap_cfg.reg_bits = 16;
1270		pcs_regmap_cfg.val_bits = 16;
1271		pcs_regmap_cfg.reg_shift = REGMAP_UPSHIFT(1);
1272	}
1273
1274	/* Create a regmap for the PCS so that it can be used by the PCS driver */
1275	pcs_regmap = devm_regmap_init_mmio(&pdev->dev, priv->pcs_base,
1276					   &pcs_regmap_cfg);
1277	if (IS_ERR(pcs_regmap)) {
1278		ret = PTR_ERR(pcs_regmap);
1279		goto err_free_netdev;
1280	}
1281	mrc.regmap = pcs_regmap;
1282	mrc.parent = &pdev->dev;
1283	mrc.valid_addr = 0x0;
1284	mrc.autoscan = false;
1285
1286	/* Rx IRQ */
1287	priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1288	if (priv->rx_irq == -ENXIO) {
1289		dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1290		ret = -ENXIO;
1291		goto err_free_netdev;
1292	}
1293
1294	/* Tx IRQ */
1295	priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1296	if (priv->tx_irq == -ENXIO) {
1297		dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1298		ret = -ENXIO;
1299		goto err_free_netdev;
1300	}
1301
1302	/* get FIFO depths from device tree */
1303	if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1304				 &priv->rx_fifo_depth)) {
1305		dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1306		ret = -ENXIO;
1307		goto err_free_netdev;
1308	}
1309
1310	if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1311				 &priv->tx_fifo_depth)) {
1312		dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1313		ret = -ENXIO;
1314		goto err_free_netdev;
1315	}
1316
1317	/* get hash filter settings for this instance */
1318	priv->hash_filter =
1319		of_property_read_bool(pdev->dev.of_node,
1320				      "altr,has-hash-multicast-filter");
1321
1322	/* Set hash filter to not set for now until the
1323	 * multicast filter receive issue is debugged
1324	 */
1325	priv->hash_filter = 0;
1326
1327	/* get supplemental address settings for this instance */
1328	priv->added_unicast =
1329		of_property_read_bool(pdev->dev.of_node,
1330				      "altr,has-supplementary-unicast");
1331
1332	priv->dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
1333	/* Max MTU is 1500, ETH_DATA_LEN */
1334	priv->dev->max_mtu = ETH_DATA_LEN;
1335
1336	/* Get the max mtu from the device tree. Note that the
1337	 * "max-frame-size" parameter is actually max mtu. Definition
1338	 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1339	 */
1340	of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1341			     &priv->dev->max_mtu);
1342
1343	/* The DMA buffer size already accounts for an alignment bias
1344	 * to avoid unaligned access exceptions for the NIOS processor,
1345	 */
1346	priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1347
1348	/* get default MAC address from device tree */
1349	ret = of_get_ethdev_address(pdev->dev.of_node, ndev);
1350	if (ret)
1351		eth_hw_addr_random(ndev);
1352
1353	/* get phy addr and create mdio */
1354	ret = altera_tse_phy_get_addr_mdio_create(ndev);
1355
1356	if (ret)
1357		goto err_free_netdev;
1358
1359	/* initialize netdev */
1360	ndev->mem_start = control_port->start;
1361	ndev->mem_end = control_port->end;
1362	ndev->netdev_ops = &altera_tse_netdev_ops;
1363	altera_tse_set_ethtool_ops(ndev);
1364
1365	altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1366
1367	if (priv->hash_filter)
1368		altera_tse_netdev_ops.ndo_set_rx_mode =
1369			tse_set_rx_mode_hashfilter;
1370
1371	/* Scatter/gather IO is not supported,
1372	 * so it is turned off
1373	 */
1374	ndev->hw_features &= ~NETIF_F_SG;
1375	ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1376
1377	/* VLAN offloading of tagging, stripping and filtering is not
1378	 * supported by hardware, but driver will accommodate the
1379	 * extra 4-byte VLAN tag for processing by upper layers
1380	 */
1381	ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1382
1383	/* setup NAPI interface */
1384	netif_napi_add(ndev, &priv->napi, tse_poll);
1385
1386	spin_lock_init(&priv->mac_cfg_lock);
1387	spin_lock_init(&priv->tx_lock);
1388	spin_lock_init(&priv->rxdma_irq_lock);
1389
1390	snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-pcs-mii", dev_name(&pdev->dev));
1391	pcs_bus = devm_mdio_regmap_register(&pdev->dev, &mrc);
1392	if (IS_ERR(pcs_bus)) {
1393		ret = PTR_ERR(pcs_bus);
1394		goto err_init_pcs;
1395	}
1396
1397	priv->pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);
1398	if (IS_ERR(priv->pcs)) {
1399		ret = PTR_ERR(priv->pcs);
1400		goto err_init_pcs;
1401	}
1402
1403	priv->phylink_config.dev = &ndev->dev;
1404	priv->phylink_config.type = PHYLINK_NETDEV;
1405	priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 |
1406						MAC_100 | MAC_1000FD;
1407
1408	phy_interface_set_rgmii(priv->phylink_config.supported_interfaces);
1409	__set_bit(PHY_INTERFACE_MODE_MII,
1410		  priv->phylink_config.supported_interfaces);
1411	__set_bit(PHY_INTERFACE_MODE_GMII,
1412		  priv->phylink_config.supported_interfaces);
1413	__set_bit(PHY_INTERFACE_MODE_SGMII,
1414		  priv->phylink_config.supported_interfaces);
1415	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
1416		  priv->phylink_config.supported_interfaces);
1417
1418	priv->phylink = phylink_create(&priv->phylink_config,
1419				       of_fwnode_handle(priv->device->of_node),
1420				       priv->phy_iface, &alt_tse_phylink_ops);
1421	if (IS_ERR(priv->phylink)) {
1422		dev_err(&pdev->dev, "failed to create phylink\n");
1423		ret = PTR_ERR(priv->phylink);
1424		goto err_init_phylink;
1425	}
1426
1427	ret = register_netdev(ndev);
1428	if (ret) {
1429		dev_err(&pdev->dev, "failed to register TSE net device\n");
1430		goto err_register_netdev;
1431	}
1432
1433	revision = ioread32(&priv->mac_dev->megacore_revision);
1434
1435	if (revision < 0xd00 || revision > 0xe00)
1436		netdev_warn(ndev, "TSE revision %x\n", revision);
1437
1438	if (netif_msg_probe(priv))
1439		dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1440			 (revision >> 8) & 0xff, revision & 0xff,
1441			 (unsigned long)control_port->start, priv->rx_irq,
1442			 priv->tx_irq);
1443
1444	return 0;
1445
1446err_register_netdev:
1447	phylink_destroy(priv->phylink);
1448err_init_phylink:
1449	lynx_pcs_destroy(priv->pcs);
1450err_init_pcs:
1451	netif_napi_del(&priv->napi);
1452	altera_tse_mdio_destroy(ndev);
1453err_free_netdev:
1454	free_netdev(ndev);
1455	return ret;
1456}
1457
1458/* Remove Altera TSE MAC device
1459 */
1460static void altera_tse_remove(struct platform_device *pdev)
1461{
1462	struct net_device *ndev = platform_get_drvdata(pdev);
1463	struct altera_tse_private *priv = netdev_priv(ndev);
1464
1465	platform_set_drvdata(pdev, NULL);
1466	altera_tse_mdio_destroy(ndev);
1467	unregister_netdev(ndev);
1468	phylink_destroy(priv->phylink);
1469	lynx_pcs_destroy(priv->pcs);
1470
1471	free_netdev(ndev);
1472}
1473
1474static const struct altera_dmaops altera_dtype_sgdma = {
1475	.altera_dtype = ALTERA_DTYPE_SGDMA,
1476	.dmamask = 32,
1477	.reset_dma = sgdma_reset,
1478	.enable_txirq = sgdma_enable_txirq,
1479	.enable_rxirq = sgdma_enable_rxirq,
1480	.disable_txirq = sgdma_disable_txirq,
1481	.disable_rxirq = sgdma_disable_rxirq,
1482	.clear_txirq = sgdma_clear_txirq,
1483	.clear_rxirq = sgdma_clear_rxirq,
1484	.tx_buffer = sgdma_tx_buffer,
1485	.tx_completions = sgdma_tx_completions,
1486	.add_rx_desc = sgdma_add_rx_desc,
1487	.get_rx_status = sgdma_rx_status,
1488	.init_dma = sgdma_initialize,
1489	.uninit_dma = sgdma_uninitialize,
1490	.start_rxdma = sgdma_start_rxdma,
1491};
1492
1493static const struct altera_dmaops altera_dtype_msgdma = {
1494	.altera_dtype = ALTERA_DTYPE_MSGDMA,
1495	.dmamask = 64,
1496	.reset_dma = msgdma_reset,
1497	.enable_txirq = msgdma_enable_txirq,
1498	.enable_rxirq = msgdma_enable_rxirq,
1499	.disable_txirq = msgdma_disable_txirq,
1500	.disable_rxirq = msgdma_disable_rxirq,
1501	.clear_txirq = msgdma_clear_txirq,
1502	.clear_rxirq = msgdma_clear_rxirq,
1503	.tx_buffer = msgdma_tx_buffer,
1504	.tx_completions = msgdma_tx_completions,
1505	.add_rx_desc = msgdma_add_rx_desc,
1506	.get_rx_status = msgdma_rx_status,
1507	.init_dma = msgdma_initialize,
1508	.uninit_dma = msgdma_uninitialize,
1509	.start_rxdma = msgdma_start_rxdma,
1510};
1511
1512static const struct of_device_id altera_tse_ids[] = {
1513	{ .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1514	{ .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1515	{ .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1516	{},
1517};
1518MODULE_DEVICE_TABLE(of, altera_tse_ids);
1519
1520static struct platform_driver altera_tse_driver = {
1521	.probe		= altera_tse_probe,
1522	.remove		= altera_tse_remove,
1523	.suspend	= NULL,
1524	.resume		= NULL,
1525	.driver		= {
1526		.name	= ALTERA_TSE_RESOURCE_NAME,
1527		.of_match_table = altera_tse_ids,
1528	},
1529};
1530
1531module_platform_driver(altera_tse_driver);
1532
1533MODULE_AUTHOR("Altera Corporation");
1534MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1535MODULE_LICENSE("GPL v2");