airoha_npu.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2025 AIROHA Inc
  4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
  5 */
  6
  7#include <linux/devcoredump.h>
  8#include <linux/firmware.h>
  9#include <linux/platform_device.h>
 10#include <linux/of_net.h>
 11#include <linux/of_platform.h>
 12#include <linux/of_reserved_mem.h>
 13#include <linux/regmap.h>
 14
 15#include "airoha_eth.h"
 16
 17#define NPU_EN7581_FIRMWARE_DATA		"airoha/en7581_npu_data.bin"
 18#define NPU_EN7581_FIRMWARE_RV32		"airoha/en7581_npu_rv32.bin"
 19#define NPU_AN7583_FIRMWARE_DATA		"airoha/an7583_npu_data.bin"
 20#define NPU_AN7583_FIRMWARE_RV32		"airoha/an7583_npu_rv32.bin"
 21#define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE	0x200000
 22#define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE	0x10000
 23#define NPU_DUMP_SIZE				512
 24
 25#define REG_NPU_LOCAL_SRAM		0x0
 26
 27#define NPU_PC_BASE_ADDR		0x305000
 28#define REG_PC_DBG(_n)			(0x305000 + ((_n) * 0x100))
 29
 30#define NPU_CLUSTER_BASE_ADDR		0x306000
 31
 32#define REG_CR_BOOT_TRIGGER		(NPU_CLUSTER_BASE_ADDR + 0x000)
 33#define REG_CR_BOOT_CONFIG		(NPU_CLUSTER_BASE_ADDR + 0x004)
 34#define REG_CR_BOOT_BASE(_n)		(NPU_CLUSTER_BASE_ADDR + 0x020 + ((_n) << 2))
 35
 36#define NPU_MBOX_BASE_ADDR		0x30c000
 37
 38#define REG_CR_MBOX_INT_STATUS		(NPU_MBOX_BASE_ADDR + 0x000)
 39#define MBOX_INT_STATUS_MASK		BIT(8)
 40
 41#define REG_CR_MBOX_INT_MASK(_n)	(NPU_MBOX_BASE_ADDR + 0x004 + ((_n) << 2))
 42#define REG_CR_MBQ0_CTRL(_n)		(NPU_MBOX_BASE_ADDR + 0x030 + ((_n) << 2))
 43#define REG_CR_MBQ8_CTRL(_n)		(NPU_MBOX_BASE_ADDR + 0x0b0 + ((_n) << 2))
 44#define REG_CR_NPU_MIB(_n)		(NPU_MBOX_BASE_ADDR + 0x140 + ((_n) << 2))
 45
 46#define NPU_WLAN_BASE_ADDR		0x30d000
 47
 48#define REG_IRQ_STATUS			(NPU_WLAN_BASE_ADDR + 0x030)
 49#define REG_IRQ_RXDONE(_n)		(NPU_WLAN_BASE_ADDR + ((_n) << 2) + 0x034)
 50#define NPU_IRQ_RX_MASK(_n)		((_n) == 1 ? BIT(17) : BIT(16))
 51
 52#define REG_TX_BASE(_n)			(NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x080)
 53#define REG_TX_DSCP_NUM(_n)		(NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x084)
 54#define REG_TX_CPU_IDX(_n)		(NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x088)
 55#define REG_TX_DMA_IDX(_n)		(NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x08c)
 56
 57#define REG_RX_BASE(_n)			(NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x180)
 58#define REG_RX_DSCP_NUM(_n)		(NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x184)
 59#define REG_RX_CPU_IDX(_n)		(NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x188)
 60#define REG_RX_DMA_IDX(_n)		(NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x18c)
 61
 62#define NPU_TIMER_BASE_ADDR		0x310100
 63#define REG_WDT_TIMER_CTRL(_n)		(NPU_TIMER_BASE_ADDR + ((_n) * 0x100))
 64#define WDT_EN_MASK			BIT(25)
 65#define WDT_INTR_MASK			BIT(21)
 66
 67enum {
 68	NPU_OP_SET = 1,
 69	NPU_OP_SET_NO_WAIT,
 70	NPU_OP_GET,
 71	NPU_OP_GET_NO_WAIT,
 72};
 73
 74enum {
 75	NPU_FUNC_WIFI,
 76	NPU_FUNC_TUNNEL,
 77	NPU_FUNC_NOTIFY,
 78	NPU_FUNC_DBA,
 79	NPU_FUNC_TR471,
 80	NPU_FUNC_PPE,
 81};
 82
 83enum {
 84	NPU_MBOX_ERROR,
 85	NPU_MBOX_SUCCESS,
 86};
 87
 88enum {
 89	PPE_FUNC_SET_WAIT,
 90	PPE_FUNC_SET_WAIT_HWNAT_INIT,
 91	PPE_FUNC_SET_WAIT_HWNAT_DEINIT,
 92	PPE_FUNC_SET_WAIT_API,
 93	PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP,
 94};
 95
 96enum {
 97	PPE2_SRAM_SET_ENTRY,
 98	PPE_SRAM_SET_ENTRY,
 99	PPE_SRAM_SET_VAL,
100	PPE_SRAM_RESET_VAL,
101};
102
103enum {
104	QDMA_WAN_ETHER = 1,
105	QDMA_WAN_PON_XDSL,
106};
107
108struct airoha_npu_fw {
109	const char *name;
110	int max_size;
111};
112
113struct airoha_npu_soc_data {
114	struct airoha_npu_fw fw_rv32;
115	struct airoha_npu_fw fw_data;
116};
117
118#define MBOX_MSG_FUNC_ID	GENMASK(14, 11)
119#define MBOX_MSG_STATIC_BUF	BIT(5)
120#define MBOX_MSG_STATUS		GENMASK(4, 2)
121#define MBOX_MSG_DONE		BIT(1)
122#define MBOX_MSG_WAIT_RSP	BIT(0)
123
124#define PPE_TYPE_L2B_IPV4	2
125#define PPE_TYPE_L2B_IPV4_IPV6	3
126
127struct ppe_mbox_data {
128	u32 func_type;
129	u32 func_id;
130	union {
131		struct {
132			u8 cds;
133			u8 xpon_hal_api;
134			u8 wan_xsi;
135			u8 ct_joyme4;
136			u8 max_packet;
137			u8 rsv[3];
138			u32 ppe_type;
139			u32 wan_mode;
140			u32 wan_sel;
141		} init_info;
142		struct {
143			u32 func_id;
144			u32 size;
145			u32 data;
146		} set_info;
147		struct {
148			u32 npu_stats_addr;
149			u32 foe_stats_addr;
150		} stats_info;
151	};
152};
153
154struct wlan_mbox_data {
155	u32 ifindex:4;
156	u32 func_type:4;
157	u32 func_id;
158	DECLARE_FLEX_ARRAY(u8, d);
159};
160
161static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
162			       void *p, int size)
163{
164	u16 core = 0; /* FIXME */
165	u32 val, offset = core << 4;
166	dma_addr_t dma_addr;
167	int ret;
168
169	dma_addr = dma_map_single(npu->dev, p, size, DMA_TO_DEVICE);
170	ret = dma_mapping_error(npu->dev, dma_addr);
171	if (ret)
172		return ret;
173
174	spin_lock_bh(&npu->cores[core].lock);
175
176	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr);
177	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, size);
178	regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val);
179	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1);
180	val = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) | MBOX_MSG_WAIT_RSP;
181	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(3) + offset, val);
182
183	ret = regmap_read_poll_timeout_atomic(npu->regmap,
184					      REG_CR_MBQ0_CTRL(3) + offset,
185					      val, (val & MBOX_MSG_DONE),
186					      100, 100 * MSEC_PER_SEC);
187	if (!ret && FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS)
188		ret = -EINVAL;
189
190	spin_unlock_bh(&npu->cores[core].lock);
191
192	dma_unmap_single(npu->dev, dma_addr, size, DMA_TO_DEVICE);
193
194	return ret;
195}
196
197static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr,
198				    const struct airoha_npu_fw *fw_info)
199{
200	const struct firmware *fw;
201	int ret;
202
203	ret = request_firmware(&fw, fw_info->name, dev);
204	if (ret)
205		return ret == -ENOENT ? -EPROBE_DEFER : ret;
206
207	if (fw->size > fw_info->max_size) {
208		dev_err(dev, "%s: fw size too overlimit (%zu)\n",
209			fw_info->name, fw->size);
210		ret = -E2BIG;
211		goto out;
212	}
213
214	memcpy_toio(addr, fw->data, fw->size);
215out:
216	release_firmware(fw);
217
218	return ret;
219}
220
221static int airoha_npu_run_firmware(struct device *dev, void __iomem *base,
222				   struct resource *res)
223{
224	const struct airoha_npu_soc_data *soc;
225	void __iomem *addr;
226	int ret;
227
228	soc = of_device_get_match_data(dev);
229	if (!soc)
230		return -EINVAL;
231
232	addr = devm_ioremap_resource(dev, res);
233	if (IS_ERR(addr))
234		return PTR_ERR(addr);
235
236	/* Load rv32 npu firmware */
237	ret = airoha_npu_load_firmware(dev, addr, &soc->fw_rv32);
238	if (ret)
239		return ret;
240
241	/* Load data npu firmware */
242	return airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM,
243					&soc->fw_data);
244}
245
246static irqreturn_t airoha_npu_mbox_handler(int irq, void *npu_instance)
247{
248	struct airoha_npu *npu = npu_instance;
249
250	/* clear mbox interrupt status */
251	regmap_write(npu->regmap, REG_CR_MBOX_INT_STATUS,
252		     MBOX_INT_STATUS_MASK);
253
254	/* acknowledge npu */
255	regmap_update_bits(npu->regmap, REG_CR_MBQ8_CTRL(3),
256			   MBOX_MSG_STATUS | MBOX_MSG_DONE, MBOX_MSG_DONE);
257
258	return IRQ_HANDLED;
259}
260
261static void airoha_npu_wdt_work(struct work_struct *work)
262{
263	struct airoha_npu_core *core;
264	struct airoha_npu *npu;
265	void *dump;
266	u32 val[3];
267	int c;
268
269	core = container_of(work, struct airoha_npu_core, wdt_work);
270	npu = core->npu;
271
272	dump = vzalloc(NPU_DUMP_SIZE);
273	if (!dump)
274		return;
275
276	c = core - &npu->cores[0];
277	regmap_bulk_read(npu->regmap, REG_PC_DBG(c), val, ARRAY_SIZE(val));
278	snprintf(dump, NPU_DUMP_SIZE, "PC: %08x SP: %08x LR: %08x\n",
279		 val[0], val[1], val[2]);
280
281	dev_coredumpv(npu->dev, dump, NPU_DUMP_SIZE, GFP_KERNEL);
282}
283
284static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance)
285{
286	struct airoha_npu_core *core = core_instance;
287	struct airoha_npu *npu = core->npu;
288	int c = core - &npu->cores[0];
289	u32 val;
290
291	regmap_set_bits(npu->regmap, REG_WDT_TIMER_CTRL(c), WDT_INTR_MASK);
292	if (!regmap_read(npu->regmap, REG_WDT_TIMER_CTRL(c), &val) &&
293	    FIELD_GET(WDT_EN_MASK, val))
294		schedule_work(&core->wdt_work);
295
296	return IRQ_HANDLED;
297}
298
299static int airoha_npu_ppe_init(struct airoha_npu *npu)
300{
301	struct ppe_mbox_data *ppe_data;
302	int err;
303
304	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
305	if (!ppe_data)
306		return -ENOMEM;
307
308	ppe_data->func_type = NPU_OP_SET;
309	ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT;
310	ppe_data->init_info.ppe_type = PPE_TYPE_L2B_IPV4_IPV6;
311	ppe_data->init_info.wan_mode = QDMA_WAN_ETHER;
312
313	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
314				  sizeof(*ppe_data));
315	kfree(ppe_data);
316
317	return err;
318}
319
320static int airoha_npu_ppe_deinit(struct airoha_npu *npu)
321{
322	struct ppe_mbox_data *ppe_data;
323	int err;
324
325	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
326	if (!ppe_data)
327		return -ENOMEM;
328
329	ppe_data->func_type = NPU_OP_SET;
330	ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT;
331
332	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
333				  sizeof(*ppe_data));
334	kfree(ppe_data);
335
336	return err;
337}
338
339static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu *npu,
340					     dma_addr_t foe_addr,
341					     int sram_num_entries)
342{
343	struct ppe_mbox_data *ppe_data;
344	int err;
345
346	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
347	if (!ppe_data)
348		return -ENOMEM;
349
350	ppe_data->func_type = NPU_OP_SET;
351	ppe_data->func_id = PPE_FUNC_SET_WAIT_API;
352	ppe_data->set_info.func_id = PPE_SRAM_RESET_VAL;
353	ppe_data->set_info.data = foe_addr;
354	ppe_data->set_info.size = sram_num_entries;
355
356	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
357				  sizeof(*ppe_data));
358	kfree(ppe_data);
359
360	return err;
361}
362
363static int airoha_npu_foe_commit_entry(struct airoha_npu *npu,
364				       dma_addr_t foe_addr,
365				       u32 entry_size, u32 hash, bool ppe2)
366{
367	struct ppe_mbox_data *ppe_data;
368	int err;
369
370	ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC);
371	if (!ppe_data)
372		return -ENOMEM;
373
374	ppe_data->func_type = NPU_OP_SET;
375	ppe_data->func_id = PPE_FUNC_SET_WAIT_API;
376	ppe_data->set_info.data = foe_addr;
377	ppe_data->set_info.size = entry_size;
378	ppe_data->set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY
379					  : PPE_SRAM_SET_ENTRY;
380
381	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
382				  sizeof(*ppe_data));
383	if (err)
384		goto out;
385
386	ppe_data->set_info.func_id = PPE_SRAM_SET_VAL;
387	ppe_data->set_info.data = hash;
388	ppe_data->set_info.size = sizeof(u32);
389
390	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
391				  sizeof(*ppe_data));
392out:
393	kfree(ppe_data);
394
395	return err;
396}
397
398static int airoha_npu_ppe_stats_setup(struct airoha_npu *npu,
399				      dma_addr_t foe_stats_addr,
400				      u32 num_stats_entries)
401{
402	int err, size = num_stats_entries * sizeof(*npu->stats);
403	struct ppe_mbox_data *ppe_data;
404
405	ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC);
406	if (!ppe_data)
407		return -ENOMEM;
408
409	ppe_data->func_type = NPU_OP_SET;
410	ppe_data->func_id = PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP;
411	ppe_data->stats_info.foe_stats_addr = foe_stats_addr;
412
413	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
414				  sizeof(*ppe_data));
415	if (err)
416		goto out;
417
418	npu->stats = devm_ioremap(npu->dev,
419				  ppe_data->stats_info.npu_stats_addr,
420				  size);
421	if (!npu->stats)
422		err = -ENOMEM;
423out:
424	kfree(ppe_data);
425
426	return err;
427}
428
429static int airoha_npu_wlan_msg_send(struct airoha_npu *npu, int ifindex,
430				    enum airoha_npu_wlan_set_cmd func_id,
431				    void *data, int data_len, gfp_t gfp)
432{
433	struct wlan_mbox_data *wlan_data;
434	int err, len;
435
436	len = sizeof(*wlan_data) + data_len;
437	wlan_data = kzalloc(len, gfp);
438	if (!wlan_data)
439		return -ENOMEM;
440
441	wlan_data->ifindex = ifindex;
442	wlan_data->func_type = NPU_OP_SET;
443	wlan_data->func_id = func_id;
444	memcpy(wlan_data->d, data, data_len);
445
446	err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);
447	kfree(wlan_data);
448
449	return err;
450}
451
452static int airoha_npu_wlan_msg_get(struct airoha_npu *npu, int ifindex,
453				   enum airoha_npu_wlan_get_cmd func_id,
454				   void *data, int data_len, gfp_t gfp)
455{
456	struct wlan_mbox_data *wlan_data;
457	int err, len;
458
459	len = sizeof(*wlan_data) + data_len;
460	wlan_data = kzalloc(len, gfp);
461	if (!wlan_data)
462		return -ENOMEM;
463
464	wlan_data->ifindex = ifindex;
465	wlan_data->func_type = NPU_OP_GET;
466	wlan_data->func_id = func_id;
467
468	err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);
469	if (!err)
470		memcpy(data, wlan_data->d, data_len);
471	kfree(wlan_data);
472
473	return err;
474}
475
476static int
477airoha_npu_wlan_set_reserved_memory(struct airoha_npu *npu,
478				    int ifindex, const char *name,
479				    enum airoha_npu_wlan_set_cmd func_id)
480{
481	struct device *dev = npu->dev;
482	struct resource res;
483	int err;
484	u32 val;
485
486	err = of_reserved_mem_region_to_resource_byname(dev->of_node, name,
487							&res);
488	if (err)
489		return err;
490
491	val = res.start;
492	return airoha_npu_wlan_msg_send(npu, ifindex, func_id, &val,
493					sizeof(val), GFP_KERNEL);
494}
495
496static int airoha_npu_wlan_init_memory(struct airoha_npu *npu)
497{
498	enum airoha_npu_wlan_set_cmd cmd = WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU;
499	u32 val = 0;
500	int err;
501
502	err = airoha_npu_wlan_msg_send(npu, 1, cmd, &val, sizeof(val),
503				       GFP_KERNEL);
504	if (err)
505		return err;
506
507	cmd = WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR;
508	err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-bufid", cmd);
509	if (err)
510		return err;
511
512	cmd = WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR;
513	err = airoha_npu_wlan_set_reserved_memory(npu, 0, "pkt", cmd);
514	if (err)
515		return err;
516
517	cmd = WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR;
518	err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-pkt", cmd);
519	if (err)
520		return err;
521
522	cmd = WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU;
523	return airoha_npu_wlan_msg_send(npu, 0, cmd, &val, sizeof(val),
524					GFP_KERNEL);
525}
526
527static u32 airoha_npu_wlan_queue_addr_get(struct airoha_npu *npu, int qid,
528					  bool xmit)
529{
530	if (xmit)
531		return REG_TX_BASE(qid + 2);
532
533	return REG_RX_BASE(qid);
534}
535
536static void airoha_npu_wlan_irq_status_set(struct airoha_npu *npu, u32 val)
537{
538	regmap_write(npu->regmap, REG_IRQ_STATUS, val);
539}
540
541static u32 airoha_npu_wlan_irq_status_get(struct airoha_npu *npu, int q)
542{
543	u32 val;
544
545	regmap_read(npu->regmap, REG_IRQ_STATUS, &val);
546	return val;
547}
548
549static void airoha_npu_wlan_irq_enable(struct airoha_npu *npu, int q)
550{
551	regmap_set_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q));
552}
553
554static void airoha_npu_wlan_irq_disable(struct airoha_npu *npu, int q)
555{
556	regmap_clear_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q));
557}
558
559struct airoha_npu *airoha_npu_get(struct device *dev)
560{
561	struct platform_device *pdev;
562	struct device_node *np;
563	struct airoha_npu *npu;
564
565	np = of_parse_phandle(dev->of_node, "airoha,npu", 0);
566	if (!np)
567		return ERR_PTR(-ENODEV);
568
569	pdev = of_find_device_by_node(np);
570
571	if (!pdev) {
572		dev_err(dev, "cannot find device node %s\n", np->name);
573		of_node_put(np);
574		return ERR_PTR(-ENODEV);
575	}
576	of_node_put(np);
577
578	if (!try_module_get(THIS_MODULE)) {
579		dev_err(dev, "failed to get the device driver module\n");
580		npu = ERR_PTR(-ENODEV);
581		goto error_pdev_put;
582	}
583
584	npu = platform_get_drvdata(pdev);
585	if (!npu) {
586		npu = ERR_PTR(-ENODEV);
587		goto error_module_put;
588	}
589
590	if (!device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER)) {
591		dev_err(&pdev->dev,
592			"failed to create device link to consumer %s\n",
593			dev_name(dev));
594		npu = ERR_PTR(-EINVAL);
595		goto error_module_put;
596	}
597
598	return npu;
599
600error_module_put:
601	module_put(THIS_MODULE);
602error_pdev_put:
603	platform_device_put(pdev);
604
605	return npu;
606}
607EXPORT_SYMBOL_GPL(airoha_npu_get);
608
609void airoha_npu_put(struct airoha_npu *npu)
610{
611	module_put(THIS_MODULE);
612	put_device(npu->dev);
613}
614EXPORT_SYMBOL_GPL(airoha_npu_put);
615
616static const struct airoha_npu_soc_data en7581_npu_soc_data = {
617	.fw_rv32 = {
618		.name = NPU_EN7581_FIRMWARE_RV32,
619		.max_size = NPU_EN7581_FIRMWARE_RV32_MAX_SIZE,
620	},
621	.fw_data = {
622		.name = NPU_EN7581_FIRMWARE_DATA,
623		.max_size = NPU_EN7581_FIRMWARE_DATA_MAX_SIZE,
624	},
625};
626
627static const struct airoha_npu_soc_data an7583_npu_soc_data = {
628	.fw_rv32 = {
629		.name = NPU_AN7583_FIRMWARE_RV32,
630		.max_size = NPU_EN7581_FIRMWARE_RV32_MAX_SIZE,
631	},
632	.fw_data = {
633		.name = NPU_AN7583_FIRMWARE_DATA,
634		.max_size = NPU_EN7581_FIRMWARE_DATA_MAX_SIZE,
635	},
636};
637
638static const struct of_device_id of_airoha_npu_match[] = {
639	{ .compatible = "airoha,en7581-npu", .data = &en7581_npu_soc_data },
640	{ .compatible = "airoha,an7583-npu", .data = &an7583_npu_soc_data },
641	{ /* sentinel */ }
642};
643MODULE_DEVICE_TABLE(of, of_airoha_npu_match);
644
645static const struct regmap_config regmap_config = {
646	.name			= "npu",
647	.reg_bits		= 32,
648	.val_bits		= 32,
649	.reg_stride		= 4,
650	.disable_locking	= true,
651};
652
653static int airoha_npu_probe(struct platform_device *pdev)
654{
655	struct device *dev = &pdev->dev;
656	struct airoha_npu *npu;
657	struct resource res;
658	void __iomem *base;
659	int i, irq, err;
660
661	base = devm_platform_ioremap_resource(pdev, 0);
662	if (IS_ERR(base))
663		return PTR_ERR(base);
664
665	npu = devm_kzalloc(dev, sizeof(*npu), GFP_KERNEL);
666	if (!npu)
667		return -ENOMEM;
668
669	npu->dev = dev;
670	npu->ops.ppe_init = airoha_npu_ppe_init;
671	npu->ops.ppe_deinit = airoha_npu_ppe_deinit;
672	npu->ops.ppe_init_stats = airoha_npu_ppe_stats_setup;
673	npu->ops.ppe_flush_sram_entries = airoha_npu_ppe_flush_sram_entries;
674	npu->ops.ppe_foe_commit_entry = airoha_npu_foe_commit_entry;
675	npu->ops.wlan_init_reserved_memory = airoha_npu_wlan_init_memory;
676	npu->ops.wlan_send_msg = airoha_npu_wlan_msg_send;
677	npu->ops.wlan_get_msg = airoha_npu_wlan_msg_get;
678	npu->ops.wlan_get_queue_addr = airoha_npu_wlan_queue_addr_get;
679	npu->ops.wlan_set_irq_status = airoha_npu_wlan_irq_status_set;
680	npu->ops.wlan_get_irq_status = airoha_npu_wlan_irq_status_get;
681	npu->ops.wlan_enable_irq = airoha_npu_wlan_irq_enable;
682	npu->ops.wlan_disable_irq = airoha_npu_wlan_irq_disable;
683
684	npu->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
685	if (IS_ERR(npu->regmap))
686		return PTR_ERR(npu->regmap);
687
688	err = of_reserved_mem_region_to_resource(dev->of_node, 0, &res);
689	if (err)
690		return err;
691
692	irq = platform_get_irq(pdev, 0);
693	if (irq < 0)
694		return irq;
695
696	err = devm_request_irq(dev, irq, airoha_npu_mbox_handler,
697			       IRQF_SHARED, "airoha-npu-mbox", npu);
698	if (err)
699		return err;
700
701	for (i = 0; i < ARRAY_SIZE(npu->cores); i++) {
702		struct airoha_npu_core *core = &npu->cores[i];
703
704		spin_lock_init(&core->lock);
705		core->npu = npu;
706
707		irq = platform_get_irq(pdev, i + 1);
708		if (irq < 0)
709			return irq;
710
711		err = devm_request_irq(dev, irq, airoha_npu_wdt_handler,
712				       IRQF_SHARED, "airoha-npu-wdt", core);
713		if (err)
714			return err;
715
716		INIT_WORK(&core->wdt_work, airoha_npu_wdt_work);
717	}
718
719	/* wlan IRQ lines */
720	for (i = 0; i < ARRAY_SIZE(npu->irqs); i++) {
721		irq = platform_get_irq(pdev, i + ARRAY_SIZE(npu->cores) + 1);
722		if (irq < 0)
723			return irq;
724
725		npu->irqs[i] = irq;
726	}
727
728	err = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
729	if (err)
730		return err;
731
732	err = airoha_npu_run_firmware(dev, base, &res);
733	if (err)
734		return dev_err_probe(dev, err, "failed to run npu firmware\n");
735
736	regmap_write(npu->regmap, REG_CR_NPU_MIB(10),
737		     res.start + NPU_EN7581_FIRMWARE_RV32_MAX_SIZE);
738	regmap_write(npu->regmap, REG_CR_NPU_MIB(11), 0x40000); /* SRAM 256K */
739	regmap_write(npu->regmap, REG_CR_NPU_MIB(12), 0);
740	regmap_write(npu->regmap, REG_CR_NPU_MIB(21), 1);
741	msleep(100);
742
743	/* setting booting address */
744	for (i = 0; i < NPU_NUM_CORES; i++)
745		regmap_write(npu->regmap, REG_CR_BOOT_BASE(i), res.start);
746	usleep_range(1000, 2000);
747
748	/* enable NPU cores */
749	regmap_write(npu->regmap, REG_CR_BOOT_CONFIG, 0xff);
750	regmap_write(npu->regmap, REG_CR_BOOT_TRIGGER, 0x1);
751	msleep(100);
752
753	platform_set_drvdata(pdev, npu);
754
755	return 0;
756}
757
758static void airoha_npu_remove(struct platform_device *pdev)
759{
760	struct airoha_npu *npu = platform_get_drvdata(pdev);
761	int i;
762
763	for (i = 0; i < ARRAY_SIZE(npu->cores); i++)
764		cancel_work_sync(&npu->cores[i].wdt_work);
765}
766
767static struct platform_driver airoha_npu_driver = {
768	.probe = airoha_npu_probe,
769	.remove = airoha_npu_remove,
770	.driver = {
771		.name = "airoha-npu",
772		.of_match_table = of_airoha_npu_match,
773	},
774};
775module_platform_driver(airoha_npu_driver);
776
777MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_DATA);
778MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_RV32);
779MODULE_FIRMWARE(NPU_AN7583_FIRMWARE_DATA);
780MODULE_FIRMWARE(NPU_AN7583_FIRMWARE_RV32);
781MODULE_LICENSE("GPL");
782MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
783MODULE_DESCRIPTION("Airoha Network Processor Unit driver");