airoha_eth.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2024 AIROHA Inc
  4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
  5 */
  6
  7#ifndef AIROHA_ETH_H
  8#define AIROHA_ETH_H
  9
 10#include <linux/debugfs.h>
 11#include <linux/etherdevice.h>
 12#include <linux/iopoll.h>
 13#include <linux/kernel.h>
 14#include <linux/netdevice.h>
 15#include <linux/reset.h>
 16#include <linux/soc/airoha/airoha_offload.h>
 17#include <net/dsa.h>
 18
 19#define AIROHA_MAX_NUM_GDM_PORTS	4
 20#define AIROHA_MAX_NUM_QDMA		2
 21#define AIROHA_MAX_NUM_IRQ_BANKS	4
 22#define AIROHA_MAX_DSA_PORTS		7
 23#define AIROHA_MAX_NUM_RSTS		3
 24#define AIROHA_MAX_MTU			9216
 25#define AIROHA_MAX_PACKET_SIZE		2048
 26#define AIROHA_NUM_QOS_CHANNELS		4
 27#define AIROHA_NUM_QOS_QUEUES		8
 28#define AIROHA_NUM_TX_RING		32
 29#define AIROHA_NUM_RX_RING		32
 30#define AIROHA_NUM_NETDEV_TX_RINGS	(AIROHA_NUM_TX_RING + \
 31					 AIROHA_NUM_QOS_CHANNELS)
 32#define AIROHA_FE_MC_MAX_VLAN_TABLE	64
 33#define AIROHA_FE_MC_MAX_VLAN_PORT	16
 34#define AIROHA_NUM_TX_IRQ		2
 35#define HW_DSCP_NUM			2048
 36#define IRQ_QUEUE_LEN(_n)		((_n) ? 1024 : 2048)
 37#define TX_DSCP_NUM			1024
 38#define RX_DSCP_NUM(_n)			\
 39	((_n) ==  2 ? 128 :		\
 40	 (_n) == 11 ? 128 :		\
 41	 (_n) == 15 ? 128 :		\
 42	 (_n) ==  0 ? 1024 : 16)
 43
 44#define PSE_RSV_PAGES			128
 45#define PSE_QUEUE_RSV_PAGES		64
 46
 47#define QDMA_METER_IDX(_n)		((_n) & 0xff)
 48#define QDMA_METER_GROUP(_n)		(((_n) >> 8) & 0x3)
 49
 50#define PPE_SRAM_NUM_ENTRIES		(8 * 1024)
 51#define PPE_STATS_NUM_ENTRIES		(4 * 1024)
 52#define PPE_DRAM_NUM_ENTRIES		(16 * 1024)
 53#define PPE_ENTRY_SIZE			80
 54#define PPE_RAM_NUM_ENTRIES_SHIFT(_n)	(__ffs((_n) >> 10))
 55
 56#define MTK_HDR_LEN			4
 57#define MTK_HDR_XMIT_TAGGED_TPID_8100	1
 58#define MTK_HDR_XMIT_TAGGED_TPID_88A8	2
 59
 60enum {
 61	QDMA_INT_REG_IDX0,
 62	QDMA_INT_REG_IDX1,
 63	QDMA_INT_REG_IDX2,
 64	QDMA_INT_REG_IDX3,
 65	QDMA_INT_REG_IDX4,
 66	QDMA_INT_REG_MAX
 67};
 68
 69enum {
 70	HSGMII_LAN_7581_PCIE0_SRCPORT	= 0x16,
 71	HSGMII_LAN_7581_PCIE1_SRCPORT,
 72	HSGMII_LAN_7581_ETH_SRCPORT,
 73	HSGMII_LAN_7581_USB_SRCPORT,
 74};
 75
 76enum {
 77	HSGMII_LAN_7583_ETH_SRCPORT	= 0x16,
 78	HSGMII_LAN_7583_PCIE_SRCPORT	= 0x18,
 79	HSGMII_LAN_7583_USB_SRCPORT,
 80};
 81
 82enum {
 83	XSI_PCIE0_VIP_PORT_MASK	= BIT(22),
 84	XSI_PCIE1_VIP_PORT_MASK	= BIT(23),
 85	XSI_USB_VIP_PORT_MASK	= BIT(25),
 86	XSI_ETH_VIP_PORT_MASK	= BIT(24),
 87};
 88
 89enum {
 90	DEV_STATE_INITIALIZED,
 91};
 92
 93enum {
 94	CDM_CRSN_QSEL_Q1 = 1,
 95	CDM_CRSN_QSEL_Q5 = 5,
 96	CDM_CRSN_QSEL_Q6 = 6,
 97	CDM_CRSN_QSEL_Q15 = 15,
 98};
 99
100enum {
101	CRSN_08 = 0x8,
102	CRSN_21 = 0x15, /* KA */
103	CRSN_22 = 0x16, /* hit bind and force route to CPU */
104	CRSN_24 = 0x18,
105	CRSN_25 = 0x19,
106};
107
108enum airoha_gdm_index {
109	AIROHA_GDM1_IDX = 1,
110	AIROHA_GDM2_IDX = 2,
111	AIROHA_GDM3_IDX = 3,
112	AIROHA_GDM4_IDX = 4,
113};
114
115enum {
116	FE_PSE_PORT_CDM1,
117	FE_PSE_PORT_GDM1,
118	FE_PSE_PORT_GDM2,
119	FE_PSE_PORT_GDM3,
120	FE_PSE_PORT_PPE1,
121	FE_PSE_PORT_CDM2,
122	FE_PSE_PORT_CDM3,
123	FE_PSE_PORT_CDM4,
124	FE_PSE_PORT_PPE2,
125	FE_PSE_PORT_GDM4,
126	FE_PSE_PORT_CDM5,
127	FE_PSE_PORT_DROP = 0xf,
128};
129
130enum tx_sched_mode {
131	TC_SCH_WRR8,
132	TC_SCH_SP,
133	TC_SCH_WRR7,
134	TC_SCH_WRR6,
135	TC_SCH_WRR5,
136	TC_SCH_WRR4,
137	TC_SCH_WRR3,
138	TC_SCH_WRR2,
139};
140
141enum trtcm_unit_type {
142	TRTCM_BYTE_UNIT,
143	TRTCM_PACKET_UNIT,
144};
145
146enum trtcm_param_type {
147	TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */
148	TRTCM_TOKEN_RATE_MODE,
149	TRTCM_BUCKETSIZE_SHIFT_MODE,
150	TRTCM_BUCKET_COUNTER_MODE,
151};
152
153enum trtcm_mode_type {
154	TRTCM_COMMIT_MODE,
155	TRTCM_PEAK_MODE,
156};
157
158enum trtcm_param {
159	TRTCM_TICK_SEL = BIT(0),
160	TRTCM_PKT_MODE = BIT(1),
161	TRTCM_METER_MODE = BIT(2),
162};
163
164#define MIN_TOKEN_SIZE				4096
165#define MAX_TOKEN_SIZE_OFFSET			17
166#define TRTCM_TOKEN_RATE_MASK			GENMASK(23, 6)
167#define TRTCM_TOKEN_RATE_FRACTION_MASK		GENMASK(5, 0)
168
169struct airoha_queue_entry {
170	union {
171		void *buf;
172		struct {
173			struct list_head list;
174			struct sk_buff *skb;
175		};
176	};
177	dma_addr_t dma_addr;
178	u16 dma_len;
179};
180
181struct airoha_queue {
182	struct airoha_qdma *qdma;
183
184	/* protect concurrent queue accesses */
185	spinlock_t lock;
186	struct airoha_queue_entry *entry;
187	struct airoha_qdma_desc *desc;
188	u16 head;
189	u16 tail;
190
191	int queued;
192	int ndesc;
193	int free_thr;
194	int buf_size;
195
196	struct napi_struct napi;
197	struct page_pool *page_pool;
198	struct sk_buff *skb;
199
200	struct list_head tx_list;
201};
202
203struct airoha_tx_irq_queue {
204	struct airoha_qdma *qdma;
205
206	struct napi_struct napi;
207
208	int size;
209	u32 *q;
210};
211
212struct airoha_hw_stats {
213	/* protect concurrent hw_stats accesses */
214	spinlock_t lock;
215	struct u64_stats_sync syncp;
216
217	/* get_stats64 */
218	u64 rx_ok_pkts;
219	u64 tx_ok_pkts;
220	u64 rx_ok_bytes;
221	u64 tx_ok_bytes;
222	u64 rx_multicast;
223	u64 rx_errors;
224	u64 rx_drops;
225	u64 tx_drops;
226	u64 rx_crc_error;
227	u64 rx_over_errors;
228	/* ethtool stats */
229	u64 tx_broadcast;
230	u64 tx_multicast;
231	u64 tx_len[7];
232	u64 rx_broadcast;
233	u64 rx_fragment;
234	u64 rx_jabber;
235	u64 rx_len[7];
236};
237
238enum {
239	AIROHA_FOE_STATE_INVALID,
240	AIROHA_FOE_STATE_UNBIND,
241	AIROHA_FOE_STATE_BIND,
242	AIROHA_FOE_STATE_FIN
243};
244
245enum {
246	PPE_PKT_TYPE_IPV4_HNAPT = 0,
247	PPE_PKT_TYPE_IPV4_ROUTE = 1,
248	PPE_PKT_TYPE_BRIDGE = 2,
249	PPE_PKT_TYPE_IPV4_DSLITE = 3,
250	PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,
251	PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,
252	PPE_PKT_TYPE_IPV6_6RD = 7,
253};
254
255#define AIROHA_FOE_MAC_SMAC_ID		GENMASK(20, 16)
256#define AIROHA_FOE_MAC_PPPOE_ID		GENMASK(15, 0)
257
258#define AIROHA_FOE_MAC_WDMA_QOS		GENMASK(15, 12)
259#define AIROHA_FOE_MAC_WDMA_BAND	BIT(11)
260#define AIROHA_FOE_MAC_WDMA_WCID	GENMASK(10, 0)
261
262struct airoha_foe_mac_info_common {
263	u16 vlan1;
264	u16 etype;
265
266	u32 dest_mac_hi;
267
268	u16 vlan2;
269	u16 dest_mac_lo;
270
271	u32 src_mac_hi;
272};
273
274struct airoha_foe_mac_info {
275	struct airoha_foe_mac_info_common common;
276
277	u16 pppoe_id;
278	u16 src_mac_lo;
279
280	u32 meter;
281};
282
283#define AIROHA_FOE_IB1_UNBIND_PREBIND		BIT(24)
284#define AIROHA_FOE_IB1_UNBIND_PACKETS		GENMASK(23, 8)
285#define AIROHA_FOE_IB1_UNBIND_TIMESTAMP		GENMASK(7, 0)
286
287#define AIROHA_FOE_IB1_BIND_STATIC		BIT(31)
288#define AIROHA_FOE_IB1_BIND_UDP			BIT(30)
289#define AIROHA_FOE_IB1_BIND_STATE		GENMASK(29, 28)
290#define AIROHA_FOE_IB1_BIND_PACKET_TYPE		GENMASK(27, 25)
291#define AIROHA_FOE_IB1_BIND_TTL			BIT(24)
292#define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP	BIT(23)
293#define AIROHA_FOE_IB1_BIND_PPPOE		BIT(22)
294#define AIROHA_FOE_IB1_BIND_VPM			GENMASK(21, 20)
295#define AIROHA_FOE_IB1_BIND_VLAN_LAYER		GENMASK(19, 16)
296#define AIROHA_FOE_IB1_BIND_KEEPALIVE		BIT(15)
297#define AIROHA_FOE_IB1_BIND_TIMESTAMP		GENMASK(14, 0)
298
299#define AIROHA_FOE_IB2_DSCP			GENMASK(31, 24)
300#define AIROHA_FOE_IB2_PORT_AG			GENMASK(23, 13)
301#define AIROHA_FOE_IB2_PCP			BIT(12)
302#define AIROHA_FOE_IB2_MULTICAST		BIT(11)
303#define AIROHA_FOE_IB2_FAST_PATH		BIT(10)
304#define AIROHA_FOE_IB2_PSE_QOS			BIT(9)
305#define AIROHA_FOE_IB2_PSE_PORT			GENMASK(8, 5)
306#define AIROHA_FOE_IB2_NBQ			GENMASK(4, 0)
307
308#define AIROHA_FOE_ACTDP			GENMASK(31, 24)
309#define AIROHA_FOE_SHAPER_ID			GENMASK(23, 16)
310#define AIROHA_FOE_CHANNEL			GENMASK(15, 11)
311#define AIROHA_FOE_QID				GENMASK(10, 8)
312#define AIROHA_FOE_DPI				BIT(7)
313#define AIROHA_FOE_TUNNEL			BIT(6)
314#define AIROHA_FOE_TUNNEL_ID			GENMASK(5, 0)
315
316#define AIROHA_FOE_TUNNEL_MTU			GENMASK(31, 16)
317#define AIROHA_FOE_ACNT_GRP3			GENMASK(15, 9)
318#define AIROHA_FOE_METER_GRP3			GENMASK(8, 5)
319#define AIROHA_FOE_METER_GRP2			GENMASK(4, 0)
320
321struct airoha_foe_bridge {
322	u32 dest_mac_hi;
323
324	u16 src_mac_hi;
325	u16 dest_mac_lo;
326
327	u32 src_mac_lo;
328
329	u32 ib2;
330
331	u32 rsv[5];
332
333	u32 data;
334
335	struct airoha_foe_mac_info l2;
336};
337
338struct airoha_foe_ipv4_tuple {
339	u32 src_ip;
340	u32 dest_ip;
341	union {
342		struct {
343			u16 dest_port;
344			u16 src_port;
345		};
346		struct {
347			u8 protocol;
348			u8 _pad[3]; /* fill with 0xa5a5a5 */
349		};
350		u32 ports;
351	};
352};
353
354struct airoha_foe_ipv4 {
355	struct airoha_foe_ipv4_tuple orig_tuple;
356
357	u32 ib2;
358
359	struct airoha_foe_ipv4_tuple new_tuple;
360
361	u32 rsv[2];
362
363	u32 data;
364
365	struct airoha_foe_mac_info l2;
366};
367
368struct airoha_foe_ipv4_dslite {
369	struct airoha_foe_ipv4_tuple ip4;
370
371	u32 ib2;
372
373	u8 flow_label[3];
374	u8 priority;
375
376	u32 rsv[4];
377
378	u32 data;
379
380	struct airoha_foe_mac_info l2;
381};
382
383struct airoha_foe_ipv6 {
384	u32 src_ip[4];
385	u32 dest_ip[4];
386
387	union {
388		struct {
389			u16 dest_port;
390			u16 src_port;
391		};
392		struct {
393			u8 protocol;
394			u8 pad[3];
395		};
396		u32 ports;
397	};
398
399	u32 data;
400
401	u32 ib2;
402
403	struct airoha_foe_mac_info_common l2;
404
405	u32 meter;
406};
407
408struct airoha_foe_entry {
409	union {
410		struct {
411			u32 ib1;
412			union {
413				struct airoha_foe_bridge bridge;
414				struct airoha_foe_ipv4 ipv4;
415				struct airoha_foe_ipv4_dslite dslite;
416				struct airoha_foe_ipv6 ipv6;
417				DECLARE_FLEX_ARRAY(u32, d);
418			};
419		};
420		u8 data[PPE_ENTRY_SIZE];
421	};
422};
423
424struct airoha_foe_stats {
425	u32 bytes;
426	u32 packets;
427};
428
429struct airoha_foe_stats64 {
430	u64 bytes;
431	u64 packets;
432};
433
434struct airoha_flow_data {
435	struct ethhdr eth;
436
437	union {
438		struct {
439			__be32 src_addr;
440			__be32 dst_addr;
441		} v4;
442
443		struct {
444			struct in6_addr src_addr;
445			struct in6_addr dst_addr;
446		} v6;
447	};
448
449	__be16 src_port;
450	__be16 dst_port;
451
452	struct {
453		struct {
454			u16 id;
455			__be16 proto;
456		} hdr[2];
457		u8 num;
458	} vlan;
459	struct {
460		u16 sid;
461		u8 num;
462	} pppoe;
463};
464
465enum airoha_flow_entry_type {
466	FLOW_TYPE_L4,
467	FLOW_TYPE_L2,
468	FLOW_TYPE_L2_SUBFLOW,
469};
470
471struct airoha_flow_table_entry {
472	union {
473		struct hlist_node list; /* PPE L3 flow entry */
474		struct {
475			struct rhash_head l2_node;  /* L2 flow entry */
476			struct hlist_head l2_flows; /* PPE L2 subflows list */
477		};
478	};
479
480	struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */
481	u32 hash;
482
483	struct airoha_foe_stats64 stats;
484	enum airoha_flow_entry_type type;
485
486	struct rhash_head node;
487	unsigned long cookie;
488
489	/* Must be last --ends in a flexible-array member. */
490	struct airoha_foe_entry data;
491};
492
493struct airoha_wdma_info {
494	u8 idx;
495	u8 queue;
496	u16 wcid;
497	u8 bss;
498};
499
500/* RX queue to IRQ mapping: BIT(q) in IRQ(n) */
501#define RX_IRQ0_BANK_PIN_MASK			0x839f
502#define RX_IRQ1_BANK_PIN_MASK			0x7fe00000
503#define RX_IRQ2_BANK_PIN_MASK			0x20
504#define RX_IRQ3_BANK_PIN_MASK			0x40
505#define RX_IRQ_BANK_PIN_MASK(_n)		\
506	(((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK :	\
507	 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK :	\
508	 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK :	\
509	 RX_IRQ0_BANK_PIN_MASK)
510
511struct airoha_irq_bank {
512	struct airoha_qdma *qdma;
513
514	/* protect concurrent irqmask accesses */
515	spinlock_t irq_lock;
516	u32 irqmask[QDMA_INT_REG_MAX];
517	int irq;
518};
519
520struct airoha_qdma {
521	struct airoha_eth *eth;
522	void __iomem *regs;
523
524	atomic_t users;
525
526	struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS];
527
528	struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ];
529
530	struct airoha_queue q_tx[AIROHA_NUM_TX_RING];
531	struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
532};
533
534struct airoha_gdm_port {
535	struct airoha_qdma *qdma;
536	struct net_device *dev;
537	int id;
538
539	struct airoha_hw_stats stats;
540
541	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
542
543	/* qos stats counters */
544	u64 cpu_tx_packets;
545	u64 fwd_tx_packets;
546
547	struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
548};
549
550#define AIROHA_RXD4_PPE_CPU_REASON	GENMASK(20, 16)
551#define AIROHA_RXD4_FOE_ENTRY		GENMASK(15, 0)
552
553struct airoha_ppe {
554	struct airoha_ppe_dev dev;
555	struct airoha_eth *eth;
556
557	void *foe;
558	dma_addr_t foe_dma;
559
560	struct rhashtable l2_flows;
561
562	struct hlist_head *foe_flow;
563	u16 *foe_check_time;
564
565	struct airoha_foe_stats *foe_stats;
566	dma_addr_t foe_stats_dma;
567
568	struct dentry *debugfs_dir;
569};
570
571struct airoha_eth_soc_data {
572	u16 version;
573	const char * const *xsi_rsts_names;
574	int num_xsi_rsts;
575	int num_ppe;
576	struct {
577		int (*get_src_port_id)(struct airoha_gdm_port *port, int nbq);
578	} ops;
579};
580
581struct airoha_eth {
582	struct device *dev;
583
584	const struct airoha_eth_soc_data *soc;
585
586	unsigned long state;
587	void __iomem *fe_regs;
588
589	struct airoha_npu __rcu *npu;
590
591	struct airoha_ppe *ppe;
592	struct rhashtable flow_table;
593
594	struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS];
595	struct reset_control_bulk_data *xsi_rsts;
596
597	struct net_device *napi_dev;
598
599	struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA];
600	struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
601};
602
603u32 airoha_rr(void __iomem *base, u32 offset);
604void airoha_wr(void __iomem *base, u32 offset, u32 val);
605u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
606
607#define airoha_fe_rr(eth, offset)				\
608	airoha_rr((eth)->fe_regs, (offset))
609#define airoha_fe_wr(eth, offset, val)				\
610	airoha_wr((eth)->fe_regs, (offset), (val))
611#define airoha_fe_rmw(eth, offset, mask, val)			\
612	airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
613#define airoha_fe_set(eth, offset, val)				\
614	airoha_rmw((eth)->fe_regs, (offset), 0, (val))
615#define airoha_fe_clear(eth, offset, val)			\
616	airoha_rmw((eth)->fe_regs, (offset), (val), 0)
617
618#define airoha_qdma_rr(qdma, offset)				\
619	airoha_rr((qdma)->regs, (offset))
620#define airoha_qdma_wr(qdma, offset, val)			\
621	airoha_wr((qdma)->regs, (offset), (val))
622#define airoha_qdma_rmw(qdma, offset, mask, val)		\
623	airoha_rmw((qdma)->regs, (offset), (mask), (val))
624#define airoha_qdma_set(qdma, offset, val)			\
625	airoha_rmw((qdma)->regs, (offset), 0, (val))
626#define airoha_qdma_clear(qdma, offset, val)			\
627	airoha_rmw((qdma)->regs, (offset), (val), 0)
628
629static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
630{
631	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
632	 * GDM{2,3,4} can be used as wan port connected to an external
633	 * phy module.
634	 */
635	return port->id == 1;
636}
637
638static inline bool airoha_is_7581(struct airoha_eth *eth)
639{
640	return eth->soc->version == 0x7581;
641}
642
643static inline bool airoha_is_7583(struct airoha_eth *eth)
644{
645	return eth->soc->version == 0x7583;
646}
647
648bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
649			      struct airoha_gdm_port *port);
650
651bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index);
652void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb,
653			  u16 hash, bool rx_wlan);
654int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data);
655int airoha_ppe_init(struct airoha_eth *eth);
656void airoha_ppe_deinit(struct airoha_eth *eth);
657void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port);
658u32 airoha_ppe_get_total_num_entries(struct airoha_ppe *ppe);
659struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
660						  u32 hash);
661void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
662				    struct airoha_foe_stats64 *stats);
663
664#ifdef CONFIG_DEBUG_FS
665int airoha_ppe_debugfs_init(struct airoha_ppe *ppe);
666#else
667static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe)
668{
669	return 0;
670}
671#endif
672
673#endif /* AIROHA_ETH_H */