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airoha_eth.c
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linux-6.19.14/drivers/net/ethernet/airoha/airoha_eth.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6#include <linux/of.h> 7#include <linux/of_net.h> 8#include <linux/of_reserved_mem.h> 9#include <linux/platform_device.h> 10#include <linux/tcp.h> 11#include <linux/u64_stats_sync.h> 12#include <net/dst_metadata.h> 13#include <net/page_pool/helpers.h> 14#include <net/pkt_cls.h> 15#include <uapi/linux/ppp_defs.h> 16 17#include "airoha_regs.h" 18#include "airoha_eth.h" 19 20u32 airoha_rr(void __iomem *base, u32 offset) 21{ 22 return readl(base + offset); 23} 24 25void airoha_wr(void __iomem *base, u32 offset, u32 val) 26{ 27 writel(val, base + offset); 28} 29 30u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 31{ 32 val |= (airoha_rr(base, offset) & ~mask); 33 airoha_wr(base, offset, val); 34 35 return val; 36} 37 38static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank, 39 int index, u32 clear, u32 set) 40{ 41 struct airoha_qdma *qdma = irq_bank->qdma; 42 int bank = irq_bank - &qdma->irq_banks[0]; 43 unsigned long flags; 44 45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) 46 return; 47 48 spin_lock_irqsave(&irq_bank->irq_lock, flags); 49 50 irq_bank->irqmask[index] &= ~clear; 51 irq_bank->irqmask[index] |= set; 52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), 53 irq_bank->irqmask[index]); 54 /* Read irq_enable register in order to guarantee the update above 55 * completes in the spinlock critical section. 56 */ 57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); 58 59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags); 60} 61 62static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank, 63 int index, u32 mask) 64{ 65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask); 66} 67 68static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank, 69 int index, u32 mask) 70{ 71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0); 72} 73 74static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr) 75{ 76 struct airoha_eth *eth = port->qdma->eth; 77 u32 val, reg; 78 79 reg = airhoa_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H 80 : REG_FE_WAN_MAC_H; 81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2]; 82 airoha_fe_wr(eth, reg, val); 83 84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5]; 85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val); 86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val); 87 88 airoha_ppe_init_upd_mem(port); 89} 90 91static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr, 92 u32 val) 93{ 94 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK, 95 FIELD_PREP(GDM_OCFQ_MASK, val)); 96 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK, 97 FIELD_PREP(GDM_MCFQ_MASK, val)); 98 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK, 99 FIELD_PREP(GDM_BCFQ_MASK, val)); 100 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK, 101 FIELD_PREP(GDM_UCFQ_MASK, val)); 102} 103 104static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 105 bool enable) 106{ 107 struct airoha_eth *eth = port->qdma->eth; 108 u32 vip_port; 109 110 switch (port->id) { 111 case 3: 112 /* FIXME: handle XSI_PCIE1_PORT */ 113 vip_port = XSI_PCIE0_VIP_PORT_MASK; 114 break; 115 case 4: 116 /* FIXME: handle XSI_USB_PORT */ 117 vip_port = XSI_ETH_VIP_PORT_MASK; 118 break; 119 default: 120 return 0; 121 } 122 123 if (enable) { 124 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port); 125 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port); 126 } else { 127 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port); 128 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port); 129 } 130 131 return 0; 132} 133 134static void airoha_fe_maccr_init(struct airoha_eth *eth) 135{ 136 int p; 137 138 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 139 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 140 GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK | 141 GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK); 142 143 airoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK, 144 FIELD_PREP(CDM_VLAN_MASK, 0x8100)); 145 146 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 147} 148 149static void airoha_fe_vip_setup(struct airoha_eth *eth) 150{ 151 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC); 152 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK); 153 154 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP); 155 airoha_fe_wr(eth, REG_FE_VIP_EN(4), 156 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 157 PATN_EN_MASK); 158 159 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP); 160 airoha_fe_wr(eth, REG_FE_VIP_EN(6), 161 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 162 PATN_EN_MASK); 163 164 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP); 165 airoha_fe_wr(eth, REG_FE_VIP_EN(7), 166 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 167 PATN_EN_MASK); 168 169 /* BOOTP (0x43) */ 170 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43); 171 airoha_fe_wr(eth, REG_FE_VIP_EN(8), 172 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 173 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 174 175 /* BOOTP (0x44) */ 176 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44); 177 airoha_fe_wr(eth, REG_FE_VIP_EN(9), 178 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 179 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 180 181 /* ISAKMP */ 182 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4); 183 airoha_fe_wr(eth, REG_FE_VIP_EN(10), 184 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 185 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 186 187 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP); 188 airoha_fe_wr(eth, REG_FE_VIP_EN(11), 189 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 190 PATN_EN_MASK); 191 192 /* DHCPv6 */ 193 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223); 194 airoha_fe_wr(eth, REG_FE_VIP_EN(12), 195 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 196 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 197 198 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP); 199 airoha_fe_wr(eth, REG_FE_VIP_EN(19), 200 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 201 PATN_EN_MASK); 202 203 /* ETH->ETH_P_1905 (0x893a) */ 204 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a); 205 airoha_fe_wr(eth, REG_FE_VIP_EN(20), 206 PATN_FCPU_EN_MASK | PATN_EN_MASK); 207 208 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP); 209 airoha_fe_wr(eth, REG_FE_VIP_EN(21), 210 PATN_FCPU_EN_MASK | PATN_EN_MASK); 211} 212 213static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, 214 u32 port, u32 queue) 215{ 216 u32 val; 217 218 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 219 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, 220 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 221 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); 222 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); 223 224 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); 225} 226 227static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 228 u32 port, u32 queue, u32 val) 229{ 230 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK, 231 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val)); 232 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 233 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK | 234 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK, 235 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 236 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) | 237 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK); 238} 239 240static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) 241{ 242 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); 243 244 return FIELD_GET(PSE_ALLRSV_MASK, val); 245} 246 247static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, 248 u32 port, u32 queue, u32 val) 249{ 250 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue); 251 u32 tmp, all_rsv, fq_limit; 252 253 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val); 254 255 /* modify all rsv */ 256 all_rsv = airoha_fe_get_pse_all_rsv(eth); 257 all_rsv += (val - orig_val); 258 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 259 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 260 261 /* modify hthd */ 262 tmp = airoha_fe_rr(eth, PSE_FQ_CFG); 263 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); 264 tmp = fq_limit - all_rsv - 0x20; 265 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 266 PSE_SHARE_USED_HTHD_MASK, 267 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp)); 268 269 tmp = fq_limit - all_rsv - 0x100; 270 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 271 PSE_SHARE_USED_MTHD_MASK, 272 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp)); 273 tmp = (3 * tmp) >> 2; 274 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, 275 PSE_SHARE_USED_LTHD_MASK, 276 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp)); 277 278 return 0; 279} 280 281static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 282{ 283 const u32 pse_port_num_queues[] = { 284 [FE_PSE_PORT_CDM1] = 6, 285 [FE_PSE_PORT_GDM1] = 6, 286 [FE_PSE_PORT_GDM2] = 32, 287 [FE_PSE_PORT_GDM3] = 6, 288 [FE_PSE_PORT_PPE1] = 4, 289 [FE_PSE_PORT_CDM2] = 6, 290 [FE_PSE_PORT_CDM3] = 8, 291 [FE_PSE_PORT_CDM4] = 10, 292 [FE_PSE_PORT_PPE2] = 4, 293 [FE_PSE_PORT_GDM4] = 2, 294 [FE_PSE_PORT_CDM5] = 2, 295 }; 296 u32 all_rsv; 297 int q; 298 299 all_rsv = airoha_fe_get_pse_all_rsv(eth); 300 if (airoha_ppe_is_enabled(eth, 1)) { 301 /* hw misses PPE2 oq rsv */ 302 all_rsv += PSE_RSV_PAGES * 303 pse_port_num_queues[FE_PSE_PORT_PPE2]; 304 } 305 airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv); 306 307 /* CMD1 */ 308 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++) 309 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q, 310 PSE_QUEUE_RSV_PAGES); 311 /* GMD1 */ 312 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++) 313 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q, 314 PSE_QUEUE_RSV_PAGES); 315 /* GMD2 */ 316 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++) 317 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0); 318 /* GMD3 */ 319 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++) 320 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q, 321 PSE_QUEUE_RSV_PAGES); 322 /* PPE1 */ 323 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { 324 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) 325 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 326 PSE_QUEUE_RSV_PAGES); 327 else 328 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0); 329 } 330 /* CDM2 */ 331 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++) 332 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q, 333 PSE_QUEUE_RSV_PAGES); 334 /* CDM3 */ 335 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++) 336 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0); 337 /* CDM4 */ 338 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++) 339 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q, 340 PSE_QUEUE_RSV_PAGES); 341 if (airoha_ppe_is_enabled(eth, 1)) { 342 /* PPE2 */ 343 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) { 344 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2) 345 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 346 q, 347 PSE_QUEUE_RSV_PAGES); 348 else 349 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 350 q, 0); 351 } 352 } 353 /* GMD4 */ 354 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++) 355 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q, 356 PSE_QUEUE_RSV_PAGES); 357 /* CDM5 */ 358 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++) 359 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q, 360 PSE_QUEUE_RSV_PAGES); 361} 362 363static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth) 364{ 365 int i; 366 367 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) { 368 int err, j; 369 u32 val; 370 371 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 372 373 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 374 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK; 375 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 376 err = read_poll_timeout(airoha_fe_rr, val, 377 val & MC_VLAN_CFG_CMD_DONE_MASK, 378 USEC_PER_MSEC, 5 * USEC_PER_MSEC, 379 false, eth, REG_MC_VLAN_CFG); 380 if (err) 381 return err; 382 383 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) { 384 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 385 386 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 387 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) | 388 MC_VLAN_CFG_RW_MASK; 389 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 390 err = read_poll_timeout(airoha_fe_rr, val, 391 val & MC_VLAN_CFG_CMD_DONE_MASK, 392 USEC_PER_MSEC, 393 5 * USEC_PER_MSEC, false, eth, 394 REG_MC_VLAN_CFG); 395 if (err) 396 return err; 397 } 398 } 399 400 return 0; 401} 402 403static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 404{ 405 /* CDM1_CRSN_QSEL */ 406 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 >> 2), 407 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 408 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 409 CDM_CRSN_QSEL_Q1)); 410 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 >> 2), 411 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 412 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 413 CDM_CRSN_QSEL_Q1)); 414 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 >> 2), 415 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 416 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 417 CDM_CRSN_QSEL_Q1)); 418 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 >> 2), 419 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 420 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 421 CDM_CRSN_QSEL_Q6)); 422 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 >> 2), 423 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 424 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 425 CDM_CRSN_QSEL_Q1)); 426 /* CDM2_CRSN_QSEL */ 427 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 >> 2), 428 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 429 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 430 CDM_CRSN_QSEL_Q1)); 431 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 >> 2), 432 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 433 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 434 CDM_CRSN_QSEL_Q1)); 435 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 >> 2), 436 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 437 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 438 CDM_CRSN_QSEL_Q1)); 439 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 >> 2), 440 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 441 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 442 CDM_CRSN_QSEL_Q6)); 443 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 >> 2), 444 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 445 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 446 CDM_CRSN_QSEL_Q1)); 447} 448 449static int airoha_fe_init(struct airoha_eth *eth) 450{ 451 airoha_fe_maccr_init(eth); 452 453 /* PSE IQ reserve */ 454 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK, 455 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10)); 456 airoha_fe_rmw(eth, REG_PSE_IQ_REV2, 457 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK, 458 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) | 459 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34)); 460 461 /* enable FE copy engine for MC/KA/DPI */ 462 airoha_fe_wr(eth, REG_FE_PCE_CFG, 463 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK); 464 /* set vip queue selection to ring 1 */ 465 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK, 466 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 467 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK, 468 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 469 /* set GDM4 source interface offset to 8 */ 470 airoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4), 471 GDM_SPORT_OFF2_MASK | 472 GDM_SPORT_OFF1_MASK | 473 GDM_SPORT_OFF0_MASK, 474 FIELD_PREP(GDM_SPORT_OFF2_MASK, 8) | 475 FIELD_PREP(GDM_SPORT_OFF1_MASK, 8) | 476 FIELD_PREP(GDM_SPORT_OFF0_MASK, 8)); 477 478 /* set PSE Page as 128B */ 479 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, 480 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK, 481 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) | 482 FE_DMA_GLO_PG_SZ_MASK); 483 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG, 484 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK | 485 FE_RST_GDM4_MBI_ARB_MASK); 486 usleep_range(1000, 2000); 487 488 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 489 * connect other rings to PSE Port0 OQ-0 490 */ 491 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4)); 492 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28)); 493 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4)); 494 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28)); 495 496 airoha_fe_vip_setup(eth); 497 airoha_fe_pse_ports_init(eth); 498 499 airoha_fe_set(eth, REG_GDM_MISC_CFG, 500 GDM2_RDM_ACK_WAIT_PREF_MASK | 501 GDM2_CHN_VLD_MODE_MASK); 502 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK, 503 FIELD_PREP(CDM_OAM_QSEL_MASK, 15)); 504 505 /* init fragment and assemble Force Port */ 506 /* NPU Core-3, NPU Bridge Channel-3 */ 507 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 508 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK, 509 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) | 510 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3)); 511 /* QDMA LAN, RX Ring-22 */ 512 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 513 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK, 514 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 515 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 516 517 airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN_MASK); 518 airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN_MASK); 519 520 airoha_fe_crsn_qsel_init(eth); 521 522 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK); 523 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 524 525 /* default aging mode for mbi unlock issue */ 526 airoha_fe_rmw(eth, REG_GDM_CHN_RLS(2), 527 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 528 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 529 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); 530 531 /* disable IFC by default */ 532 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK); 533 534 /* enable 1:N vlan action, init vlan table */ 535 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK); 536 537 return airoha_fe_mc_vlan_clear(eth); 538} 539 540static int airoha_qdma_fill_rx_queue(struct airoha_queue *q) 541{ 542 struct airoha_qdma *qdma = q->qdma; 543 int qid = q - &qdma->q_rx[0]; 544 int nframes = 0; 545 546 while (q->queued < q->ndesc - 1) { 547 struct airoha_queue_entry *e = &q->entry[q->head]; 548 struct airoha_qdma_desc *desc = &q->desc[q->head]; 549 struct page *page; 550 int offset; 551 u32 val; 552 553 page = page_pool_dev_alloc_frag(q->page_pool, &offset, 554 q->buf_size); 555 if (!page) 556 break; 557 558 q->head = (q->head + 1) % q->ndesc; 559 q->queued++; 560 nframes++; 561 562 e->buf = page_address(page) + offset; 563 e->dma_addr = page_pool_get_dma_addr(page) + offset; 564 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size); 565 566 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len); 567 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 568 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr)); 569 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head); 570 WRITE_ONCE(desc->data, cpu_to_le32(val)); 571 WRITE_ONCE(desc->msg0, 0); 572 WRITE_ONCE(desc->msg1, 0); 573 WRITE_ONCE(desc->msg2, 0); 574 WRITE_ONCE(desc->msg3, 0); 575 576 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), 577 RX_RING_CPU_IDX_MASK, 578 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 579 } 580 581 return nframes; 582} 583 584static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, 585 struct airoha_qdma_desc *desc) 586{ 587 u32 port, sport, msg1 = le32_to_cpu(desc->msg1); 588 589 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1); 590 switch (sport) { 591 case 0x10 ... 0x14: 592 port = 0; 593 break; 594 case 0x2 ... 0x4: 595 port = sport - 1; 596 break; 597 default: 598 return -EINVAL; 599 } 600 601 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port; 602} 603 604static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 605{ 606 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 607 struct airoha_qdma *qdma = q->qdma; 608 struct airoha_eth *eth = qdma->eth; 609 int qid = q - &qdma->q_rx[0]; 610 int done = 0; 611 612 while (done < budget) { 613 struct airoha_queue_entry *e = &q->entry[q->tail]; 614 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 615 u32 hash, reason, msg1 = le32_to_cpu(desc->msg1); 616 struct page *page = virt_to_head_page(e->buf); 617 u32 desc_ctrl = le32_to_cpu(desc->ctrl); 618 struct airoha_gdm_port *port; 619 int data_len, len, p; 620 621 if (!(desc_ctrl & QDMA_DESC_DONE_MASK)) 622 break; 623 624 q->tail = (q->tail + 1) % q->ndesc; 625 q->queued--; 626 627 dma_sync_single_for_cpu(eth->dev, e->dma_addr, 628 SKB_WITH_OVERHEAD(q->buf_size), dir); 629 630 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl); 631 data_len = q->skb ? q->buf_size 632 : SKB_WITH_OVERHEAD(q->buf_size); 633 if (!len || data_len < len) 634 goto free_frag; 635 636 p = airoha_qdma_get_gdm_port(eth, desc); 637 if (p < 0 || !eth->ports[p]) 638 goto free_frag; 639 640 port = eth->ports[p]; 641 if (!q->skb) { /* first buffer */ 642 q->skb = napi_build_skb(e->buf, q->buf_size); 643 if (!q->skb) 644 goto free_frag; 645 646 __skb_put(q->skb, len); 647 skb_mark_for_recycle(q->skb); 648 q->skb->dev = port->dev; 649 q->skb->protocol = eth_type_trans(q->skb, port->dev); 650 q->skb->ip_summed = CHECKSUM_UNNECESSARY; 651 skb_record_rx_queue(q->skb, qid); 652 } else { /* scattered frame */ 653 struct skb_shared_info *shinfo = skb_shinfo(q->skb); 654 int nr_frags = shinfo->nr_frags; 655 656 if (nr_frags >= ARRAY_SIZE(shinfo->frags)) 657 goto free_frag; 658 659 skb_add_rx_frag(q->skb, nr_frags, page, 660 e->buf - page_address(page), len, 661 q->buf_size); 662 } 663 664 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl)) 665 continue; 666 667 if (netdev_uses_dsa(port->dev)) { 668 /* PPE module requires untagged packets to work 669 * properly and it provides DSA port index via the 670 * DMA descriptor. Report DSA tag to the DSA stack 671 * via skb dst info. 672 */ 673 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, 674 le32_to_cpu(desc->msg0)); 675 676 if (sptag < ARRAY_SIZE(port->dsa_meta) && 677 port->dsa_meta[sptag]) 678 skb_dst_set_noref(q->skb, 679 &port->dsa_meta[sptag]->dst); 680 } 681 682 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1); 683 if (hash != AIROHA_RXD4_FOE_ENTRY) 684 skb_set_hash(q->skb, jhash_1word(hash, 0), 685 PKT_HASH_TYPE_L4); 686 687 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1); 688 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 689 airoha_ppe_check_skb(ð->ppe->dev, q->skb, hash, 690 false); 691 692 done++; 693 napi_gro_receive(&q->napi, q->skb); 694 q->skb = NULL; 695 continue; 696free_frag: 697 if (q->skb) { 698 dev_kfree_skb(q->skb); 699 q->skb = NULL; 700 } 701 page_pool_put_full_page(q->page_pool, page, true); 702 } 703 airoha_qdma_fill_rx_queue(q); 704 705 return done; 706} 707 708static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget) 709{ 710 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi); 711 int cur, done = 0; 712 713 do { 714 cur = airoha_qdma_rx_process(q, budget - done); 715 done += cur; 716 } while (cur && done < budget); 717 718 if (done < budget && napi_complete(napi)) { 719 struct airoha_qdma *qdma = q->qdma; 720 int i, qid = q - &qdma->q_rx[0]; 721 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1 722 : QDMA_INT_REG_IDX2; 723 724 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 725 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i))) 726 continue; 727 728 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg, 729 BIT(qid % RX_DONE_HIGH_OFFSET)); 730 } 731 } 732 733 return done; 734} 735 736static int airoha_qdma_init_rx_queue(struct airoha_queue *q, 737 struct airoha_qdma *qdma, int ndesc) 738{ 739 const struct page_pool_params pp_params = { 740 .order = 0, 741 .pool_size = 256, 742 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 743 .dma_dir = DMA_FROM_DEVICE, 744 .max_len = PAGE_SIZE, 745 .nid = NUMA_NO_NODE, 746 .dev = qdma->eth->dev, 747 .napi = &q->napi, 748 }; 749 struct airoha_eth *eth = qdma->eth; 750 int qid = q - &qdma->q_rx[0], thr; 751 dma_addr_t dma_addr; 752 753 q->buf_size = PAGE_SIZE / 2; 754 q->ndesc = ndesc; 755 q->qdma = qdma; 756 757 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 758 GFP_KERNEL); 759 if (!q->entry) 760 return -ENOMEM; 761 762 q->page_pool = page_pool_create(&pp_params); 763 if (IS_ERR(q->page_pool)) { 764 int err = PTR_ERR(q->page_pool); 765 766 q->page_pool = NULL; 767 return err; 768 } 769 770 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 771 &dma_addr, GFP_KERNEL); 772 if (!q->desc) 773 return -ENOMEM; 774 775 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll); 776 777 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); 778 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), 779 RX_RING_SIZE_MASK, 780 FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); 781 782 thr = clamp(ndesc >> 3, 1, 32); 783 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, 784 FIELD_PREP(RX_RING_THR_MASK, thr)); 785 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 786 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); 787 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK); 788 789 airoha_qdma_fill_rx_queue(q); 790 791 return 0; 792} 793 794static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q) 795{ 796 struct airoha_qdma *qdma = q->qdma; 797 struct airoha_eth *eth = qdma->eth; 798 int qid = q - &qdma->q_rx[0]; 799 800 while (q->queued) { 801 struct airoha_queue_entry *e = &q->entry[q->tail]; 802 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 803 struct page *page = virt_to_head_page(e->buf); 804 805 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len, 806 page_pool_get_dma_dir(q->page_pool)); 807 page_pool_put_full_page(q->page_pool, page, false); 808 /* Reset DMA descriptor */ 809 WRITE_ONCE(desc->ctrl, 0); 810 WRITE_ONCE(desc->addr, 0); 811 WRITE_ONCE(desc->data, 0); 812 WRITE_ONCE(desc->msg0, 0); 813 WRITE_ONCE(desc->msg1, 0); 814 WRITE_ONCE(desc->msg2, 0); 815 WRITE_ONCE(desc->msg3, 0); 816 817 q->tail = (q->tail + 1) % q->ndesc; 818 q->queued--; 819 } 820 821 q->head = q->tail; 822 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 823 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->tail)); 824} 825 826static int airoha_qdma_init_rx(struct airoha_qdma *qdma) 827{ 828 int i; 829 830 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 831 int err; 832 833 if (!(RX_DONE_INT_MASK & BIT(i))) { 834 /* rx-queue not binded to irq */ 835 continue; 836 } 837 838 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, 839 RX_DSCP_NUM(i)); 840 if (err) 841 return err; 842 } 843 844 return 0; 845} 846 847static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) 848{ 849 struct airoha_tx_irq_queue *irq_q; 850 int id, done = 0, irq_queued; 851 struct airoha_qdma *qdma; 852 struct airoha_eth *eth; 853 u32 status, head; 854 855 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi); 856 qdma = irq_q->qdma; 857 id = irq_q - &qdma->q_tx_irq[0]; 858 eth = qdma->eth; 859 860 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id)); 861 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status); 862 head = head % irq_q->size; 863 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status); 864 865 while (irq_queued > 0 && done < budget) { 866 u32 qid, val = irq_q->q[head]; 867 struct airoha_qdma_desc *desc; 868 struct airoha_queue_entry *e; 869 struct airoha_queue *q; 870 u32 index, desc_ctrl; 871 struct sk_buff *skb; 872 873 if (val == 0xff) 874 break; 875 876 irq_q->q[head] = 0xff; /* mark as done */ 877 head = (head + 1) % irq_q->size; 878 irq_queued--; 879 done++; 880 881 qid = FIELD_GET(IRQ_RING_IDX_MASK, val); 882 if (qid >= ARRAY_SIZE(qdma->q_tx)) 883 continue; 884 885 q = &qdma->q_tx[qid]; 886 if (!q->ndesc) 887 continue; 888 889 index = FIELD_GET(IRQ_DESC_IDX_MASK, val); 890 if (index >= q->ndesc) 891 continue; 892 893 spin_lock_bh(&q->lock); 894 895 if (!q->queued) 896 goto unlock; 897 898 desc = &q->desc[index]; 899 desc_ctrl = le32_to_cpu(desc->ctrl); 900 901 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) && 902 !(desc_ctrl & QDMA_DESC_DROP_MASK)) 903 goto unlock; 904 905 e = &q->entry[index]; 906 skb = e->skb; 907 908 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 909 DMA_TO_DEVICE); 910 e->dma_addr = 0; 911 list_add_tail(&e->list, &q->tx_list); 912 913 WRITE_ONCE(desc->msg0, 0); 914 WRITE_ONCE(desc->msg1, 0); 915 q->queued--; 916 917 if (skb) { 918 u16 queue = skb_get_queue_mapping(skb); 919 struct netdev_queue *txq; 920 921 txq = netdev_get_tx_queue(skb->dev, queue); 922 netdev_tx_completed_queue(txq, 1, skb->len); 923 if (netif_tx_queue_stopped(txq) && 924 q->ndesc - q->queued >= q->free_thr) 925 netif_tx_wake_queue(txq); 926 927 dev_kfree_skb_any(skb); 928 } 929unlock: 930 spin_unlock_bh(&q->lock); 931 } 932 933 if (done) { 934 int i, len = done >> 7; 935 936 for (i = 0; i < len; i++) 937 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 938 IRQ_CLEAR_LEN_MASK, 0x80); 939 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 940 IRQ_CLEAR_LEN_MASK, (done & 0x7f)); 941 } 942 943 if (done < budget && napi_complete(napi)) 944 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 945 TX_DONE_INT_MASK(id)); 946 947 return done; 948} 949 950static int airoha_qdma_init_tx_queue(struct airoha_queue *q, 951 struct airoha_qdma *qdma, int size) 952{ 953 struct airoha_eth *eth = qdma->eth; 954 int i, qid = q - &qdma->q_tx[0]; 955 dma_addr_t dma_addr; 956 957 spin_lock_init(&q->lock); 958 q->ndesc = size; 959 q->qdma = qdma; 960 q->free_thr = 1 + MAX_SKB_FRAGS; 961 INIT_LIST_HEAD(&q->tx_list); 962 963 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 964 GFP_KERNEL); 965 if (!q->entry) 966 return -ENOMEM; 967 968 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 969 &dma_addr, GFP_KERNEL); 970 if (!q->desc) 971 return -ENOMEM; 972 973 for (i = 0; i < q->ndesc; i++) { 974 u32 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1); 975 976 list_add_tail(&q->entry[i].list, &q->tx_list); 977 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val)); 978 } 979 980 /* xmit ring drop default setting */ 981 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid), 982 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK); 983 984 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); 985 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 986 FIELD_PREP(TX_RING_CPU_IDX_MASK, 0)); 987 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 988 FIELD_PREP(TX_RING_DMA_IDX_MASK, 0)); 989 990 return 0; 991} 992 993static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, 994 struct airoha_qdma *qdma, int size) 995{ 996 int id = irq_q - &qdma->q_tx_irq[0]; 997 struct airoha_eth *eth = qdma->eth; 998 dma_addr_t dma_addr; 999 1000 netif_napi_add_tx(eth->napi_dev, &irq_q->napi, 1001 airoha_qdma_tx_napi_poll); 1002 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32), 1003 &dma_addr, GFP_KERNEL); 1004 if (!irq_q->q) 1005 return -ENOMEM; 1006 1007 memset(irq_q->q, 0xff, size * sizeof(u32)); 1008 irq_q->size = size; 1009 irq_q->qdma = qdma; 1010 1011 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); 1012 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, 1013 FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); 1014 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK, 1015 FIELD_PREP(TX_IRQ_THR_MASK, 1)); 1016 1017 return 0; 1018} 1019 1020static int airoha_qdma_init_tx(struct airoha_qdma *qdma) 1021{ 1022 int i, err; 1023 1024 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1025 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, 1026 IRQ_QUEUE_LEN(i)); 1027 if (err) 1028 return err; 1029 } 1030 1031 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1032 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, 1033 TX_DSCP_NUM); 1034 if (err) 1035 return err; 1036 } 1037 1038 return 0; 1039} 1040 1041static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q) 1042{ 1043 struct airoha_eth *eth = q->qdma->eth; 1044 int i; 1045 1046 spin_lock_bh(&q->lock); 1047 for (i = 0; i < q->ndesc; i++) { 1048 struct airoha_queue_entry *e = &q->entry[i]; 1049 1050 if (!e->dma_addr) 1051 continue; 1052 1053 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 1054 DMA_TO_DEVICE); 1055 dev_kfree_skb_any(e->skb); 1056 e->dma_addr = 0; 1057 e->skb = NULL; 1058 list_add_tail(&e->list, &q->tx_list); 1059 q->queued--; 1060 } 1061 spin_unlock_bh(&q->lock); 1062} 1063 1064static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) 1065{ 1066 int size, index, num_desc = HW_DSCP_NUM; 1067 struct airoha_eth *eth = qdma->eth; 1068 int id = qdma - ð->qdma[0]; 1069 u32 status, buf_size; 1070 dma_addr_t dma_addr; 1071 const char *name; 1072 1073 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id); 1074 if (!name) 1075 return -ENOMEM; 1076 1077 buf_size = id ? AIROHA_MAX_PACKET_SIZE / 2 : AIROHA_MAX_PACKET_SIZE; 1078 index = of_property_match_string(eth->dev->of_node, 1079 "memory-region-names", name); 1080 if (index >= 0) { 1081 struct reserved_mem *rmem; 1082 struct device_node *np; 1083 1084 /* Consume reserved memory for hw forwarding buffers queue if 1085 * available in the DTS 1086 */ 1087 np = of_parse_phandle(eth->dev->of_node, "memory-region", 1088 index); 1089 if (!np) 1090 return -ENODEV; 1091 1092 rmem = of_reserved_mem_lookup(np); 1093 of_node_put(np); 1094 dma_addr = rmem->base; 1095 /* Compute the number of hw descriptors according to the 1096 * reserved memory size and the payload buffer size 1097 */ 1098 num_desc = div_u64(rmem->size, buf_size); 1099 } else { 1100 size = buf_size * num_desc; 1101 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, 1102 GFP_KERNEL)) 1103 return -ENOMEM; 1104 } 1105 1106 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); 1107 1108 size = num_desc * sizeof(struct airoha_qdma_fwd_desc); 1109 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL)) 1110 return -ENOMEM; 1111 1112 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); 1113 /* QDMA0: 2KB. QDMA1: 1KB */ 1114 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, 1115 HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 1116 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, !!id)); 1117 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK, 1118 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128)); 1119 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, 1120 LMGR_INIT_START | LMGR_SRAM_MODE_MASK | 1121 HW_FWD_DESC_NUM_MASK, 1122 FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) | 1123 LMGR_INIT_START | LMGR_SRAM_MODE_MASK); 1124 1125 return read_poll_timeout(airoha_qdma_rr, status, 1126 !(status & LMGR_INIT_START), USEC_PER_MSEC, 1127 30 * USEC_PER_MSEC, true, qdma, 1128 REG_LMGR_INIT_CFG); 1129} 1130 1131static void airoha_qdma_init_qos(struct airoha_qdma *qdma) 1132{ 1133 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK); 1134 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK); 1135 1136 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG, 1137 PSE_BUF_ESTIMATE_EN_MASK); 1138 1139 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG, 1140 EGRESS_RATE_METER_EN_MASK | 1141 EGRESS_RATE_METER_EQ_RATE_EN_MASK); 1142 /* 2047us x 31 = 63.457ms */ 1143 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1144 EGRESS_RATE_METER_WINDOW_SZ_MASK, 1145 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f)); 1146 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1147 EGRESS_RATE_METER_TIMESLICE_MASK, 1148 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff)); 1149 1150 /* ratelimit init */ 1151 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK); 1152 /* fast-tick 25us */ 1153 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK, 1154 FIELD_PREP(GLB_FAST_TICK_MASK, 25)); 1155 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK, 1156 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40)); 1157 1158 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK); 1159 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK, 1160 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25)); 1161 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, 1162 EGRESS_SLOW_TICK_RATIO_MASK, 1163 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40)); 1164 1165 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK); 1166 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG, 1167 INGRESS_TRTCM_MODE_MASK); 1168 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK, 1169 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125)); 1170 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, 1171 INGRESS_SLOW_TICK_RATIO_MASK, 1172 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8)); 1173 1174 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK); 1175 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK, 1176 FIELD_PREP(SLA_FAST_TICK_MASK, 25)); 1177 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK, 1178 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40)); 1179} 1180 1181static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma) 1182{ 1183 int i; 1184 1185 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) { 1186 /* Tx-cpu transferred count */ 1187 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0); 1188 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1189 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1190 CNTR_ALL_DSCP_RING_EN_MASK | 1191 FIELD_PREP(CNTR_CHAN_MASK, i)); 1192 /* Tx-fwd transferred count */ 1193 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0); 1194 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1195 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1196 CNTR_ALL_DSCP_RING_EN_MASK | 1197 FIELD_PREP(CNTR_SRC_MASK, 1) | 1198 FIELD_PREP(CNTR_CHAN_MASK, i)); 1199 } 1200} 1201 1202static int airoha_qdma_hw_init(struct airoha_qdma *qdma) 1203{ 1204 int i; 1205 1206 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1207 /* clear pending irqs */ 1208 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1209 /* setup rx irqs */ 1210 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0, 1211 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1212 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1, 1213 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1214 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2, 1215 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1216 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3, 1217 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1218 } 1219 /* setup tx irqs */ 1220 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 1221 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK); 1222 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4, 1223 TX_COHERENT_HIGH_INT_MASK); 1224 1225 /* setup irq binding */ 1226 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1227 if (!qdma->q_tx[i].ndesc) 1228 continue; 1229 1230 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i)) 1231 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i), 1232 TX_RING_IRQ_BLOCKING_CFG_MASK); 1233 else 1234 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i), 1235 TX_RING_IRQ_BLOCKING_CFG_MASK); 1236 } 1237 1238 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, 1239 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) | 1240 GLOBAL_CFG_CPU_TXR_RR_MASK | 1241 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | 1242 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK | 1243 GLOBAL_CFG_MULTICAST_EN_MASK | 1244 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK | 1245 GLOBAL_CFG_TX_WB_DONE_MASK | 1246 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2)); 1247 1248 airoha_qdma_init_qos(qdma); 1249 1250 /* disable qdma rx delay interrupt */ 1251 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1252 if (!qdma->q_rx[i].ndesc) 1253 continue; 1254 1255 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), 1256 RX_DELAY_INT_MASK); 1257 } 1258 1259 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG, 1260 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN); 1261 airoha_qdma_init_qos_stats(qdma); 1262 1263 return 0; 1264} 1265 1266static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1267{ 1268 struct airoha_irq_bank *irq_bank = dev_instance; 1269 struct airoha_qdma *qdma = irq_bank->qdma; 1270 u32 rx_intr_mask = 0, rx_intr1, rx_intr2; 1271 u32 intr[ARRAY_SIZE(irq_bank->irqmask)]; 1272 int i; 1273 1274 for (i = 0; i < ARRAY_SIZE(intr); i++) { 1275 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1276 intr[i] &= irq_bank->irqmask[i]; 1277 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1278 } 1279 1280 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1281 return IRQ_NONE; 1282 1283 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK; 1284 if (rx_intr1) { 1285 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1); 1286 rx_intr_mask |= rx_intr1; 1287 } 1288 1289 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK; 1290 if (rx_intr2) { 1291 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2); 1292 rx_intr_mask |= (rx_intr2 << 16); 1293 } 1294 1295 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) { 1296 if (!qdma->q_rx[i].ndesc) 1297 continue; 1298 1299 if (rx_intr_mask & BIT(i)) 1300 napi_schedule(&qdma->q_rx[i].napi); 1301 } 1302 1303 if (intr[0] & INT_TX_MASK) { 1304 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1305 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1306 continue; 1307 1308 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0, 1309 TX_DONE_INT_MASK(i)); 1310 napi_schedule(&qdma->q_tx_irq[i].napi); 1311 } 1312 } 1313 1314 return IRQ_HANDLED; 1315} 1316 1317static int airoha_qdma_init_irq_banks(struct platform_device *pdev, 1318 struct airoha_qdma *qdma) 1319{ 1320 struct airoha_eth *eth = qdma->eth; 1321 int i, id = qdma - ð->qdma[0]; 1322 1323 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1324 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i]; 1325 int err, irq_index = 4 * id + i; 1326 const char *name; 1327 1328 spin_lock_init(&irq_bank->irq_lock); 1329 irq_bank->qdma = qdma; 1330 1331 irq_bank->irq = platform_get_irq(pdev, irq_index); 1332 if (irq_bank->irq < 0) 1333 return irq_bank->irq; 1334 1335 name = devm_kasprintf(eth->dev, GFP_KERNEL, 1336 KBUILD_MODNAME ".%d", irq_index); 1337 if (!name) 1338 return -ENOMEM; 1339 1340 err = devm_request_irq(eth->dev, irq_bank->irq, 1341 airoha_irq_handler, IRQF_SHARED, name, 1342 irq_bank); 1343 if (err) 1344 return err; 1345 } 1346 1347 return 0; 1348} 1349 1350static int airoha_qdma_init(struct platform_device *pdev, 1351 struct airoha_eth *eth, 1352 struct airoha_qdma *qdma) 1353{ 1354 int err, id = qdma - ð->qdma[0]; 1355 const char *res; 1356 1357 qdma->eth = eth; 1358 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1359 if (!res) 1360 return -ENOMEM; 1361 1362 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res); 1363 if (IS_ERR(qdma->regs)) 1364 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1365 "failed to iomap qdma%d regs\n", id); 1366 1367 err = airoha_qdma_init_irq_banks(pdev, qdma); 1368 if (err) 1369 return err; 1370 1371 err = airoha_qdma_init_rx(qdma); 1372 if (err) 1373 return err; 1374 1375 err = airoha_qdma_init_tx(qdma); 1376 if (err) 1377 return err; 1378 1379 err = airoha_qdma_init_hfwd_queues(qdma); 1380 if (err) 1381 return err; 1382 1383 return airoha_qdma_hw_init(qdma); 1384} 1385 1386static int airoha_hw_init(struct platform_device *pdev, 1387 struct airoha_eth *eth) 1388{ 1389 int err, i; 1390 1391 /* disable xsi */ 1392 err = reset_control_bulk_assert(eth->soc->num_xsi_rsts, eth->xsi_rsts); 1393 if (err) 1394 return err; 1395 1396 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts); 1397 if (err) 1398 return err; 1399 1400 msleep(20); 1401 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts); 1402 if (err) 1403 return err; 1404 1405 msleep(20); 1406 err = airoha_fe_init(eth); 1407 if (err) 1408 return err; 1409 1410 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 1411 err = airoha_qdma_init(pdev, eth, ð->qdma[i]); 1412 if (err) 1413 return err; 1414 } 1415 1416 err = airoha_ppe_init(eth); 1417 if (err) 1418 return err; 1419 1420 set_bit(DEV_STATE_INITIALIZED, ð->state); 1421 1422 return 0; 1423} 1424 1425static void airoha_hw_cleanup(struct airoha_qdma *qdma) 1426{ 1427 int i; 1428 1429 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1430 if (!qdma->q_rx[i].ndesc) 1431 continue; 1432 1433 netif_napi_del(&qdma->q_rx[i].napi); 1434 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]); 1435 if (qdma->q_rx[i].page_pool) 1436 page_pool_destroy(qdma->q_rx[i].page_pool); 1437 } 1438 1439 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1440 netif_napi_del(&qdma->q_tx_irq[i].napi); 1441 1442 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1443 if (!qdma->q_tx[i].ndesc) 1444 continue; 1445 1446 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1447 } 1448} 1449 1450static void airoha_qdma_start_napi(struct airoha_qdma *qdma) 1451{ 1452 int i; 1453 1454 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1455 napi_enable(&qdma->q_tx_irq[i].napi); 1456 1457 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1458 if (!qdma->q_rx[i].ndesc) 1459 continue; 1460 1461 napi_enable(&qdma->q_rx[i].napi); 1462 } 1463} 1464 1465static void airoha_qdma_stop_napi(struct airoha_qdma *qdma) 1466{ 1467 int i; 1468 1469 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1470 napi_disable(&qdma->q_tx_irq[i].napi); 1471 1472 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1473 if (!qdma->q_rx[i].ndesc) 1474 continue; 1475 1476 napi_disable(&qdma->q_rx[i].napi); 1477 } 1478} 1479 1480static void airoha_update_hw_stats(struct airoha_gdm_port *port) 1481{ 1482 struct airoha_eth *eth = port->qdma->eth; 1483 u32 val, i = 0; 1484 1485 spin_lock(&port->stats.lock); 1486 u64_stats_update_begin(&port->stats.syncp); 1487 1488 /* TX */ 1489 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id)); 1490 port->stats.tx_ok_pkts += ((u64)val << 32); 1491 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id)); 1492 port->stats.tx_ok_pkts += val; 1493 1494 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id)); 1495 port->stats.tx_ok_bytes += ((u64)val << 32); 1496 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id)); 1497 port->stats.tx_ok_bytes += val; 1498 1499 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id)); 1500 port->stats.tx_drops += val; 1501 1502 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id)); 1503 port->stats.tx_broadcast += val; 1504 1505 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id)); 1506 port->stats.tx_multicast += val; 1507 1508 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id)); 1509 port->stats.tx_len[i] += val; 1510 1511 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id)); 1512 port->stats.tx_len[i] += ((u64)val << 32); 1513 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id)); 1514 port->stats.tx_len[i++] += val; 1515 1516 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id)); 1517 port->stats.tx_len[i] += ((u64)val << 32); 1518 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id)); 1519 port->stats.tx_len[i++] += val; 1520 1521 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id)); 1522 port->stats.tx_len[i] += ((u64)val << 32); 1523 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id)); 1524 port->stats.tx_len[i++] += val; 1525 1526 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id)); 1527 port->stats.tx_len[i] += ((u64)val << 32); 1528 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id)); 1529 port->stats.tx_len[i++] += val; 1530 1531 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id)); 1532 port->stats.tx_len[i] += ((u64)val << 32); 1533 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id)); 1534 port->stats.tx_len[i++] += val; 1535 1536 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id)); 1537 port->stats.tx_len[i] += ((u64)val << 32); 1538 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id)); 1539 port->stats.tx_len[i++] += val; 1540 1541 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id)); 1542 port->stats.tx_len[i++] += val; 1543 1544 /* RX */ 1545 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id)); 1546 port->stats.rx_ok_pkts += ((u64)val << 32); 1547 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id)); 1548 port->stats.rx_ok_pkts += val; 1549 1550 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id)); 1551 port->stats.rx_ok_bytes += ((u64)val << 32); 1552 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id)); 1553 port->stats.rx_ok_bytes += val; 1554 1555 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id)); 1556 port->stats.rx_drops += val; 1557 1558 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id)); 1559 port->stats.rx_broadcast += val; 1560 1561 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id)); 1562 port->stats.rx_multicast += val; 1563 1564 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id)); 1565 port->stats.rx_errors += val; 1566 1567 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id)); 1568 port->stats.rx_crc_error += val; 1569 1570 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id)); 1571 port->stats.rx_over_errors += val; 1572 1573 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id)); 1574 port->stats.rx_fragment += val; 1575 1576 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id)); 1577 port->stats.rx_jabber += val; 1578 1579 i = 0; 1580 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id)); 1581 port->stats.rx_len[i] += val; 1582 1583 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id)); 1584 port->stats.rx_len[i] += ((u64)val << 32); 1585 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id)); 1586 port->stats.rx_len[i++] += val; 1587 1588 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id)); 1589 port->stats.rx_len[i] += ((u64)val << 32); 1590 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id)); 1591 port->stats.rx_len[i++] += val; 1592 1593 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id)); 1594 port->stats.rx_len[i] += ((u64)val << 32); 1595 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id)); 1596 port->stats.rx_len[i++] += val; 1597 1598 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id)); 1599 port->stats.rx_len[i] += ((u64)val << 32); 1600 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id)); 1601 port->stats.rx_len[i++] += val; 1602 1603 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id)); 1604 port->stats.rx_len[i] += ((u64)val << 32); 1605 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id)); 1606 port->stats.rx_len[i++] += val; 1607 1608 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id)); 1609 port->stats.rx_len[i] += ((u64)val << 32); 1610 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id)); 1611 port->stats.rx_len[i++] += val; 1612 1613 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id)); 1614 port->stats.rx_len[i++] += val; 1615 1616 /* reset mib counters */ 1617 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id), 1618 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK); 1619 1620 u64_stats_update_end(&port->stats.syncp); 1621 spin_unlock(&port->stats.lock); 1622} 1623 1624static int airoha_dev_open(struct net_device *dev) 1625{ 1626 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN; 1627 struct airoha_gdm_port *port = netdev_priv(dev); 1628 struct airoha_qdma *qdma = port->qdma; 1629 1630 netif_tx_start_all_queues(dev); 1631 err = airoha_set_vip_for_gdm_port(port, true); 1632 if (err) 1633 return err; 1634 1635 if (netdev_uses_dsa(dev)) 1636 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1637 GDM_STAG_EN_MASK); 1638 else 1639 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1640 GDM_STAG_EN_MASK); 1641 1642 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id), 1643 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1644 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1645 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1646 1647 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, 1648 GLOBAL_CFG_TX_DMA_EN_MASK | 1649 GLOBAL_CFG_RX_DMA_EN_MASK); 1650 atomic_inc(&qdma->users); 1651 1652 return 0; 1653} 1654 1655static int airoha_dev_stop(struct net_device *dev) 1656{ 1657 struct airoha_gdm_port *port = netdev_priv(dev); 1658 struct airoha_qdma *qdma = port->qdma; 1659 int i, err; 1660 1661 netif_tx_disable(dev); 1662 err = airoha_set_vip_for_gdm_port(port, false); 1663 if (err) 1664 return err; 1665 1666 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) 1667 netdev_tx_reset_subqueue(dev, i); 1668 1669 if (atomic_dec_and_test(&qdma->users)) { 1670 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, 1671 GLOBAL_CFG_TX_DMA_EN_MASK | 1672 GLOBAL_CFG_RX_DMA_EN_MASK); 1673 1674 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1675 if (!qdma->q_tx[i].ndesc) 1676 continue; 1677 1678 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1679 } 1680 } 1681 1682 return 0; 1683} 1684 1685static int airoha_dev_set_macaddr(struct net_device *dev, void *p) 1686{ 1687 struct airoha_gdm_port *port = netdev_priv(dev); 1688 int err; 1689 1690 err = eth_mac_addr(dev, p); 1691 if (err) 1692 return err; 1693 1694 airoha_set_macaddr(port, dev->dev_addr); 1695 1696 return 0; 1697} 1698 1699static int airhoha_set_gdm2_loopback(struct airoha_gdm_port *port) 1700{ 1701 struct airoha_eth *eth = port->qdma->eth; 1702 u32 val, pse_port, chan, nbq; 1703 int src_port; 1704 1705 /* Forward the traffic to the proper GDM port */ 1706 pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1707 : FE_PSE_PORT_GDM4; 1708 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port); 1709 airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC_MASK); 1710 1711 /* Enable GDM2 loopback */ 1712 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff); 1713 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff); 1714 1715 chan = port->id == AIROHA_GDM3_IDX ? airoha_is_7581(eth) ? 4 : 3 : 0; 1716 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2), 1717 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1718 FIELD_PREP(LPBK_CHAN_MASK, chan) | 1719 LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK | 1720 LBK_CHAN_MODE_MASK | LPBK_EN_MASK); 1721 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2), 1722 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1723 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1724 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1725 1726 /* Disable VIP and IFC for GDM2 */ 1727 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2)); 1728 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2)); 1729 1730 /* XXX: handle XSI_USB_PORT and XSI_PCE1_PORT */ 1731 nbq = port->id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0; 1732 src_port = eth->soc->ops.get_src_port_id(port, nbq); 1733 if (src_port < 0) 1734 return src_port; 1735 1736 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1737 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1738 FIELD_PREP(WAN0_MASK, src_port)); 1739 val = src_port & SP_CPORT_DFT_MASK; 1740 airoha_fe_rmw(eth, 1741 REG_SP_DFT_CPORT(src_port >> fls(SP_CPORT_DFT_MASK)), 1742 SP_CPORT_MASK(val), 1743 FE_PSE_PORT_CDM2 << __ffs(SP_CPORT_MASK(val))); 1744 1745 if (port->id != AIROHA_GDM3_IDX && airoha_is_7581(eth)) 1746 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, 1747 FC_ID_OF_SRC_PORT24_MASK, 1748 FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2)); 1749 1750 return 0; 1751} 1752 1753static int airoha_dev_init(struct net_device *dev) 1754{ 1755 struct airoha_gdm_port *port = netdev_priv(dev); 1756 struct airoha_qdma *qdma = port->qdma; 1757 struct airoha_eth *eth = qdma->eth; 1758 u32 pse_port, fe_cpu_port; 1759 u8 ppe_id; 1760 1761 airoha_set_macaddr(port, dev->dev_addr); 1762 1763 switch (port->id) { 1764 case 3: 1765 case 4: 1766 /* If GDM2 is active we can't enable loopback */ 1767 if (!eth->ports[1]) { 1768 int err; 1769 1770 err = airhoha_set_gdm2_loopback(port); 1771 if (err) 1772 return err; 1773 } 1774 fallthrough; 1775 case 2: 1776 if (airoha_ppe_is_enabled(eth, 1)) { 1777 /* For PPE2 always use secondary cpu port. */ 1778 fe_cpu_port = FE_PSE_PORT_CDM2; 1779 pse_port = FE_PSE_PORT_PPE2; 1780 break; 1781 } 1782 fallthrough; 1783 default: { 1784 u8 qdma_id = qdma - ð->qdma[0]; 1785 1786 /* For PPE1 select cpu port according to the running QDMA. */ 1787 fe_cpu_port = qdma_id ? FE_PSE_PORT_CDM2 : FE_PSE_PORT_CDM1; 1788 pse_port = FE_PSE_PORT_PPE1; 1789 break; 1790 } 1791 } 1792 1793 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port); 1794 ppe_id = pse_port == FE_PSE_PORT_PPE2 ? 1 : 0; 1795 airoha_fe_rmw(eth, REG_PPE_DFT_CPORT0(ppe_id), 1796 DFT_CPORT_MASK(port->id), 1797 fe_cpu_port << __ffs(DFT_CPORT_MASK(port->id))); 1798 1799 return 0; 1800} 1801 1802static void airoha_dev_get_stats64(struct net_device *dev, 1803 struct rtnl_link_stats64 *storage) 1804{ 1805 struct airoha_gdm_port *port = netdev_priv(dev); 1806 unsigned int start; 1807 1808 airoha_update_hw_stats(port); 1809 do { 1810 start = u64_stats_fetch_begin(&port->stats.syncp); 1811 storage->rx_packets = port->stats.rx_ok_pkts; 1812 storage->tx_packets = port->stats.tx_ok_pkts; 1813 storage->rx_bytes = port->stats.rx_ok_bytes; 1814 storage->tx_bytes = port->stats.tx_ok_bytes; 1815 storage->multicast = port->stats.rx_multicast; 1816 storage->rx_errors = port->stats.rx_errors; 1817 storage->rx_dropped = port->stats.rx_drops; 1818 storage->tx_dropped = port->stats.tx_drops; 1819 storage->rx_crc_errors = port->stats.rx_crc_error; 1820 storage->rx_over_errors = port->stats.rx_over_errors; 1821 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1822} 1823 1824static int airoha_dev_change_mtu(struct net_device *dev, int mtu) 1825{ 1826 struct airoha_gdm_port *port = netdev_priv(dev); 1827 struct airoha_eth *eth = port->qdma->eth; 1828 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN; 1829 1830 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id), 1831 GDM_LONG_LEN_MASK, 1832 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1833 WRITE_ONCE(dev->mtu, mtu); 1834 1835 return 0; 1836} 1837 1838static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb, 1839 struct net_device *sb_dev) 1840{ 1841 struct airoha_gdm_port *port = netdev_priv(dev); 1842 int queue, channel; 1843 1844 /* For dsa device select QoS channel according to the dsa user port 1845 * index, rely on port id otherwise. Select QoS queue based on the 1846 * skb priority. 1847 */ 1848 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id; 1849 channel = channel % AIROHA_NUM_QOS_CHANNELS; 1850 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ 1851 queue = channel * AIROHA_NUM_QOS_QUEUES + queue; 1852 1853 return queue < dev->num_tx_queues ? queue : 0; 1854} 1855 1856static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev) 1857{ 1858#if IS_ENABLED(CONFIG_NET_DSA) 1859 struct ethhdr *ehdr; 1860 u8 xmit_tpid; 1861 u16 tag; 1862 1863 if (!netdev_uses_dsa(dev)) 1864 return 0; 1865 1866 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) 1867 return 0; 1868 1869 if (skb_cow_head(skb, 0)) 1870 return 0; 1871 1872 ehdr = (struct ethhdr *)skb->data; 1873 tag = be16_to_cpu(ehdr->h_proto); 1874 xmit_tpid = tag >> 8; 1875 1876 switch (xmit_tpid) { 1877 case MTK_HDR_XMIT_TAGGED_TPID_8100: 1878 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q); 1879 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8); 1880 break; 1881 case MTK_HDR_XMIT_TAGGED_TPID_88A8: 1882 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD); 1883 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8); 1884 break; 1885 default: 1886 /* PPE module requires untagged DSA packets to work properly, 1887 * so move DSA tag to DMA descriptor. 1888 */ 1889 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN); 1890 __skb_pull(skb, MTK_HDR_LEN); 1891 break; 1892 } 1893 1894 return tag; 1895#else 1896 return 0; 1897#endif 1898} 1899 1900static int airoha_get_fe_port(struct airoha_gdm_port *port) 1901{ 1902 struct airoha_qdma *qdma = port->qdma; 1903 struct airoha_eth *eth = qdma->eth; 1904 1905 switch (eth->soc->version) { 1906 case 0x7583: 1907 return port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1908 : port->id; 1909 case 0x7581: 1910 default: 1911 return port->id == AIROHA_GDM4_IDX ? FE_PSE_PORT_GDM4 1912 : port->id; 1913 } 1914} 1915 1916static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, 1917 struct net_device *dev) 1918{ 1919 struct airoha_gdm_port *port = netdev_priv(dev); 1920 struct airoha_qdma *qdma = port->qdma; 1921 u32 nr_frags, tag, msg0, msg1, len; 1922 struct airoha_queue_entry *e; 1923 struct netdev_queue *txq; 1924 struct airoha_queue *q; 1925 LIST_HEAD(tx_list); 1926 void *data; 1927 int i, qid; 1928 u16 index; 1929 u8 fport; 1930 1931 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx); 1932 tag = airoha_get_dsa_tag(skb, dev); 1933 1934 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, 1935 qid / AIROHA_NUM_QOS_QUEUES) | 1936 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK, 1937 qid % AIROHA_NUM_QOS_QUEUES) | 1938 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag); 1939 if (skb->ip_summed == CHECKSUM_PARTIAL) 1940 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) | 1941 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) | 1942 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1); 1943 1944 /* TSO: fill MSS info in tcp checksum field */ 1945 if (skb_is_gso(skb)) { 1946 if (skb_cow_head(skb, 0)) 1947 goto error; 1948 1949 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | 1950 SKB_GSO_TCPV6)) { 1951 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size); 1952 1953 tcp_hdr(skb)->check = (__force __sum16)csum; 1954 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1); 1955 } 1956 } 1957 1958 fport = airoha_get_fe_port(port); 1959 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | 1960 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); 1961 1962 q = &qdma->q_tx[qid]; 1963 if (WARN_ON_ONCE(!q->ndesc)) 1964 goto error; 1965 1966 spin_lock_bh(&q->lock); 1967 1968 txq = netdev_get_tx_queue(dev, qid); 1969 nr_frags = 1 + skb_shinfo(skb)->nr_frags; 1970 1971 if (q->queued + nr_frags >= q->ndesc) { 1972 /* not enough space in the queue */ 1973 netif_tx_stop_queue(txq); 1974 spin_unlock_bh(&q->lock); 1975 return NETDEV_TX_BUSY; 1976 } 1977 1978 len = skb_headlen(skb); 1979 data = skb->data; 1980 1981 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 1982 list); 1983 index = e - q->entry; 1984 1985 for (i = 0; i < nr_frags; i++) { 1986 struct airoha_qdma_desc *desc = &q->desc[index]; 1987 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1988 dma_addr_t addr; 1989 u32 val; 1990 1991 addr = dma_map_single(dev->dev.parent, data, len, 1992 DMA_TO_DEVICE); 1993 if (unlikely(dma_mapping_error(dev->dev.parent, addr))) 1994 goto error_unmap; 1995 1996 list_move_tail(&e->list, &tx_list); 1997 e->skb = i ? NULL : skb; 1998 e->dma_addr = addr; 1999 e->dma_len = len; 2000 2001 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 2002 list); 2003 index = e - q->entry; 2004 2005 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len); 2006 if (i < nr_frags - 1) 2007 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1); 2008 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 2009 WRITE_ONCE(desc->addr, cpu_to_le32(addr)); 2010 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); 2011 WRITE_ONCE(desc->data, cpu_to_le32(val)); 2012 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); 2013 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); 2014 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); 2015 2016 data = skb_frag_address(frag); 2017 len = skb_frag_size(frag); 2018 } 2019 q->queued += i; 2020 2021 skb_tx_timestamp(skb); 2022 netdev_tx_sent_queue(txq, skb->len); 2023 2024 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 2025 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), 2026 TX_RING_CPU_IDX_MASK, 2027 FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); 2028 2029 if (q->ndesc - q->queued < q->free_thr) 2030 netif_tx_stop_queue(txq); 2031 2032 spin_unlock_bh(&q->lock); 2033 2034 return NETDEV_TX_OK; 2035 2036error_unmap: 2037 while (!list_empty(&tx_list)) { 2038 e = list_first_entry(&tx_list, struct airoha_queue_entry, 2039 list); 2040 dma_unmap_single(dev->dev.parent, e->dma_addr, e->dma_len, 2041 DMA_TO_DEVICE); 2042 e->dma_addr = 0; 2043 list_move_tail(&e->list, &q->tx_list); 2044 } 2045 2046 spin_unlock_bh(&q->lock); 2047error: 2048 dev_kfree_skb_any(skb); 2049 dev->stats.tx_dropped++; 2050 2051 return NETDEV_TX_OK; 2052} 2053 2054static void airoha_ethtool_get_drvinfo(struct net_device *dev, 2055 struct ethtool_drvinfo *info) 2056{ 2057 struct airoha_gdm_port *port = netdev_priv(dev); 2058 struct airoha_eth *eth = port->qdma->eth; 2059 2060 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver)); 2061 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info)); 2062} 2063 2064static void airoha_ethtool_get_mac_stats(struct net_device *dev, 2065 struct ethtool_eth_mac_stats *stats) 2066{ 2067 struct airoha_gdm_port *port = netdev_priv(dev); 2068 unsigned int start; 2069 2070 airoha_update_hw_stats(port); 2071 do { 2072 start = u64_stats_fetch_begin(&port->stats.syncp); 2073 stats->FramesTransmittedOK = port->stats.tx_ok_pkts; 2074 stats->OctetsTransmittedOK = port->stats.tx_ok_bytes; 2075 stats->MulticastFramesXmittedOK = port->stats.tx_multicast; 2076 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast; 2077 stats->FramesReceivedOK = port->stats.rx_ok_pkts; 2078 stats->OctetsReceivedOK = port->stats.rx_ok_bytes; 2079 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast; 2080 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2081} 2082 2083static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = { 2084 { 0, 64 }, 2085 { 65, 127 }, 2086 { 128, 255 }, 2087 { 256, 511 }, 2088 { 512, 1023 }, 2089 { 1024, 1518 }, 2090 { 1519, 10239 }, 2091 {}, 2092}; 2093 2094static void 2095airoha_ethtool_get_rmon_stats(struct net_device *dev, 2096 struct ethtool_rmon_stats *stats, 2097 const struct ethtool_rmon_hist_range **ranges) 2098{ 2099 struct airoha_gdm_port *port = netdev_priv(dev); 2100 struct airoha_hw_stats *hw_stats = &port->stats; 2101 unsigned int start; 2102 2103 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2104 ARRAY_SIZE(hw_stats->tx_len) + 1); 2105 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2106 ARRAY_SIZE(hw_stats->rx_len) + 1); 2107 2108 *ranges = airoha_ethtool_rmon_ranges; 2109 airoha_update_hw_stats(port); 2110 do { 2111 int i; 2112 2113 start = u64_stats_fetch_begin(&port->stats.syncp); 2114 stats->fragments = hw_stats->rx_fragment; 2115 stats->jabbers = hw_stats->rx_jabber; 2116 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1; 2117 i++) { 2118 stats->hist[i] = hw_stats->rx_len[i]; 2119 stats->hist_tx[i] = hw_stats->tx_len[i]; 2120 } 2121 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2122} 2123 2124static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port, 2125 int channel, enum tx_sched_mode mode, 2126 const u16 *weights, u8 n_weights) 2127{ 2128 int i; 2129 2130 for (i = 0; i < AIROHA_NUM_TX_RING; i++) 2131 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), 2132 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); 2133 2134 for (i = 0; i < n_weights; i++) { 2135 u32 status; 2136 int err; 2137 2138 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG, 2139 TWRR_RW_CMD_MASK | 2140 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) | 2141 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) | 2142 FIELD_PREP(TWRR_VALUE_MASK, weights[i])); 2143 err = read_poll_timeout(airoha_qdma_rr, status, 2144 status & TWRR_RW_CMD_DONE, 2145 USEC_PER_MSEC, 10 * USEC_PER_MSEC, 2146 true, port->qdma, 2147 REG_TXWRR_WEIGHT_CFG); 2148 if (err) 2149 return err; 2150 } 2151 2152 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3), 2153 CHAN_QOS_MODE_MASK(channel), 2154 mode << __ffs(CHAN_QOS_MODE_MASK(channel))); 2155 2156 return 0; 2157} 2158 2159static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port, 2160 int channel) 2161{ 2162 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2163 2164 return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w, 2165 ARRAY_SIZE(w)); 2166} 2167 2168static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port, 2169 int channel, 2170 struct tc_ets_qopt_offload *opt) 2171{ 2172 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; 2173 enum tx_sched_mode mode = TC_SCH_SP; 2174 u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2175 int i, nstrict = 0; 2176 2177 if (p->bands > AIROHA_NUM_QOS_QUEUES) 2178 return -EINVAL; 2179 2180 for (i = 0; i < p->bands; i++) { 2181 if (!p->quanta[i]) 2182 nstrict++; 2183 } 2184 2185 /* this configuration is not supported by the hw */ 2186 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) 2187 return -EINVAL; 2188 2189 /* EN7581 SoC supports fixed QoS band priority where WRR queues have 2190 * lowest priorities with respect to SP ones. 2191 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn 2192 */ 2193 for (i = 0; i < nstrict; i++) { 2194 if (p->priomap[p->bands - i - 1] != i) 2195 return -EINVAL; 2196 } 2197 2198 for (i = 0; i < p->bands - nstrict; i++) { 2199 if (p->priomap[i] != nstrict + i) 2200 return -EINVAL; 2201 2202 w[i] = p->weights[nstrict + i]; 2203 } 2204 2205 if (!nstrict) 2206 mode = TC_SCH_WRR8; 2207 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1) 2208 mode = nstrict + 1; 2209 2210 return airoha_qdma_set_chan_tx_sched(port, channel, mode, w, 2211 ARRAY_SIZE(w)); 2212} 2213 2214static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port, 2215 int channel, 2216 struct tc_ets_qopt_offload *opt) 2217{ 2218 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma, 2219 REG_CNTR_VAL(channel << 1)); 2220 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma, 2221 REG_CNTR_VAL((channel << 1) + 1)); 2222 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) + 2223 (fwd_tx_packets - port->fwd_tx_packets); 2224 _bstats_update(opt->stats.bstats, 0, tx_packets); 2225 2226 port->cpu_tx_packets = cpu_tx_packets; 2227 port->fwd_tx_packets = fwd_tx_packets; 2228 2229 return 0; 2230} 2231 2232static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port, 2233 struct tc_ets_qopt_offload *opt) 2234{ 2235 int channel; 2236 2237 if (opt->parent == TC_H_ROOT) 2238 return -EINVAL; 2239 2240 channel = TC_H_MAJ(opt->handle) >> 16; 2241 channel = channel % AIROHA_NUM_QOS_CHANNELS; 2242 2243 switch (opt->command) { 2244 case TC_ETS_REPLACE: 2245 return airoha_qdma_set_tx_ets_sched(port, channel, opt); 2246 case TC_ETS_DESTROY: 2247 /* PRIO is default qdisc scheduler */ 2248 return airoha_qdma_set_tx_prio_sched(port, channel); 2249 case TC_ETS_STATS: 2250 return airoha_qdma_get_tx_ets_stats(port, channel, opt); 2251 default: 2252 return -EOPNOTSUPP; 2253 } 2254} 2255 2256static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id, 2257 u32 addr, enum trtcm_param_type param, 2258 u32 *val_low, u32 *val_high) 2259{ 2260 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2261 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2262 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2263 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2264 2265 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2266 if (read_poll_timeout(airoha_qdma_rr, val, 2267 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2268 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma, 2269 REG_TRTCM_CFG_PARAM(addr))) 2270 return -ETIMEDOUT; 2271 2272 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2273 if (val_high) 2274 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2275 2276 return 0; 2277} 2278 2279static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id, 2280 u32 addr, enum trtcm_param_type param, 2281 u32 val) 2282{ 2283 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2284 u32 config = RATE_LIMIT_PARAM_RW_MASK | 2285 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2286 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2287 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2288 2289 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2290 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2291 2292 return read_poll_timeout(airoha_qdma_rr, val, 2293 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2294 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2295 qdma, REG_TRTCM_CFG_PARAM(addr)); 2296} 2297 2298static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id, 2299 u32 addr, bool enable, u32 enable_mask) 2300{ 2301 u32 val; 2302 int err; 2303 2304 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2305 &val, NULL); 2306 if (err) 2307 return err; 2308 2309 val = enable ? val | enable_mask : val & ~enable_mask; 2310 2311 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2312 val); 2313} 2314 2315static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma, 2316 int queue_id, u32 rate_val, 2317 u32 bucket_size) 2318{ 2319 u32 val, config, tick, unit, rate, rate_frac; 2320 int err; 2321 2322 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2323 TRTCM_MISC_MODE, &config, NULL); 2324 if (err) 2325 return err; 2326 2327 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG); 2328 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2329 if (config & TRTCM_TICK_SEL) 2330 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2331 if (!tick) 2332 return -EINVAL; 2333 2334 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2335 if (!unit) 2336 return -EINVAL; 2337 2338 rate = rate_val / unit; 2339 rate_frac = rate_val % unit; 2340 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2341 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2342 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2343 2344 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2345 TRTCM_TOKEN_RATE_MODE, rate); 2346 if (err) 2347 return err; 2348 2349 val = bucket_size; 2350 if (!(config & TRTCM_PKT_MODE)) 2351 val = max_t(u32, val, MIN_TOKEN_SIZE); 2352 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2353 2354 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2355 TRTCM_BUCKETSIZE_SHIFT_MODE, val); 2356} 2357 2358static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id, 2359 bool enable, enum trtcm_unit_type unit) 2360{ 2361 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8; 2362 enum trtcm_param mode = TRTCM_METER_MODE; 2363 int err; 2364 2365 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0; 2366 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2367 enable, mode); 2368 if (err) 2369 return err; 2370 2371 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2372 tick_sel, TRTCM_TICK_SEL); 2373} 2374 2375static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel, 2376 u32 addr, enum trtcm_param_type param, 2377 enum trtcm_mode_type mode, 2378 u32 *val_low, u32 *val_high) 2379{ 2380 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2381 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2382 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2383 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2384 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2385 2386 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2387 if (read_poll_timeout(airoha_qdma_rr, val, 2388 val & TRTCM_PARAM_RW_DONE_MASK, 2389 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2390 qdma, REG_TRTCM_CFG_PARAM(addr))) 2391 return -ETIMEDOUT; 2392 2393 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2394 if (val_high) 2395 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2396 2397 return 0; 2398} 2399 2400static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel, 2401 u32 addr, enum trtcm_param_type param, 2402 enum trtcm_mode_type mode, u32 val) 2403{ 2404 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2405 u32 config = TRTCM_PARAM_RW_MASK | 2406 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2407 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2408 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2409 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2410 2411 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2412 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2413 2414 return read_poll_timeout(airoha_qdma_rr, val, 2415 val & TRTCM_PARAM_RW_DONE_MASK, 2416 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2417 qdma, REG_TRTCM_CFG_PARAM(addr)); 2418} 2419 2420static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel, 2421 u32 addr, enum trtcm_mode_type mode, 2422 bool enable, u32 enable_mask) 2423{ 2424 u32 val; 2425 2426 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2427 mode, &val, NULL)) 2428 return -EINVAL; 2429 2430 val = enable ? val | enable_mask : val & ~enable_mask; 2431 2432 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2433 mode, val); 2434} 2435 2436static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma, 2437 int channel, u32 addr, 2438 enum trtcm_mode_type mode, 2439 u32 rate_val, u32 bucket_size) 2440{ 2441 u32 val, config, tick, unit, rate, rate_frac; 2442 int err; 2443 2444 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2445 mode, &config, NULL)) 2446 return -EINVAL; 2447 2448 val = airoha_qdma_rr(qdma, addr); 2449 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2450 if (config & TRTCM_TICK_SEL) 2451 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2452 if (!tick) 2453 return -EINVAL; 2454 2455 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2456 if (!unit) 2457 return -EINVAL; 2458 2459 rate = rate_val / unit; 2460 rate_frac = rate_val % unit; 2461 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2462 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2463 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2464 2465 err = airoha_qdma_set_trtcm_param(qdma, channel, addr, 2466 TRTCM_TOKEN_RATE_MODE, mode, rate); 2467 if (err) 2468 return err; 2469 2470 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE); 2471 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2472 2473 return airoha_qdma_set_trtcm_param(qdma, channel, addr, 2474 TRTCM_BUCKETSIZE_SHIFT_MODE, 2475 mode, val); 2476} 2477 2478static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port, 2479 int channel, u32 rate, 2480 u32 bucket_size) 2481{ 2482 int i, err; 2483 2484 for (i = 0; i <= TRTCM_PEAK_MODE; i++) { 2485 err = airoha_qdma_set_trtcm_config(port->qdma, channel, 2486 REG_EGRESS_TRTCM_CFG, i, 2487 !!rate, TRTCM_METER_MODE); 2488 if (err) 2489 return err; 2490 2491 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel, 2492 REG_EGRESS_TRTCM_CFG, 2493 i, rate, bucket_size); 2494 if (err) 2495 return err; 2496 } 2497 2498 return 0; 2499} 2500 2501static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port, 2502 struct tc_htb_qopt_offload *opt) 2503{ 2504 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2505 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */ 2506 struct net_device *dev = port->dev; 2507 int num_tx_queues = dev->real_num_tx_queues; 2508 int err; 2509 2510 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) { 2511 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid"); 2512 return -EINVAL; 2513 } 2514 2515 err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum); 2516 if (err) { 2517 NL_SET_ERR_MSG_MOD(opt->extack, 2518 "failed configuring htb offload"); 2519 return err; 2520 } 2521 2522 if (opt->command == TC_HTB_NODE_MODIFY) 2523 return 0; 2524 2525 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1); 2526 if (err) { 2527 airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum); 2528 NL_SET_ERR_MSG_MOD(opt->extack, 2529 "failed setting real_num_tx_queues"); 2530 return err; 2531 } 2532 2533 set_bit(channel, port->qos_sq_bmap); 2534 opt->qid = AIROHA_NUM_TX_RING + channel; 2535 2536 return 0; 2537} 2538 2539static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port, 2540 u32 rate, u32 bucket_size, 2541 enum trtcm_unit_type unit_type) 2542{ 2543 struct airoha_qdma *qdma = port->qdma; 2544 int i; 2545 2546 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 2547 int err; 2548 2549 if (!qdma->q_rx[i].ndesc) 2550 continue; 2551 2552 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type); 2553 if (err) 2554 return err; 2555 2556 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate, 2557 bucket_size); 2558 if (err) 2559 return err; 2560 } 2561 2562 return 0; 2563} 2564 2565static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f) 2566{ 2567 const struct flow_action *actions = &f->rule->action; 2568 const struct flow_action_entry *act; 2569 2570 if (!flow_action_has_entries(actions)) { 2571 NL_SET_ERR_MSG_MOD(f->common.extack, 2572 "filter run with no actions"); 2573 return -EINVAL; 2574 } 2575 2576 if (!flow_offload_has_one_action(actions)) { 2577 NL_SET_ERR_MSG_MOD(f->common.extack, 2578 "only once action per filter is supported"); 2579 return -EOPNOTSUPP; 2580 } 2581 2582 act = &actions->entries[0]; 2583 if (act->id != FLOW_ACTION_POLICE) { 2584 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action"); 2585 return -EOPNOTSUPP; 2586 } 2587 2588 if (act->police.exceed.act_id != FLOW_ACTION_DROP) { 2589 NL_SET_ERR_MSG_MOD(f->common.extack, 2590 "invalid exceed action id"); 2591 return -EOPNOTSUPP; 2592 } 2593 2594 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) { 2595 NL_SET_ERR_MSG_MOD(f->common.extack, 2596 "invalid notexceed action id"); 2597 return -EOPNOTSUPP; 2598 } 2599 2600 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT && 2601 !flow_action_is_last_entry(actions, act)) { 2602 NL_SET_ERR_MSG_MOD(f->common.extack, 2603 "action accept must be last"); 2604 return -EOPNOTSUPP; 2605 } 2606 2607 if (act->police.peakrate_bytes_ps || act->police.avrate || 2608 act->police.overhead || act->police.mtu) { 2609 NL_SET_ERR_MSG_MOD(f->common.extack, 2610 "peakrate/avrate/overhead/mtu unsupported"); 2611 return -EOPNOTSUPP; 2612 } 2613 2614 return 0; 2615} 2616 2617static int airoha_dev_tc_matchall(struct net_device *dev, 2618 struct tc_cls_matchall_offload *f) 2619{ 2620 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT; 2621 struct airoha_gdm_port *port = netdev_priv(dev); 2622 u32 rate = 0, bucket_size = 0; 2623 2624 switch (f->command) { 2625 case TC_CLSMATCHALL_REPLACE: { 2626 const struct flow_action_entry *act; 2627 int err; 2628 2629 err = airoha_tc_matchall_act_validate(f); 2630 if (err) 2631 return err; 2632 2633 act = &f->rule->action.entries[0]; 2634 if (act->police.rate_pkt_ps) { 2635 rate = act->police.rate_pkt_ps; 2636 bucket_size = act->police.burst_pkt; 2637 unit_type = TRTCM_PACKET_UNIT; 2638 } else { 2639 rate = div_u64(act->police.rate_bytes_ps, 1000); 2640 rate = rate << 3; /* Kbps */ 2641 bucket_size = act->police.burst; 2642 } 2643 fallthrough; 2644 } 2645 case TC_CLSMATCHALL_DESTROY: 2646 return airoha_qdma_set_rx_meter(port, rate, bucket_size, 2647 unit_type); 2648 default: 2649 return -EOPNOTSUPP; 2650 } 2651} 2652 2653static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type, 2654 void *type_data, void *cb_priv) 2655{ 2656 struct net_device *dev = cb_priv; 2657 struct airoha_gdm_port *port = netdev_priv(dev); 2658 struct airoha_eth *eth = port->qdma->eth; 2659 2660 if (!tc_can_offload(dev)) 2661 return -EOPNOTSUPP; 2662 2663 switch (type) { 2664 case TC_SETUP_CLSFLOWER: 2665 return airoha_ppe_setup_tc_block_cb(ð->ppe->dev, type_data); 2666 case TC_SETUP_CLSMATCHALL: 2667 return airoha_dev_tc_matchall(dev, type_data); 2668 default: 2669 return -EOPNOTSUPP; 2670 } 2671} 2672 2673static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port, 2674 struct flow_block_offload *f) 2675{ 2676 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb; 2677 static LIST_HEAD(block_cb_list); 2678 struct flow_block_cb *block_cb; 2679 2680 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2681 return -EOPNOTSUPP; 2682 2683 f->driver_block_list = &block_cb_list; 2684 switch (f->command) { 2685 case FLOW_BLOCK_BIND: 2686 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2687 if (block_cb) { 2688 flow_block_cb_incref(block_cb); 2689 return 0; 2690 } 2691 block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL); 2692 if (IS_ERR(block_cb)) 2693 return PTR_ERR(block_cb); 2694 2695 flow_block_cb_incref(block_cb); 2696 flow_block_cb_add(block_cb, f); 2697 list_add_tail(&block_cb->driver_list, &block_cb_list); 2698 return 0; 2699 case FLOW_BLOCK_UNBIND: 2700 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2701 if (!block_cb) 2702 return -ENOENT; 2703 2704 if (!flow_block_cb_decref(block_cb)) { 2705 flow_block_cb_remove(block_cb, f); 2706 list_del(&block_cb->driver_list); 2707 } 2708 return 0; 2709 default: 2710 return -EOPNOTSUPP; 2711 } 2712} 2713 2714static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue) 2715{ 2716 struct net_device *dev = port->dev; 2717 2718 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1); 2719 airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0); 2720 clear_bit(queue, port->qos_sq_bmap); 2721} 2722 2723static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port, 2724 struct tc_htb_qopt_offload *opt) 2725{ 2726 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2727 2728 if (!test_bit(channel, port->qos_sq_bmap)) { 2729 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2730 return -EINVAL; 2731 } 2732 2733 airoha_tc_remove_htb_queue(port, channel); 2734 2735 return 0; 2736} 2737 2738static int airoha_tc_htb_destroy(struct airoha_gdm_port *port) 2739{ 2740 int q; 2741 2742 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS) 2743 airoha_tc_remove_htb_queue(port, q); 2744 2745 return 0; 2746} 2747 2748static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port, 2749 struct tc_htb_qopt_offload *opt) 2750{ 2751 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2752 2753 if (!test_bit(channel, port->qos_sq_bmap)) { 2754 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2755 return -EINVAL; 2756 } 2757 2758 opt->qid = AIROHA_NUM_TX_RING + channel; 2759 2760 return 0; 2761} 2762 2763static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port, 2764 struct tc_htb_qopt_offload *opt) 2765{ 2766 switch (opt->command) { 2767 case TC_HTB_CREATE: 2768 break; 2769 case TC_HTB_DESTROY: 2770 return airoha_tc_htb_destroy(port); 2771 case TC_HTB_NODE_MODIFY: 2772 case TC_HTB_LEAF_ALLOC_QUEUE: 2773 return airoha_tc_htb_alloc_leaf_queue(port, opt); 2774 case TC_HTB_LEAF_DEL: 2775 case TC_HTB_LEAF_DEL_LAST: 2776 case TC_HTB_LEAF_DEL_LAST_FORCE: 2777 return airoha_tc_htb_delete_leaf_queue(port, opt); 2778 case TC_HTB_LEAF_QUERY_QUEUE: 2779 return airoha_tc_get_htb_get_leaf_queue(port, opt); 2780 default: 2781 return -EOPNOTSUPP; 2782 } 2783 2784 return 0; 2785} 2786 2787static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 2788 void *type_data) 2789{ 2790 struct airoha_gdm_port *port = netdev_priv(dev); 2791 2792 switch (type) { 2793 case TC_SETUP_QDISC_ETS: 2794 return airoha_tc_setup_qdisc_ets(port, type_data); 2795 case TC_SETUP_QDISC_HTB: 2796 return airoha_tc_setup_qdisc_htb(port, type_data); 2797 case TC_SETUP_BLOCK: 2798 case TC_SETUP_FT: 2799 return airoha_dev_setup_tc_block(port, type_data); 2800 default: 2801 return -EOPNOTSUPP; 2802 } 2803} 2804 2805static const struct net_device_ops airoha_netdev_ops = { 2806 .ndo_init = airoha_dev_init, 2807 .ndo_open = airoha_dev_open, 2808 .ndo_stop = airoha_dev_stop, 2809 .ndo_change_mtu = airoha_dev_change_mtu, 2810 .ndo_select_queue = airoha_dev_select_queue, 2811 .ndo_start_xmit = airoha_dev_xmit, 2812 .ndo_get_stats64 = airoha_dev_get_stats64, 2813 .ndo_set_mac_address = airoha_dev_set_macaddr, 2814 .ndo_setup_tc = airoha_dev_tc_setup, 2815}; 2816 2817static const struct ethtool_ops airoha_ethtool_ops = { 2818 .get_drvinfo = airoha_ethtool_get_drvinfo, 2819 .get_eth_mac_stats = airoha_ethtool_get_mac_stats, 2820 .get_rmon_stats = airoha_ethtool_get_rmon_stats, 2821 .get_link = ethtool_op_get_link, 2822}; 2823 2824static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port) 2825{ 2826 int i; 2827 2828 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2829 struct metadata_dst *md_dst; 2830 2831 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 2832 GFP_KERNEL); 2833 if (!md_dst) 2834 return -ENOMEM; 2835 2836 md_dst->u.port_info.port_id = i; 2837 port->dsa_meta[i] = md_dst; 2838 } 2839 2840 return 0; 2841} 2842 2843static void airoha_metadata_dst_free(struct airoha_gdm_port *port) 2844{ 2845 int i; 2846 2847 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2848 if (!port->dsa_meta[i]) 2849 continue; 2850 2851 metadata_dst_free(port->dsa_meta[i]); 2852 } 2853} 2854 2855bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 2856 struct airoha_gdm_port *port) 2857{ 2858 int i; 2859 2860 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2861 if (eth->ports[i] == port) 2862 return true; 2863 } 2864 2865 return false; 2866} 2867 2868static int airoha_alloc_gdm_port(struct airoha_eth *eth, 2869 struct device_node *np, int index) 2870{ 2871 const __be32 *id_ptr = of_get_property(np, "reg", NULL); 2872 struct airoha_gdm_port *port; 2873 struct airoha_qdma *qdma; 2874 struct net_device *dev; 2875 int err, p; 2876 u32 id; 2877 2878 if (!id_ptr) { 2879 dev_err(eth->dev, "missing gdm port id\n"); 2880 return -EINVAL; 2881 } 2882 2883 id = be32_to_cpup(id_ptr); 2884 p = id - 1; 2885 2886 if (!id || id > ARRAY_SIZE(eth->ports)) { 2887 dev_err(eth->dev, "invalid gdm port id: %d\n", id); 2888 return -EINVAL; 2889 } 2890 2891 if (eth->ports[p]) { 2892 dev_err(eth->dev, "duplicate gdm port id: %d\n", id); 2893 return -EINVAL; 2894 } 2895 2896 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port), 2897 AIROHA_NUM_NETDEV_TX_RINGS, 2898 AIROHA_NUM_RX_RING); 2899 if (!dev) { 2900 dev_err(eth->dev, "alloc_etherdev failed\n"); 2901 return -ENOMEM; 2902 } 2903 2904 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA]; 2905 dev->netdev_ops = &airoha_netdev_ops; 2906 dev->ethtool_ops = &airoha_ethtool_ops; 2907 dev->max_mtu = AIROHA_MAX_MTU; 2908 dev->watchdog_timeo = 5 * HZ; 2909 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 2910 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | 2911 NETIF_F_SG | NETIF_F_TSO | 2912 NETIF_F_HW_TC; 2913 dev->features |= dev->hw_features; 2914 dev->vlan_features = dev->hw_features; 2915 dev->dev.of_node = np; 2916 dev->irq = qdma->irq_banks[0].irq; 2917 SET_NETDEV_DEV(dev, eth->dev); 2918 2919 /* reserve hw queues for HTB offloading */ 2920 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING); 2921 if (err) 2922 return err; 2923 2924 err = of_get_ethdev_address(np, dev); 2925 if (err) { 2926 if (err == -EPROBE_DEFER) 2927 return err; 2928 2929 eth_hw_addr_random(dev); 2930 dev_info(eth->dev, "generated random MAC address %pM\n", 2931 dev->dev_addr); 2932 } 2933 2934 port = netdev_priv(dev); 2935 u64_stats_init(&port->stats.syncp); 2936 spin_lock_init(&port->stats.lock); 2937 port->qdma = qdma; 2938 port->dev = dev; 2939 port->id = id; 2940 eth->ports[p] = port; 2941 2942 return airoha_metadata_dst_alloc(port); 2943} 2944 2945static int airoha_register_gdm_devices(struct airoha_eth *eth) 2946{ 2947 int i; 2948 2949 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2950 struct airoha_gdm_port *port = eth->ports[i]; 2951 int err; 2952 2953 if (!port) 2954 continue; 2955 2956 err = register_netdev(port->dev); 2957 if (err) 2958 return err; 2959 } 2960 2961 return 0; 2962} 2963 2964static int airoha_probe(struct platform_device *pdev) 2965{ 2966 struct reset_control_bulk_data *xsi_rsts; 2967 struct device_node *np; 2968 struct airoha_eth *eth; 2969 int i, err; 2970 2971 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2972 if (!eth) 2973 return -ENOMEM; 2974 2975 eth->soc = of_device_get_match_data(&pdev->dev); 2976 if (!eth->soc) 2977 return -EINVAL; 2978 2979 eth->dev = &pdev->dev; 2980 2981 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32)); 2982 if (err) { 2983 dev_err(eth->dev, "failed configuring DMA mask\n"); 2984 return err; 2985 } 2986 2987 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe"); 2988 if (IS_ERR(eth->fe_regs)) 2989 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs), 2990 "failed to iomap fe regs\n"); 2991 2992 eth->rsts[0].id = "fe"; 2993 eth->rsts[1].id = "pdma"; 2994 eth->rsts[2].id = "qdma"; 2995 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2996 ARRAY_SIZE(eth->rsts), 2997 eth->rsts); 2998 if (err) { 2999 dev_err(eth->dev, "failed to get bulk reset lines\n"); 3000 return err; 3001 } 3002 3003 xsi_rsts = devm_kcalloc(eth->dev, 3004 eth->soc->num_xsi_rsts, sizeof(*xsi_rsts), 3005 GFP_KERNEL); 3006 if (!xsi_rsts) 3007 return -ENOMEM; 3008 3009 eth->xsi_rsts = xsi_rsts; 3010 for (i = 0; i < eth->soc->num_xsi_rsts; i++) 3011 eth->xsi_rsts[i].id = eth->soc->xsi_rsts_names[i]; 3012 3013 err = devm_reset_control_bulk_get_exclusive(eth->dev, 3014 eth->soc->num_xsi_rsts, 3015 eth->xsi_rsts); 3016 if (err) { 3017 dev_err(eth->dev, "failed to get bulk xsi reset lines\n"); 3018 return err; 3019 } 3020 3021 eth->napi_dev = alloc_netdev_dummy(0); 3022 if (!eth->napi_dev) 3023 return -ENOMEM; 3024 3025 /* Enable threaded NAPI by default */ 3026 eth->napi_dev->threaded = true; 3027 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name)); 3028 platform_set_drvdata(pdev, eth); 3029 3030 err = airoha_hw_init(pdev, eth); 3031 if (err) 3032 goto error_hw_cleanup; 3033 3034 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3035 airoha_qdma_start_napi(ð->qdma[i]); 3036 3037 i = 0; 3038 for_each_child_of_node(pdev->dev.of_node, np) { 3039 if (!of_device_is_compatible(np, "airoha,eth-mac")) 3040 continue; 3041 3042 if (!of_device_is_available(np)) 3043 continue; 3044 3045 err = airoha_alloc_gdm_port(eth, np, i++); 3046 if (err) { 3047 of_node_put(np); 3048 goto error_napi_stop; 3049 } 3050 } 3051 3052 err = airoha_register_gdm_devices(eth); 3053 if (err) 3054 goto error_napi_stop; 3055 3056 return 0; 3057 3058error_napi_stop: 3059 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3060 airoha_qdma_stop_napi(ð->qdma[i]); 3061 airoha_ppe_deinit(eth); 3062error_hw_cleanup: 3063 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3064 airoha_hw_cleanup(ð->qdma[i]); 3065 3066 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3067 struct airoha_gdm_port *port = eth->ports[i]; 3068 3069 if (!port) 3070 continue; 3071 3072 if (port->dev->reg_state == NETREG_REGISTERED) 3073 unregister_netdev(port->dev); 3074 airoha_metadata_dst_free(port); 3075 } 3076 free_netdev(eth->napi_dev); 3077 platform_set_drvdata(pdev, NULL); 3078 3079 return err; 3080} 3081 3082static void airoha_remove(struct platform_device *pdev) 3083{ 3084 struct airoha_eth *eth = platform_get_drvdata(pdev); 3085 int i; 3086 3087 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 3088 airoha_qdma_stop_napi(ð->qdma[i]); 3089 airoha_hw_cleanup(ð->qdma[i]); 3090 } 3091 3092 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3093 struct airoha_gdm_port *port = eth->ports[i]; 3094 3095 if (!port) 3096 continue; 3097 3098 unregister_netdev(port->dev); 3099 airoha_metadata_dst_free(port); 3100 } 3101 free_netdev(eth->napi_dev); 3102 3103 airoha_ppe_deinit(eth); 3104 platform_set_drvdata(pdev, NULL); 3105} 3106 3107static const char * const en7581_xsi_rsts_names[] = { 3108 "xsi-mac", 3109 "hsi0-mac", 3110 "hsi1-mac", 3111 "hsi-mac", 3112 "xfp-mac", 3113}; 3114 3115static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3116{ 3117 switch (port->id) { 3118 case 3: 3119 /* 7581 SoC supports PCIe serdes on GDM3 port */ 3120 if (nbq == 4) 3121 return HSGMII_LAN_7581_PCIE0_SRCPORT; 3122 if (nbq == 5) 3123 return HSGMII_LAN_7581_PCIE1_SRCPORT; 3124 break; 3125 case 4: 3126 /* 7581 SoC supports eth and usb serdes on GDM4 port */ 3127 if (!nbq) 3128 return HSGMII_LAN_7581_ETH_SRCPORT; 3129 if (nbq == 1) 3130 return HSGMII_LAN_7581_USB_SRCPORT; 3131 break; 3132 default: 3133 break; 3134 } 3135 3136 return -EINVAL; 3137} 3138 3139static const char * const an7583_xsi_rsts_names[] = { 3140 "xsi-mac", 3141 "hsi0-mac", 3142 "hsi1-mac", 3143 "xfp-mac", 3144}; 3145 3146static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3147{ 3148 switch (port->id) { 3149 case 3: 3150 /* 7583 SoC supports eth serdes on GDM3 port */ 3151 if (!nbq) 3152 return HSGMII_LAN_7583_ETH_SRCPORT; 3153 break; 3154 case 4: 3155 /* 7583 SoC supports PCIe and USB serdes on GDM4 port */ 3156 if (!nbq) 3157 return HSGMII_LAN_7583_PCIE_SRCPORT; 3158 if (nbq == 1) 3159 return HSGMII_LAN_7583_USB_SRCPORT; 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 return -EINVAL; 3166} 3167 3168static const struct airoha_eth_soc_data en7581_soc_data = { 3169 .version = 0x7581, 3170 .xsi_rsts_names = en7581_xsi_rsts_names, 3171 .num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names), 3172 .num_ppe = 2, 3173 .ops = { 3174 .get_src_port_id = airoha_en7581_get_src_port_id, 3175 }, 3176}; 3177 3178static const struct airoha_eth_soc_data an7583_soc_data = { 3179 .version = 0x7583, 3180 .xsi_rsts_names = an7583_xsi_rsts_names, 3181 .num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names), 3182 .num_ppe = 1, 3183 .ops = { 3184 .get_src_port_id = airoha_an7583_get_src_port_id, 3185 }, 3186}; 3187 3188static const struct of_device_id of_airoha_match[] = { 3189 { .compatible = "airoha,en7581-eth", .data = &en7581_soc_data }, 3190 { .compatible = "airoha,an7583-eth", .data = &an7583_soc_data }, 3191 { /* sentinel */ } 3192}; 3193MODULE_DEVICE_TABLE(of, of_airoha_match); 3194 3195static struct platform_driver airoha_driver = { 3196 .probe = airoha_probe, 3197 .remove = airoha_remove, 3198 .driver = { 3199 .name = KBUILD_MODNAME, 3200 .of_match_table = of_airoha_match, 3201 }, 3202}; 3203module_platform_driver(airoha_driver); 3204 3205MODULE_LICENSE("GPL"); 3206MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 3207MODULE_DESCRIPTION("Ethernet driver for Airoha SoC");
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