FILE
yt921x.h
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linux-6.19.14/drivers/net/dsa/yt921x.h
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 2025 David Yang 4 */ 5 6#ifndef __YT921X_H 7#define __YT921X_H 8 9#include <net/dsa.h> 10 11#define YT921X_SMI_SWITCHID_M GENMASK(3, 2) 12#define YT921X_SMI_SWITCHID(x) FIELD_PREP(YT921X_SMI_SWITCHID_M, (x)) 13#define YT921X_SMI_AD BIT(1) 14#define YT921X_SMI_ADDR 0 15#define YT921X_SMI_DATA YT921X_SMI_AD 16#define YT921X_SMI_RW BIT(0) 17#define YT921X_SMI_WRITE 0 18#define YT921X_SMI_READ YT921X_SMI_RW 19 20#define YT921X_SWITCHID_NUM 4 21 22#define YT921X_RST 0x80000 23#define YT921X_RST_HW BIT(31) 24#define YT921X_RST_SW BIT(1) 25#define YT921X_FUNC 0x80004 26#define YT921X_FUNC_MIB BIT(1) 27#define YT921X_CHIP_ID 0x80008 28#define YT921X_CHIP_ID_MAJOR GENMASK(31, 16) 29#define YT921X_EXT_CPU_PORT 0x8000c 30#define YT921X_EXT_CPU_PORT_TAG_EN BIT(15) 31#define YT921X_EXT_CPU_PORT_PORT_EN BIT(14) 32#define YT921X_EXT_CPU_PORT_PORT_M GENMASK(3, 0) 33#define YT921X_EXT_CPU_PORT_PORT(x) FIELD_PREP(YT921X_EXT_CPU_PORT_PORT_M, (x)) 34#define YT921X_CPU_TAG_TPID 0x80010 35#define YT921X_CPU_TAG_TPID_TPID_M GENMASK(15, 0) 36/* Same as ETH_P_YT921X, but this represents the true HW default, while the 37 * former is a local convention chosen by us. 38 */ 39#define YT921X_CPU_TAG_TPID_TPID_DEFAULT 0x9988 40#define YT921X_PVID_SEL 0x80014 41#define YT921X_PVID_SEL_SVID_PORTn(port) BIT(port) 42#define YT921X_SERDES_CTRL 0x80028 43#define YT921X_SERDES_CTRL_PORTn_TEST(port) BIT((port) - 3) 44#define YT921X_SERDES_CTRL_PORTn(port) BIT((port) - 8) 45#define YT921X_IO_LEVEL 0x80030 46#define YT9215_IO_LEVEL_NORMAL_M GENMASK(5, 4) 47#define YT9215_IO_LEVEL_NORMAL(x) FIELD_PREP(YT9215_IO_LEVEL_NORMAL_M, (x)) 48#define YT9215_IO_LEVEL_NORMAL_3V3 YT9215_IO_LEVEL_NORMAL(0) 49#define YT9215_IO_LEVEL_NORMAL_1V8 YT9215_IO_LEVEL_NORMAL(3) 50#define YT9215_IO_LEVEL_RGMII1_M GENMASK(3, 2) 51#define YT9215_IO_LEVEL_RGMII1(x) FIELD_PREP(YT9215_IO_LEVEL_RGMII1_M, (x)) 52#define YT9215_IO_LEVEL_RGMII1_3V3 YT9215_IO_LEVEL_RGMII1(0) 53#define YT9215_IO_LEVEL_RGMII1_2V5 YT9215_IO_LEVEL_RGMII1(1) 54#define YT9215_IO_LEVEL_RGMII1_1V8 YT9215_IO_LEVEL_RGMII1(2) 55#define YT9215_IO_LEVEL_RGMII0_M GENMASK(1, 0) 56#define YT9215_IO_LEVEL_RGMII0(x) FIELD_PREP(YT9215_IO_LEVEL_RGMII0_M, (x)) 57#define YT9215_IO_LEVEL_RGMII0_3V3 YT9215_IO_LEVEL_RGMII0(0) 58#define YT9215_IO_LEVEL_RGMII0_2V5 YT9215_IO_LEVEL_RGMII0(1) 59#define YT9215_IO_LEVEL_RGMII0_1V8 YT9215_IO_LEVEL_RGMII0(2) 60#define YT9218_IO_LEVEL_RGMII1_M GENMASK(5, 4) 61#define YT9218_IO_LEVEL_RGMII1(x) FIELD_PREP(YT9218_IO_LEVEL_RGMII1_M, (x)) 62#define YT9218_IO_LEVEL_RGMII1_3V3 YT9218_IO_LEVEL_RGMII1(0) 63#define YT9218_IO_LEVEL_RGMII1_2V5 YT9218_IO_LEVEL_RGMII1(1) 64#define YT9218_IO_LEVEL_RGMII1_1V8 YT9218_IO_LEVEL_RGMII1(2) 65#define YT9218_IO_LEVEL_RGMII0_M GENMASK(3, 2) 66#define YT9218_IO_LEVEL_RGMII0(x) FIELD_PREP(YT9218_IO_LEVEL_RGMII0_M, (x)) 67#define YT9218_IO_LEVEL_RGMII0_3V3 YT9218_IO_LEVEL_RGMII0(0) 68#define YT9218_IO_LEVEL_RGMII0_2V5 YT9218_IO_LEVEL_RGMII0(1) 69#define YT9218_IO_LEVEL_RGMII0_1V8 YT9218_IO_LEVEL_RGMII0(2) 70#define YT9218_IO_LEVEL_NORMAL_M GENMASK(1, 0) 71#define YT9218_IO_LEVEL_NORMAL(x) FIELD_PREP(YT9218_IO_LEVEL_NORMAL_M, (x)) 72#define YT9218_IO_LEVEL_NORMAL_3V3 YT9218_IO_LEVEL_NORMAL(0) 73#define YT9218_IO_LEVEL_NORMAL_1V8 YT9218_IO_LEVEL_NORMAL(3) 74#define YT921X_MAC_ADDR_HI2 0x80080 75#define YT921X_MAC_ADDR_LO4 0x80084 76#define YT921X_SERDESn(port) (0x8008c + 4 * ((port) - 8)) 77#define YT921X_SERDES_MODE_M GENMASK(9, 7) 78#define YT921X_SERDES_MODE(x) FIELD_PREP(YT921X_SERDES_MODE_M, (x)) 79#define YT921X_SERDES_MODE_SGMII YT921X_SERDES_MODE(0) 80#define YT921X_SERDES_MODE_REVSGMII YT921X_SERDES_MODE(1) 81#define YT921X_SERDES_MODE_1000BASEX YT921X_SERDES_MODE(2) 82#define YT921X_SERDES_MODE_100BASEX YT921X_SERDES_MODE(3) 83#define YT921X_SERDES_MODE_2500BASEX YT921X_SERDES_MODE(4) 84#define YT921X_SERDES_RX_PAUSE BIT(6) 85#define YT921X_SERDES_TX_PAUSE BIT(5) 86#define YT921X_SERDES_LINK BIT(4) /* force link */ 87#define YT921X_SERDES_DUPLEX_FULL BIT(3) 88#define YT921X_SERDES_SPEED_M GENMASK(2, 0) 89#define YT921X_SERDES_SPEED(x) FIELD_PREP(YT921X_SERDES_SPEED_M, (x)) 90#define YT921X_SERDES_SPEED_10 YT921X_SERDES_SPEED(0) 91#define YT921X_SERDES_SPEED_100 YT921X_SERDES_SPEED(1) 92#define YT921X_SERDES_SPEED_1000 YT921X_SERDES_SPEED(2) 93#define YT921X_SERDES_SPEED_10000 YT921X_SERDES_SPEED(3) 94#define YT921X_SERDES_SPEED_2500 YT921X_SERDES_SPEED(4) 95#define YT921X_PORTn_CTRL(port) (0x80100 + 4 * (port)) 96#define YT921X_PORT_CTRL_PAUSE_AN BIT(10) 97#define YT921X_PORTn_STATUS(port) (0x80200 + 4 * (port)) 98#define YT921X_PORT_LINK BIT(9) /* CTRL: auto negotiation */ 99#define YT921X_PORT_HALF_PAUSE BIT(8) /* Half-duplex back pressure mode */ 100#define YT921X_PORT_DUPLEX_FULL BIT(7) 101#define YT921X_PORT_RX_PAUSE BIT(6) 102#define YT921X_PORT_TX_PAUSE BIT(5) 103#define YT921X_PORT_RX_MAC_EN BIT(4) 104#define YT921X_PORT_TX_MAC_EN BIT(3) 105#define YT921X_PORT_SPEED_M GENMASK(2, 0) 106#define YT921X_PORT_SPEED(x) FIELD_PREP(YT921X_PORT_SPEED_M, (x)) 107#define YT921X_PORT_SPEED_10 YT921X_PORT_SPEED(0) 108#define YT921X_PORT_SPEED_100 YT921X_PORT_SPEED(1) 109#define YT921X_PORT_SPEED_1000 YT921X_PORT_SPEED(2) 110#define YT921X_PORT_SPEED_10000 YT921X_PORT_SPEED(3) 111#define YT921X_PORT_SPEED_2500 YT921X_PORT_SPEED(4) 112#define YT921X_PON_STRAP_FUNC 0x80320 113#define YT921X_PON_STRAP_VAL 0x80324 114#define YT921X_PON_STRAP_CAP 0x80328 115#define YT921X_PON_STRAP_EEE BIT(16) 116#define YT921X_PON_STRAP_LOOP_DETECT BIT(7) 117#define YT921X_MDIO_POLLINGn(port) (0x80364 + 4 * ((port) - 8)) 118#define YT921X_MDIO_POLLING_DUPLEX_FULL BIT(4) 119#define YT921X_MDIO_POLLING_LINK BIT(3) 120#define YT921X_MDIO_POLLING_SPEED_M GENMASK(2, 0) 121#define YT921X_MDIO_POLLING_SPEED(x) FIELD_PREP(YT921X_MDIO_POLLING_SPEED_M, (x)) 122#define YT921X_MDIO_POLLING_SPEED_10 YT921X_MDIO_POLLING_SPEED(0) 123#define YT921X_MDIO_POLLING_SPEED_100 YT921X_MDIO_POLLING_SPEED(1) 124#define YT921X_MDIO_POLLING_SPEED_1000 YT921X_MDIO_POLLING_SPEED(2) 125#define YT921X_MDIO_POLLING_SPEED_10000 YT921X_MDIO_POLLING_SPEED(3) 126#define YT921X_MDIO_POLLING_SPEED_2500 YT921X_MDIO_POLLING_SPEED(4) 127#define YT921X_SENSOR 0x8036c 128#define YT921X_SENSOR_TEMP BIT(18) 129#define YT921X_TEMP 0x80374 130#define YT921X_CHIP_MODE 0x80388 131#define YT921X_CHIP_MODE_MODE GENMASK(1, 0) 132#define YT921X_XMII_CTRL 0x80394 133#define YT921X_XMII_CTRL_PORTn(port) BIT(9 - (port)) /* Yes, it's reversed */ 134#define YT921X_XMIIn(port) (0x80400 + 8 * ((port) - 8)) 135#define YT921X_XMII_MODE_M GENMASK(31, 29) 136#define YT921X_XMII_MODE(x) FIELD_PREP(YT921X_XMII_MODE_M, (x)) 137#define YT921X_XMII_MODE_MII YT921X_XMII_MODE(0) 138#define YT921X_XMII_MODE_REVMII YT921X_XMII_MODE(1) 139#define YT921X_XMII_MODE_RMII YT921X_XMII_MODE(2) 140#define YT921X_XMII_MODE_REVRMII YT921X_XMII_MODE(3) 141#define YT921X_XMII_MODE_RGMII YT921X_XMII_MODE(4) 142#define YT921X_XMII_MODE_DISABLE YT921X_XMII_MODE(5) 143#define YT921X_XMII_LINK BIT(19) /* force link */ 144#define YT921X_XMII_EN BIT(18) 145#define YT921X_XMII_SOFT_RST BIT(17) 146#define YT921X_XMII_RGMII_TX_DELAY_150PS_M GENMASK(16, 13) 147#define YT921X_XMII_RGMII_TX_DELAY_150PS(x) FIELD_PREP(YT921X_XMII_RGMII_TX_DELAY_150PS_M, (x)) 148#define YT921X_XMII_TX_CLK_IN BIT(11) 149#define YT921X_XMII_RX_CLK_IN BIT(10) 150#define YT921X_XMII_RGMII_TX_DELAY_2NS BIT(8) 151#define YT921X_XMII_RGMII_TX_CLK_OUT BIT(7) 152#define YT921X_XMII_RGMII_RX_DELAY_150PS_M GENMASK(6, 3) 153#define YT921X_XMII_RGMII_RX_DELAY_150PS(x) FIELD_PREP(YT921X_XMII_RGMII_RX_DELAY_150PS_M, (x)) 154#define YT921X_XMII_RMII_PHY_TX_CLK_OUT BIT(2) 155#define YT921X_XMII_REVMII_TX_CLK_OUT BIT(1) 156#define YT921X_XMII_REVMII_RX_CLK_OUT BIT(0) 157 158#define YT921X_MACn_FRAME(port) (0x81008 + 0x1000 * (port)) 159#define YT921X_MAC_FRAME_SIZE_M GENMASK(21, 8) 160#define YT921X_MAC_FRAME_SIZE(x) FIELD_PREP(YT921X_MAC_FRAME_SIZE_M, (x)) 161 162#define YT921X_EEEn_VAL(port) (0xa0000 + 0x40 * (port)) 163#define YT921X_EEE_VAL_DATA BIT(1) 164 165#define YT921X_EEE_CTRL 0xb0000 166#define YT921X_EEE_CTRL_ENn(port) BIT(port) 167 168#define YT921X_MIB_CTRL 0xc0004 169#define YT921X_MIB_CTRL_CLEAN BIT(30) 170#define YT921X_MIB_CTRL_PORT_M GENMASK(6, 3) 171#define YT921X_MIB_CTRL_PORT(x) FIELD_PREP(YT921X_MIB_CTRL_PORT_M, (x)) 172#define YT921X_MIB_CTRL_ONE_PORT BIT(1) 173#define YT921X_MIB_CTRL_ALL_PORT BIT(0) 174#define YT921X_MIBn_DATA0(port) (0xc0100 + 0x100 * (port)) 175#define YT921X_MIBn_DATAm(port, x) (YT921X_MIBn_DATA0(port) + 4 * (x)) 176#define YT921X_MIB_DATA_RX_BROADCAST 0x00 177#define YT921X_MIB_DATA_RX_PAUSE 0x04 178#define YT921X_MIB_DATA_RX_MULTICAST 0x08 179#define YT921X_MIB_DATA_RX_CRC_ERR 0x0c 180 181#define YT921X_MIB_DATA_RX_ALIGN_ERR 0x10 182#define YT921X_MIB_DATA_RX_UNDERSIZE_ERR 0x14 183#define YT921X_MIB_DATA_RX_FRAG_ERR 0x18 184#define YT921X_MIB_DATA_RX_PKT_SZ_64 0x1c 185 186#define YT921X_MIB_DATA_RX_PKT_SZ_65_TO_127 0x20 187#define YT921X_MIB_DATA_RX_PKT_SZ_128_TO_255 0x24 188#define YT921X_MIB_DATA_RX_PKT_SZ_256_TO_511 0x28 189#define YT921X_MIB_DATA_RX_PKT_SZ_512_TO_1023 0x2c 190 191#define YT921X_MIB_DATA_RX_PKT_SZ_1024_TO_1518 0x30 192#define YT921X_MIB_DATA_RX_PKT_SZ_1519_TO_MAX 0x34 193/* 0x38: unused */ 194#define YT921X_MIB_DATA_RX_GOOD_BYTES 0x3c 195 196/* 0x40: 64 bytes */ 197#define YT921X_MIB_DATA_RX_BAD_BYTES 0x44 198/* 0x48: 64 bytes */ 199#define YT921X_MIB_DATA_RX_OVERSIZE_ERR 0x4c 200 201#define YT921X_MIB_DATA_RX_DROPPED 0x50 202#define YT921X_MIB_DATA_TX_BROADCAST 0x54 203#define YT921X_MIB_DATA_TX_PAUSE 0x58 204#define YT921X_MIB_DATA_TX_MULTICAST 0x5c 205 206#define YT921X_MIB_DATA_TX_UNDERSIZE_ERR 0x60 207#define YT921X_MIB_DATA_TX_PKT_SZ_64 0x64 208#define YT921X_MIB_DATA_TX_PKT_SZ_65_TO_127 0x68 209#define YT921X_MIB_DATA_TX_PKT_SZ_128_TO_255 0x6c 210 211#define YT921X_MIB_DATA_TX_PKT_SZ_256_TO_511 0x70 212#define YT921X_MIB_DATA_TX_PKT_SZ_512_TO_1023 0x74 213#define YT921X_MIB_DATA_TX_PKT_SZ_1024_TO_1518 0x78 214#define YT921X_MIB_DATA_TX_PKT_SZ_1519_TO_MAX 0x7c 215 216/* 0x80: unused */ 217#define YT921X_MIB_DATA_TX_GOOD_BYTES 0x84 218/* 0x88: 64 bytes */ 219#define YT921X_MIB_DATA_TX_COLLISION 0x8c 220 221#define YT921X_MIB_DATA_TX_EXCESSIVE_COLLISION 0x90 222#define YT921X_MIB_DATA_TX_MULTIPLE_COLLISION 0x94 223#define YT921X_MIB_DATA_TX_SINGLE_COLLISION 0x98 224#define YT921X_MIB_DATA_TX_PKT 0x9c 225 226#define YT921X_MIB_DATA_TX_DEFERRED 0xa0 227#define YT921X_MIB_DATA_TX_LATE_COLLISION 0xa4 228#define YT921X_MIB_DATA_RX_OAM 0xa8 229#define YT921X_MIB_DATA_TX_OAM 0xac 230 231#define YT921X_EDATA_CTRL 0xe0000 232#define YT921X_EDATA_CTRL_ADDR_M GENMASK(15, 8) 233#define YT921X_EDATA_CTRL_ADDR(x) FIELD_PREP(YT921X_EDATA_CTRL_ADDR_M, (x)) 234#define YT921X_EDATA_CTRL_OP_M GENMASK(3, 0) 235#define YT921X_EDATA_CTRL_OP(x) FIELD_PREP(YT921X_EDATA_CTRL_OP_M, (x)) 236#define YT921X_EDATA_CTRL_READ YT921X_EDATA_CTRL_OP(5) 237#define YT921X_EDATA_DATA 0xe0004 238#define YT921X_EDATA_DATA_DATA_M GENMASK(31, 24) 239#define YT921X_EDATA_DATA_STATUS_M GENMASK(3, 0) 240#define YT921X_EDATA_DATA_STATUS(x) FIELD_PREP(YT921X_EDATA_DATA_STATUS_M, (x)) 241#define YT921X_EDATA_DATA_IDLE YT921X_EDATA_DATA_STATUS(3) 242 243#define YT921X_EXT_MBUS_OP 0x6a000 244#define YT921X_INT_MBUS_OP 0xf0000 245#define YT921X_MBUS_OP_START BIT(0) 246#define YT921X_EXT_MBUS_CTRL 0x6a004 247#define YT921X_INT_MBUS_CTRL 0xf0004 248#define YT921X_MBUS_CTRL_PORT_M GENMASK(25, 21) 249#define YT921X_MBUS_CTRL_PORT(x) FIELD_PREP(YT921X_MBUS_CTRL_PORT_M, (x)) 250#define YT921X_MBUS_CTRL_REG_M GENMASK(20, 16) 251#define YT921X_MBUS_CTRL_REG(x) FIELD_PREP(YT921X_MBUS_CTRL_REG_M, (x)) 252#define YT921X_MBUS_CTRL_TYPE_M GENMASK(11, 8) /* wild guess */ 253#define YT921X_MBUS_CTRL_TYPE(x) FIELD_PREP(YT921X_MBUS_CTRL_TYPE_M, (x)) 254#define YT921X_MBUS_CTRL_TYPE_C22 YT921X_MBUS_CTRL_TYPE(4) 255#define YT921X_MBUS_CTRL_OP_M GENMASK(3, 2) /* wild guess */ 256#define YT921X_MBUS_CTRL_OP(x) FIELD_PREP(YT921X_MBUS_CTRL_OP_M, (x)) 257#define YT921X_MBUS_CTRL_WRITE YT921X_MBUS_CTRL_OP(1) 258#define YT921X_MBUS_CTRL_READ YT921X_MBUS_CTRL_OP(2) 259#define YT921X_EXT_MBUS_DOUT 0x6a008 260#define YT921X_INT_MBUS_DOUT 0xf0008 261#define YT921X_EXT_MBUS_DIN 0x6a00c 262#define YT921X_INT_MBUS_DIN 0xf000c 263 264#define YT921X_PORTn_EGR(port) (0x100000 + 4 * (port)) 265#define YT921X_PORT_EGR_TPID_CTAG_M GENMASK(5, 4) 266#define YT921X_PORT_EGR_TPID_CTAG(x) FIELD_PREP(YT921X_PORT_EGR_TPID_CTAG_M, (x)) 267#define YT921X_PORT_EGR_TPID_STAG_M GENMASK(3, 2) 268#define YT921X_PORT_EGR_TPID_STAG(x) FIELD_PREP(YT921X_PORT_EGR_TPID_STAG_M, (x)) 269#define YT921X_TPID_EGRn(x) (0x100300 + 4 * (x)) /* [0, 3] */ 270#define YT921X_TPID_EGR_TPID_M GENMASK(15, 0) 271 272#define YT921X_VLAN_IGR_FILTER 0x180280 273#define YT921X_VLAN_IGR_FILTER_PORTn_BYPASS_IGMP(port) BIT((port) + 11) 274#define YT921X_VLAN_IGR_FILTER_PORTn(port) BIT(port) 275#define YT921X_PORTn_ISOLATION(port) (0x180294 + 4 * (port)) 276#define YT921X_PORT_ISOLATION_BLOCKn(port) BIT(port) 277#define YT921X_STPn(n) (0x18038c + 4 * (n)) 278#define YT921X_STP_PORTn_M(port) GENMASK(2 * (port) + 1, 2 * (port)) 279#define YT921X_STP_PORTn(port, x) ((x) << (2 * (port))) 280#define YT921X_STP_PORTn_DISABLED(port) YT921X_STP_PORTn(port, 0) 281#define YT921X_STP_PORTn_LEARNING(port) YT921X_STP_PORTn(port, 1) 282#define YT921X_STP_PORTn_BLOCKING(port) YT921X_STP_PORTn(port, 2) 283#define YT921X_STP_PORTn_FORWARD(port) YT921X_STP_PORTn(port, 3) 284#define YT921X_PORTn_LEARN(port) (0x1803d0 + 4 * (port)) 285#define YT921X_PORT_LEARN_VID_LEARN_MULTI_EN BIT(22) 286#define YT921X_PORT_LEARN_VID_LEARN_MODE BIT(21) 287#define YT921X_PORT_LEARN_VID_LEARN_EN BIT(20) 288#define YT921X_PORT_LEARN_SUSPEND_COPY_EN BIT(19) 289#define YT921X_PORT_LEARN_SUSPEND_DROP_EN BIT(18) 290#define YT921X_PORT_LEARN_DIS BIT(17) 291#define YT921X_PORT_LEARN_LIMIT_EN BIT(16) 292#define YT921X_PORT_LEARN_LIMIT_M GENMASK(15, 8) 293#define YT921X_PORT_LEARN_LIMIT(x) FIELD_PREP(YT921X_PORT_LEARN_LIMIT_M, (x)) 294#define YT921X_PORT_LEARN_DROP_ON_EXCEEDED BIT(2) 295#define YT921X_PORT_LEARN_MODE_M GENMASK(1, 0) 296#define YT921X_PORT_LEARN_MODE(x) FIELD_PREP(YT921X_PORT_LEARN_MODE_M, (x)) 297#define YT921X_PORT_LEARN_MODE_AUTO YT921X_PORT_LEARN_MODE(0) 298#define YT921X_PORT_LEARN_MODE_AUTO_AND_COPY YT921X_PORT_LEARN_MODE(1) 299#define YT921X_PORT_LEARN_MODE_CPU_CONTROL YT921X_PORT_LEARN_MODE(2) 300#define YT921X_AGEING 0x180440 301#define YT921X_AGEING_INTERVAL_M GENMASK(15, 0) 302#define YT921X_FDB_IN0 0x180454 303#define YT921X_FDB_IN1 0x180458 304#define YT921X_FDB_IN2 0x18045c 305#define YT921X_FDB_OP 0x180460 306#define YT921X_FDB_OP_INDEX_M GENMASK(22, 11) 307#define YT921X_FDB_OP_INDEX(x) FIELD_PREP(YT921X_FDB_OP_INDEX_M, (x)) 308#define YT921X_FDB_OP_MODE_INDEX BIT(10) /* mac+fid / index */ 309#define YT921X_FDB_OP_FLUSH_MCAST BIT(9) /* ucast / mcast */ 310#define YT921X_FDB_OP_FLUSH_M GENMASK(8, 7) 311#define YT921X_FDB_OP_FLUSH(x) FIELD_PREP(YT921X_FDB_OP_FLUSH_M, (x)) 312#define YT921X_FDB_OP_FLUSH_ALL YT921X_FDB_OP_FLUSH(0) 313#define YT921X_FDB_OP_FLUSH_PORT YT921X_FDB_OP_FLUSH(1) 314#define YT921X_FDB_OP_FLUSH_PORT_VID YT921X_FDB_OP_FLUSH(2) 315#define YT921X_FDB_OP_FLUSH_VID YT921X_FDB_OP_FLUSH(3) 316#define YT921X_FDB_OP_FLUSH_STATIC BIT(6) 317#define YT921X_FDB_OP_NEXT_TYPE_M GENMASK(5, 4) 318#define YT921X_FDB_OP_NEXT_TYPE(x) FIELD_PREP(YT921X_FDB_OP_NEXT_TYPE_M, (x)) 319#define YT921X_FDB_OP_NEXT_TYPE_UCAST_PORT YT921X_FDB_OP_NEXT_TYPE(0) 320#define YT921X_FDB_OP_NEXT_TYPE_UCAST_VID YT921X_FDB_OP_NEXT_TYPE(1) 321#define YT921X_FDB_OP_NEXT_TYPE_UCAST YT921X_FDB_OP_NEXT_TYPE(2) 322#define YT921X_FDB_OP_NEXT_TYPE_MCAST YT921X_FDB_OP_NEXT_TYPE(3) 323#define YT921X_FDB_OP_OP_M GENMASK(3, 1) 324#define YT921X_FDB_OP_OP(x) FIELD_PREP(YT921X_FDB_OP_OP_M, (x)) 325#define YT921X_FDB_OP_OP_ADD YT921X_FDB_OP_OP(0) 326#define YT921X_FDB_OP_OP_DEL YT921X_FDB_OP_OP(1) 327#define YT921X_FDB_OP_OP_GET_ONE YT921X_FDB_OP_OP(2) 328#define YT921X_FDB_OP_OP_GET_NEXT YT921X_FDB_OP_OP(3) 329#define YT921X_FDB_OP_OP_FLUSH YT921X_FDB_OP_OP(4) 330#define YT921X_FDB_OP_START BIT(0) 331#define YT921X_FDB_RESULT 0x180464 332#define YT921X_FDB_RESULT_DONE BIT(15) 333#define YT921X_FDB_RESULT_NOTFOUND BIT(14) 334#define YT921X_FDB_RESULT_OVERWRITED BIT(13) 335#define YT921X_FDB_RESULT_INDEX_M GENMASK(11, 0) 336#define YT921X_FDB_RESULT_INDEX(x) FIELD_PREP(YT921X_FDB_RESULT_INDEX_M, (x)) 337#define YT921X_FDB_OUT0 0x1804b0 338#define YT921X_FDB_IO0_ADDR_HI4_M GENMASK(31, 0) 339#define YT921X_FDB_OUT1 0x1804b4 340#define YT921X_FDB_IO1_EGR_INT_PRI_EN BIT(31) 341#define YT921X_FDB_IO1_STATUS_M GENMASK(30, 28) 342#define YT921X_FDB_IO1_STATUS(x) FIELD_PREP(YT921X_FDB_IO1_STATUS_M, (x)) 343#define YT921X_FDB_IO1_STATUS_INVALID YT921X_FDB_IO1_STATUS(0) 344#define YT921X_FDB_IO1_STATUS_MIN_TIME YT921X_FDB_IO1_STATUS(1) 345#define YT921X_FDB_IO1_STATUS_MOVE_AGING_MAX_TIME YT921X_FDB_IO1_STATUS(3) 346#define YT921X_FDB_IO1_STATUS_MAX_TIME YT921X_FDB_IO1_STATUS(5) 347#define YT921X_FDB_IO1_STATUS_PENDING YT921X_FDB_IO1_STATUS(6) 348#define YT921X_FDB_IO1_STATUS_STATIC YT921X_FDB_IO1_STATUS(7) 349#define YT921X_FDB_IO1_FID_M GENMASK(27, 16) /* filtering ID (VID) */ 350#define YT921X_FDB_IO1_FID(x) FIELD_PREP(YT921X_FDB_IO1_FID_M, (x)) 351#define YT921X_FDB_IO1_ADDR_LO2_M GENMASK(15, 0) 352#define YT921X_FDB_OUT2 0x1804b8 353#define YT921X_FDB_IO2_MOVE_AGING_STATUS_M GENMASK(31, 30) 354#define YT921X_FDB_IO2_IGR_DROP BIT(29) 355#define YT921X_FDB_IO2_EGR_PORTS_M GENMASK(28, 18) 356#define YT921X_FDB_IO2_EGR_PORTS(x) FIELD_PREP(YT921X_FDB_IO2_EGR_PORTS_M, (x)) 357#define YT921X_FDB_IO2_EGR_DROP BIT(17) 358#define YT921X_FDB_IO2_COPY_TO_CPU BIT(16) 359#define YT921X_FDB_IO2_IGR_INT_PRI_EN BIT(15) 360#define YT921X_FDB_IO2_INT_PRI_M GENMASK(14, 12) 361#define YT921X_FDB_IO2_INT_PRI(x) FIELD_PREP(YT921X_FDB_IO2_INT_PRI_M, (x)) 362#define YT921X_FDB_IO2_NEW_VID_M GENMASK(11, 0) 363#define YT921X_FDB_IO2_NEW_VID(x) FIELD_PREP(YT921X_FDB_IO2_NEW_VID_M, (x)) 364#define YT921X_FILTER_UNK_UCAST 0x180508 365#define YT921X_FILTER_UNK_MCAST 0x18050c 366#define YT921X_FILTER_MCAST 0x180510 367#define YT921X_FILTER_BCAST 0x180514 368#define YT921X_FILTER_PORTS_M GENMASK(10, 0) 369#define YT921X_FILTER_PORTS(x) FIELD_PREP(YT921X_FILTER_PORTS_M, (x)) 370#define YT921X_FILTER_PORTn(port) BIT(port) 371#define YT921X_VLAN_EGR_FILTER 0x180598 372#define YT921X_VLAN_EGR_FILTER_PORTn(port) BIT(port) 373#define YT921X_CPU_COPY 0x180690 374#define YT921X_CPU_COPY_FORCE_INT_PORT BIT(2) 375#define YT921X_CPU_COPY_TO_INT_CPU BIT(1) 376#define YT921X_CPU_COPY_TO_EXT_CPU BIT(0) 377#define YT921X_ACT_UNK_UCAST 0x180734 378#define YT921X_ACT_UNK_MCAST 0x180738 379#define YT921X_ACT_UNK_MCAST_BYPASS_DROP_RMA BIT(23) 380#define YT921X_ACT_UNK_MCAST_BYPASS_DROP_IGMP BIT(22) 381#define YT921X_ACT_UNK_ACTn_M(port) GENMASK(2 * (port) + 1, 2 * (port)) 382#define YT921X_ACT_UNK_ACTn(port, x) ((x) << (2 * (port))) 383#define YT921X_ACT_UNK_ACTn_FORWARD(port) YT921X_ACT_UNK_ACTn(port, 0) /* flood */ 384#define YT921X_ACT_UNK_ACTn_TRAP(port) YT921X_ACT_UNK_ACTn(port, 1) /* steer to CPU */ 385#define YT921X_ACT_UNK_ACTn_DROP(port) YT921X_ACT_UNK_ACTn(port, 2) /* discard */ 386/* NEVER use this action; see comments in the tag driver */ 387#define YT921X_ACT_UNK_ACTn_COPY(port) YT921X_ACT_UNK_ACTn(port, 3) /* flood and copy */ 388#define YT921X_FDB_HW_FLUSH 0x180958 389#define YT921X_FDB_HW_FLUSH_ON_LINKDOWN BIT(0) 390 391#define YT921X_VLANn_CTRL(vlan) (0x188000 + 8 * (vlan)) 392#define YT921X_VLAN_CTRL_UNTAG_PORTS_M GENMASK_ULL(50, 40) 393#define YT921X_VLAN_CTRL_UNTAG_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_UNTAG_PORTS_M, (x)) 394#define YT921X_VLAN_CTRL_UNTAG_PORTn(port) BIT_ULL((port) + 40) 395#define YT921X_VLAN_CTRL_STP_ID_M GENMASK_ULL(39, 36) 396#define YT921X_VLAN_CTRL_STP_ID(x) FIELD_PREP(YT921X_VLAN_CTRL_STP_ID_M, (x)) 397#define YT921X_VLAN_CTRL_SVLAN_EN BIT_ULL(35) 398#define YT921X_VLAN_CTRL_FID_M GENMASK_ULL(34, 23) 399#define YT921X_VLAN_CTRL_FID(x) FIELD_PREP(YT921X_VLAN_CTRL_FID_M, (x)) 400#define YT921X_VLAN_CTRL_LEARN_DIS BIT_ULL(22) 401#define YT921X_VLAN_CTRL_INT_PRI_EN BIT_ULL(21) 402#define YT921X_VLAN_CTRL_INT_PRI_M GENMASK_ULL(20, 18) 403#define YT921X_VLAN_CTRL_PORTS_M GENMASK_ULL(17, 7) 404#define YT921X_VLAN_CTRL_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_PORTS_M, (x)) 405#define YT921X_VLAN_CTRL_PORTn(port) BIT_ULL((port) + 7) 406#define YT921X_VLAN_CTRL_BYPASS_1X_AC BIT_ULL(6) 407#define YT921X_VLAN_CTRL_METER_EN BIT_ULL(5) 408#define YT921X_VLAN_CTRL_METER_ID_M GENMASK_ULL(4, 0) 409 410#define YT921X_TPID_IGRn(x) (0x210000 + 4 * (x)) /* [0, 3] */ 411#define YT921X_TPID_IGR_TPID_M GENMASK(15, 0) 412#define YT921X_PORTn_IGR_TPID(port) (0x210010 + 4 * (port)) 413#define YT921X_PORT_IGR_TPIDn_STAG_M GENMASK(7, 4) 414#define YT921X_PORT_IGR_TPIDn_STAG(x) BIT((x) + 4) 415#define YT921X_PORT_IGR_TPIDn_CTAG_M GENMASK(3, 0) 416#define YT921X_PORT_IGR_TPIDn_CTAG(x) BIT(x) 417 418#define YT921X_PORTn_VLAN_CTRL(port) (0x230010 + 4 * (port)) 419#define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_EN BIT(31) 420#define YT921X_PORT_VLAN_CTRL_CVLAN_PRI_EN BIT(30) 421#define YT921X_PORT_VLAN_CTRL_SVID_M GENMASK(29, 18) 422#define YT921X_PORT_VLAN_CTRL_SVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL_SVID_M, (x)) 423#define YT921X_PORT_VLAN_CTRL_CVID_M GENMASK(17, 6) 424#define YT921X_PORT_VLAN_CTRL_CVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL_CVID_M, (x)) 425#define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_M GENMASK(5, 3) 426#define YT921X_PORT_VLAN_CTRL_CVLAN_PRI_M GENMASK(2, 0) 427#define YT921X_PORTn_VLAN_CTRL1(port) (0x230080 + 4 * (port)) 428#define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_EN BIT(8) 429#define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_PROFILE_ID_M GENMASK(7, 4) 430#define YT921X_PORT_VLAN_CTRL1_SVLAN_DROP_TAGGED BIT(3) 431#define YT921X_PORT_VLAN_CTRL1_SVLAN_DROP_UNTAGGED BIT(2) 432#define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_TAGGED BIT(1) 433#define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED BIT(0) 434 435#define YT921X_MIRROR 0x300300 436#define YT921X_MIRROR_IGR_PORTS_M GENMASK(26, 16) 437#define YT921X_MIRROR_IGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_IGR_PORTS_M, (x)) 438#define YT921X_MIRROR_IGR_PORTn(port) BIT((port) + 16) 439#define YT921X_MIRROR_EGR_PORTS_M GENMASK(14, 4) 440#define YT921X_MIRROR_EGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_EGR_PORTS_M, (x)) 441#define YT921X_MIRROR_EGR_PORTn(port) BIT((port) + 4) 442#define YT921X_MIRROR_PORT_M GENMASK(3, 0) 443#define YT921X_MIRROR_PORT(x) FIELD_PREP(YT921X_MIRROR_PORT_M, (x)) 444 445#define YT921X_EDATA_EXTMODE 0xfb 446#define YT921X_EDATA_LEN 0x100 447 448#define YT921X_FDB_NUM 4096 449 450enum yt921x_fdb_entry_status { 451 YT921X_FDB_ENTRY_STATUS_INVALID = 0, 452 YT921X_FDB_ENTRY_STATUS_MIN_TIME = 1, 453 YT921X_FDB_ENTRY_STATUS_MOVE_AGING_MAX_TIME = 3, 454 YT921X_FDB_ENTRY_STATUS_MAX_TIME = 5, 455 YT921X_FDB_ENTRY_STATUS_PENDING = 6, 456 YT921X_FDB_ENTRY_STATUS_STATIC = 7, 457}; 458 459#define YT921X_MSTI_NUM 16 460 461#define YT9215_MAJOR 0x9002 462#define YT9218_MAJOR 0x9001 463 464/* required for a hard reset */ 465#define YT921X_RST_DELAY_US 10000 466 467#define YT921X_FRAME_SIZE_MAX 0x2400 /* 9216 */ 468 469#define YT921X_TAG_LEN 8 470 471/* 8 internal + 2 external + 1 mcu */ 472#define YT921X_PORT_NUM 11 473 474#define yt921x_port_is_internal(port) ((port) < 8) 475#define yt921x_port_is_external(port) (8 <= (port) && (port) < 9) 476 477struct yt921x_mib { 478 u64 rx_broadcast; 479 u64 rx_pause; 480 u64 rx_multicast; 481 u64 rx_crc_errors; 482 483 u64 rx_alignment_errors; 484 u64 rx_undersize_errors; 485 u64 rx_fragment_errors; 486 u64 rx_64byte; 487 488 u64 rx_65_127byte; 489 u64 rx_128_255byte; 490 u64 rx_256_511byte; 491 u64 rx_512_1023byte; 492 493 u64 rx_1024_1518byte; 494 u64 rx_jumbo; 495 u64 rx_good_bytes; 496 497 u64 rx_bad_bytes; 498 u64 rx_oversize_errors; 499 500 u64 rx_dropped; 501 u64 tx_broadcast; 502 u64 tx_pause; 503 u64 tx_multicast; 504 505 u64 tx_undersize_errors; 506 u64 tx_64byte; 507 u64 tx_65_127byte; 508 u64 tx_128_255byte; 509 510 u64 tx_256_511byte; 511 u64 tx_512_1023byte; 512 u64 tx_1024_1518byte; 513 u64 tx_jumbo; 514 515 u64 tx_good_bytes; 516 u64 tx_collisions; 517 518 u64 tx_aborted_errors; 519 u64 tx_multiple_collisions; 520 u64 tx_single_collisions; 521 u64 tx_good; 522 523 u64 tx_deferred; 524 u64 tx_late_collisions; 525 u64 rx_oam; 526 u64 tx_oam; 527}; 528 529struct yt921x_port { 530 unsigned char index; 531 532 bool hairpin; 533 bool isolated; 534 535 struct delayed_work mib_read; 536 struct yt921x_mib mib; 537 u64 rx_frames; 538 u64 tx_frames; 539}; 540 541struct yt921x_reg_ops { 542 int (*read)(void *context, u32 reg, u32 *valp); 543 int (*write)(void *context, u32 reg, u32 val); 544}; 545 546struct yt921x_priv { 547 struct dsa_switch ds; 548 549 const struct yt921x_info *info; 550 /* cache of dsa_cpu_ports(ds) */ 551 u16 cpu_ports_mask; 552 553 /* protect the access to the switch registers */ 554 struct mutex reg_lock; 555 const struct yt921x_reg_ops *reg_ops; 556 void *reg_ctx; 557 558 /* mdio master bus */ 559 struct mii_bus *mbus_int; 560 struct mii_bus *mbus_ext; 561 562 struct yt921x_port ports[YT921X_PORT_NUM]; 563 564 u16 eee_ports_mask; 565}; 566 567#endif
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