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yt921x.c
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linux-6.19.14/drivers/net/dsa/yt921x.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Driver for Motorcomm YT921x Switch 4 * 5 * Should work on YT9213/YT9214/YT9215/YT9218, but only tested on YT9215+SGMII, 6 * be sure to do your own checks before porting to another chip. 7 * 8 * Copyright (c) 2025 David Yang 9 */ 10 11#include <linux/etherdevice.h> 12#include <linux/if_bridge.h> 13#include <linux/if_hsr.h> 14#include <linux/if_vlan.h> 15#include <linux/iopoll.h> 16#include <linux/mdio.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/of_mdio.h> 20#include <linux/of_net.h> 21 22#include <net/dsa.h> 23 24#include "yt921x.h" 25 26struct yt921x_mib_desc { 27 unsigned int size; 28 unsigned int offset; 29 const char *name; 30}; 31 32#define MIB_DESC(_size, _offset, _name) \ 33 {_size, _offset, _name} 34 35/* Must agree with yt921x_mib 36 * 37 * Unstructured fields (name != NULL) will appear in get_ethtool_stats(), 38 * structured go to their *_stats() methods, but we need their sizes and offsets 39 * to perform 32bit MIB overflow wraparound. 40 */ 41static const struct yt921x_mib_desc yt921x_mib_descs[] = { 42 MIB_DESC(1, YT921X_MIB_DATA_RX_BROADCAST, NULL), 43 MIB_DESC(1, YT921X_MIB_DATA_RX_PAUSE, NULL), 44 MIB_DESC(1, YT921X_MIB_DATA_RX_MULTICAST, NULL), 45 MIB_DESC(1, YT921X_MIB_DATA_RX_CRC_ERR, NULL), 46 47 MIB_DESC(1, YT921X_MIB_DATA_RX_ALIGN_ERR, NULL), 48 MIB_DESC(1, YT921X_MIB_DATA_RX_UNDERSIZE_ERR, NULL), 49 MIB_DESC(1, YT921X_MIB_DATA_RX_FRAG_ERR, NULL), 50 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_64, NULL), 51 52 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_65_TO_127, NULL), 53 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_128_TO_255, NULL), 54 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_256_TO_511, NULL), 55 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_512_TO_1023, NULL), 56 57 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_1024_TO_1518, NULL), 58 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_1519_TO_MAX, NULL), 59 MIB_DESC(2, YT921X_MIB_DATA_RX_GOOD_BYTES, NULL), 60 61 MIB_DESC(2, YT921X_MIB_DATA_RX_BAD_BYTES, "RxBadBytes"), 62 MIB_DESC(1, YT921X_MIB_DATA_RX_OVERSIZE_ERR, NULL), 63 64 MIB_DESC(1, YT921X_MIB_DATA_RX_DROPPED, NULL), 65 MIB_DESC(1, YT921X_MIB_DATA_TX_BROADCAST, NULL), 66 MIB_DESC(1, YT921X_MIB_DATA_TX_PAUSE, NULL), 67 MIB_DESC(1, YT921X_MIB_DATA_TX_MULTICAST, NULL), 68 69 MIB_DESC(1, YT921X_MIB_DATA_TX_UNDERSIZE_ERR, NULL), 70 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_64, NULL), 71 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_65_TO_127, NULL), 72 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_128_TO_255, NULL), 73 74 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_256_TO_511, NULL), 75 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_512_TO_1023, NULL), 76 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_1024_TO_1518, NULL), 77 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_1519_TO_MAX, NULL), 78 79 MIB_DESC(2, YT921X_MIB_DATA_TX_GOOD_BYTES, NULL), 80 MIB_DESC(1, YT921X_MIB_DATA_TX_COLLISION, NULL), 81 82 MIB_DESC(1, YT921X_MIB_DATA_TX_EXCESSIVE_COLLISION, NULL), 83 MIB_DESC(1, YT921X_MIB_DATA_TX_MULTIPLE_COLLISION, NULL), 84 MIB_DESC(1, YT921X_MIB_DATA_TX_SINGLE_COLLISION, NULL), 85 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT, NULL), 86 87 MIB_DESC(1, YT921X_MIB_DATA_TX_DEFERRED, NULL), 88 MIB_DESC(1, YT921X_MIB_DATA_TX_LATE_COLLISION, NULL), 89 MIB_DESC(1, YT921X_MIB_DATA_RX_OAM, "RxOAM"), 90 MIB_DESC(1, YT921X_MIB_DATA_TX_OAM, "TxOAM"), 91}; 92 93struct yt921x_info { 94 const char *name; 95 u16 major; 96 /* Unknown, seems to be plain enumeration */ 97 u8 mode; 98 u8 extmode; 99 /* Ports with integral GbE PHYs, not including MCU Port 10 */ 100 u16 internal_mask; 101 /* TODO: see comments in yt921x_dsa_phylink_get_caps() */ 102 u16 external_mask; 103}; 104 105#define YT921X_PORT_MASK_INTn(port) BIT(port) 106#define YT921X_PORT_MASK_INT0_n(n) GENMASK((n) - 1, 0) 107#define YT921X_PORT_MASK_EXT0 BIT(8) 108#define YT921X_PORT_MASK_EXT1 BIT(9) 109 110static const struct yt921x_info yt921x_infos[] = { 111 { 112 "YT9215SC", YT9215_MAJOR, 1, 0, 113 YT921X_PORT_MASK_INT0_n(5), 114 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 115 }, 116 { 117 "YT9215S", YT9215_MAJOR, 2, 0, 118 YT921X_PORT_MASK_INT0_n(5), 119 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 120 }, 121 { 122 "YT9215RB", YT9215_MAJOR, 3, 0, 123 YT921X_PORT_MASK_INT0_n(5), 124 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 125 }, 126 { 127 "YT9214NB", YT9215_MAJOR, 3, 2, 128 YT921X_PORT_MASK_INTn(1) | YT921X_PORT_MASK_INTn(3), 129 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 130 }, 131 { 132 "YT9213NB", YT9215_MAJOR, 3, 3, 133 YT921X_PORT_MASK_INTn(1) | YT921X_PORT_MASK_INTn(3), 134 YT921X_PORT_MASK_EXT1, 135 }, 136 { 137 "YT9218N", YT9218_MAJOR, 0, 0, 138 YT921X_PORT_MASK_INT0_n(8), 139 0, 140 }, 141 { 142 "YT9218MB", YT9218_MAJOR, 1, 0, 143 YT921X_PORT_MASK_INT0_n(8), 144 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 145 }, 146 {} 147}; 148 149#define YT921X_NAME "yt921x" 150 151#define YT921X_VID_UNWARE 4095 152 153#define YT921X_POLL_SLEEP_US 10000 154#define YT921X_POLL_TIMEOUT_US 100000 155 156/* The interval should be small enough to avoid overflow of 32bit MIBs. 157 * 158 * Until we can read MIBs from stats64 call directly (i.e. sleep 159 * there), we have to poll stats more frequently then it is actually needed. 160 * For overflow protection, normally, 100 sec interval should have been OK. 161 */ 162#define YT921X_STATS_INTERVAL_JIFFIES (3 * HZ) 163 164struct yt921x_reg_mdio { 165 struct mii_bus *bus; 166 int addr; 167 /* SWITCH_ID_1 / SWITCH_ID_0 of the device 168 * 169 * This is a way to multiplex multiple devices on the same MII phyaddr 170 * and should be configurable in DT. However, MDIO core simply doesn't 171 * allow multiple devices over one reg addr, so this is a fixed value 172 * for now until a solution is found. 173 * 174 * Keep this because we need switchid to form MII regaddrs anyway. 175 */ 176 unsigned char switchid; 177}; 178 179/* TODO: SPI/I2C */ 180 181#define to_yt921x_priv(_ds) container_of_const(_ds, struct yt921x_priv, ds) 182#define to_device(priv) ((priv)->ds.dev) 183 184static int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) 185{ 186 WARN_ON(!mutex_is_locked(&priv->reg_lock)); 187 188 return priv->reg_ops->read(priv->reg_ctx, reg, valp); 189} 190 191static int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) 192{ 193 WARN_ON(!mutex_is_locked(&priv->reg_lock)); 194 195 return priv->reg_ops->write(priv->reg_ctx, reg, val); 196} 197 198static int 199yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp) 200{ 201 u32 val; 202 int res; 203 int ret; 204 205 ret = read_poll_timeout(yt921x_reg_read, res, 206 res || (val & mask) == *valp, 207 YT921X_POLL_SLEEP_US, YT921X_POLL_TIMEOUT_US, 208 false, priv, reg, &val); 209 if (ret) 210 return ret; 211 if (res) 212 return res; 213 214 *valp = val; 215 return 0; 216} 217 218static int 219yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u32 val) 220{ 221 int res; 222 u32 v; 223 u32 u; 224 225 res = yt921x_reg_read(priv, reg, &v); 226 if (res) 227 return res; 228 229 u = v; 230 u &= ~mask; 231 u |= val; 232 if (u == v) 233 return 0; 234 235 return yt921x_reg_write(priv, reg, u); 236} 237 238static int yt921x_reg_set_bits(struct yt921x_priv *priv, u32 reg, u32 mask) 239{ 240 return yt921x_reg_update_bits(priv, reg, 0, mask); 241} 242 243static int yt921x_reg_clear_bits(struct yt921x_priv *priv, u32 reg, u32 mask) 244{ 245 return yt921x_reg_update_bits(priv, reg, mask, 0); 246} 247 248static int 249yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool set) 250{ 251 return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); 252} 253 254/* Some registers, like VLANn_CTRL, should always be written in 64-bit, even if 255 * you are to write only the lower / upper 32 bits. 256 * 257 * There is no such restriction for reading, but we still provide 64-bit read 258 * wrappers so that we always handle u64 values. 259 */ 260 261static int yt921x_reg64_read(struct yt921x_priv *priv, u32 reg, u64 *valp) 262{ 263 u32 lo; 264 u32 hi; 265 int res; 266 267 res = yt921x_reg_read(priv, reg, &lo); 268 if (res) 269 return res; 270 res = yt921x_reg_read(priv, reg + 4, &hi); 271 if (res) 272 return res; 273 274 *valp = ((u64)hi << 32) | lo; 275 return 0; 276} 277 278static int yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, u64 val) 279{ 280 int res; 281 282 res = yt921x_reg_write(priv, reg, (u32)val); 283 if (res) 284 return res; 285 return yt921x_reg_write(priv, reg + 4, (u32)(val >> 32)); 286} 287 288static int 289yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, u64 mask, u64 val) 290{ 291 int res; 292 u64 v; 293 u64 u; 294 295 res = yt921x_reg64_read(priv, reg, &v); 296 if (res) 297 return res; 298 299 u = v; 300 u &= ~mask; 301 u |= val; 302 if (u == v) 303 return 0; 304 305 return yt921x_reg64_write(priv, reg, u); 306} 307 308static int yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, u64 mask) 309{ 310 return yt921x_reg64_update_bits(priv, reg, mask, 0); 311} 312 313static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) 314{ 315 struct yt921x_reg_mdio *mdio = context; 316 struct mii_bus *bus = mdio->bus; 317 int addr = mdio->addr; 318 u32 reg_addr; 319 u32 reg_data; 320 u32 val; 321 int res; 322 323 /* Hold the mdio bus lock to avoid (un)locking for 4 times */ 324 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 325 326 reg_addr = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_ADDR | 327 YT921X_SMI_READ; 328 res = __mdiobus_write(bus, addr, reg_addr, (u16)(reg >> 16)); 329 if (res) 330 goto end; 331 res = __mdiobus_write(bus, addr, reg_addr, (u16)reg); 332 if (res) 333 goto end; 334 335 reg_data = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_DATA | 336 YT921X_SMI_READ; 337 res = __mdiobus_read(bus, addr, reg_data); 338 if (res < 0) 339 goto end; 340 val = (u16)res; 341 res = __mdiobus_read(bus, addr, reg_data); 342 if (res < 0) 343 goto end; 344 val = (val << 16) | (u16)res; 345 346 *valp = val; 347 res = 0; 348 349end: 350 mutex_unlock(&bus->mdio_lock); 351 return res; 352} 353 354static int yt921x_reg_mdio_write(void *context, u32 reg, u32 val) 355{ 356 struct yt921x_reg_mdio *mdio = context; 357 struct mii_bus *bus = mdio->bus; 358 int addr = mdio->addr; 359 u32 reg_addr; 360 u32 reg_data; 361 int res; 362 363 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 364 365 reg_addr = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_ADDR | 366 YT921X_SMI_WRITE; 367 res = __mdiobus_write(bus, addr, reg_addr, (u16)(reg >> 16)); 368 if (res) 369 goto end; 370 res = __mdiobus_write(bus, addr, reg_addr, (u16)reg); 371 if (res) 372 goto end; 373 374 reg_data = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_DATA | 375 YT921X_SMI_WRITE; 376 res = __mdiobus_write(bus, addr, reg_data, (u16)(val >> 16)); 377 if (res) 378 goto end; 379 res = __mdiobus_write(bus, addr, reg_data, (u16)val); 380 if (res) 381 goto end; 382 383 res = 0; 384 385end: 386 mutex_unlock(&bus->mdio_lock); 387 return res; 388} 389 390static const struct yt921x_reg_ops yt921x_reg_ops_mdio = { 391 .read = yt921x_reg_mdio_read, 392 .write = yt921x_reg_mdio_write, 393}; 394 395/* TODO: SPI/I2C */ 396 397static int yt921x_intif_wait(struct yt921x_priv *priv) 398{ 399 u32 val = 0; 400 401 return yt921x_reg_wait(priv, YT921X_INT_MBUS_OP, YT921X_MBUS_OP_START, 402 &val); 403} 404 405static int 406yt921x_intif_read(struct yt921x_priv *priv, int port, int reg, u16 *valp) 407{ 408 struct device *dev = to_device(priv); 409 u32 mask; 410 u32 ctrl; 411 u32 val; 412 int res; 413 414 res = yt921x_intif_wait(priv); 415 if (res) 416 return res; 417 418 mask = YT921X_MBUS_CTRL_PORT_M | YT921X_MBUS_CTRL_REG_M | 419 YT921X_MBUS_CTRL_OP_M; 420 ctrl = YT921X_MBUS_CTRL_PORT(port) | YT921X_MBUS_CTRL_REG(reg) | 421 YT921X_MBUS_CTRL_READ; 422 res = yt921x_reg_update_bits(priv, YT921X_INT_MBUS_CTRL, mask, ctrl); 423 if (res) 424 return res; 425 res = yt921x_reg_write(priv, YT921X_INT_MBUS_OP, YT921X_MBUS_OP_START); 426 if (res) 427 return res; 428 429 res = yt921x_intif_wait(priv); 430 if (res) 431 return res; 432 res = yt921x_reg_read(priv, YT921X_INT_MBUS_DIN, &val); 433 if (res) 434 return res; 435 436 if ((u16)val != val) 437 dev_info(dev, 438 "%s: port %d, reg 0x%x: Expected u16, got 0x%08x\n", 439 __func__, port, reg, val); 440 *valp = (u16)val; 441 return 0; 442} 443 444static int 445yt921x_intif_write(struct yt921x_priv *priv, int port, int reg, u16 val) 446{ 447 u32 mask; 448 u32 ctrl; 449 int res; 450 451 res = yt921x_intif_wait(priv); 452 if (res) 453 return res; 454 455 mask = YT921X_MBUS_CTRL_PORT_M | YT921X_MBUS_CTRL_REG_M | 456 YT921X_MBUS_CTRL_OP_M; 457 ctrl = YT921X_MBUS_CTRL_PORT(port) | YT921X_MBUS_CTRL_REG(reg) | 458 YT921X_MBUS_CTRL_WRITE; 459 res = yt921x_reg_update_bits(priv, YT921X_INT_MBUS_CTRL, mask, ctrl); 460 if (res) 461 return res; 462 res = yt921x_reg_write(priv, YT921X_INT_MBUS_DOUT, val); 463 if (res) 464 return res; 465 res = yt921x_reg_write(priv, YT921X_INT_MBUS_OP, YT921X_MBUS_OP_START); 466 if (res) 467 return res; 468 469 return yt921x_intif_wait(priv); 470} 471 472static int yt921x_mbus_int_read(struct mii_bus *mbus, int port, int reg) 473{ 474 struct yt921x_priv *priv = mbus->priv; 475 u16 val; 476 int res; 477 478 if (port >= YT921X_PORT_NUM) 479 return U16_MAX; 480 481 mutex_lock(&priv->reg_lock); 482 res = yt921x_intif_read(priv, port, reg, &val); 483 mutex_unlock(&priv->reg_lock); 484 485 if (res) 486 return res; 487 return val; 488} 489 490static int 491yt921x_mbus_int_write(struct mii_bus *mbus, int port, int reg, u16 data) 492{ 493 struct yt921x_priv *priv = mbus->priv; 494 int res; 495 496 if (port >= YT921X_PORT_NUM) 497 return -ENODEV; 498 499 mutex_lock(&priv->reg_lock); 500 res = yt921x_intif_write(priv, port, reg, data); 501 mutex_unlock(&priv->reg_lock); 502 503 return res; 504} 505 506static int 507yt921x_mbus_int_init(struct yt921x_priv *priv, struct device_node *mnp) 508{ 509 struct device *dev = to_device(priv); 510 struct mii_bus *mbus; 511 int res; 512 513 mbus = devm_mdiobus_alloc(dev); 514 if (!mbus) 515 return -ENOMEM; 516 517 mbus->name = "YT921x internal MDIO bus"; 518 snprintf(mbus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); 519 mbus->priv = priv; 520 mbus->read = yt921x_mbus_int_read; 521 mbus->write = yt921x_mbus_int_write; 522 mbus->parent = dev; 523 mbus->phy_mask = (u32)~GENMASK(YT921X_PORT_NUM - 1, 0); 524 525 res = devm_of_mdiobus_register(dev, mbus, mnp); 526 if (res) 527 return res; 528 529 priv->mbus_int = mbus; 530 531 return 0; 532} 533 534static int yt921x_extif_wait(struct yt921x_priv *priv) 535{ 536 u32 val = 0; 537 538 return yt921x_reg_wait(priv, YT921X_EXT_MBUS_OP, YT921X_MBUS_OP_START, 539 &val); 540} 541 542static int 543yt921x_extif_read(struct yt921x_priv *priv, int port, int reg, u16 *valp) 544{ 545 struct device *dev = to_device(priv); 546 u32 mask; 547 u32 ctrl; 548 u32 val; 549 int res; 550 551 res = yt921x_extif_wait(priv); 552 if (res) 553 return res; 554 555 mask = YT921X_MBUS_CTRL_PORT_M | YT921X_MBUS_CTRL_REG_M | 556 YT921X_MBUS_CTRL_TYPE_M | YT921X_MBUS_CTRL_OP_M; 557 ctrl = YT921X_MBUS_CTRL_PORT(port) | YT921X_MBUS_CTRL_REG(reg) | 558 YT921X_MBUS_CTRL_TYPE_C22 | YT921X_MBUS_CTRL_READ; 559 res = yt921x_reg_update_bits(priv, YT921X_EXT_MBUS_CTRL, mask, ctrl); 560 if (res) 561 return res; 562 res = yt921x_reg_write(priv, YT921X_EXT_MBUS_OP, YT921X_MBUS_OP_START); 563 if (res) 564 return res; 565 566 res = yt921x_extif_wait(priv); 567 if (res) 568 return res; 569 res = yt921x_reg_read(priv, YT921X_EXT_MBUS_DIN, &val); 570 if (res) 571 return res; 572 573 if ((u16)val != val) 574 dev_info(dev, 575 "%s: port %d, reg 0x%x: Expected u16, got 0x%08x\n", 576 __func__, port, reg, val); 577 *valp = (u16)val; 578 return 0; 579} 580 581static int 582yt921x_extif_write(struct yt921x_priv *priv, int port, int reg, u16 val) 583{ 584 u32 mask; 585 u32 ctrl; 586 int res; 587 588 res = yt921x_extif_wait(priv); 589 if (res) 590 return res; 591 592 mask = YT921X_MBUS_CTRL_PORT_M | YT921X_MBUS_CTRL_REG_M | 593 YT921X_MBUS_CTRL_TYPE_M | YT921X_MBUS_CTRL_OP_M; 594 ctrl = YT921X_MBUS_CTRL_PORT(port) | YT921X_MBUS_CTRL_REG(reg) | 595 YT921X_MBUS_CTRL_TYPE_C22 | YT921X_MBUS_CTRL_WRITE; 596 res = yt921x_reg_update_bits(priv, YT921X_EXT_MBUS_CTRL, mask, ctrl); 597 if (res) 598 return res; 599 res = yt921x_reg_write(priv, YT921X_EXT_MBUS_DOUT, val); 600 if (res) 601 return res; 602 res = yt921x_reg_write(priv, YT921X_EXT_MBUS_OP, YT921X_MBUS_OP_START); 603 if (res) 604 return res; 605 606 return yt921x_extif_wait(priv); 607} 608 609static int yt921x_mbus_ext_read(struct mii_bus *mbus, int port, int reg) 610{ 611 struct yt921x_priv *priv = mbus->priv; 612 u16 val; 613 int res; 614 615 mutex_lock(&priv->reg_lock); 616 res = yt921x_extif_read(priv, port, reg, &val); 617 mutex_unlock(&priv->reg_lock); 618 619 if (res) 620 return res; 621 return val; 622} 623 624static int 625yt921x_mbus_ext_write(struct mii_bus *mbus, int port, int reg, u16 data) 626{ 627 struct yt921x_priv *priv = mbus->priv; 628 int res; 629 630 mutex_lock(&priv->reg_lock); 631 res = yt921x_extif_write(priv, port, reg, data); 632 mutex_unlock(&priv->reg_lock); 633 634 return res; 635} 636 637static int 638yt921x_mbus_ext_init(struct yt921x_priv *priv, struct device_node *mnp) 639{ 640 struct device *dev = to_device(priv); 641 struct mii_bus *mbus; 642 int res; 643 644 mbus = devm_mdiobus_alloc(dev); 645 if (!mbus) 646 return -ENOMEM; 647 648 mbus->name = "YT921x external MDIO bus"; 649 snprintf(mbus->id, MII_BUS_ID_SIZE, "%s@ext", dev_name(dev)); 650 mbus->priv = priv; 651 /* TODO: c45? */ 652 mbus->read = yt921x_mbus_ext_read; 653 mbus->write = yt921x_mbus_ext_write; 654 mbus->parent = dev; 655 656 res = devm_of_mdiobus_register(dev, mbus, mnp); 657 if (res) 658 return res; 659 660 priv->mbus_ext = mbus; 661 662 return 0; 663} 664 665/* Read and handle overflow of 32bit MIBs. MIB buffer must be zeroed before. */ 666static int yt921x_read_mib(struct yt921x_priv *priv, int port) 667{ 668 struct yt921x_port *pp = &priv->ports[port]; 669 struct device *dev = to_device(priv); 670 struct yt921x_mib *mib = &pp->mib; 671 int res = 0; 672 673 /* Reading of yt921x_port::mib is not protected by a lock and it's vain 674 * to keep its consistency, since we have to read registers one by one 675 * and there is no way to make a snapshot of MIB stats. 676 * 677 * Writing (by this function only) is and should be protected by 678 * reg_lock. 679 */ 680 681 for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { 682 const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; 683 u32 reg = YT921X_MIBn_DATA0(port) + desc->offset; 684 u64 *valp = &((u64 *)mib)[i]; 685 u32 val0; 686 u64 val; 687 688 res = yt921x_reg_read(priv, reg, &val0); 689 if (res) 690 break; 691 692 if (desc->size <= 1) { 693 u64 old_val = *valp; 694 695 val = (old_val & ~(u64)U32_MAX) | val0; 696 if (val < old_val) 697 val += 1ull << 32; 698 } else { 699 u32 val1; 700 701 res = yt921x_reg_read(priv, reg + 4, &val1); 702 if (res) 703 break; 704 val = ((u64)val1 << 32) | val0; 705 } 706 707 WRITE_ONCE(*valp, val); 708 } 709 710 pp->rx_frames = mib->rx_64byte + mib->rx_65_127byte + 711 mib->rx_128_255byte + mib->rx_256_511byte + 712 mib->rx_512_1023byte + mib->rx_1024_1518byte + 713 mib->rx_jumbo; 714 pp->tx_frames = mib->tx_64byte + mib->tx_65_127byte + 715 mib->tx_128_255byte + mib->tx_256_511byte + 716 mib->tx_512_1023byte + mib->tx_1024_1518byte + 717 mib->tx_jumbo; 718 719 if (res) 720 dev_err(dev, "Failed to %s port %d: %i\n", "read stats for", 721 port, res); 722 return res; 723} 724 725static void yt921x_poll_mib(struct work_struct *work) 726{ 727 struct yt921x_port *pp = container_of_const(work, struct yt921x_port, 728 mib_read.work); 729 struct yt921x_priv *priv = (void *)(pp - pp->index) - 730 offsetof(struct yt921x_priv, ports); 731 unsigned long delay = YT921X_STATS_INTERVAL_JIFFIES; 732 int port = pp->index; 733 int res; 734 735 mutex_lock(&priv->reg_lock); 736 res = yt921x_read_mib(priv, port); 737 mutex_unlock(&priv->reg_lock); 738 if (res) 739 delay *= 4; 740 741 schedule_delayed_work(&pp->mib_read, delay); 742} 743 744static void 745yt921x_dsa_get_strings(struct dsa_switch *ds, int port, u32 stringset, 746 uint8_t *data) 747{ 748 if (stringset != ETH_SS_STATS) 749 return; 750 751 for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { 752 const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; 753 754 if (desc->name) 755 ethtool_puts(&data, desc->name); 756 } 757} 758 759static void 760yt921x_dsa_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 761{ 762 struct yt921x_priv *priv = to_yt921x_priv(ds); 763 struct yt921x_port *pp = &priv->ports[port]; 764 struct yt921x_mib *mib = &pp->mib; 765 size_t j; 766 767 mutex_lock(&priv->reg_lock); 768 yt921x_read_mib(priv, port); 769 mutex_unlock(&priv->reg_lock); 770 771 j = 0; 772 for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { 773 const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; 774 775 if (!desc->name) 776 continue; 777 778 data[j] = ((u64 *)mib)[i]; 779 j++; 780 } 781} 782 783static int yt921x_dsa_get_sset_count(struct dsa_switch *ds, int port, int sset) 784{ 785 int cnt = 0; 786 787 if (sset != ETH_SS_STATS) 788 return 0; 789 790 for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { 791 const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; 792 793 if (desc->name) 794 cnt++; 795 } 796 797 return cnt; 798} 799 800static void 801yt921x_dsa_get_eth_mac_stats(struct dsa_switch *ds, int port, 802 struct ethtool_eth_mac_stats *mac_stats) 803{ 804 struct yt921x_priv *priv = to_yt921x_priv(ds); 805 struct yt921x_port *pp = &priv->ports[port]; 806 struct yt921x_mib *mib = &pp->mib; 807 808 mutex_lock(&priv->reg_lock); 809 yt921x_read_mib(priv, port); 810 mutex_unlock(&priv->reg_lock); 811 812 mac_stats->FramesTransmittedOK = pp->tx_frames; 813 mac_stats->SingleCollisionFrames = mib->tx_single_collisions; 814 mac_stats->MultipleCollisionFrames = mib->tx_multiple_collisions; 815 mac_stats->FramesReceivedOK = pp->rx_frames; 816 mac_stats->FrameCheckSequenceErrors = mib->rx_crc_errors; 817 mac_stats->AlignmentErrors = mib->rx_alignment_errors; 818 mac_stats->OctetsTransmittedOK = mib->tx_good_bytes; 819 mac_stats->FramesWithDeferredXmissions = mib->tx_deferred; 820 mac_stats->LateCollisions = mib->tx_late_collisions; 821 mac_stats->FramesAbortedDueToXSColls = mib->tx_aborted_errors; 822 /* mac_stats->FramesLostDueToIntMACXmitError */ 823 /* mac_stats->CarrierSenseErrors */ 824 mac_stats->OctetsReceivedOK = mib->rx_good_bytes; 825 /* mac_stats->FramesLostDueToIntMACRcvError */ 826 mac_stats->MulticastFramesXmittedOK = mib->tx_multicast; 827 mac_stats->BroadcastFramesXmittedOK = mib->tx_broadcast; 828 /* mac_stats->FramesWithExcessiveDeferral */ 829 mac_stats->MulticastFramesReceivedOK = mib->rx_multicast; 830 mac_stats->BroadcastFramesReceivedOK = mib->rx_broadcast; 831 /* mac_stats->InRangeLengthErrors */ 832 /* mac_stats->OutOfRangeLengthField */ 833 mac_stats->FrameTooLongErrors = mib->rx_oversize_errors; 834} 835 836static void 837yt921x_dsa_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 838 struct ethtool_eth_ctrl_stats *ctrl_stats) 839{ 840 struct yt921x_priv *priv = to_yt921x_priv(ds); 841 struct yt921x_port *pp = &priv->ports[port]; 842 struct yt921x_mib *mib = &pp->mib; 843 844 mutex_lock(&priv->reg_lock); 845 yt921x_read_mib(priv, port); 846 mutex_unlock(&priv->reg_lock); 847 848 ctrl_stats->MACControlFramesTransmitted = mib->tx_pause; 849 ctrl_stats->MACControlFramesReceived = mib->rx_pause; 850 /* ctrl_stats->UnsupportedOpcodesReceived */ 851} 852 853static const struct ethtool_rmon_hist_range yt921x_rmon_ranges[] = { 854 { 0, 64 }, 855 { 65, 127 }, 856 { 128, 255 }, 857 { 256, 511 }, 858 { 512, 1023 }, 859 { 1024, 1518 }, 860 { 1519, YT921X_FRAME_SIZE_MAX }, 861 {} 862}; 863 864static void 865yt921x_dsa_get_rmon_stats(struct dsa_switch *ds, int port, 866 struct ethtool_rmon_stats *rmon_stats, 867 const struct ethtool_rmon_hist_range **ranges) 868{ 869 struct yt921x_priv *priv = to_yt921x_priv(ds); 870 struct yt921x_port *pp = &priv->ports[port]; 871 struct yt921x_mib *mib = &pp->mib; 872 873 mutex_lock(&priv->reg_lock); 874 yt921x_read_mib(priv, port); 875 mutex_unlock(&priv->reg_lock); 876 877 *ranges = yt921x_rmon_ranges; 878 879 rmon_stats->undersize_pkts = mib->rx_undersize_errors; 880 rmon_stats->oversize_pkts = mib->rx_oversize_errors; 881 rmon_stats->fragments = mib->rx_alignment_errors; 882 /* rmon_stats->jabbers */ 883 884 rmon_stats->hist[0] = mib->rx_64byte; 885 rmon_stats->hist[1] = mib->rx_65_127byte; 886 rmon_stats->hist[2] = mib->rx_128_255byte; 887 rmon_stats->hist[3] = mib->rx_256_511byte; 888 rmon_stats->hist[4] = mib->rx_512_1023byte; 889 rmon_stats->hist[5] = mib->rx_1024_1518byte; 890 rmon_stats->hist[6] = mib->rx_jumbo; 891 892 rmon_stats->hist_tx[0] = mib->tx_64byte; 893 rmon_stats->hist_tx[1] = mib->tx_65_127byte; 894 rmon_stats->hist_tx[2] = mib->tx_128_255byte; 895 rmon_stats->hist_tx[3] = mib->tx_256_511byte; 896 rmon_stats->hist_tx[4] = mib->tx_512_1023byte; 897 rmon_stats->hist_tx[5] = mib->tx_1024_1518byte; 898 rmon_stats->hist_tx[6] = mib->tx_jumbo; 899} 900 901static void 902yt921x_dsa_get_stats64(struct dsa_switch *ds, int port, 903 struct rtnl_link_stats64 *stats) 904{ 905 struct yt921x_priv *priv = to_yt921x_priv(ds); 906 struct yt921x_port *pp = &priv->ports[port]; 907 struct yt921x_mib *mib = &pp->mib; 908 909 stats->rx_length_errors = mib->rx_undersize_errors + 910 mib->rx_fragment_errors; 911 stats->rx_over_errors = mib->rx_oversize_errors; 912 stats->rx_crc_errors = mib->rx_crc_errors; 913 stats->rx_frame_errors = mib->rx_alignment_errors; 914 /* stats->rx_fifo_errors */ 915 /* stats->rx_missed_errors */ 916 917 stats->tx_aborted_errors = mib->tx_aborted_errors; 918 /* stats->tx_carrier_errors */ 919 stats->tx_fifo_errors = mib->tx_undersize_errors; 920 /* stats->tx_heartbeat_errors */ 921 stats->tx_window_errors = mib->tx_late_collisions; 922 923 stats->rx_packets = pp->rx_frames; 924 stats->tx_packets = pp->tx_frames; 925 stats->rx_bytes = mib->rx_good_bytes - ETH_FCS_LEN * stats->rx_packets; 926 stats->tx_bytes = mib->tx_good_bytes - ETH_FCS_LEN * stats->tx_packets; 927 stats->rx_errors = stats->rx_length_errors + stats->rx_over_errors + 928 stats->rx_crc_errors + stats->rx_frame_errors; 929 stats->tx_errors = stats->tx_aborted_errors + stats->tx_fifo_errors + 930 stats->tx_window_errors; 931 stats->rx_dropped = mib->rx_dropped; 932 /* stats->tx_dropped */ 933 stats->multicast = mib->rx_multicast; 934 stats->collisions = mib->tx_collisions; 935} 936 937static void 938yt921x_dsa_get_pause_stats(struct dsa_switch *ds, int port, 939 struct ethtool_pause_stats *pause_stats) 940{ 941 struct yt921x_priv *priv = to_yt921x_priv(ds); 942 struct yt921x_port *pp = &priv->ports[port]; 943 struct yt921x_mib *mib = &pp->mib; 944 945 mutex_lock(&priv->reg_lock); 946 yt921x_read_mib(priv, port); 947 mutex_unlock(&priv->reg_lock); 948 949 pause_stats->tx_pause_frames = mib->tx_pause; 950 pause_stats->rx_pause_frames = mib->rx_pause; 951} 952 953static int 954yt921x_set_eee(struct yt921x_priv *priv, int port, struct ethtool_keee *e) 955{ 956 /* Poor datasheet for EEE operations; don't ask if you are confused */ 957 958 bool enable = e->eee_enabled; 959 u16 new_mask; 960 int res; 961 962 /* Enable / disable global EEE */ 963 new_mask = priv->eee_ports_mask; 964 new_mask &= ~BIT(port); 965 new_mask |= !enable ? 0 : BIT(port); 966 967 if (!!new_mask != !!priv->eee_ports_mask) { 968 res = yt921x_reg_toggle_bits(priv, YT921X_PON_STRAP_FUNC, 969 YT921X_PON_STRAP_EEE, !!new_mask); 970 if (res) 971 return res; 972 res = yt921x_reg_toggle_bits(priv, YT921X_PON_STRAP_VAL, 973 YT921X_PON_STRAP_EEE, !!new_mask); 974 if (res) 975 return res; 976 } 977 978 priv->eee_ports_mask = new_mask; 979 980 /* Enable / disable port EEE */ 981 res = yt921x_reg_toggle_bits(priv, YT921X_EEE_CTRL, 982 YT921X_EEE_CTRL_ENn(port), enable); 983 if (res) 984 return res; 985 res = yt921x_reg_toggle_bits(priv, YT921X_EEEn_VAL(port), 986 YT921X_EEE_VAL_DATA, enable); 987 if (res) 988 return res; 989 990 return 0; 991} 992 993static int 994yt921x_dsa_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 995{ 996 struct yt921x_priv *priv = to_yt921x_priv(ds); 997 int res; 998 999 mutex_lock(&priv->reg_lock); 1000 res = yt921x_set_eee(priv, port, e); 1001 mutex_unlock(&priv->reg_lock); 1002 1003 return res; 1004} 1005 1006static int 1007yt921x_dsa_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1008{ 1009 /* Only serves as packet filter, since the frame size is always set to 1010 * maximum after reset 1011 */ 1012 1013 struct yt921x_priv *priv = to_yt921x_priv(ds); 1014 struct dsa_port *dp = dsa_to_port(ds, port); 1015 int frame_size; 1016 int res; 1017 1018 frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN; 1019 if (dsa_port_is_cpu(dp)) 1020 frame_size += YT921X_TAG_LEN; 1021 1022 mutex_lock(&priv->reg_lock); 1023 res = yt921x_reg_update_bits(priv, YT921X_MACn_FRAME(port), 1024 YT921X_MAC_FRAME_SIZE_M, 1025 YT921X_MAC_FRAME_SIZE(frame_size)); 1026 mutex_unlock(&priv->reg_lock); 1027 1028 return res; 1029} 1030 1031static int yt921x_dsa_port_max_mtu(struct dsa_switch *ds, int port) 1032{ 1033 /* Only called for user ports, exclude tag len here */ 1034 return YT921X_FRAME_SIZE_MAX - ETH_HLEN - ETH_FCS_LEN - YT921X_TAG_LEN; 1035} 1036 1037static int 1038yt921x_mirror_del(struct yt921x_priv *priv, int port, bool ingress) 1039{ 1040 u32 mask; 1041 1042 if (ingress) 1043 mask = YT921X_MIRROR_IGR_PORTn(port); 1044 else 1045 mask = YT921X_MIRROR_EGR_PORTn(port); 1046 return yt921x_reg_clear_bits(priv, YT921X_MIRROR, mask); 1047} 1048 1049static int 1050yt921x_mirror_add(struct yt921x_priv *priv, int port, bool ingress, 1051 int to_local_port, struct netlink_ext_ack *extack) 1052{ 1053 u32 srcs; 1054 u32 ctrl; 1055 u32 val; 1056 u32 dst; 1057 int res; 1058 1059 if (ingress) 1060 srcs = YT921X_MIRROR_IGR_PORTn(port); 1061 else 1062 srcs = YT921X_MIRROR_EGR_PORTn(port); 1063 dst = YT921X_MIRROR_PORT(to_local_port); 1064 1065 res = yt921x_reg_read(priv, YT921X_MIRROR, &val); 1066 if (res) 1067 return res; 1068 1069 /* other mirror tasks & different dst port -> conflict */ 1070 if ((val & ~srcs & (YT921X_MIRROR_EGR_PORTS_M | 1071 YT921X_MIRROR_IGR_PORTS_M)) && 1072 (val & YT921X_MIRROR_PORT_M) != dst) { 1073 NL_SET_ERR_MSG_MOD(extack, 1074 "Sniffer port is already configured, delete existing rules & retry"); 1075 return -EBUSY; 1076 } 1077 1078 ctrl = val & ~YT921X_MIRROR_PORT_M; 1079 ctrl |= srcs; 1080 ctrl |= dst; 1081 1082 if (ctrl == val) 1083 return 0; 1084 1085 return yt921x_reg_write(priv, YT921X_MIRROR, ctrl); 1086} 1087 1088static void 1089yt921x_dsa_port_mirror_del(struct dsa_switch *ds, int port, 1090 struct dsa_mall_mirror_tc_entry *mirror) 1091{ 1092 struct yt921x_priv *priv = to_yt921x_priv(ds); 1093 struct device *dev = to_device(priv); 1094 int res; 1095 1096 mutex_lock(&priv->reg_lock); 1097 res = yt921x_mirror_del(priv, port, mirror->ingress); 1098 mutex_unlock(&priv->reg_lock); 1099 1100 if (res) 1101 dev_err(dev, "Failed to %s port %d: %i\n", "unmirror", 1102 port, res); 1103} 1104 1105static int 1106yt921x_dsa_port_mirror_add(struct dsa_switch *ds, int port, 1107 struct dsa_mall_mirror_tc_entry *mirror, 1108 bool ingress, struct netlink_ext_ack *extack) 1109{ 1110 struct yt921x_priv *priv = to_yt921x_priv(ds); 1111 int res; 1112 1113 mutex_lock(&priv->reg_lock); 1114 res = yt921x_mirror_add(priv, port, ingress, 1115 mirror->to_local_port, extack); 1116 mutex_unlock(&priv->reg_lock); 1117 1118 return res; 1119} 1120 1121static int yt921x_fdb_wait(struct yt921x_priv *priv, u32 *valp) 1122{ 1123 struct device *dev = to_device(priv); 1124 u32 val = YT921X_FDB_RESULT_DONE; 1125 int res; 1126 1127 res = yt921x_reg_wait(priv, YT921X_FDB_RESULT, YT921X_FDB_RESULT_DONE, 1128 &val); 1129 if (res) { 1130 dev_err(dev, "FDB probably stuck\n"); 1131 return res; 1132 } 1133 1134 *valp = val; 1135 return 0; 1136} 1137 1138static int 1139yt921x_fdb_in01(struct yt921x_priv *priv, const unsigned char *addr, 1140 u16 vid, u32 ctrl1) 1141{ 1142 u32 ctrl; 1143 int res; 1144 1145 ctrl = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 1146 res = yt921x_reg_write(priv, YT921X_FDB_IN0, ctrl); 1147 if (res) 1148 return res; 1149 1150 ctrl = ctrl1 | YT921X_FDB_IO1_FID(vid) | (addr[4] << 8) | addr[5]; 1151 return yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl); 1152} 1153 1154static int 1155yt921x_fdb_has(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 1156 u16 *indexp) 1157{ 1158 u32 ctrl; 1159 u32 val; 1160 int res; 1161 1162 res = yt921x_fdb_in01(priv, addr, vid, 0); 1163 if (res) 1164 return res; 1165 1166 ctrl = 0; 1167 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 1168 if (res) 1169 return res; 1170 1171 ctrl = YT921X_FDB_OP_OP_GET_ONE | YT921X_FDB_OP_START; 1172 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1173 if (res) 1174 return res; 1175 1176 res = yt921x_fdb_wait(priv, &val); 1177 if (res) 1178 return res; 1179 if (val & YT921X_FDB_RESULT_NOTFOUND) { 1180 *indexp = YT921X_FDB_NUM; 1181 return 0; 1182 } 1183 1184 *indexp = FIELD_GET(YT921X_FDB_RESULT_INDEX_M, val); 1185 return 0; 1186} 1187 1188static int 1189yt921x_fdb_read(struct yt921x_priv *priv, unsigned char *addr, u16 *vidp, 1190 u16 *ports_maskp, u16 *indexp, u8 *statusp) 1191{ 1192 struct device *dev = to_device(priv); 1193 u16 index; 1194 u32 data0; 1195 u32 data1; 1196 u32 data2; 1197 u32 val; 1198 int res; 1199 1200 res = yt921x_fdb_wait(priv, &val); 1201 if (res) 1202 return res; 1203 if (val & YT921X_FDB_RESULT_NOTFOUND) { 1204 *ports_maskp = 0; 1205 return 0; 1206 } 1207 index = FIELD_GET(YT921X_FDB_RESULT_INDEX_M, val); 1208 1209 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &data1); 1210 if (res) 1211 return res; 1212 if ((data1 & YT921X_FDB_IO1_STATUS_M) == 1213 YT921X_FDB_IO1_STATUS_INVALID) { 1214 *ports_maskp = 0; 1215 return 0; 1216 } 1217 1218 res = yt921x_reg_read(priv, YT921X_FDB_OUT0, &data0); 1219 if (res) 1220 return res; 1221 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &data2); 1222 if (res) 1223 return res; 1224 1225 addr[0] = data0 >> 24; 1226 addr[1] = data0 >> 16; 1227 addr[2] = data0 >> 8; 1228 addr[3] = data0; 1229 addr[4] = data1 >> 8; 1230 addr[5] = data1; 1231 *vidp = FIELD_GET(YT921X_FDB_IO1_FID_M, data1); 1232 *indexp = index; 1233 *ports_maskp = FIELD_GET(YT921X_FDB_IO2_EGR_PORTS_M, data2); 1234 *statusp = FIELD_GET(YT921X_FDB_IO1_STATUS_M, data1); 1235 1236 dev_dbg(dev, 1237 "%s: index 0x%x, mac %02x:%02x:%02x:%02x:%02x:%02x, vid %d, ports 0x%x, status %d\n", 1238 __func__, *indexp, addr[0], addr[1], addr[2], addr[3], 1239 addr[4], addr[5], *vidp, *ports_maskp, *statusp); 1240 return 0; 1241} 1242 1243static int 1244yt921x_fdb_dump(struct yt921x_priv *priv, u16 ports_mask, 1245 dsa_fdb_dump_cb_t *cb, void *data) 1246{ 1247 unsigned char addr[ETH_ALEN]; 1248 u8 status; 1249 u16 pmask; 1250 u16 index; 1251 u32 ctrl; 1252 u16 vid; 1253 int res; 1254 1255 ctrl = YT921X_FDB_OP_INDEX(0) | YT921X_FDB_OP_MODE_INDEX | 1256 YT921X_FDB_OP_OP_GET_ONE | YT921X_FDB_OP_START; 1257 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1258 if (res) 1259 return res; 1260 res = yt921x_fdb_read(priv, addr, &vid, &pmask, &index, &status); 1261 if (res) 1262 return res; 1263 if ((pmask & ports_mask) && !is_multicast_ether_addr(addr)) { 1264 res = cb(addr, vid, 1265 status == YT921X_FDB_ENTRY_STATUS_STATIC, data); 1266 if (res) 1267 return res; 1268 } 1269 1270 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1271 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 1272 if (res) 1273 return res; 1274 1275 index = 0; 1276 do { 1277 ctrl = YT921X_FDB_OP_INDEX(index) | YT921X_FDB_OP_MODE_INDEX | 1278 YT921X_FDB_OP_NEXT_TYPE_UCAST_PORT | 1279 YT921X_FDB_OP_OP_GET_NEXT | YT921X_FDB_OP_START; 1280 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1281 if (res) 1282 return res; 1283 1284 res = yt921x_fdb_read(priv, addr, &vid, &pmask, &index, 1285 &status); 1286 if (res) 1287 return res; 1288 if (!pmask) 1289 break; 1290 1291 if ((pmask & ports_mask) && !is_multicast_ether_addr(addr)) { 1292 res = cb(addr, vid, 1293 status == YT921X_FDB_ENTRY_STATUS_STATIC, 1294 data); 1295 if (res) 1296 return res; 1297 } 1298 1299 /* Never call GET_NEXT with 4095, otherwise it will hang 1300 * forever until a reset! 1301 */ 1302 } while (index < YT921X_FDB_NUM - 1); 1303 1304 return 0; 1305} 1306 1307static int 1308yt921x_fdb_flush_raw(struct yt921x_priv *priv, u16 ports_mask, u16 vid, 1309 bool flush_static) 1310{ 1311 u32 ctrl; 1312 u32 val; 1313 int res; 1314 1315 if (vid < 4096) { 1316 ctrl = YT921X_FDB_IO1_FID(vid); 1317 res = yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl); 1318 if (res) 1319 return res; 1320 } 1321 1322 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1323 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 1324 if (res) 1325 return res; 1326 1327 ctrl = YT921X_FDB_OP_OP_FLUSH | YT921X_FDB_OP_START; 1328 if (vid >= 4096) 1329 ctrl |= YT921X_FDB_OP_FLUSH_PORT; 1330 else 1331 ctrl |= YT921X_FDB_OP_FLUSH_PORT_VID; 1332 if (flush_static) 1333 ctrl |= YT921X_FDB_OP_FLUSH_STATIC; 1334 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1335 if (res) 1336 return res; 1337 1338 res = yt921x_fdb_wait(priv, &val); 1339 if (res) 1340 return res; 1341 1342 return 0; 1343} 1344 1345static int 1346yt921x_fdb_flush_port(struct yt921x_priv *priv, int port, bool flush_static) 1347{ 1348 return yt921x_fdb_flush_raw(priv, BIT(port), 4096, flush_static); 1349} 1350 1351static int 1352yt921x_fdb_add_index_in12(struct yt921x_priv *priv, u16 index, u16 ctrl1, 1353 u16 ctrl2) 1354{ 1355 u32 ctrl; 1356 u32 val; 1357 int res; 1358 1359 res = yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl1); 1360 if (res) 1361 return res; 1362 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl2); 1363 if (res) 1364 return res; 1365 1366 ctrl = YT921X_FDB_OP_INDEX(index) | YT921X_FDB_OP_MODE_INDEX | 1367 YT921X_FDB_OP_OP_ADD | YT921X_FDB_OP_START; 1368 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1369 if (res) 1370 return res; 1371 1372 return yt921x_fdb_wait(priv, &val); 1373} 1374 1375static int 1376yt921x_fdb_add(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 1377 u16 ports_mask) 1378{ 1379 u32 ctrl; 1380 u32 val; 1381 int res; 1382 1383 ctrl = YT921X_FDB_IO1_STATUS_STATIC; 1384 res = yt921x_fdb_in01(priv, addr, vid, ctrl); 1385 if (res) 1386 return res; 1387 1388 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1389 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 1390 if (res) 1391 return res; 1392 1393 ctrl = YT921X_FDB_OP_OP_ADD | YT921X_FDB_OP_START; 1394 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1395 if (res) 1396 return res; 1397 1398 return yt921x_fdb_wait(priv, &val); 1399} 1400 1401static int 1402yt921x_fdb_leave(struct yt921x_priv *priv, const unsigned char *addr, 1403 u16 vid, u16 ports_mask) 1404{ 1405 u16 index; 1406 u32 ctrl1; 1407 u32 ctrl2; 1408 u32 ctrl; 1409 u32 val2; 1410 u32 val; 1411 int res; 1412 1413 /* Check for presence */ 1414 res = yt921x_fdb_has(priv, addr, vid, &index); 1415 if (res) 1416 return res; 1417 if (index >= YT921X_FDB_NUM) 1418 return 0; 1419 1420 /* Check if action required */ 1421 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &val2); 1422 if (res) 1423 return res; 1424 1425 ctrl2 = val2 & ~YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1426 if (ctrl2 == val2) 1427 return 0; 1428 if (!(ctrl2 & YT921X_FDB_IO2_EGR_PORTS_M)) { 1429 ctrl = YT921X_FDB_OP_OP_DEL | YT921X_FDB_OP_START; 1430 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1431 if (res) 1432 return res; 1433 1434 return yt921x_fdb_wait(priv, &val); 1435 } 1436 1437 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &ctrl1); 1438 if (res) 1439 return res; 1440 1441 return yt921x_fdb_add_index_in12(priv, index, ctrl1, ctrl2); 1442} 1443 1444static int 1445yt921x_fdb_join(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 1446 u16 ports_mask) 1447{ 1448 u16 index; 1449 u32 ctrl1; 1450 u32 ctrl2; 1451 u32 val1; 1452 u32 val2; 1453 int res; 1454 1455 /* Check for presence */ 1456 res = yt921x_fdb_has(priv, addr, vid, &index); 1457 if (res) 1458 return res; 1459 if (index >= YT921X_FDB_NUM) 1460 return yt921x_fdb_add(priv, addr, vid, ports_mask); 1461 1462 /* Check if action required */ 1463 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &val1); 1464 if (res) 1465 return res; 1466 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &val2); 1467 if (res) 1468 return res; 1469 1470 ctrl1 = val1 & ~YT921X_FDB_IO1_STATUS_M; 1471 ctrl1 |= YT921X_FDB_IO1_STATUS_STATIC; 1472 ctrl2 = val2 | YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1473 if (ctrl1 == val1 && ctrl2 == val2) 1474 return 0; 1475 1476 return yt921x_fdb_add_index_in12(priv, index, ctrl1, ctrl2); 1477} 1478 1479static int 1480yt921x_dsa_port_fdb_dump(struct dsa_switch *ds, int port, 1481 dsa_fdb_dump_cb_t *cb, void *data) 1482{ 1483 struct yt921x_priv *priv = to_yt921x_priv(ds); 1484 int res; 1485 1486 mutex_lock(&priv->reg_lock); 1487 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show" 1488 * only wants to see unicast 1489 */ 1490 res = yt921x_fdb_dump(priv, BIT(port), cb, data); 1491 mutex_unlock(&priv->reg_lock); 1492 1493 return res; 1494} 1495 1496static void yt921x_dsa_port_fast_age(struct dsa_switch *ds, int port) 1497{ 1498 struct yt921x_priv *priv = to_yt921x_priv(ds); 1499 struct device *dev = to_device(priv); 1500 int res; 1501 1502 mutex_lock(&priv->reg_lock); 1503 res = yt921x_fdb_flush_port(priv, port, false); 1504 mutex_unlock(&priv->reg_lock); 1505 1506 if (res) 1507 dev_err(dev, "Failed to %s port %d: %i\n", "clear FDB for", 1508 port, res); 1509} 1510 1511static int 1512yt921x_dsa_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 1513{ 1514 struct yt921x_priv *priv = to_yt921x_priv(ds); 1515 u32 ctrl; 1516 int res; 1517 1518 /* AGEING reg is set in 5s step */ 1519 ctrl = clamp(msecs / 5000, 1, U16_MAX); 1520 1521 mutex_lock(&priv->reg_lock); 1522 res = yt921x_reg_write(priv, YT921X_AGEING, ctrl); 1523 mutex_unlock(&priv->reg_lock); 1524 1525 return res; 1526} 1527 1528static int 1529yt921x_dsa_port_fdb_del(struct dsa_switch *ds, int port, 1530 const unsigned char *addr, u16 vid, struct dsa_db db) 1531{ 1532 struct yt921x_priv *priv = to_yt921x_priv(ds); 1533 int res; 1534 1535 mutex_lock(&priv->reg_lock); 1536 res = yt921x_fdb_leave(priv, addr, vid, BIT(port)); 1537 mutex_unlock(&priv->reg_lock); 1538 1539 return res; 1540} 1541 1542static int 1543yt921x_dsa_port_fdb_add(struct dsa_switch *ds, int port, 1544 const unsigned char *addr, u16 vid, struct dsa_db db) 1545{ 1546 struct yt921x_priv *priv = to_yt921x_priv(ds); 1547 int res; 1548 1549 mutex_lock(&priv->reg_lock); 1550 res = yt921x_fdb_join(priv, addr, vid, BIT(port)); 1551 mutex_unlock(&priv->reg_lock); 1552 1553 return res; 1554} 1555 1556static int 1557yt921x_dsa_port_mdb_del(struct dsa_switch *ds, int port, 1558 const struct switchdev_obj_port_mdb *mdb, 1559 struct dsa_db db) 1560{ 1561 struct yt921x_priv *priv = to_yt921x_priv(ds); 1562 const unsigned char *addr = mdb->addr; 1563 u16 vid = mdb->vid; 1564 int res; 1565 1566 mutex_lock(&priv->reg_lock); 1567 res = yt921x_fdb_leave(priv, addr, vid, BIT(port)); 1568 mutex_unlock(&priv->reg_lock); 1569 1570 return res; 1571} 1572 1573static int 1574yt921x_dsa_port_mdb_add(struct dsa_switch *ds, int port, 1575 const struct switchdev_obj_port_mdb *mdb, 1576 struct dsa_db db) 1577{ 1578 struct yt921x_priv *priv = to_yt921x_priv(ds); 1579 const unsigned char *addr = mdb->addr; 1580 u16 vid = mdb->vid; 1581 int res; 1582 1583 mutex_lock(&priv->reg_lock); 1584 res = yt921x_fdb_join(priv, addr, vid, BIT(port)); 1585 mutex_unlock(&priv->reg_lock); 1586 1587 return res; 1588} 1589 1590static int 1591yt921x_port_set_pvid(struct yt921x_priv *priv, int port, u16 vid) 1592{ 1593 u32 mask; 1594 u32 ctrl; 1595 1596 mask = YT921X_PORT_VLAN_CTRL_CVID_M; 1597 ctrl = YT921X_PORT_VLAN_CTRL_CVID(vid); 1598 return yt921x_reg_update_bits(priv, YT921X_PORTn_VLAN_CTRL(port), 1599 mask, ctrl); 1600} 1601 1602static int 1603yt921x_vlan_filtering(struct yt921x_priv *priv, int port, bool vlan_filtering) 1604{ 1605 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 1606 struct net_device *bdev; 1607 u16 pvid; 1608 u32 mask; 1609 u32 ctrl; 1610 int res; 1611 1612 bdev = dsa_port_bridge_dev_get(dp); 1613 1614 if (!bdev || !vlan_filtering) 1615 pvid = YT921X_VID_UNWARE; 1616 else 1617 br_vlan_get_pvid(bdev, &pvid); 1618 res = yt921x_port_set_pvid(priv, port, pvid); 1619 if (res) 1620 return res; 1621 1622 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_TAGGED | 1623 YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1624 ctrl = 0; 1625 /* Do not drop tagged frames here; let VLAN_IGR_FILTER do it */ 1626 if (vlan_filtering && !pvid) 1627 ctrl |= YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1628 res = yt921x_reg_update_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), 1629 mask, ctrl); 1630 if (res) 1631 return res; 1632 1633 res = yt921x_reg_toggle_bits(priv, YT921X_VLAN_IGR_FILTER, 1634 YT921X_VLAN_IGR_FILTER_PORTn(port), 1635 vlan_filtering); 1636 if (res) 1637 return res; 1638 1639 /* Turn on / off VLAN awareness */ 1640 mask = YT921X_PORT_IGR_TPIDn_CTAG_M; 1641 if (!vlan_filtering) 1642 ctrl = 0; 1643 else 1644 ctrl = YT921X_PORT_IGR_TPIDn_CTAG(0); 1645 res = yt921x_reg_update_bits(priv, YT921X_PORTn_IGR_TPID(port), 1646 mask, ctrl); 1647 if (res) 1648 return res; 1649 1650 return 0; 1651} 1652 1653static int 1654yt921x_vlan_del(struct yt921x_priv *priv, int port, u16 vid) 1655{ 1656 u64 mask64; 1657 1658 mask64 = YT921X_VLAN_CTRL_PORTS(port) | 1659 YT921X_VLAN_CTRL_UNTAG_PORTn(port); 1660 1661 return yt921x_reg64_clear_bits(priv, YT921X_VLANn_CTRL(vid), mask64); 1662} 1663 1664static int 1665yt921x_vlan_add(struct yt921x_priv *priv, int port, u16 vid, bool untagged) 1666{ 1667 u64 mask64; 1668 u64 ctrl64; 1669 1670 mask64 = YT921X_VLAN_CTRL_PORTn(port) | 1671 YT921X_VLAN_CTRL_PORTS(priv->cpu_ports_mask); 1672 ctrl64 = mask64; 1673 1674 mask64 |= YT921X_VLAN_CTRL_UNTAG_PORTn(port); 1675 if (untagged) 1676 ctrl64 |= YT921X_VLAN_CTRL_UNTAG_PORTn(port); 1677 1678 return yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(vid), 1679 mask64, ctrl64); 1680} 1681 1682static int 1683yt921x_pvid_clear(struct yt921x_priv *priv, int port) 1684{ 1685 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 1686 bool vlan_filtering; 1687 u32 mask; 1688 int res; 1689 1690 vlan_filtering = dsa_port_is_vlan_filtering(dp); 1691 1692 res = yt921x_port_set_pvid(priv, port, 1693 vlan_filtering ? 0 : YT921X_VID_UNWARE); 1694 if (res) 1695 return res; 1696 1697 if (vlan_filtering) { 1698 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1699 res = yt921x_reg_set_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), 1700 mask); 1701 if (res) 1702 return res; 1703 } 1704 1705 return 0; 1706} 1707 1708static int 1709yt921x_pvid_set(struct yt921x_priv *priv, int port, u16 vid) 1710{ 1711 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 1712 bool vlan_filtering; 1713 u32 mask; 1714 int res; 1715 1716 vlan_filtering = dsa_port_is_vlan_filtering(dp); 1717 1718 if (vlan_filtering) { 1719 res = yt921x_port_set_pvid(priv, port, vid); 1720 if (res) 1721 return res; 1722 } 1723 1724 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1725 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), mask); 1726 if (res) 1727 return res; 1728 1729 return 0; 1730} 1731 1732static int 1733yt921x_dsa_port_vlan_filtering(struct dsa_switch *ds, int port, 1734 bool vlan_filtering, 1735 struct netlink_ext_ack *extack) 1736{ 1737 struct yt921x_priv *priv = to_yt921x_priv(ds); 1738 int res; 1739 1740 if (dsa_is_cpu_port(ds, port)) 1741 return 0; 1742 1743 mutex_lock(&priv->reg_lock); 1744 res = yt921x_vlan_filtering(priv, port, vlan_filtering); 1745 mutex_unlock(&priv->reg_lock); 1746 1747 return res; 1748} 1749 1750static int 1751yt921x_dsa_port_vlan_del(struct dsa_switch *ds, int port, 1752 const struct switchdev_obj_port_vlan *vlan) 1753{ 1754 struct yt921x_priv *priv = to_yt921x_priv(ds); 1755 u16 vid = vlan->vid; 1756 u16 pvid; 1757 int res; 1758 1759 if (dsa_is_cpu_port(ds, port)) 1760 return 0; 1761 1762 mutex_lock(&priv->reg_lock); 1763 do { 1764 struct dsa_port *dp = dsa_to_port(ds, port); 1765 struct net_device *bdev; 1766 1767 res = yt921x_vlan_del(priv, port, vid); 1768 if (res) 1769 break; 1770 1771 bdev = dsa_port_bridge_dev_get(dp); 1772 if (bdev) { 1773 br_vlan_get_pvid(bdev, &pvid); 1774 if (pvid == vid) 1775 res = yt921x_pvid_clear(priv, port); 1776 } 1777 } while (0); 1778 mutex_unlock(&priv->reg_lock); 1779 1780 return res; 1781} 1782 1783static int 1784yt921x_dsa_port_vlan_add(struct dsa_switch *ds, int port, 1785 const struct switchdev_obj_port_vlan *vlan, 1786 struct netlink_ext_ack *extack) 1787{ 1788 struct yt921x_priv *priv = to_yt921x_priv(ds); 1789 u16 vid = vlan->vid; 1790 u16 pvid; 1791 int res; 1792 1793 /* CPU port is supposed to be a member of every VLAN; see 1794 * yt921x_vlan_add() and yt921x_port_setup() 1795 */ 1796 if (dsa_is_cpu_port(ds, port)) 1797 return 0; 1798 1799 mutex_lock(&priv->reg_lock); 1800 do { 1801 struct dsa_port *dp = dsa_to_port(ds, port); 1802 struct net_device *bdev; 1803 1804 res = yt921x_vlan_add(priv, port, vid, 1805 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1806 if (res) 1807 break; 1808 1809 bdev = dsa_port_bridge_dev_get(dp); 1810 if (bdev) { 1811 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { 1812 res = yt921x_pvid_set(priv, port, vid); 1813 } else { 1814 br_vlan_get_pvid(bdev, &pvid); 1815 if (pvid == vid) 1816 res = yt921x_pvid_clear(priv, port); 1817 } 1818 } 1819 } while (0); 1820 mutex_unlock(&priv->reg_lock); 1821 1822 return res; 1823} 1824 1825static int yt921x_userport_standalone(struct yt921x_priv *priv, int port) 1826{ 1827 u32 mask; 1828 u32 ctrl; 1829 int res; 1830 1831 ctrl = ~priv->cpu_ports_mask; 1832 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), ctrl); 1833 if (res) 1834 return res; 1835 1836 /* Turn off FDB learning to prevent FDB pollution */ 1837 mask = YT921X_PORT_LEARN_DIS; 1838 res = yt921x_reg_set_bits(priv, YT921X_PORTn_LEARN(port), mask); 1839 if (res) 1840 return res; 1841 1842 /* Turn off VLAN awareness */ 1843 mask = YT921X_PORT_IGR_TPIDn_CTAG_M; 1844 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_IGR_TPID(port), mask); 1845 if (res) 1846 return res; 1847 1848 /* Unrelated since learning is off and all packets are trapped; 1849 * set it anyway 1850 */ 1851 res = yt921x_port_set_pvid(priv, port, YT921X_VID_UNWARE); 1852 if (res) 1853 return res; 1854 1855 return 0; 1856} 1857 1858static int yt921x_userport_bridge(struct yt921x_priv *priv, int port) 1859{ 1860 u32 mask; 1861 int res; 1862 1863 mask = YT921X_PORT_LEARN_DIS; 1864 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_LEARN(port), mask); 1865 if (res) 1866 return res; 1867 1868 return 0; 1869} 1870 1871static int yt921x_isolate(struct yt921x_priv *priv, int port) 1872{ 1873 u32 mask; 1874 int res; 1875 1876 mask = BIT(port); 1877 for (int i = 0; i < YT921X_PORT_NUM; i++) { 1878 if ((BIT(i) & priv->cpu_ports_mask) || i == port) 1879 continue; 1880 1881 res = yt921x_reg_set_bits(priv, YT921X_PORTn_ISOLATION(i), 1882 mask); 1883 if (res) 1884 return res; 1885 } 1886 1887 return 0; 1888} 1889 1890/* Make sure to include the CPU port in ports_mask, or your bridge will 1891 * not have it. 1892 */ 1893static int yt921x_bridge(struct yt921x_priv *priv, u16 ports_mask) 1894{ 1895 unsigned long targets_mask = ports_mask & ~priv->cpu_ports_mask; 1896 u32 isolated_mask; 1897 u32 ctrl; 1898 int port; 1899 int res; 1900 1901 isolated_mask = 0; 1902 for_each_set_bit(port, &targets_mask, YT921X_PORT_NUM) { 1903 struct yt921x_port *pp = &priv->ports[port]; 1904 1905 if (pp->isolated) 1906 isolated_mask |= BIT(port); 1907 } 1908 1909 /* Block from non-cpu bridge ports ... */ 1910 for_each_set_bit(port, &targets_mask, YT921X_PORT_NUM) { 1911 struct yt921x_port *pp = &priv->ports[port]; 1912 1913 /* to non-bridge ports */ 1914 ctrl = ~ports_mask; 1915 /* to isolated ports when isolated */ 1916 if (pp->isolated) 1917 ctrl |= isolated_mask; 1918 /* to itself when non-hairpin */ 1919 if (!pp->hairpin) 1920 ctrl |= BIT(port); 1921 else 1922 ctrl &= ~BIT(port); 1923 1924 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), 1925 ctrl); 1926 if (res) 1927 return res; 1928 } 1929 1930 return 0; 1931} 1932 1933static int yt921x_bridge_leave(struct yt921x_priv *priv, int port) 1934{ 1935 int res; 1936 1937 res = yt921x_userport_standalone(priv, port); 1938 if (res) 1939 return res; 1940 1941 res = yt921x_isolate(priv, port); 1942 if (res) 1943 return res; 1944 1945 return 0; 1946} 1947 1948static int 1949yt921x_bridge_join(struct yt921x_priv *priv, int port, u16 ports_mask) 1950{ 1951 int res; 1952 1953 res = yt921x_userport_bridge(priv, port); 1954 if (res) 1955 return res; 1956 1957 res = yt921x_bridge(priv, ports_mask); 1958 if (res) 1959 return res; 1960 1961 return 0; 1962} 1963 1964static u32 1965dsa_bridge_ports(struct dsa_switch *ds, const struct net_device *bdev) 1966{ 1967 struct dsa_port *dp; 1968 u32 mask = 0; 1969 1970 dsa_switch_for_each_user_port(dp, ds) 1971 if (dsa_port_offloads_bridge_dev(dp, bdev)) 1972 mask |= BIT(dp->index); 1973 1974 return mask; 1975} 1976 1977static int 1978yt921x_bridge_flags(struct yt921x_priv *priv, int port, 1979 struct switchdev_brport_flags flags) 1980{ 1981 struct yt921x_port *pp = &priv->ports[port]; 1982 bool do_flush; 1983 u32 mask; 1984 int res; 1985 1986 if (flags.mask & BR_LEARNING) { 1987 bool learning = flags.val & BR_LEARNING; 1988 1989 mask = YT921X_PORT_LEARN_DIS; 1990 res = yt921x_reg_toggle_bits(priv, YT921X_PORTn_LEARN(port), 1991 mask, !learning); 1992 if (res) 1993 return res; 1994 } 1995 1996 /* BR_FLOOD, BR_MCAST_FLOOD: see the comment where ACT_UNK_ACTn_TRAP 1997 * is set 1998 */ 1999 2000 /* BR_BCAST_FLOOD: we can filter bcast, but cannot trap them */ 2001 2002 do_flush = false; 2003 if (flags.mask & BR_HAIRPIN_MODE) { 2004 pp->hairpin = flags.val & BR_HAIRPIN_MODE; 2005 do_flush = true; 2006 } 2007 if (flags.mask & BR_ISOLATED) { 2008 pp->isolated = flags.val & BR_ISOLATED; 2009 do_flush = true; 2010 } 2011 if (do_flush) { 2012 struct dsa_switch *ds = &priv->ds; 2013 struct dsa_port *dp = dsa_to_port(ds, port); 2014 struct net_device *bdev; 2015 2016 bdev = dsa_port_bridge_dev_get(dp); 2017 if (bdev) { 2018 u32 ports_mask; 2019 2020 ports_mask = dsa_bridge_ports(ds, bdev); 2021 ports_mask |= priv->cpu_ports_mask; 2022 res = yt921x_bridge(priv, ports_mask); 2023 if (res) 2024 return res; 2025 } 2026 } 2027 2028 return 0; 2029} 2030 2031static int 2032yt921x_dsa_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2033 struct switchdev_brport_flags flags, 2034 struct netlink_ext_ack *extack) 2035{ 2036 if (flags.mask & ~(BR_HAIRPIN_MODE | BR_LEARNING | BR_FLOOD | 2037 BR_MCAST_FLOOD | BR_ISOLATED)) 2038 return -EINVAL; 2039 return 0; 2040} 2041 2042static int 2043yt921x_dsa_port_bridge_flags(struct dsa_switch *ds, int port, 2044 struct switchdev_brport_flags flags, 2045 struct netlink_ext_ack *extack) 2046{ 2047 struct yt921x_priv *priv = to_yt921x_priv(ds); 2048 int res; 2049 2050 if (dsa_is_cpu_port(ds, port)) 2051 return 0; 2052 2053 mutex_lock(&priv->reg_lock); 2054 res = yt921x_bridge_flags(priv, port, flags); 2055 mutex_unlock(&priv->reg_lock); 2056 2057 return res; 2058} 2059 2060static void 2061yt921x_dsa_port_bridge_leave(struct dsa_switch *ds, int port, 2062 struct dsa_bridge bridge) 2063{ 2064 struct yt921x_priv *priv = to_yt921x_priv(ds); 2065 struct device *dev = to_device(priv); 2066 int res; 2067 2068 if (dsa_is_cpu_port(ds, port)) 2069 return; 2070 2071 mutex_lock(&priv->reg_lock); 2072 res = yt921x_bridge_leave(priv, port); 2073 mutex_unlock(&priv->reg_lock); 2074 2075 if (res) 2076 dev_err(dev, "Failed to %s port %d: %i\n", "unbridge", 2077 port, res); 2078} 2079 2080static int 2081yt921x_dsa_port_bridge_join(struct dsa_switch *ds, int port, 2082 struct dsa_bridge bridge, bool *tx_fwd_offload, 2083 struct netlink_ext_ack *extack) 2084{ 2085 struct yt921x_priv *priv = to_yt921x_priv(ds); 2086 u16 ports_mask; 2087 int res; 2088 2089 if (dsa_is_cpu_port(ds, port)) 2090 return 0; 2091 2092 ports_mask = dsa_bridge_ports(ds, bridge.dev); 2093 ports_mask |= priv->cpu_ports_mask; 2094 2095 mutex_lock(&priv->reg_lock); 2096 res = yt921x_bridge_join(priv, port, ports_mask); 2097 mutex_unlock(&priv->reg_lock); 2098 2099 return res; 2100} 2101 2102static int 2103yt921x_dsa_port_mst_state_set(struct dsa_switch *ds, int port, 2104 const struct switchdev_mst_state *st) 2105{ 2106 struct yt921x_priv *priv = to_yt921x_priv(ds); 2107 u32 mask; 2108 u32 ctrl; 2109 int res; 2110 2111 mask = YT921X_STP_PORTn_M(port); 2112 switch (st->state) { 2113 case BR_STATE_DISABLED: 2114 ctrl = YT921X_STP_PORTn_DISABLED(port); 2115 break; 2116 case BR_STATE_LISTENING: 2117 case BR_STATE_LEARNING: 2118 ctrl = YT921X_STP_PORTn_LEARNING(port); 2119 break; 2120 case BR_STATE_FORWARDING: 2121 default: 2122 ctrl = YT921X_STP_PORTn_FORWARD(port); 2123 break; 2124 case BR_STATE_BLOCKING: 2125 ctrl = YT921X_STP_PORTn_BLOCKING(port); 2126 break; 2127 } 2128 2129 mutex_lock(&priv->reg_lock); 2130 res = yt921x_reg_update_bits(priv, YT921X_STPn(st->msti), mask, ctrl); 2131 mutex_unlock(&priv->reg_lock); 2132 2133 return res; 2134} 2135 2136static int 2137yt921x_dsa_vlan_msti_set(struct dsa_switch *ds, struct dsa_bridge bridge, 2138 const struct switchdev_vlan_msti *msti) 2139{ 2140 struct yt921x_priv *priv = to_yt921x_priv(ds); 2141 u64 mask64; 2142 u64 ctrl64; 2143 int res; 2144 2145 if (!msti->vid) 2146 return -EINVAL; 2147 if (!msti->msti || msti->msti >= YT921X_MSTI_NUM) 2148 return -EINVAL; 2149 2150 mask64 = YT921X_VLAN_CTRL_STP_ID_M; 2151 ctrl64 = YT921X_VLAN_CTRL_STP_ID(msti->msti); 2152 2153 mutex_lock(&priv->reg_lock); 2154 res = yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(msti->vid), 2155 mask64, ctrl64); 2156 mutex_unlock(&priv->reg_lock); 2157 2158 return res; 2159} 2160 2161static void 2162yt921x_dsa_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2163{ 2164 struct yt921x_priv *priv = to_yt921x_priv(ds); 2165 struct dsa_port *dp = dsa_to_port(ds, port); 2166 struct device *dev = to_device(priv); 2167 bool learning; 2168 u32 mask; 2169 u32 ctrl; 2170 int res; 2171 2172 mask = YT921X_STP_PORTn_M(port); 2173 learning = false; 2174 switch (state) { 2175 case BR_STATE_DISABLED: 2176 ctrl = YT921X_STP_PORTn_DISABLED(port); 2177 break; 2178 case BR_STATE_LISTENING: 2179 ctrl = YT921X_STP_PORTn_LEARNING(port); 2180 break; 2181 case BR_STATE_LEARNING: 2182 ctrl = YT921X_STP_PORTn_LEARNING(port); 2183 learning = dp->learning; 2184 break; 2185 case BR_STATE_FORWARDING: 2186 default: 2187 ctrl = YT921X_STP_PORTn_FORWARD(port); 2188 learning = dp->learning; 2189 break; 2190 case BR_STATE_BLOCKING: 2191 ctrl = YT921X_STP_PORTn_BLOCKING(port); 2192 break; 2193 } 2194 2195 mutex_lock(&priv->reg_lock); 2196 do { 2197 res = yt921x_reg_update_bits(priv, YT921X_STPn(0), mask, ctrl); 2198 if (res) 2199 break; 2200 2201 mask = YT921X_PORT_LEARN_DIS; 2202 ctrl = !learning ? YT921X_PORT_LEARN_DIS : 0; 2203 res = yt921x_reg_update_bits(priv, YT921X_PORTn_LEARN(port), 2204 mask, ctrl); 2205 } while (0); 2206 mutex_unlock(&priv->reg_lock); 2207 2208 if (res) 2209 dev_err(dev, "Failed to %s port %d: %i\n", "set STP state for", 2210 port, res); 2211} 2212 2213static int yt921x_port_down(struct yt921x_priv *priv, int port) 2214{ 2215 u32 mask; 2216 int res; 2217 2218 mask = YT921X_PORT_LINK | YT921X_PORT_RX_MAC_EN | YT921X_PORT_TX_MAC_EN; 2219 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_CTRL(port), mask); 2220 if (res) 2221 return res; 2222 2223 if (yt921x_port_is_external(port)) { 2224 mask = YT921X_SERDES_LINK; 2225 res = yt921x_reg_clear_bits(priv, YT921X_SERDESn(port), mask); 2226 if (res) 2227 return res; 2228 2229 mask = YT921X_XMII_LINK; 2230 res = yt921x_reg_clear_bits(priv, YT921X_XMIIn(port), mask); 2231 if (res) 2232 return res; 2233 } 2234 2235 return 0; 2236} 2237 2238static int 2239yt921x_port_up(struct yt921x_priv *priv, int port, unsigned int mode, 2240 phy_interface_t interface, int speed, int duplex, 2241 bool tx_pause, bool rx_pause) 2242{ 2243 u32 mask; 2244 u32 ctrl; 2245 int res; 2246 2247 switch (speed) { 2248 case SPEED_10: 2249 ctrl = YT921X_PORT_SPEED_10; 2250 break; 2251 case SPEED_100: 2252 ctrl = YT921X_PORT_SPEED_100; 2253 break; 2254 case SPEED_1000: 2255 ctrl = YT921X_PORT_SPEED_1000; 2256 break; 2257 case SPEED_2500: 2258 ctrl = YT921X_PORT_SPEED_2500; 2259 break; 2260 case SPEED_10000: 2261 ctrl = YT921X_PORT_SPEED_10000; 2262 break; 2263 default: 2264 return -EINVAL; 2265 } 2266 if (duplex == DUPLEX_FULL) 2267 ctrl |= YT921X_PORT_DUPLEX_FULL; 2268 if (tx_pause) 2269 ctrl |= YT921X_PORT_TX_PAUSE; 2270 if (rx_pause) 2271 ctrl |= YT921X_PORT_RX_PAUSE; 2272 ctrl |= YT921X_PORT_RX_MAC_EN | YT921X_PORT_TX_MAC_EN; 2273 res = yt921x_reg_write(priv, YT921X_PORTn_CTRL(port), ctrl); 2274 if (res) 2275 return res; 2276 2277 if (yt921x_port_is_external(port)) { 2278 mask = YT921X_SERDES_SPEED_M; 2279 switch (speed) { 2280 case SPEED_10: 2281 ctrl = YT921X_SERDES_SPEED_10; 2282 break; 2283 case SPEED_100: 2284 ctrl = YT921X_SERDES_SPEED_100; 2285 break; 2286 case SPEED_1000: 2287 ctrl = YT921X_SERDES_SPEED_1000; 2288 break; 2289 case SPEED_2500: 2290 ctrl = YT921X_SERDES_SPEED_2500; 2291 break; 2292 case SPEED_10000: 2293 ctrl = YT921X_SERDES_SPEED_10000; 2294 break; 2295 default: 2296 return -EINVAL; 2297 } 2298 mask |= YT921X_SERDES_DUPLEX_FULL; 2299 if (duplex == DUPLEX_FULL) 2300 ctrl |= YT921X_SERDES_DUPLEX_FULL; 2301 mask |= YT921X_SERDES_TX_PAUSE; 2302 if (tx_pause) 2303 ctrl |= YT921X_SERDES_TX_PAUSE; 2304 mask |= YT921X_SERDES_RX_PAUSE; 2305 if (rx_pause) 2306 ctrl |= YT921X_SERDES_RX_PAUSE; 2307 mask |= YT921X_SERDES_LINK; 2308 ctrl |= YT921X_SERDES_LINK; 2309 res = yt921x_reg_update_bits(priv, YT921X_SERDESn(port), 2310 mask, ctrl); 2311 if (res) 2312 return res; 2313 2314 mask = YT921X_XMII_LINK; 2315 res = yt921x_reg_set_bits(priv, YT921X_XMIIn(port), mask); 2316 if (res) 2317 return res; 2318 2319 switch (speed) { 2320 case SPEED_10: 2321 ctrl = YT921X_MDIO_POLLING_SPEED_10; 2322 break; 2323 case SPEED_100: 2324 ctrl = YT921X_MDIO_POLLING_SPEED_100; 2325 break; 2326 case SPEED_1000: 2327 ctrl = YT921X_MDIO_POLLING_SPEED_1000; 2328 break; 2329 case SPEED_2500: 2330 ctrl = YT921X_MDIO_POLLING_SPEED_2500; 2331 break; 2332 case SPEED_10000: 2333 ctrl = YT921X_MDIO_POLLING_SPEED_10000; 2334 break; 2335 default: 2336 return -EINVAL; 2337 } 2338 if (duplex == DUPLEX_FULL) 2339 ctrl |= YT921X_MDIO_POLLING_DUPLEX_FULL; 2340 ctrl |= YT921X_MDIO_POLLING_LINK; 2341 res = yt921x_reg_write(priv, YT921X_MDIO_POLLINGn(port), ctrl); 2342 if (res) 2343 return res; 2344 } 2345 2346 return 0; 2347} 2348 2349static int 2350yt921x_port_config(struct yt921x_priv *priv, int port, unsigned int mode, 2351 phy_interface_t interface) 2352{ 2353 struct device *dev = to_device(priv); 2354 u32 mask; 2355 u32 ctrl; 2356 int res; 2357 2358 if (!yt921x_port_is_external(port)) { 2359 if (interface != PHY_INTERFACE_MODE_INTERNAL) { 2360 dev_err(dev, "Wrong mode %d on port %d\n", 2361 interface, port); 2362 return -EINVAL; 2363 } 2364 return 0; 2365 } 2366 2367 switch (interface) { 2368 /* SERDES */ 2369 case PHY_INTERFACE_MODE_SGMII: 2370 case PHY_INTERFACE_MODE_100BASEX: 2371 case PHY_INTERFACE_MODE_1000BASEX: 2372 case PHY_INTERFACE_MODE_2500BASEX: 2373 mask = YT921X_SERDES_CTRL_PORTn(port); 2374 res = yt921x_reg_set_bits(priv, YT921X_SERDES_CTRL, mask); 2375 if (res) 2376 return res; 2377 2378 mask = YT921X_XMII_CTRL_PORTn(port); 2379 res = yt921x_reg_clear_bits(priv, YT921X_XMII_CTRL, mask); 2380 if (res) 2381 return res; 2382 2383 mask = YT921X_SERDES_MODE_M; 2384 switch (interface) { 2385 case PHY_INTERFACE_MODE_SGMII: 2386 ctrl = YT921X_SERDES_MODE_SGMII; 2387 break; 2388 case PHY_INTERFACE_MODE_100BASEX: 2389 ctrl = YT921X_SERDES_MODE_100BASEX; 2390 break; 2391 case PHY_INTERFACE_MODE_1000BASEX: 2392 ctrl = YT921X_SERDES_MODE_1000BASEX; 2393 break; 2394 case PHY_INTERFACE_MODE_2500BASEX: 2395 ctrl = YT921X_SERDES_MODE_2500BASEX; 2396 break; 2397 default: 2398 return -EINVAL; 2399 } 2400 res = yt921x_reg_update_bits(priv, YT921X_SERDESn(port), 2401 mask, ctrl); 2402 if (res) 2403 return res; 2404 2405 break; 2406 /* add XMII support here */ 2407 default: 2408 return -EINVAL; 2409 } 2410 2411 return 0; 2412} 2413 2414static void 2415yt921x_phylink_mac_link_down(struct phylink_config *config, unsigned int mode, 2416 phy_interface_t interface) 2417{ 2418 struct dsa_port *dp = dsa_phylink_to_port(config); 2419 struct yt921x_priv *priv = to_yt921x_priv(dp->ds); 2420 int port = dp->index; 2421 int res; 2422 2423 /* No need to sync; port control block is hold until device remove */ 2424 cancel_delayed_work(&priv->ports[port].mib_read); 2425 2426 mutex_lock(&priv->reg_lock); 2427 res = yt921x_port_down(priv, port); 2428 mutex_unlock(&priv->reg_lock); 2429 2430 if (res) 2431 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "bring down", 2432 port, res); 2433} 2434 2435static void 2436yt921x_phylink_mac_link_up(struct phylink_config *config, 2437 struct phy_device *phydev, unsigned int mode, 2438 phy_interface_t interface, int speed, int duplex, 2439 bool tx_pause, bool rx_pause) 2440{ 2441 struct dsa_port *dp = dsa_phylink_to_port(config); 2442 struct yt921x_priv *priv = to_yt921x_priv(dp->ds); 2443 int port = dp->index; 2444 int res; 2445 2446 mutex_lock(&priv->reg_lock); 2447 res = yt921x_port_up(priv, port, mode, interface, speed, duplex, 2448 tx_pause, rx_pause); 2449 mutex_unlock(&priv->reg_lock); 2450 2451 if (res) 2452 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "bring up", 2453 port, res); 2454 2455 schedule_delayed_work(&priv->ports[port].mib_read, 0); 2456} 2457 2458static void 2459yt921x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2460 const struct phylink_link_state *state) 2461{ 2462 struct dsa_port *dp = dsa_phylink_to_port(config); 2463 struct yt921x_priv *priv = to_yt921x_priv(dp->ds); 2464 int port = dp->index; 2465 int res; 2466 2467 mutex_lock(&priv->reg_lock); 2468 res = yt921x_port_config(priv, port, mode, state->interface); 2469 mutex_unlock(&priv->reg_lock); 2470 2471 if (res) 2472 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "config", 2473 port, res); 2474} 2475 2476static void 2477yt921x_dsa_phylink_get_caps(struct dsa_switch *ds, int port, 2478 struct phylink_config *config) 2479{ 2480 struct yt921x_priv *priv = to_yt921x_priv(ds); 2481 const struct yt921x_info *info = priv->info; 2482 2483 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2484 MAC_10 | MAC_100 | MAC_1000; 2485 2486 if (info->internal_mask & BIT(port)) { 2487 /* Port 10 for MCU should probably go here too. But since that 2488 * is untested yet, turn it down for the moment by letting it 2489 * fall to the default branch. 2490 */ 2491 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2492 config->supported_interfaces); 2493 } else if (info->external_mask & BIT(port)) { 2494 /* TODO: external ports may support SERDES only, XMII only, or 2495 * SERDES + XMII depending on the chip. However, we can't get 2496 * the accurate config table due to lack of document, thus 2497 * we simply declare SERDES + XMII and rely on the correctness 2498 * of devicetree for now. 2499 */ 2500 2501 /* SERDES */ 2502 __set_bit(PHY_INTERFACE_MODE_SGMII, 2503 config->supported_interfaces); 2504 /* REVSGMII (SGMII in PHY role) should go here, once 2505 * PHY_INTERFACE_MODE_REVSGMII is introduced. 2506 */ 2507 __set_bit(PHY_INTERFACE_MODE_100BASEX, 2508 config->supported_interfaces); 2509 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2510 config->supported_interfaces); 2511 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2512 config->supported_interfaces); 2513 config->mac_capabilities |= MAC_2500FD; 2514 2515 /* XMII */ 2516 2517 /* Not tested. To add support for XMII: 2518 * - Add proper interface modes below 2519 * - Handle them in yt921x_port_config() 2520 */ 2521 } 2522 /* no such port: empty supported_interfaces causes phylink to turn it 2523 * down 2524 */ 2525} 2526 2527static int yt921x_port_setup(struct yt921x_priv *priv, int port) 2528{ 2529 struct dsa_switch *ds = &priv->ds; 2530 u32 ctrl; 2531 int res; 2532 2533 res = yt921x_userport_standalone(priv, port); 2534 if (res) 2535 return res; 2536 2537 if (dsa_is_cpu_port(ds, port)) { 2538 /* Egress of CPU port is supposed to be completely controlled 2539 * via tagging, so set to oneway isolated (drop all packets 2540 * without tag). 2541 */ 2542 ctrl = ~(u32)0; 2543 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), 2544 ctrl); 2545 if (res) 2546 return res; 2547 2548 /* To simplify FDB "isolation" simulation, we also disable 2549 * learning on the CPU port, and let software identify packets 2550 * towarding CPU (either trapped or a static FDB entry is 2551 * matched, no matter which bridge that entry is for), which is 2552 * already done by yt921x_userport_standalone(). As a result, 2553 * VLAN-awareness becomes unrelated on the CPU port (set to 2554 * VLAN-unaware by the way). 2555 */ 2556 } 2557 2558 return 0; 2559} 2560 2561static enum dsa_tag_protocol 2562yt921x_dsa_get_tag_protocol(struct dsa_switch *ds, int port, 2563 enum dsa_tag_protocol m) 2564{ 2565 return DSA_TAG_PROTO_YT921X; 2566} 2567 2568static int yt921x_dsa_port_setup(struct dsa_switch *ds, int port) 2569{ 2570 struct yt921x_priv *priv = to_yt921x_priv(ds); 2571 int res; 2572 2573 mutex_lock(&priv->reg_lock); 2574 res = yt921x_port_setup(priv, port); 2575 mutex_unlock(&priv->reg_lock); 2576 2577 return res; 2578} 2579 2580static int yt921x_edata_wait(struct yt921x_priv *priv, u32 *valp) 2581{ 2582 u32 val = YT921X_EDATA_DATA_IDLE; 2583 int res; 2584 2585 res = yt921x_reg_wait(priv, YT921X_EDATA_DATA, 2586 YT921X_EDATA_DATA_STATUS_M, &val); 2587 if (res) 2588 return res; 2589 2590 *valp = val; 2591 return 0; 2592} 2593 2594static int 2595yt921x_edata_read_cont(struct yt921x_priv *priv, u8 addr, u8 *valp) 2596{ 2597 u32 ctrl; 2598 u32 val; 2599 int res; 2600 2601 ctrl = YT921X_EDATA_CTRL_ADDR(addr) | YT921X_EDATA_CTRL_READ; 2602 res = yt921x_reg_write(priv, YT921X_EDATA_CTRL, ctrl); 2603 if (res) 2604 return res; 2605 res = yt921x_edata_wait(priv, &val); 2606 if (res) 2607 return res; 2608 2609 *valp = FIELD_GET(YT921X_EDATA_DATA_DATA_M, val); 2610 return 0; 2611} 2612 2613static int yt921x_edata_read(struct yt921x_priv *priv, u8 addr, u8 *valp) 2614{ 2615 u32 val; 2616 int res; 2617 2618 res = yt921x_edata_wait(priv, &val); 2619 if (res) 2620 return res; 2621 return yt921x_edata_read_cont(priv, addr, valp); 2622} 2623 2624static int yt921x_chip_detect(struct yt921x_priv *priv) 2625{ 2626 struct device *dev = to_device(priv); 2627 const struct yt921x_info *info; 2628 u8 extmode; 2629 u32 chipid; 2630 u32 major; 2631 u32 mode; 2632 int res; 2633 2634 res = yt921x_reg_read(priv, YT921X_CHIP_ID, &chipid); 2635 if (res) 2636 return res; 2637 2638 major = FIELD_GET(YT921X_CHIP_ID_MAJOR, chipid); 2639 2640 for (info = yt921x_infos; info->name; info++) 2641 if (info->major == major) 2642 break; 2643 if (!info->name) { 2644 dev_err(dev, "Unexpected chipid 0x%x\n", chipid); 2645 return -ENODEV; 2646 } 2647 2648 res = yt921x_reg_read(priv, YT921X_CHIP_MODE, &mode); 2649 if (res) 2650 return res; 2651 res = yt921x_edata_read(priv, YT921X_EDATA_EXTMODE, &extmode); 2652 if (res) 2653 return res; 2654 2655 for (; info->name; info++) 2656 if (info->major == major && info->mode == mode && 2657 info->extmode == extmode) 2658 break; 2659 if (!info->name) { 2660 dev_err(dev, 2661 "Unsupported chipid 0x%x with chipmode 0x%x 0x%x\n", 2662 chipid, mode, extmode); 2663 return -ENODEV; 2664 } 2665 2666 /* Print chipid here since we are interested in lower 16 bits */ 2667 dev_info(dev, 2668 "Motorcomm %s ethernet switch, chipid: 0x%x, chipmode: 0x%x 0x%x\n", 2669 info->name, chipid, mode, extmode); 2670 2671 priv->info = info; 2672 return 0; 2673} 2674 2675static int yt921x_chip_reset(struct yt921x_priv *priv) 2676{ 2677 struct device *dev = to_device(priv); 2678 u16 eth_p_tag; 2679 u32 val; 2680 int res; 2681 2682 res = yt921x_chip_detect(priv); 2683 if (res) 2684 return res; 2685 2686 /* Reset */ 2687 res = yt921x_reg_write(priv, YT921X_RST, YT921X_RST_HW); 2688 if (res) 2689 return res; 2690 2691 /* RST_HW is almost same as GPIO hard reset, so we need this delay. */ 2692 fsleep(YT921X_RST_DELAY_US); 2693 2694 val = 0; 2695 res = yt921x_reg_wait(priv, YT921X_RST, ~0, &val); 2696 if (res) 2697 return res; 2698 2699 /* Check for tag EtherType; do it after reset in case you messed it up 2700 * before. 2701 */ 2702 res = yt921x_reg_read(priv, YT921X_CPU_TAG_TPID, &val); 2703 if (res) 2704 return res; 2705 eth_p_tag = FIELD_GET(YT921X_CPU_TAG_TPID_TPID_M, val); 2706 if (eth_p_tag != ETH_P_YT921X) { 2707 dev_err(dev, "Tag type 0x%x != 0x%x\n", eth_p_tag, 2708 ETH_P_YT921X); 2709 /* Despite being possible, we choose not to set CPU_TAG_TPID, 2710 * since there is no way it can be different unless you have the 2711 * wrong chip. 2712 */ 2713 return -EINVAL; 2714 } 2715 2716 return 0; 2717} 2718 2719static int yt921x_chip_setup(struct yt921x_priv *priv) 2720{ 2721 struct dsa_switch *ds = &priv->ds; 2722 unsigned long cpu_ports_mask; 2723 u64 ctrl64; 2724 u32 ctrl; 2725 int port; 2726 int res; 2727 2728 /* Enable DSA */ 2729 priv->cpu_ports_mask = dsa_cpu_ports(ds); 2730 2731 ctrl = YT921X_EXT_CPU_PORT_TAG_EN | YT921X_EXT_CPU_PORT_PORT_EN | 2732 YT921X_EXT_CPU_PORT_PORT(__ffs(priv->cpu_ports_mask)); 2733 res = yt921x_reg_write(priv, YT921X_EXT_CPU_PORT, ctrl); 2734 if (res) 2735 return res; 2736 2737 /* Enable and clear MIB */ 2738 res = yt921x_reg_set_bits(priv, YT921X_FUNC, YT921X_FUNC_MIB); 2739 if (res) 2740 return res; 2741 2742 ctrl = YT921X_MIB_CTRL_CLEAN | YT921X_MIB_CTRL_ALL_PORT; 2743 res = yt921x_reg_write(priv, YT921X_MIB_CTRL, ctrl); 2744 if (res) 2745 return res; 2746 2747 /* Setup software switch */ 2748 ctrl = YT921X_CPU_COPY_TO_EXT_CPU; 2749 res = yt921x_reg_write(priv, YT921X_CPU_COPY, ctrl); 2750 if (res) 2751 return res; 2752 2753 ctrl = GENMASK(10, 0); 2754 res = yt921x_reg_write(priv, YT921X_FILTER_UNK_UCAST, ctrl); 2755 if (res) 2756 return res; 2757 res = yt921x_reg_write(priv, YT921X_FILTER_UNK_MCAST, ctrl); 2758 if (res) 2759 return res; 2760 2761 /* YT921x does not support native DSA port bridging, so we use port 2762 * isolation to emulate it. However, be especially careful that port 2763 * isolation takes _after_ FDB lookups, i.e. if an FDB entry (from 2764 * another bridge) is matched and the destination port (in another 2765 * bridge) is blocked, the packet will be dropped instead of flooding to 2766 * the "bridged" ports, thus we need to trap and handle those packets by 2767 * software. 2768 * 2769 * If there is no more than one bridge, we might be able to drop them 2770 * directly given some conditions are met, but we trap them in all cases 2771 * for now. 2772 */ 2773 ctrl = 0; 2774 for (int i = 0; i < YT921X_PORT_NUM; i++) 2775 ctrl |= YT921X_ACT_UNK_ACTn_TRAP(i); 2776 /* Except for CPU ports, if any packets are sent via CPU ports without 2777 * tag, they should be dropped. 2778 */ 2779 cpu_ports_mask = priv->cpu_ports_mask; 2780 for_each_set_bit(port, &cpu_ports_mask, YT921X_PORT_NUM) { 2781 ctrl &= ~YT921X_ACT_UNK_ACTn_M(port); 2782 ctrl |= YT921X_ACT_UNK_ACTn_DROP(port); 2783 } 2784 res = yt921x_reg_write(priv, YT921X_ACT_UNK_UCAST, ctrl); 2785 if (res) 2786 return res; 2787 res = yt921x_reg_write(priv, YT921X_ACT_UNK_MCAST, ctrl); 2788 if (res) 2789 return res; 2790 2791 /* Tagged VID 0 should be treated as untagged, which confuses the 2792 * hardware a lot 2793 */ 2794 ctrl64 = YT921X_VLAN_CTRL_LEARN_DIS | YT921X_VLAN_CTRL_PORTS_M; 2795 res = yt921x_reg64_write(priv, YT921X_VLANn_CTRL(0), ctrl64); 2796 if (res) 2797 return res; 2798 2799 /* Miscellaneous */ 2800 res = yt921x_reg_set_bits(priv, YT921X_SENSOR, YT921X_SENSOR_TEMP); 2801 if (res) 2802 return res; 2803 2804 return 0; 2805} 2806 2807static int yt921x_dsa_setup(struct dsa_switch *ds) 2808{ 2809 struct yt921x_priv *priv = to_yt921x_priv(ds); 2810 struct device *dev = to_device(priv); 2811 struct device_node *np = dev->of_node; 2812 struct device_node *child; 2813 int res; 2814 2815 mutex_lock(&priv->reg_lock); 2816 res = yt921x_chip_reset(priv); 2817 mutex_unlock(&priv->reg_lock); 2818 2819 if (res) 2820 return res; 2821 2822 /* Register the internal mdio bus. Nodes for internal ports should have 2823 * proper phy-handle pointing to their PHYs. Not enabling the internal 2824 * bus is possible, though pretty wired, if internal ports are not used. 2825 */ 2826 child = of_get_child_by_name(np, "mdio"); 2827 if (child) { 2828 res = yt921x_mbus_int_init(priv, child); 2829 of_node_put(child); 2830 if (res) 2831 return res; 2832 } 2833 2834 /* External mdio bus is optional */ 2835 child = of_get_child_by_name(np, "mdio-external"); 2836 if (child) { 2837 res = yt921x_mbus_ext_init(priv, child); 2838 of_node_put(child); 2839 if (res) 2840 return res; 2841 2842 dev_err(dev, "Untested external mdio bus\n"); 2843 return -ENODEV; 2844 } 2845 2846 mutex_lock(&priv->reg_lock); 2847 res = yt921x_chip_setup(priv); 2848 mutex_unlock(&priv->reg_lock); 2849 2850 if (res) 2851 return res; 2852 2853 return 0; 2854} 2855 2856static const struct phylink_mac_ops yt921x_phylink_mac_ops = { 2857 .mac_link_down = yt921x_phylink_mac_link_down, 2858 .mac_link_up = yt921x_phylink_mac_link_up, 2859 .mac_config = yt921x_phylink_mac_config, 2860}; 2861 2862static const struct dsa_switch_ops yt921x_dsa_switch_ops = { 2863 /* mib */ 2864 .get_strings = yt921x_dsa_get_strings, 2865 .get_ethtool_stats = yt921x_dsa_get_ethtool_stats, 2866 .get_sset_count = yt921x_dsa_get_sset_count, 2867 .get_eth_mac_stats = yt921x_dsa_get_eth_mac_stats, 2868 .get_eth_ctrl_stats = yt921x_dsa_get_eth_ctrl_stats, 2869 .get_rmon_stats = yt921x_dsa_get_rmon_stats, 2870 .get_stats64 = yt921x_dsa_get_stats64, 2871 .get_pause_stats = yt921x_dsa_get_pause_stats, 2872 /* eee */ 2873 .support_eee = dsa_supports_eee, 2874 .set_mac_eee = yt921x_dsa_set_mac_eee, 2875 /* mtu */ 2876 .port_change_mtu = yt921x_dsa_port_change_mtu, 2877 .port_max_mtu = yt921x_dsa_port_max_mtu, 2878 /* hsr */ 2879 .port_hsr_leave = dsa_port_simple_hsr_leave, 2880 .port_hsr_join = dsa_port_simple_hsr_join, 2881 /* mirror */ 2882 .port_mirror_del = yt921x_dsa_port_mirror_del, 2883 .port_mirror_add = yt921x_dsa_port_mirror_add, 2884 /* fdb */ 2885 .port_fdb_dump = yt921x_dsa_port_fdb_dump, 2886 .port_fast_age = yt921x_dsa_port_fast_age, 2887 .set_ageing_time = yt921x_dsa_set_ageing_time, 2888 .port_fdb_del = yt921x_dsa_port_fdb_del, 2889 .port_fdb_add = yt921x_dsa_port_fdb_add, 2890 .port_mdb_del = yt921x_dsa_port_mdb_del, 2891 .port_mdb_add = yt921x_dsa_port_mdb_add, 2892 /* vlan */ 2893 .port_vlan_filtering = yt921x_dsa_port_vlan_filtering, 2894 .port_vlan_del = yt921x_dsa_port_vlan_del, 2895 .port_vlan_add = yt921x_dsa_port_vlan_add, 2896 /* bridge */ 2897 .port_pre_bridge_flags = yt921x_dsa_port_pre_bridge_flags, 2898 .port_bridge_flags = yt921x_dsa_port_bridge_flags, 2899 .port_bridge_leave = yt921x_dsa_port_bridge_leave, 2900 .port_bridge_join = yt921x_dsa_port_bridge_join, 2901 /* mst */ 2902 .port_mst_state_set = yt921x_dsa_port_mst_state_set, 2903 .vlan_msti_set = yt921x_dsa_vlan_msti_set, 2904 .port_stp_state_set = yt921x_dsa_port_stp_state_set, 2905 /* port */ 2906 .get_tag_protocol = yt921x_dsa_get_tag_protocol, 2907 .phylink_get_caps = yt921x_dsa_phylink_get_caps, 2908 .port_setup = yt921x_dsa_port_setup, 2909 /* chip */ 2910 .setup = yt921x_dsa_setup, 2911}; 2912 2913static void yt921x_mdio_shutdown(struct mdio_device *mdiodev) 2914{ 2915 struct yt921x_priv *priv = mdiodev_get_drvdata(mdiodev); 2916 2917 if (!priv) 2918 return; 2919 2920 dsa_switch_shutdown(&priv->ds); 2921} 2922 2923static void yt921x_mdio_remove(struct mdio_device *mdiodev) 2924{ 2925 struct yt921x_priv *priv = mdiodev_get_drvdata(mdiodev); 2926 2927 if (!priv) 2928 return; 2929 2930 for (size_t i = ARRAY_SIZE(priv->ports); i-- > 0; ) { 2931 struct yt921x_port *pp = &priv->ports[i]; 2932 2933 disable_delayed_work_sync(&pp->mib_read); 2934 } 2935 2936 dsa_unregister_switch(&priv->ds); 2937 2938 mutex_destroy(&priv->reg_lock); 2939} 2940 2941static int yt921x_mdio_probe(struct mdio_device *mdiodev) 2942{ 2943 struct device *dev = &mdiodev->dev; 2944 struct yt921x_reg_mdio *mdio; 2945 struct yt921x_priv *priv; 2946 struct dsa_switch *ds; 2947 2948 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2949 if (!priv) 2950 return -ENOMEM; 2951 2952 mdio = devm_kzalloc(dev, sizeof(*mdio), GFP_KERNEL); 2953 if (!mdio) 2954 return -ENOMEM; 2955 2956 mdio->bus = mdiodev->bus; 2957 mdio->addr = mdiodev->addr; 2958 mdio->switchid = 0; 2959 2960 mutex_init(&priv->reg_lock); 2961 2962 priv->reg_ops = &yt921x_reg_ops_mdio; 2963 priv->reg_ctx = mdio; 2964 2965 for (size_t i = 0; i < ARRAY_SIZE(priv->ports); i++) { 2966 struct yt921x_port *pp = &priv->ports[i]; 2967 2968 pp->index = i; 2969 INIT_DELAYED_WORK(&pp->mib_read, yt921x_poll_mib); 2970 } 2971 2972 ds = &priv->ds; 2973 ds->dev = dev; 2974 ds->assisted_learning_on_cpu_port = true; 2975 ds->priv = priv; 2976 ds->ops = &yt921x_dsa_switch_ops; 2977 ds->ageing_time_min = 1 * 5000; 2978 ds->ageing_time_max = U16_MAX * 5000; 2979 ds->phylink_mac_ops = &yt921x_phylink_mac_ops; 2980 ds->num_ports = YT921X_PORT_NUM; 2981 2982 mdiodev_set_drvdata(mdiodev, priv); 2983 2984 return dsa_register_switch(ds); 2985} 2986 2987static const struct of_device_id yt921x_of_match[] = { 2988 { .compatible = "motorcomm,yt9215" }, 2989 {} 2990}; 2991MODULE_DEVICE_TABLE(of, yt921x_of_match); 2992 2993static struct mdio_driver yt921x_mdio_driver = { 2994 .probe = yt921x_mdio_probe, 2995 .remove = yt921x_mdio_remove, 2996 .shutdown = yt921x_mdio_shutdown, 2997 .mdiodrv.driver = { 2998 .name = YT921X_NAME, 2999 .of_match_table = yt921x_of_match, 3000 }, 3001}; 3002 3003mdio_module_driver(yt921x_mdio_driver); 3004 3005MODULE_AUTHOR("David Yang <mmyangfl@gmail.com>"); 3006MODULE_DESCRIPTION("Driver for Motorcomm YT921x Switch"); 3007MODULE_LICENSE("GPL");
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