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sja1105_main.c
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linux-6.19.14/drivers/net/dsa/sja1105/sja1105_main.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8#include <linux/delay.h> 9#include <linux/module.h> 10#include <linux/printk.h> 11#include <linux/spi/spi.h> 12#include <linux/errno.h> 13#include <linux/gpio/consumer.h> 14#include <linux/phylink.h> 15#include <linux/of.h> 16#include <linux/of_net.h> 17#include <linux/of_mdio.h> 18#include <linux/netdev_features.h> 19#include <linux/netdevice.h> 20#include <linux/if_bridge.h> 21#include <linux/if_ether.h> 22#include <linux/dsa/8021q.h> 23#include <linux/units.h> 24 25#include "sja1105.h" 26#include "sja1105_tas.h" 27 28#define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull 29 30/* Configure the optional reset pin and bring up switch */ 31static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len, 32 unsigned int startup_delay) 33{ 34 struct gpio_desc *gpio; 35 36 gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 37 if (IS_ERR(gpio)) 38 return PTR_ERR(gpio); 39 40 if (!gpio) 41 return 0; 42 43 gpiod_set_value_cansleep(gpio, 1); 44 /* Wait for minimum reset pulse length */ 45 msleep(pulse_len); 46 gpiod_set_value_cansleep(gpio, 0); 47 /* Wait until chip is ready after reset */ 48 msleep(startup_delay); 49 50 gpiod_put(gpio); 51 52 return 0; 53} 54 55static void 56sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd, 57 int from, int to, bool allow) 58{ 59 if (allow) 60 l2_fwd[from].reach_port |= BIT(to); 61 else 62 l2_fwd[from].reach_port &= ~BIT(to); 63} 64 65static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd, 66 int from, int to) 67{ 68 return !!(l2_fwd[from].reach_port & BIT(to)); 69} 70 71static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid) 72{ 73 struct sja1105_vlan_lookup_entry *vlan; 74 int count, i; 75 76 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; 77 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; 78 79 for (i = 0; i < count; i++) 80 if (vlan[i].vlanid == vid) 81 return i; 82 83 /* Return an invalid entry index if not found */ 84 return -1; 85} 86 87static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop) 88{ 89 struct sja1105_private *priv = ds->priv; 90 struct sja1105_mac_config_entry *mac; 91 92 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 93 94 if (mac[port].drpuntag == drop) 95 return 0; 96 97 mac[port].drpuntag = drop; 98 99 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 100 &mac[port], true); 101} 102 103static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid) 104{ 105 struct sja1105_mac_config_entry *mac; 106 107 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 108 109 if (mac[port].vlanid == pvid) 110 return 0; 111 112 mac[port].vlanid = pvid; 113 114 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 115 &mac[port], true); 116} 117 118static int sja1105_commit_pvid(struct dsa_switch *ds, int port) 119{ 120 struct dsa_port *dp = dsa_to_port(ds, port); 121 struct net_device *br = dsa_port_bridge_dev_get(dp); 122 struct sja1105_private *priv = ds->priv; 123 struct sja1105_vlan_lookup_entry *vlan; 124 bool drop_untagged = false; 125 int match, rc; 126 u16 pvid; 127 128 if (br && br_vlan_enabled(br)) 129 pvid = priv->bridge_pvid[port]; 130 else 131 pvid = priv->tag_8021q_pvid[port]; 132 133 rc = sja1105_pvid_apply(priv, port, pvid); 134 if (rc) 135 return rc; 136 137 /* Only force dropping of untagged packets when the port is under a 138 * VLAN-aware bridge. When the tag_8021q pvid is used, we are 139 * deliberately removing the RX VLAN from the port's VMEMB_PORT list, 140 * to prevent DSA tag spoofing from the link partner. Untagged packets 141 * are the only ones that should be received with tag_8021q, so 142 * definitely don't drop them. 143 */ 144 if (pvid == priv->bridge_pvid[port]) { 145 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; 146 147 match = sja1105_is_vlan_configured(priv, pvid); 148 149 if (match < 0 || !(vlan[match].vmemb_port & BIT(port))) 150 drop_untagged = true; 151 } 152 153 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 154 drop_untagged = true; 155 156 return sja1105_drop_untagged(ds, port, drop_untagged); 157} 158 159static int sja1105_init_mac_settings(struct sja1105_private *priv) 160{ 161 struct sja1105_mac_config_entry default_mac = { 162 /* Enable all 8 priority queues on egress. 163 * Every queue i holds top[i] - base[i] frames. 164 * Sum of top[i] - base[i] is 511 (max hardware limit). 165 */ 166 .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF}, 167 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0}, 168 .enabled = {true, true, true, true, true, true, true, true}, 169 /* Keep standard IFG of 12 bytes on egress. */ 170 .ifg = 0, 171 /* Always put the MAC speed in automatic mode, where it can be 172 * adjusted at runtime by PHYLINK. 173 */ 174 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO], 175 /* No static correction for 1-step 1588 events */ 176 .tp_delin = 0, 177 .tp_delout = 0, 178 /* Disable aging for critical TTEthernet traffic */ 179 .maxage = 0xFF, 180 /* Internal VLAN (pvid) to apply to untagged ingress */ 181 .vlanprio = 0, 182 .vlanid = 1, 183 .ing_mirr = false, 184 .egr_mirr = false, 185 /* Don't drop traffic with other EtherType than ETH_P_IP */ 186 .drpnona664 = false, 187 /* Don't drop double-tagged traffic */ 188 .drpdtag = false, 189 /* Don't drop untagged traffic */ 190 .drpuntag = false, 191 /* Don't retag 802.1p (VID 0) traffic with the pvid */ 192 .retag = false, 193 /* Disable learning and I/O on user ports by default - 194 * STP will enable it. 195 */ 196 .dyn_learn = false, 197 .egress = false, 198 .ingress = false, 199 }; 200 struct sja1105_mac_config_entry *mac; 201 struct dsa_switch *ds = priv->ds; 202 struct sja1105_table *table; 203 struct dsa_port *dp; 204 205 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG]; 206 207 /* Discard previous MAC Configuration Table */ 208 if (table->entry_count) { 209 kfree(table->entries); 210 table->entry_count = 0; 211 } 212 213 table->entries = kcalloc(table->ops->max_entry_count, 214 table->ops->unpacked_entry_size, GFP_KERNEL); 215 if (!table->entries) 216 return -ENOMEM; 217 218 table->entry_count = table->ops->max_entry_count; 219 220 mac = table->entries; 221 222 list_for_each_entry(dp, &ds->dst->ports, list) { 223 if (dp->ds != ds) 224 continue; 225 226 mac[dp->index] = default_mac; 227 228 /* Let sja1105_bridge_stp_state_set() keep address learning 229 * enabled for the DSA ports. CPU ports use software-assisted 230 * learning to ensure that only FDB entries belonging to the 231 * bridge are learned, and that they are learned towards all 232 * CPU ports in a cross-chip topology if multiple CPU ports 233 * exist. 234 */ 235 if (dsa_port_is_dsa(dp)) 236 dp->learning = true; 237 238 /* Disallow untagged packets from being received on the 239 * CPU and DSA ports. 240 */ 241 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp)) 242 mac[dp->index].drpuntag = true; 243 } 244 245 return 0; 246} 247 248static int sja1105_init_mii_settings(struct sja1105_private *priv) 249{ 250 struct device *dev = &priv->spidev->dev; 251 struct sja1105_xmii_params_entry *mii; 252 struct dsa_switch *ds = priv->ds; 253 struct sja1105_table *table; 254 int i; 255 256 table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS]; 257 258 /* Discard previous xMII Mode Parameters Table */ 259 if (table->entry_count) { 260 kfree(table->entries); 261 table->entry_count = 0; 262 } 263 264 table->entries = kcalloc(table->ops->max_entry_count, 265 table->ops->unpacked_entry_size, GFP_KERNEL); 266 if (!table->entries) 267 return -ENOMEM; 268 269 /* Override table based on PHYLINK DT bindings */ 270 table->entry_count = table->ops->max_entry_count; 271 272 mii = table->entries; 273 274 for (i = 0; i < ds->num_ports; i++) { 275 sja1105_mii_role_t role = XMII_MAC; 276 277 if (dsa_is_unused_port(priv->ds, i)) 278 continue; 279 280 switch (priv->phy_mode[i]) { 281 case PHY_INTERFACE_MODE_INTERNAL: 282 if (priv->info->internal_phy[i] == SJA1105_NO_PHY) 283 goto unsupported; 284 285 mii->xmii_mode[i] = XMII_MODE_MII; 286 if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX) 287 mii->special[i] = true; 288 289 break; 290 case PHY_INTERFACE_MODE_REVMII: 291 role = XMII_PHY; 292 fallthrough; 293 case PHY_INTERFACE_MODE_MII: 294 if (!priv->info->supports_mii[i]) 295 goto unsupported; 296 297 mii->xmii_mode[i] = XMII_MODE_MII; 298 break; 299 case PHY_INTERFACE_MODE_REVRMII: 300 role = XMII_PHY; 301 fallthrough; 302 case PHY_INTERFACE_MODE_RMII: 303 if (!priv->info->supports_rmii[i]) 304 goto unsupported; 305 306 mii->xmii_mode[i] = XMII_MODE_RMII; 307 break; 308 case PHY_INTERFACE_MODE_RGMII: 309 case PHY_INTERFACE_MODE_RGMII_ID: 310 case PHY_INTERFACE_MODE_RGMII_RXID: 311 case PHY_INTERFACE_MODE_RGMII_TXID: 312 if (!priv->info->supports_rgmii[i]) 313 goto unsupported; 314 315 mii->xmii_mode[i] = XMII_MODE_RGMII; 316 break; 317 case PHY_INTERFACE_MODE_SGMII: 318 if (!priv->info->supports_sgmii[i]) 319 goto unsupported; 320 321 mii->xmii_mode[i] = XMII_MODE_SGMII; 322 mii->special[i] = true; 323 break; 324 case PHY_INTERFACE_MODE_2500BASEX: 325 if (!priv->info->supports_2500basex[i]) 326 goto unsupported; 327 328 mii->xmii_mode[i] = XMII_MODE_SGMII; 329 mii->special[i] = true; 330 break; 331unsupported: 332 default: 333 dev_err(dev, "Unsupported PHY mode %s on port %d!\n", 334 phy_modes(priv->phy_mode[i]), i); 335 return -EINVAL; 336 } 337 338 mii->phy_mac[i] = role; 339 } 340 return 0; 341} 342 343static int sja1105_init_static_fdb(struct sja1105_private *priv) 344{ 345 struct sja1105_l2_lookup_entry *l2_lookup; 346 struct sja1105_table *table; 347 int port; 348 349 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; 350 351 /* We only populate the FDB table through dynamic L2 Address Lookup 352 * entries, except for a special entry at the end which is a catch-all 353 * for unknown multicast and will be used to control flooding domain. 354 */ 355 if (table->entry_count) { 356 kfree(table->entries); 357 table->entry_count = 0; 358 } 359 360 if (!priv->info->can_limit_mcast_flood) 361 return 0; 362 363 table->entries = kcalloc(1, table->ops->unpacked_entry_size, 364 GFP_KERNEL); 365 if (!table->entries) 366 return -ENOMEM; 367 368 table->entry_count = 1; 369 l2_lookup = table->entries; 370 371 /* All L2 multicast addresses have an odd first octet */ 372 l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST; 373 l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST; 374 l2_lookup[0].lockeds = true; 375 l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1; 376 377 /* Flood multicast to every port by default */ 378 for (port = 0; port < priv->ds->num_ports; port++) 379 if (!dsa_is_unused_port(priv->ds, port)) 380 l2_lookup[0].destports |= BIT(port); 381 382 return 0; 383} 384 385static int sja1105_init_l2_lookup_params(struct sja1105_private *priv) 386{ 387 struct sja1105_l2_lookup_params_entry default_l2_lookup_params = { 388 /* Learned FDB entries are forgotten after 300 seconds */ 389 .maxage = SJA1105_AGEING_TIME_MS(300000), 390 /* All entries within a FDB bin are available for learning */ 391 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE, 392 /* And the P/Q/R/S equivalent setting: */ 393 .start_dynspc = 0, 394 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */ 395 .poly = 0x97, 396 /* Always use Independent VLAN Learning (IVL) */ 397 .shared_learn = false, 398 /* Don't discard management traffic based on ENFPORT - 399 * we don't perform SMAC port enforcement anyway, so 400 * what we are setting here doesn't matter. 401 */ 402 .no_enf_hostprt = false, 403 /* Don't learn SMAC for mac_fltres1 and mac_fltres0. 404 * Maybe correlate with no_linklocal_learn from bridge driver? 405 */ 406 .no_mgmt_learn = true, 407 /* P/Q/R/S only */ 408 .use_static = true, 409 /* Dynamically learned FDB entries can overwrite other (older) 410 * dynamic FDB entries 411 */ 412 .owr_dyn = true, 413 .drpnolearn = true, 414 }; 415 struct dsa_switch *ds = priv->ds; 416 int port, num_used_ports = 0; 417 struct sja1105_table *table; 418 u64 max_fdb_entries; 419 420 for (port = 0; port < ds->num_ports; port++) 421 if (!dsa_is_unused_port(ds, port)) 422 num_used_ports++; 423 424 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports; 425 426 for (port = 0; port < ds->num_ports; port++) { 427 if (dsa_is_unused_port(ds, port)) 428 continue; 429 430 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries; 431 } 432 433 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; 434 435 if (table->entry_count) { 436 kfree(table->entries); 437 table->entry_count = 0; 438 } 439 440 table->entries = kcalloc(table->ops->max_entry_count, 441 table->ops->unpacked_entry_size, GFP_KERNEL); 442 if (!table->entries) 443 return -ENOMEM; 444 445 table->entry_count = table->ops->max_entry_count; 446 447 /* This table only has a single entry */ 448 ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] = 449 default_l2_lookup_params; 450 451 return 0; 452} 453 454/* Set up a default VLAN for untagged traffic injected from the CPU 455 * using management routes (e.g. STP, PTP) as opposed to tag_8021q. 456 * All DT-defined ports are members of this VLAN, and there are no 457 * restrictions on forwarding (since the CPU selects the destination). 458 * Frames from this VLAN will always be transmitted as untagged, and 459 * neither the bridge nor the 8021q module cannot create this VLAN ID. 460 */ 461static int sja1105_init_static_vlan(struct sja1105_private *priv) 462{ 463 struct sja1105_table *table; 464 struct sja1105_vlan_lookup_entry pvid = { 465 .type_entry = SJA1110_VLAN_D_TAG, 466 .ving_mirr = 0, 467 .vegr_mirr = 0, 468 .vmemb_port = 0, 469 .vlan_bc = 0, 470 .tag_port = 0, 471 .vlanid = SJA1105_DEFAULT_VLAN, 472 }; 473 struct dsa_switch *ds = priv->ds; 474 int port; 475 476 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; 477 478 if (table->entry_count) { 479 kfree(table->entries); 480 table->entry_count = 0; 481 } 482 483 table->entries = kzalloc(table->ops->unpacked_entry_size, 484 GFP_KERNEL); 485 if (!table->entries) 486 return -ENOMEM; 487 488 table->entry_count = 1; 489 490 for (port = 0; port < ds->num_ports; port++) { 491 if (dsa_is_unused_port(ds, port)) 492 continue; 493 494 pvid.vmemb_port |= BIT(port); 495 pvid.vlan_bc |= BIT(port); 496 pvid.tag_port &= ~BIT(port); 497 498 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 499 priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN; 500 priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN; 501 } 502 } 503 504 ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid; 505 return 0; 506} 507 508static int sja1105_init_l2_forwarding(struct sja1105_private *priv) 509{ 510 struct sja1105_l2_forwarding_entry *l2fwd; 511 struct dsa_switch *ds = priv->ds; 512 struct dsa_switch_tree *dst; 513 struct sja1105_table *table; 514 struct dsa_link *dl; 515 int port, tc; 516 int from, to; 517 518 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING]; 519 520 if (table->entry_count) { 521 kfree(table->entries); 522 table->entry_count = 0; 523 } 524 525 table->entries = kcalloc(table->ops->max_entry_count, 526 table->ops->unpacked_entry_size, GFP_KERNEL); 527 if (!table->entries) 528 return -ENOMEM; 529 530 table->entry_count = table->ops->max_entry_count; 531 532 l2fwd = table->entries; 533 534 /* First 5 entries in the L2 Forwarding Table define the forwarding 535 * rules and the VLAN PCP to ingress queue mapping. 536 * Set up the ingress queue mapping first. 537 */ 538 for (port = 0; port < ds->num_ports; port++) { 539 if (dsa_is_unused_port(ds, port)) 540 continue; 541 542 for (tc = 0; tc < SJA1105_NUM_TC; tc++) 543 l2fwd[port].vlan_pmap[tc] = tc; 544 } 545 546 /* Then manage the forwarding domain for user ports. These can forward 547 * only to the always-on domain (CPU port and DSA links) 548 */ 549 for (from = 0; from < ds->num_ports; from++) { 550 if (!dsa_is_user_port(ds, from)) 551 continue; 552 553 for (to = 0; to < ds->num_ports; to++) { 554 if (!dsa_is_cpu_port(ds, to) && 555 !dsa_is_dsa_port(ds, to)) 556 continue; 557 558 l2fwd[from].bc_domain |= BIT(to); 559 l2fwd[from].fl_domain |= BIT(to); 560 561 sja1105_port_allow_traffic(l2fwd, from, to, true); 562 } 563 } 564 565 /* Then manage the forwarding domain for DSA links and CPU ports (the 566 * always-on domain). These can send packets to any enabled port except 567 * themselves. 568 */ 569 for (from = 0; from < ds->num_ports; from++) { 570 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from)) 571 continue; 572 573 for (to = 0; to < ds->num_ports; to++) { 574 if (dsa_is_unused_port(ds, to)) 575 continue; 576 577 if (from == to) 578 continue; 579 580 l2fwd[from].bc_domain |= BIT(to); 581 l2fwd[from].fl_domain |= BIT(to); 582 583 sja1105_port_allow_traffic(l2fwd, from, to, true); 584 } 585 } 586 587 /* In odd topologies ("H" connections where there is a DSA link to 588 * another switch which also has its own CPU port), TX packets can loop 589 * back into the system (they are flooded from CPU port 1 to the DSA 590 * link, and from there to CPU port 2). Prevent this from happening by 591 * cutting RX from DSA links towards our CPU port, if the remote switch 592 * has its own CPU port and therefore doesn't need ours for network 593 * stack termination. 594 */ 595 dst = ds->dst; 596 597 list_for_each_entry(dl, &dst->rtable, list) { 598 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp) 599 continue; 600 601 from = dl->dp->index; 602 to = dsa_upstream_port(ds, from); 603 604 dev_warn(ds->dev, 605 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n", 606 from, to); 607 608 sja1105_port_allow_traffic(l2fwd, from, to, false); 609 610 l2fwd[from].bc_domain &= ~BIT(to); 611 l2fwd[from].fl_domain &= ~BIT(to); 612 } 613 614 /* Finally, manage the egress flooding domain. All ports start up with 615 * flooding enabled, including the CPU port and DSA links. 616 */ 617 for (port = 0; port < ds->num_ports; port++) { 618 if (dsa_is_unused_port(ds, port)) 619 continue; 620 621 priv->ucast_egress_floods |= BIT(port); 622 priv->bcast_egress_floods |= BIT(port); 623 } 624 625 /* Next 8 entries define VLAN PCP mapping from ingress to egress. 626 * Create a one-to-one mapping. 627 */ 628 for (tc = 0; tc < SJA1105_NUM_TC; tc++) { 629 for (port = 0; port < ds->num_ports; port++) { 630 if (dsa_is_unused_port(ds, port)) 631 continue; 632 633 l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc; 634 } 635 636 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true; 637 } 638 639 return 0; 640} 641 642static int sja1110_init_pcp_remapping(struct sja1105_private *priv) 643{ 644 struct sja1110_pcp_remapping_entry *pcp_remap; 645 struct dsa_switch *ds = priv->ds; 646 struct sja1105_table *table; 647 int port, tc; 648 649 table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING]; 650 651 /* Nothing to do for SJA1105 */ 652 if (!table->ops->max_entry_count) 653 return 0; 654 655 if (table->entry_count) { 656 kfree(table->entries); 657 table->entry_count = 0; 658 } 659 660 table->entries = kcalloc(table->ops->max_entry_count, 661 table->ops->unpacked_entry_size, GFP_KERNEL); 662 if (!table->entries) 663 return -ENOMEM; 664 665 table->entry_count = table->ops->max_entry_count; 666 667 pcp_remap = table->entries; 668 669 /* Repeat the configuration done for vlan_pmap */ 670 for (port = 0; port < ds->num_ports; port++) { 671 if (dsa_is_unused_port(ds, port)) 672 continue; 673 674 for (tc = 0; tc < SJA1105_NUM_TC; tc++) 675 pcp_remap[port].egrpcp[tc] = tc; 676 } 677 678 return 0; 679} 680 681static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv) 682{ 683 struct sja1105_l2_forwarding_params_entry *l2fwd_params; 684 struct sja1105_table *table; 685 686 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; 687 688 if (table->entry_count) { 689 kfree(table->entries); 690 table->entry_count = 0; 691 } 692 693 table->entries = kcalloc(table->ops->max_entry_count, 694 table->ops->unpacked_entry_size, GFP_KERNEL); 695 if (!table->entries) 696 return -ENOMEM; 697 698 table->entry_count = table->ops->max_entry_count; 699 700 /* This table only has a single entry */ 701 l2fwd_params = table->entries; 702 703 /* Disallow dynamic reconfiguration of vlan_pmap */ 704 l2fwd_params->max_dynp = 0; 705 /* Use a single memory partition for all ingress queues */ 706 l2fwd_params->part_spc[0] = priv->info->max_frame_mem; 707 708 return 0; 709} 710 711void sja1105_frame_memory_partitioning(struct sja1105_private *priv) 712{ 713 struct sja1105_l2_forwarding_params_entry *l2_fwd_params; 714 struct sja1105_vl_forwarding_params_entry *vl_fwd_params; 715 struct sja1105_table *table; 716 717 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; 718 l2_fwd_params = table->entries; 719 l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY; 720 721 /* If we have any critical-traffic virtual links, we need to reserve 722 * some frame buffer memory for them. At the moment, hardcode the value 723 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks 724 * remaining for best-effort traffic. TODO: figure out a more flexible 725 * way to perform the frame buffer partitioning. 726 */ 727 if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count) 728 return; 729 730 table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS]; 731 vl_fwd_params = table->entries; 732 733 l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY; 734 vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY; 735} 736 737/* SJA1110 TDMACONFIGIDX values: 738 * 739 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports 740 * -----+----------------+---------------+---------------+--------------- 741 * 0 | 0, [5:10] | [1:2] | [3:4] | retag 742 * 1 |0, [5:10], retag| [1:2] | [3:4] | - 743 * 2 | 0, [5:10] | [1:3], retag | 4 | - 744 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | - 745 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | - 746 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | - 747 * 14 | 0, [5:10] | [1:4], retag | - | - 748 * 15 | [5:10] | [0:4], retag | - | - 749 */ 750static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv) 751{ 752 struct sja1105_general_params_entry *general_params; 753 struct sja1105_table *table; 754 bool port_1_is_base_tx; 755 bool port_3_is_2500; 756 bool port_4_is_2500; 757 u64 tdmaconfigidx; 758 759 if (priv->info->device_id != SJA1110_DEVICE_ID) 760 return; 761 762 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; 763 general_params = table->entries; 764 765 /* All the settings below are "as opposed to SGMII", which is the 766 * other pinmuxing option. 767 */ 768 port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL; 769 port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX; 770 port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX; 771 772 if (port_1_is_base_tx) 773 /* Retagging port will operate at 1 Gbps */ 774 tdmaconfigidx = 5; 775 else if (port_3_is_2500 && port_4_is_2500) 776 /* Retagging port will operate at 100 Mbps */ 777 tdmaconfigidx = 1; 778 else if (port_3_is_2500) 779 /* Retagging port will operate at 1 Gbps */ 780 tdmaconfigidx = 3; 781 else if (port_4_is_2500) 782 /* Retagging port will operate at 1 Gbps */ 783 tdmaconfigidx = 2; 784 else 785 /* Retagging port will operate at 1 Gbps */ 786 tdmaconfigidx = 14; 787 788 general_params->tdmaconfigidx = tdmaconfigidx; 789} 790 791static int sja1105_init_topology(struct sja1105_private *priv, 792 struct sja1105_general_params_entry *general_params) 793{ 794 struct dsa_switch *ds = priv->ds; 795 int port; 796 797 /* The host port is the destination for traffic matching mac_fltres1 798 * and mac_fltres0 on all ports except itself. Default to an invalid 799 * value. 800 */ 801 general_params->host_port = ds->num_ports; 802 803 /* Link-local traffic received on casc_port will be forwarded 804 * to host_port without embedding the source port and device ID 805 * info in the destination MAC address, and no RX timestamps will be 806 * taken either (presumably because it is a cascaded port and a 807 * downstream SJA switch already did that). 808 * To disable the feature, we need to do different things depending on 809 * switch generation. On SJA1105 we need to set an invalid port, while 810 * on SJA1110 which support multiple cascaded ports, this field is a 811 * bitmask so it must be left zero. 812 */ 813 if (!priv->info->multiple_cascade_ports) 814 general_params->casc_port = ds->num_ports; 815 816 for (port = 0; port < ds->num_ports; port++) { 817 bool is_upstream = dsa_is_upstream_port(ds, port); 818 bool is_dsa_link = dsa_is_dsa_port(ds, port); 819 820 /* Upstream ports can be dedicated CPU ports or 821 * upstream-facing DSA links 822 */ 823 if (is_upstream) { 824 if (general_params->host_port == ds->num_ports) { 825 general_params->host_port = port; 826 } else { 827 dev_err(ds->dev, 828 "Port %llu is already a host port, configuring %d as one too is not supported\n", 829 general_params->host_port, port); 830 return -EINVAL; 831 } 832 } 833 834 /* Cascade ports are downstream-facing DSA links */ 835 if (is_dsa_link && !is_upstream) { 836 if (priv->info->multiple_cascade_ports) { 837 general_params->casc_port |= BIT(port); 838 } else if (general_params->casc_port == ds->num_ports) { 839 general_params->casc_port = port; 840 } else { 841 dev_err(ds->dev, 842 "Port %llu is already a cascade port, configuring %d as one too is not supported\n", 843 general_params->casc_port, port); 844 return -EINVAL; 845 } 846 } 847 } 848 849 if (general_params->host_port == ds->num_ports) { 850 dev_err(ds->dev, "No host port configured\n"); 851 return -EINVAL; 852 } 853 854 return 0; 855} 856 857static int sja1105_init_general_params(struct sja1105_private *priv) 858{ 859 struct sja1105_general_params_entry default_general_params = { 860 /* Allow dynamic changing of the mirror port */ 861 .mirr_ptacu = true, 862 .switchid = priv->ds->index, 863 /* Priority queue for link-local management frames 864 * (both ingress to and egress from CPU - PTP, STP etc) 865 */ 866 .hostprio = 7, 867 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A, 868 .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK, 869 .incl_srcpt1 = true, 870 .send_meta1 = true, 871 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B, 872 .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK, 873 .incl_srcpt0 = true, 874 .send_meta0 = true, 875 /* Default to an invalid value */ 876 .mirr_port = priv->ds->num_ports, 877 /* No TTEthernet */ 878 .vllupformat = SJA1105_VL_FORMAT_PSFP, 879 .vlmarker = 0, 880 .vlmask = 0, 881 /* Only update correctionField for 1-step PTP (L2 transport) */ 882 .ignore2stf = 0, 883 /* Forcefully disable VLAN filtering by telling 884 * the switch that VLAN has a different EtherType. 885 */ 886 .tpid = ETH_P_SJA1105, 887 .tpid2 = ETH_P_SJA1105, 888 /* Enable the TTEthernet engine on SJA1110 */ 889 .tte_en = true, 890 /* Set up the EtherType for control packets on SJA1110 */ 891 .header_type = ETH_P_SJA1110, 892 }; 893 struct sja1105_general_params_entry *general_params; 894 struct sja1105_table *table; 895 int rc; 896 897 rc = sja1105_init_topology(priv, &default_general_params); 898 if (rc) 899 return rc; 900 901 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; 902 903 if (table->entry_count) { 904 kfree(table->entries); 905 table->entry_count = 0; 906 } 907 908 table->entries = kcalloc(table->ops->max_entry_count, 909 table->ops->unpacked_entry_size, GFP_KERNEL); 910 if (!table->entries) 911 return -ENOMEM; 912 913 table->entry_count = table->ops->max_entry_count; 914 915 general_params = table->entries; 916 917 /* This table only has a single entry */ 918 general_params[0] = default_general_params; 919 920 sja1110_select_tdmaconfigidx(priv); 921 922 return 0; 923} 924 925static int sja1105_init_avb_params(struct sja1105_private *priv) 926{ 927 struct sja1105_avb_params_entry *avb; 928 struct sja1105_table *table; 929 930 table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS]; 931 932 /* Discard previous AVB Parameters Table */ 933 if (table->entry_count) { 934 kfree(table->entries); 935 table->entry_count = 0; 936 } 937 938 table->entries = kcalloc(table->ops->max_entry_count, 939 table->ops->unpacked_entry_size, GFP_KERNEL); 940 if (!table->entries) 941 return -ENOMEM; 942 943 table->entry_count = table->ops->max_entry_count; 944 945 avb = table->entries; 946 947 /* Configure the MAC addresses for meta frames */ 948 avb->destmeta = SJA1105_META_DMAC; 949 avb->srcmeta = SJA1105_META_SMAC; 950 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by 951 * default. This is because there might be boards with a hardware 952 * layout where enabling the pin as output might cause an electrical 953 * clash. On E/T the pin is always an output, which the board designers 954 * probably already knew, so even if there are going to be electrical 955 * issues, there's nothing we can do. 956 */ 957 avb->cas_master = false; 958 959 return 0; 960} 961 962/* The L2 policing table is 2-stage. The table is looked up for each frame 963 * according to the ingress port, whether it was broadcast or not, and the 964 * classified traffic class (given by VLAN PCP). This portion of the lookup is 965 * fixed, and gives access to the SHARINDX, an indirection register pointing 966 * within the policing table itself, which is used to resolve the policer that 967 * will be used for this frame. 968 * 969 * Stage 1 Stage 2 970 * +------------+--------+ +---------------------------------+ 971 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU | 972 * +------------+--------+ +---------------------------------+ 973 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU | 974 * +------------+--------+ +---------------------------------+ 975 * ... | Policer 2: Rate, Burst, MTU | 976 * +------------+--------+ +---------------------------------+ 977 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU | 978 * +------------+--------+ +---------------------------------+ 979 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU | 980 * +------------+--------+ +---------------------------------+ 981 * ... | Policer 5: Rate, Burst, MTU | 982 * +------------+--------+ +---------------------------------+ 983 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU | 984 * +------------+--------+ +---------------------------------+ 985 * ... | Policer 7: Rate, Burst, MTU | 986 * +------------+--------+ +---------------------------------+ 987 * |Port 4 TC 7 |SHARINDX| ... 988 * +------------+--------+ 989 * |Port 0 BCAST|SHARINDX| ... 990 * +------------+--------+ 991 * |Port 1 BCAST|SHARINDX| ... 992 * +------------+--------+ 993 * ... ... 994 * +------------+--------+ +---------------------------------+ 995 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU | 996 * +------------+--------+ +---------------------------------+ 997 * 998 * In this driver, we shall use policers 0-4 as statically alocated port 999 * (matchall) policers. So we need to make the SHARINDX for all lookups 1000 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast 1001 * lookup) equal. 1002 * The remaining policers (40) shall be dynamically allocated for flower 1003 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff. 1004 */ 1005#define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000) 1006 1007static int sja1105_init_l2_policing(struct sja1105_private *priv) 1008{ 1009 struct sja1105_l2_policing_entry *policing; 1010 struct dsa_switch *ds = priv->ds; 1011 struct sja1105_table *table; 1012 int port, tc; 1013 1014 table = &priv->static_config.tables[BLK_IDX_L2_POLICING]; 1015 1016 /* Discard previous L2 Policing Table */ 1017 if (table->entry_count) { 1018 kfree(table->entries); 1019 table->entry_count = 0; 1020 } 1021 1022 table->entries = kcalloc(table->ops->max_entry_count, 1023 table->ops->unpacked_entry_size, GFP_KERNEL); 1024 if (!table->entries) 1025 return -ENOMEM; 1026 1027 table->entry_count = table->ops->max_entry_count; 1028 1029 policing = table->entries; 1030 1031 /* Setup shared indices for the matchall policers */ 1032 for (port = 0; port < ds->num_ports; port++) { 1033 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port; 1034 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port; 1035 1036 for (tc = 0; tc < SJA1105_NUM_TC; tc++) 1037 policing[port * SJA1105_NUM_TC + tc].sharindx = port; 1038 1039 policing[bcast].sharindx = port; 1040 /* Only SJA1110 has multicast policers */ 1041 if (mcast < table->ops->max_entry_count) 1042 policing[mcast].sharindx = port; 1043 } 1044 1045 /* Setup the matchall policer parameters */ 1046 for (port = 0; port < ds->num_ports; port++) { 1047 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1048 1049 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1050 mtu += VLAN_HLEN; 1051 1052 policing[port].smax = 65535; /* Burst size in bytes */ 1053 policing[port].rate = SJA1105_RATE_MBPS(1000); 1054 policing[port].maxlen = mtu; 1055 policing[port].partition = 0; 1056 } 1057 1058 return 0; 1059} 1060 1061static int sja1105_static_config_load(struct sja1105_private *priv) 1062{ 1063 int rc; 1064 1065 sja1105_static_config_free(&priv->static_config); 1066 rc = sja1105_static_config_init(&priv->static_config, 1067 priv->info->static_ops, 1068 priv->info->device_id); 1069 if (rc) 1070 return rc; 1071 1072 /* Build static configuration */ 1073 rc = sja1105_init_mac_settings(priv); 1074 if (rc < 0) 1075 return rc; 1076 rc = sja1105_init_mii_settings(priv); 1077 if (rc < 0) 1078 return rc; 1079 rc = sja1105_init_static_fdb(priv); 1080 if (rc < 0) 1081 return rc; 1082 rc = sja1105_init_static_vlan(priv); 1083 if (rc < 0) 1084 return rc; 1085 rc = sja1105_init_l2_lookup_params(priv); 1086 if (rc < 0) 1087 return rc; 1088 rc = sja1105_init_l2_forwarding(priv); 1089 if (rc < 0) 1090 return rc; 1091 rc = sja1105_init_l2_forwarding_params(priv); 1092 if (rc < 0) 1093 return rc; 1094 rc = sja1105_init_l2_policing(priv); 1095 if (rc < 0) 1096 return rc; 1097 rc = sja1105_init_general_params(priv); 1098 if (rc < 0) 1099 return rc; 1100 rc = sja1105_init_avb_params(priv); 1101 if (rc < 0) 1102 return rc; 1103 rc = sja1110_init_pcp_remapping(priv); 1104 if (rc < 0) 1105 return rc; 1106 1107 /* Send initial configuration to hardware via SPI */ 1108 return sja1105_static_config_upload(priv); 1109} 1110 1111/* This is the "new way" for a MAC driver to configure its RGMII delay lines, 1112 * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps" 1113 * properties. It has the advantage of working with fixed links and with PHYs 1114 * that apply RGMII delays too, and the MAC driver needs not perform any 1115 * special checks. 1116 * 1117 * Previously we were acting upon the "phy-mode" property when we were 1118 * operating in fixed-link, basically acting as a PHY, but with a reversed 1119 * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should 1120 * behave as if it is connected to a PHY which has applied RGMII delays in the 1121 * TX direction. So if anything, RX delays should have been added by the MAC, 1122 * but we were adding TX delays. 1123 * 1124 * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall 1125 * back to the legacy behavior and apply delays on fixed-link ports based on 1126 * the reverse interpretation of the phy-mode. This is a deviation from the 1127 * expected default behavior which is to simply apply no delays. To achieve 1128 * that behavior with the new bindings, it is mandatory to specify 1129 * "{rx,tx}-internal-delay-ps" with a value of 0. 1130 */ 1131static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port, 1132 struct device_node *port_dn) 1133{ 1134 phy_interface_t phy_mode = priv->phy_mode[port]; 1135 struct device *dev = &priv->spidev->dev; 1136 int rx_delay = -1, tx_delay = -1; 1137 1138 if (!phy_interface_mode_is_rgmii(phy_mode)) 1139 return 0; 1140 1141 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 1142 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 1143 1144 if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) { 1145 dev_warn(dev, 1146 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 1147 "please update device tree to specify \"rx-internal-delay-ps\" and " 1148 "\"tx-internal-delay-ps\"", 1149 port); 1150 1151 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 1152 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1153 rx_delay = 2000; 1154 1155 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 1156 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1157 tx_delay = 2000; 1158 } 1159 1160 if (rx_delay < 0) 1161 rx_delay = 0; 1162 if (tx_delay < 0) 1163 tx_delay = 0; 1164 1165 if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) { 1166 dev_err(dev, "Chip cannot apply RGMII delays\n"); 1167 return -EINVAL; 1168 } 1169 1170 if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) || 1171 (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) || 1172 (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) || 1173 (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) { 1174 dev_err(dev, 1175 "port %d RGMII delay values out of range, must be between %d and %d ps\n", 1176 port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS); 1177 return -ERANGE; 1178 } 1179 1180 priv->rgmii_rx_delay_ps[port] = rx_delay; 1181 priv->rgmii_tx_delay_ps[port] = tx_delay; 1182 1183 return 0; 1184} 1185 1186static int sja1105_parse_ports_node(struct sja1105_private *priv, 1187 struct device_node *ports_node) 1188{ 1189 struct device *dev = &priv->spidev->dev; 1190 1191 for_each_available_child_of_node_scoped(ports_node, child) { 1192 struct device_node *phy_node; 1193 phy_interface_t phy_mode; 1194 u32 index; 1195 int err; 1196 1197 /* Get switch port number from DT */ 1198 if (of_property_read_u32(child, "reg", &index) < 0) { 1199 dev_err(dev, "Port number not defined in device tree " 1200 "(property \"reg\")\n"); 1201 return -ENODEV; 1202 } 1203 1204 /* Get PHY mode from DT */ 1205 err = of_get_phy_mode(child, &phy_mode); 1206 if (err) { 1207 dev_err(dev, "Failed to read phy-mode or " 1208 "phy-interface-type property for port %d\n", 1209 index); 1210 return -ENODEV; 1211 } 1212 1213 phy_node = of_parse_phandle(child, "phy-handle", 0); 1214 if (!phy_node) { 1215 if (!of_phy_is_fixed_link(child)) { 1216 dev_err(dev, "phy-handle or fixed-link " 1217 "properties missing!\n"); 1218 return -ENODEV; 1219 } 1220 /* phy-handle is missing, but fixed-link isn't. 1221 * So it's a fixed link. Default to PHY role. 1222 */ 1223 priv->fixed_link[index] = true; 1224 } else { 1225 of_node_put(phy_node); 1226 } 1227 1228 priv->phy_mode[index] = phy_mode; 1229 1230 err = sja1105_parse_rgmii_delays(priv, index, child); 1231 if (err) 1232 return err; 1233 } 1234 1235 return 0; 1236} 1237 1238static int sja1105_parse_dt(struct sja1105_private *priv) 1239{ 1240 struct device *dev = &priv->spidev->dev; 1241 struct device_node *switch_node = dev->of_node; 1242 struct device_node *ports_node; 1243 int rc; 1244 1245 ports_node = of_get_child_by_name(switch_node, "ports"); 1246 if (!ports_node) 1247 ports_node = of_get_child_by_name(switch_node, "ethernet-ports"); 1248 if (!ports_node) { 1249 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n"); 1250 return -ENODEV; 1251 } 1252 1253 rc = sja1105_parse_ports_node(priv, ports_node); 1254 of_node_put(ports_node); 1255 1256 return rc; 1257} 1258 1259static int sja1105_set_port_speed(struct sja1105_private *priv, int port, 1260 int speed_mbps) 1261{ 1262 struct sja1105_mac_config_entry *mac; 1263 u64 speed; 1264 1265 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration 1266 * tables. On E/T, MAC reconfig tables are not readable, only writable. 1267 * We have to *know* what the MAC looks like. For the sake of keeping 1268 * the code common, we'll use the static configuration tables as a 1269 * reasonable approximation for both E/T and P/Q/R/S. 1270 */ 1271 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 1272 1273 switch (speed_mbps) { 1274 case SPEED_UNKNOWN: 1275 /* PHYLINK called sja1105_mac_config() to inform us about 1276 * the state->interface, but AN has not completed and the 1277 * speed is not yet valid. UM10944.pdf says that setting 1278 * SJA1105_SPEED_AUTO at runtime disables the port, so that is 1279 * ok for power consumption in case AN will never complete - 1280 * otherwise PHYLINK should come back with a new update. 1281 */ 1282 speed = priv->info->port_speed[SJA1105_SPEED_AUTO]; 1283 break; 1284 case SPEED_10: 1285 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS]; 1286 break; 1287 case SPEED_100: 1288 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS]; 1289 break; 1290 case SPEED_1000: 1291 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS]; 1292 break; 1293 case SPEED_2500: 1294 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS]; 1295 break; 1296 default: 1297 dev_err(priv->ds->dev, "Invalid speed %iMbps\n", speed_mbps); 1298 return -EINVAL; 1299 } 1300 1301 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration 1302 * table, since this will be used for the clocking setup, and we no 1303 * longer need to store it in the static config (already told hardware 1304 * we want auto during upload phase). 1305 */ 1306 mac[port].speed = speed; 1307 1308 return 0; 1309} 1310 1311/* Write the MAC Configuration Table entry and, if necessary, the CGU settings, 1312 * after a link speedchange for this port. 1313 */ 1314static int sja1105_set_port_config(struct sja1105_private *priv, int port) 1315{ 1316 struct sja1105_mac_config_entry *mac; 1317 struct device *dev = priv->ds->dev; 1318 int rc; 1319 1320 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration 1321 * tables. On E/T, MAC reconfig tables are not readable, only writable. 1322 * We have to *know* what the MAC looks like. For the sake of keeping 1323 * the code common, we'll use the static configuration tables as a 1324 * reasonable approximation for both E/T and P/Q/R/S. 1325 */ 1326 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 1327 1328 /* Write to the dynamic reconfiguration tables */ 1329 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 1330 &mac[port], true); 1331 if (rc < 0) { 1332 dev_err(dev, "Failed to write MAC config: %d\n", rc); 1333 return rc; 1334 } 1335 1336 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at 1337 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and 1338 * RMII no change of the clock setup is required. Actually, changing 1339 * the clock setup does interrupt the clock signal for a certain time 1340 * which causes trouble for all PHYs relying on this signal. 1341 */ 1342 if (!phy_interface_mode_is_rgmii(priv->phy_mode[port])) 1343 return 0; 1344 1345 return sja1105_clocking_setup_port(priv, port); 1346} 1347 1348static struct phylink_pcs * 1349sja1105_mac_select_pcs(struct phylink_config *config, phy_interface_t iface) 1350{ 1351 struct dsa_port *dp = dsa_phylink_to_port(config); 1352 struct sja1105_private *priv = dp->ds->priv; 1353 1354 return priv->pcs[dp->index]; 1355} 1356 1357static void sja1105_mac_config(struct phylink_config *config, 1358 unsigned int mode, 1359 const struct phylink_link_state *state) 1360{ 1361} 1362 1363static void sja1105_mac_link_down(struct phylink_config *config, 1364 unsigned int mode, 1365 phy_interface_t interface) 1366{ 1367 struct dsa_port *dp = dsa_phylink_to_port(config); 1368 1369 sja1105_inhibit_tx(dp->ds->priv, BIT(dp->index), true); 1370} 1371 1372static void sja1105_mac_link_up(struct phylink_config *config, 1373 struct phy_device *phydev, 1374 unsigned int mode, 1375 phy_interface_t interface, 1376 int speed, int duplex, 1377 bool tx_pause, bool rx_pause) 1378{ 1379 struct dsa_port *dp = dsa_phylink_to_port(config); 1380 struct sja1105_private *priv = dp->ds->priv; 1381 int port = dp->index; 1382 1383 if (!sja1105_set_port_speed(priv, port, speed)) 1384 sja1105_set_port_config(priv, port); 1385 1386 sja1105_inhibit_tx(priv, BIT(port), false); 1387} 1388 1389static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port, 1390 struct phylink_config *config) 1391{ 1392 struct sja1105_private *priv = ds->priv; 1393 struct sja1105_xmii_params_entry *mii; 1394 phy_interface_t phy_mode; 1395 1396 phy_mode = priv->phy_mode[port]; 1397 if (phy_mode == PHY_INTERFACE_MODE_SGMII || 1398 phy_mode == PHY_INTERFACE_MODE_2500BASEX) { 1399 /* Changing the PHY mode on SERDES ports is possible and makes 1400 * sense, because that is done through the XPCS. We allow 1401 * changes between SGMII and 2500base-X. 1402 */ 1403 if (priv->info->supports_sgmii[port]) 1404 __set_bit(PHY_INTERFACE_MODE_SGMII, 1405 config->supported_interfaces); 1406 1407 if (priv->info->supports_2500basex[port]) 1408 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 1409 config->supported_interfaces); 1410 } else { 1411 /* The SJA1105 MAC programming model is through the static 1412 * config (the xMII Mode table cannot be dynamically 1413 * reconfigured), and we have to program that early. 1414 */ 1415 __set_bit(phy_mode, config->supported_interfaces); 1416 } 1417 1418 /* The MAC does not support pause frames, and also doesn't 1419 * support half-duplex traffic modes. 1420 */ 1421 config->mac_capabilities = MAC_10FD | MAC_100FD; 1422 1423 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; 1424 if (mii->xmii_mode[port] == XMII_MODE_RGMII || 1425 mii->xmii_mode[port] == XMII_MODE_SGMII) 1426 config->mac_capabilities |= MAC_1000FD; 1427 1428 if (priv->info->supports_2500basex[port]) 1429 config->mac_capabilities |= MAC_2500FD; 1430} 1431 1432static int 1433sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port, 1434 const struct sja1105_l2_lookup_entry *requested) 1435{ 1436 struct sja1105_l2_lookup_entry *l2_lookup; 1437 struct sja1105_table *table; 1438 int i; 1439 1440 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; 1441 l2_lookup = table->entries; 1442 1443 for (i = 0; i < table->entry_count; i++) 1444 if (l2_lookup[i].macaddr == requested->macaddr && 1445 l2_lookup[i].vlanid == requested->vlanid && 1446 l2_lookup[i].destports & BIT(port)) 1447 return i; 1448 1449 return -1; 1450} 1451 1452/* We want FDB entries added statically through the bridge command to persist 1453 * across switch resets, which are a common thing during normal SJA1105 1454 * operation. So we have to back them up in the static configuration tables 1455 * and hence apply them on next static config upload... yay! 1456 */ 1457static int 1458sja1105_static_fdb_change(struct sja1105_private *priv, int port, 1459 const struct sja1105_l2_lookup_entry *requested, 1460 bool keep) 1461{ 1462 struct sja1105_l2_lookup_entry *l2_lookup; 1463 struct sja1105_table *table; 1464 int rc, match; 1465 1466 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; 1467 1468 match = sja1105_find_static_fdb_entry(priv, port, requested); 1469 if (match < 0) { 1470 /* Can't delete a missing entry. */ 1471 if (!keep) 1472 return 0; 1473 1474 /* No match => new entry */ 1475 rc = sja1105_table_resize(table, table->entry_count + 1); 1476 if (rc) 1477 return rc; 1478 1479 match = table->entry_count - 1; 1480 } 1481 1482 /* Assign pointer after the resize (it may be new memory) */ 1483 l2_lookup = table->entries; 1484 1485 /* We have a match. 1486 * If the job was to add this FDB entry, it's already done (mostly 1487 * anyway, since the port forwarding mask may have changed, case in 1488 * which we update it). 1489 * Otherwise we have to delete it. 1490 */ 1491 if (keep) { 1492 l2_lookup[match] = *requested; 1493 return 0; 1494 } 1495 1496 /* To remove, the strategy is to overwrite the element with 1497 * the last one, and then reduce the array size by 1 1498 */ 1499 l2_lookup[match] = l2_lookup[table->entry_count - 1]; 1500 return sja1105_table_resize(table, table->entry_count - 1); 1501} 1502 1503/* First-generation switches have a 4-way set associative TCAM that 1504 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of 1505 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin). 1506 * For the placement of a newly learnt FDB entry, the switch selects the bin 1507 * based on a hash function, and the way within that bin incrementally. 1508 */ 1509static int sja1105et_fdb_index(int bin, int way) 1510{ 1511 return bin * SJA1105ET_FDB_BIN_SIZE + way; 1512} 1513 1514static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin, 1515 const u8 *addr, u16 vid, 1516 struct sja1105_l2_lookup_entry *match, 1517 int *last_unused) 1518{ 1519 int way; 1520 1521 for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) { 1522 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1523 int index = sja1105et_fdb_index(bin, way); 1524 1525 /* Skip unused entries, optionally marking them 1526 * into the return value 1527 */ 1528 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1529 index, &l2_lookup)) { 1530 if (last_unused) 1531 *last_unused = way; 1532 continue; 1533 } 1534 1535 if (l2_lookup.macaddr == ether_addr_to_u64(addr) && 1536 l2_lookup.vlanid == vid) { 1537 if (match) 1538 *match = l2_lookup; 1539 return way; 1540 } 1541 } 1542 /* Return an invalid entry index if not found */ 1543 return -1; 1544} 1545 1546int sja1105et_fdb_add(struct dsa_switch *ds, int port, 1547 const unsigned char *addr, u16 vid) 1548{ 1549 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp; 1550 struct sja1105_private *priv = ds->priv; 1551 struct device *dev = ds->dev; 1552 int last_unused = -1; 1553 int start, end, i; 1554 int bin, way, rc; 1555 1556 bin = sja1105et_fdb_hash(priv, addr, vid); 1557 1558 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, 1559 &l2_lookup, &last_unused); 1560 if (way >= 0) { 1561 /* We have an FDB entry. Is our port in the destination 1562 * mask? If yes, we need to do nothing. If not, we need 1563 * to rewrite the entry by adding this port to it. 1564 */ 1565 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds) 1566 return 0; 1567 l2_lookup.destports |= BIT(port); 1568 } else { 1569 int index = sja1105et_fdb_index(bin, way); 1570 1571 /* We don't have an FDB entry. We construct a new one and 1572 * try to find a place for it within the FDB table. 1573 */ 1574 l2_lookup.macaddr = ether_addr_to_u64(addr); 1575 l2_lookup.destports = BIT(port); 1576 l2_lookup.vlanid = vid; 1577 1578 if (last_unused >= 0) { 1579 way = last_unused; 1580 } else { 1581 /* Bin is full, need to evict somebody. 1582 * Choose victim at random. If you get these messages 1583 * often, you may need to consider changing the 1584 * distribution function: 1585 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly 1586 */ 1587 get_random_bytes(&way, sizeof(u8)); 1588 way %= SJA1105ET_FDB_BIN_SIZE; 1589 dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n", 1590 bin, addr, way); 1591 /* Evict entry */ 1592 sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1593 index, NULL, false); 1594 } 1595 } 1596 l2_lookup.lockeds = true; 1597 l2_lookup.index = sja1105et_fdb_index(bin, way); 1598 1599 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1600 l2_lookup.index, &l2_lookup, 1601 true); 1602 if (rc < 0) 1603 return rc; 1604 1605 /* Invalidate a dynamically learned entry if that exists */ 1606 start = sja1105et_fdb_index(bin, 0); 1607 end = sja1105et_fdb_index(bin, way); 1608 1609 for (i = start; i < end; i++) { 1610 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1611 i, &tmp); 1612 if (rc == -ENOENT) 1613 continue; 1614 if (rc) 1615 return rc; 1616 1617 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid) 1618 continue; 1619 1620 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1621 i, NULL, false); 1622 if (rc) 1623 return rc; 1624 1625 break; 1626 } 1627 1628 return sja1105_static_fdb_change(priv, port, &l2_lookup, true); 1629} 1630 1631int sja1105et_fdb_del(struct dsa_switch *ds, int port, 1632 const unsigned char *addr, u16 vid) 1633{ 1634 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1635 struct sja1105_private *priv = ds->priv; 1636 int index, bin, way, rc; 1637 bool keep; 1638 1639 bin = sja1105et_fdb_hash(priv, addr, vid); 1640 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, 1641 &l2_lookup, NULL); 1642 if (way < 0) 1643 return 0; 1644 index = sja1105et_fdb_index(bin, way); 1645 1646 /* We have an FDB entry. Is our port in the destination mask? If yes, 1647 * we need to remove it. If the resulting port mask becomes empty, we 1648 * need to completely evict the FDB entry. 1649 * Otherwise we just write it back. 1650 */ 1651 l2_lookup.destports &= ~BIT(port); 1652 1653 if (l2_lookup.destports) 1654 keep = true; 1655 else 1656 keep = false; 1657 1658 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1659 index, &l2_lookup, keep); 1660 if (rc < 0) 1661 return rc; 1662 1663 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep); 1664} 1665 1666int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, 1667 const unsigned char *addr, u16 vid) 1668{ 1669 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp; 1670 struct sja1105_private *priv = ds->priv; 1671 int rc, i; 1672 1673 /* Search for an existing entry in the FDB table */ 1674 l2_lookup.macaddr = ether_addr_to_u64(addr); 1675 l2_lookup.vlanid = vid; 1676 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); 1677 l2_lookup.mask_vlanid = VLAN_VID_MASK; 1678 l2_lookup.destports = BIT(port); 1679 1680 tmp = l2_lookup; 1681 1682 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1683 SJA1105_SEARCH, &tmp); 1684 if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) { 1685 /* Found a static entry and this port is already in the entry's 1686 * port mask => job done 1687 */ 1688 if ((tmp.destports & BIT(port)) && tmp.lockeds) 1689 return 0; 1690 1691 l2_lookup = tmp; 1692 1693 /* l2_lookup.index is populated by the switch in case it 1694 * found something. 1695 */ 1696 l2_lookup.destports |= BIT(port); 1697 goto skip_finding_an_index; 1698 } 1699 1700 /* Not found, so try to find an unused spot in the FDB. 1701 * This is slightly inefficient because the strategy is knock-knock at 1702 * every possible position from 0 to 1023. 1703 */ 1704 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { 1705 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1706 i, NULL); 1707 if (rc < 0) 1708 break; 1709 } 1710 if (i == SJA1105_MAX_L2_LOOKUP_COUNT) { 1711 dev_err(ds->dev, "FDB is full, cannot add entry.\n"); 1712 return -EINVAL; 1713 } 1714 l2_lookup.index = i; 1715 1716skip_finding_an_index: 1717 l2_lookup.lockeds = true; 1718 1719 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1720 l2_lookup.index, &l2_lookup, 1721 true); 1722 if (rc < 0) 1723 return rc; 1724 1725 /* The switch learns dynamic entries and looks up the FDB left to 1726 * right. It is possible that our addition was concurrent with the 1727 * dynamic learning of the same address, so now that the static entry 1728 * has been installed, we are certain that address learning for this 1729 * particular address has been turned off, so the dynamic entry either 1730 * is in the FDB at an index smaller than the static one, or isn't (it 1731 * can also be at a larger index, but in that case it is inactive 1732 * because the static FDB entry will match first, and the dynamic one 1733 * will eventually age out). Search for a dynamically learned address 1734 * prior to our static one and invalidate it. 1735 */ 1736 tmp = l2_lookup; 1737 1738 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1739 SJA1105_SEARCH, &tmp); 1740 if (rc < 0) { 1741 dev_err(ds->dev, 1742 "port %d failed to read back entry for %pM vid %d: %pe\n", 1743 port, addr, vid, ERR_PTR(rc)); 1744 return rc; 1745 } 1746 1747 if (tmp.index < l2_lookup.index) { 1748 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1749 tmp.index, NULL, false); 1750 if (rc < 0) 1751 return rc; 1752 } 1753 1754 return sja1105_static_fdb_change(priv, port, &l2_lookup, true); 1755} 1756 1757int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, 1758 const unsigned char *addr, u16 vid) 1759{ 1760 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1761 struct sja1105_private *priv = ds->priv; 1762 bool keep; 1763 int rc; 1764 1765 l2_lookup.macaddr = ether_addr_to_u64(addr); 1766 l2_lookup.vlanid = vid; 1767 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); 1768 l2_lookup.mask_vlanid = VLAN_VID_MASK; 1769 l2_lookup.destports = BIT(port); 1770 1771 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1772 SJA1105_SEARCH, &l2_lookup); 1773 if (rc < 0) 1774 return 0; 1775 1776 l2_lookup.destports &= ~BIT(port); 1777 1778 /* Decide whether we remove just this port from the FDB entry, 1779 * or if we remove it completely. 1780 */ 1781 if (l2_lookup.destports) 1782 keep = true; 1783 else 1784 keep = false; 1785 1786 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1787 l2_lookup.index, &l2_lookup, keep); 1788 if (rc < 0) 1789 return rc; 1790 1791 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep); 1792} 1793 1794static int sja1105_fdb_add(struct dsa_switch *ds, int port, 1795 const unsigned char *addr, u16 vid, 1796 struct dsa_db db) 1797{ 1798 struct sja1105_private *priv = ds->priv; 1799 int rc; 1800 1801 if (!vid) { 1802 switch (db.type) { 1803 case DSA_DB_PORT: 1804 vid = dsa_tag_8021q_standalone_vid(db.dp); 1805 break; 1806 case DSA_DB_BRIDGE: 1807 vid = dsa_tag_8021q_bridge_vid(db.bridge.num); 1808 break; 1809 default: 1810 return -EOPNOTSUPP; 1811 } 1812 } 1813 1814 mutex_lock(&priv->fdb_lock); 1815 rc = priv->info->fdb_add_cmd(ds, port, addr, vid); 1816 mutex_unlock(&priv->fdb_lock); 1817 1818 return rc; 1819} 1820 1821static int __sja1105_fdb_del(struct dsa_switch *ds, int port, 1822 const unsigned char *addr, u16 vid, 1823 struct dsa_db db) 1824{ 1825 struct sja1105_private *priv = ds->priv; 1826 1827 if (!vid) { 1828 switch (db.type) { 1829 case DSA_DB_PORT: 1830 vid = dsa_tag_8021q_standalone_vid(db.dp); 1831 break; 1832 case DSA_DB_BRIDGE: 1833 vid = dsa_tag_8021q_bridge_vid(db.bridge.num); 1834 break; 1835 default: 1836 return -EOPNOTSUPP; 1837 } 1838 } 1839 1840 return priv->info->fdb_del_cmd(ds, port, addr, vid); 1841} 1842 1843static int sja1105_fdb_del(struct dsa_switch *ds, int port, 1844 const unsigned char *addr, u16 vid, 1845 struct dsa_db db) 1846{ 1847 struct sja1105_private *priv = ds->priv; 1848 int rc; 1849 1850 mutex_lock(&priv->fdb_lock); 1851 rc = __sja1105_fdb_del(ds, port, addr, vid, db); 1852 mutex_unlock(&priv->fdb_lock); 1853 1854 return rc; 1855} 1856 1857static int sja1105_fdb_dump(struct dsa_switch *ds, int port, 1858 dsa_fdb_dump_cb_t *cb, void *data) 1859{ 1860 struct sja1105_private *priv = ds->priv; 1861 struct device *dev = ds->dev; 1862 int i; 1863 1864 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { 1865 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1866 u8 macaddr[ETH_ALEN]; 1867 int rc; 1868 1869 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1870 i, &l2_lookup); 1871 /* No fdb entry at i, not an issue */ 1872 if (rc == -ENOENT) 1873 continue; 1874 if (rc) { 1875 dev_err(dev, "Failed to dump FDB: %d\n", rc); 1876 return rc; 1877 } 1878 1879 /* FDB dump callback is per port. This means we have to 1880 * disregard a valid entry if it's not for this port, even if 1881 * only to revisit it later. This is inefficient because the 1882 * 1024-sized FDB table needs to be traversed 4 times through 1883 * SPI during a 'bridge fdb show' command. 1884 */ 1885 if (!(l2_lookup.destports & BIT(port))) 1886 continue; 1887 1888 u64_to_ether_addr(l2_lookup.macaddr, macaddr); 1889 1890 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show" 1891 * only wants to see unicast 1892 */ 1893 if (is_multicast_ether_addr(macaddr)) 1894 continue; 1895 1896 /* We need to hide the dsa_8021q VLANs from the user. */ 1897 if (vid_is_dsa_8021q(l2_lookup.vlanid)) 1898 l2_lookup.vlanid = 0; 1899 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data); 1900 if (rc) 1901 return rc; 1902 } 1903 return 0; 1904} 1905 1906static void sja1105_fast_age(struct dsa_switch *ds, int port) 1907{ 1908 struct dsa_port *dp = dsa_to_port(ds, port); 1909 struct sja1105_private *priv = ds->priv; 1910 struct dsa_db db = { 1911 .type = DSA_DB_BRIDGE, 1912 .bridge = { 1913 .dev = dsa_port_bridge_dev_get(dp), 1914 .num = dsa_port_bridge_num_get(dp), 1915 }, 1916 }; 1917 int i; 1918 1919 mutex_lock(&priv->fdb_lock); 1920 1921 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { 1922 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1923 u8 macaddr[ETH_ALEN]; 1924 int rc; 1925 1926 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1927 i, &l2_lookup); 1928 /* No fdb entry at i, not an issue */ 1929 if (rc == -ENOENT) 1930 continue; 1931 if (rc) { 1932 dev_err(ds->dev, "Failed to read FDB: %pe\n", 1933 ERR_PTR(rc)); 1934 break; 1935 } 1936 1937 if (!(l2_lookup.destports & BIT(port))) 1938 continue; 1939 1940 /* Don't delete static FDB entries */ 1941 if (l2_lookup.lockeds) 1942 continue; 1943 1944 u64_to_ether_addr(l2_lookup.macaddr, macaddr); 1945 1946 rc = __sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db); 1947 if (rc) { 1948 dev_err(ds->dev, 1949 "Failed to delete FDB entry %pM vid %lld: %pe\n", 1950 macaddr, l2_lookup.vlanid, ERR_PTR(rc)); 1951 break; 1952 } 1953 } 1954 1955 mutex_unlock(&priv->fdb_lock); 1956} 1957 1958static int sja1105_mdb_add(struct dsa_switch *ds, int port, 1959 const struct switchdev_obj_port_mdb *mdb, 1960 struct dsa_db db) 1961{ 1962 return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db); 1963} 1964 1965static int sja1105_mdb_del(struct dsa_switch *ds, int port, 1966 const struct switchdev_obj_port_mdb *mdb, 1967 struct dsa_db db) 1968{ 1969 return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db); 1970} 1971 1972/* Common function for unicast and broadcast flood configuration. 1973 * Flooding is configured between each {ingress, egress} port pair, and since 1974 * the bridge's semantics are those of "egress flooding", it means we must 1975 * enable flooding towards this port from all ingress ports that are in the 1976 * same forwarding domain. 1977 */ 1978static int sja1105_manage_flood_domains(struct sja1105_private *priv) 1979{ 1980 struct sja1105_l2_forwarding_entry *l2_fwd; 1981 struct dsa_switch *ds = priv->ds; 1982 int from, to, rc; 1983 1984 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; 1985 1986 for (from = 0; from < ds->num_ports; from++) { 1987 u64 fl_domain = 0, bc_domain = 0; 1988 1989 for (to = 0; to < priv->ds->num_ports; to++) { 1990 if (!sja1105_can_forward(l2_fwd, from, to)) 1991 continue; 1992 1993 if (priv->ucast_egress_floods & BIT(to)) 1994 fl_domain |= BIT(to); 1995 if (priv->bcast_egress_floods & BIT(to)) 1996 bc_domain |= BIT(to); 1997 } 1998 1999 /* Nothing changed, nothing to do */ 2000 if (l2_fwd[from].fl_domain == fl_domain && 2001 l2_fwd[from].bc_domain == bc_domain) 2002 continue; 2003 2004 l2_fwd[from].fl_domain = fl_domain; 2005 l2_fwd[from].bc_domain = bc_domain; 2006 2007 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, 2008 from, &l2_fwd[from], true); 2009 if (rc < 0) 2010 return rc; 2011 } 2012 2013 return 0; 2014} 2015 2016static int sja1105_bridge_member(struct dsa_switch *ds, int port, 2017 struct dsa_bridge bridge, bool member) 2018{ 2019 struct sja1105_l2_forwarding_entry *l2_fwd; 2020 struct sja1105_private *priv = ds->priv; 2021 int i, rc; 2022 2023 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; 2024 2025 for (i = 0; i < ds->num_ports; i++) { 2026 /* Add this port to the forwarding matrix of the 2027 * other ports in the same bridge, and viceversa. 2028 */ 2029 if (!dsa_is_user_port(ds, i)) 2030 continue; 2031 /* For the ports already under the bridge, only one thing needs 2032 * to be done, and that is to add this port to their 2033 * reachability domain. So we can perform the SPI write for 2034 * them immediately. However, for this port itself (the one 2035 * that is new to the bridge), we need to add all other ports 2036 * to its reachability domain. So we do that incrementally in 2037 * this loop, and perform the SPI write only at the end, once 2038 * the domain contains all other bridge ports. 2039 */ 2040 if (i == port) 2041 continue; 2042 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2043 continue; 2044 sja1105_port_allow_traffic(l2_fwd, i, port, member); 2045 sja1105_port_allow_traffic(l2_fwd, port, i, member); 2046 2047 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, 2048 i, &l2_fwd[i], true); 2049 if (rc < 0) 2050 return rc; 2051 } 2052 2053 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, 2054 port, &l2_fwd[port], true); 2055 if (rc) 2056 return rc; 2057 2058 rc = sja1105_commit_pvid(ds, port); 2059 if (rc) 2060 return rc; 2061 2062 return sja1105_manage_flood_domains(priv); 2063} 2064 2065static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port, 2066 u8 state) 2067{ 2068 struct dsa_port *dp = dsa_to_port(ds, port); 2069 struct sja1105_private *priv = ds->priv; 2070 struct sja1105_mac_config_entry *mac; 2071 2072 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 2073 2074 switch (state) { 2075 case BR_STATE_DISABLED: 2076 case BR_STATE_BLOCKING: 2077 case BR_STATE_LISTENING: 2078 /* From UM10944 description of DRPDTAG (why put this there?): 2079 * "Management traffic flows to the port regardless of the state 2080 * of the INGRESS flag". So BPDUs are still be allowed to pass. 2081 * At the moment no difference between DISABLED and BLOCKING. 2082 */ 2083 mac[port].ingress = false; 2084 mac[port].egress = false; 2085 mac[port].dyn_learn = false; 2086 break; 2087 case BR_STATE_LEARNING: 2088 mac[port].ingress = true; 2089 mac[port].egress = false; 2090 mac[port].dyn_learn = dp->learning; 2091 break; 2092 case BR_STATE_FORWARDING: 2093 mac[port].ingress = true; 2094 mac[port].egress = true; 2095 mac[port].dyn_learn = dp->learning; 2096 break; 2097 default: 2098 dev_err(ds->dev, "invalid STP state: %d\n", state); 2099 return; 2100 } 2101 2102 sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 2103 &mac[port], true); 2104} 2105 2106static int sja1105_bridge_join(struct dsa_switch *ds, int port, 2107 struct dsa_bridge bridge, 2108 bool *tx_fwd_offload, 2109 struct netlink_ext_ack *extack) 2110{ 2111 int rc; 2112 2113 rc = sja1105_bridge_member(ds, port, bridge, true); 2114 if (rc) 2115 return rc; 2116 2117 rc = dsa_tag_8021q_bridge_join(ds, port, bridge, tx_fwd_offload, 2118 extack); 2119 if (rc) { 2120 sja1105_bridge_member(ds, port, bridge, false); 2121 return rc; 2122 } 2123 2124 return 0; 2125} 2126 2127static void sja1105_bridge_leave(struct dsa_switch *ds, int port, 2128 struct dsa_bridge bridge) 2129{ 2130 dsa_tag_8021q_bridge_leave(ds, port, bridge); 2131 sja1105_bridge_member(ds, port, bridge, false); 2132} 2133 2134/* Port 0 (the uC port) does not have CBS shapers */ 2135#define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio)) 2136 2137static int sja1105_find_cbs_shaper(struct sja1105_private *priv, 2138 int port, int prio) 2139{ 2140 int i; 2141 2142 if (priv->info->fixed_cbs_mapping) { 2143 i = SJA1110_FIXED_CBS(port, prio); 2144 if (i >= 0 && i < priv->info->num_cbs_shapers) 2145 return i; 2146 2147 return -1; 2148 } 2149 2150 for (i = 0; i < priv->info->num_cbs_shapers; i++) 2151 if (priv->cbs[i].port == port && priv->cbs[i].prio == prio) 2152 return i; 2153 2154 return -1; 2155} 2156 2157static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv) 2158{ 2159 int i; 2160 2161 if (priv->info->fixed_cbs_mapping) 2162 return -1; 2163 2164 for (i = 0; i < priv->info->num_cbs_shapers; i++) 2165 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope) 2166 return i; 2167 2168 return -1; 2169} 2170 2171static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port, 2172 int prio) 2173{ 2174 int i; 2175 2176 for (i = 0; i < priv->info->num_cbs_shapers; i++) { 2177 struct sja1105_cbs_entry *cbs = &priv->cbs[i]; 2178 2179 if (cbs->port == port && cbs->prio == prio) { 2180 memset(cbs, 0, sizeof(*cbs)); 2181 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, 2182 i, cbs, true); 2183 } 2184 } 2185 2186 return 0; 2187} 2188 2189static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port, 2190 struct tc_cbs_qopt_offload *offload) 2191{ 2192 struct sja1105_private *priv = ds->priv; 2193 struct sja1105_cbs_entry *cbs; 2194 s64 port_transmit_rate_kbps; 2195 int index; 2196 2197 if (!offload->enable) 2198 return sja1105_delete_cbs_shaper(priv, port, offload->queue); 2199 2200 /* The user may be replacing an existing shaper */ 2201 index = sja1105_find_cbs_shaper(priv, port, offload->queue); 2202 if (index < 0) { 2203 /* That isn't the case - see if we can allocate a new one */ 2204 index = sja1105_find_unused_cbs_shaper(priv); 2205 if (index < 0) 2206 return -ENOSPC; 2207 } 2208 2209 cbs = &priv->cbs[index]; 2210 cbs->port = port; 2211 cbs->prio = offload->queue; 2212 /* locredit and sendslope are negative by definition. In hardware, 2213 * positive values must be provided, and the negative sign is implicit. 2214 */ 2215 cbs->credit_hi = offload->hicredit; 2216 cbs->credit_lo = abs(offload->locredit); 2217 /* User space is in kbits/sec, while the hardware in bytes/sec times 2218 * link speed. Since the given offload->sendslope is good only for the 2219 * current link speed anyway, and user space is likely to reprogram it 2220 * when that changes, don't even bother to track the port's link speed, 2221 * but deduce the port transmit rate from idleslope - sendslope. 2222 */ 2223 port_transmit_rate_kbps = offload->idleslope - offload->sendslope; 2224 cbs->idle_slope = div_s64(offload->idleslope * BYTES_PER_KBIT, 2225 port_transmit_rate_kbps); 2226 cbs->send_slope = div_s64(abs(offload->sendslope * BYTES_PER_KBIT), 2227 port_transmit_rate_kbps); 2228 /* Convert the negative values from 64-bit 2's complement 2229 * to 32-bit 2's complement (for the case of 0x80000000 whose 2230 * negative is still negative). 2231 */ 2232 cbs->credit_lo &= GENMASK_ULL(31, 0); 2233 cbs->send_slope &= GENMASK_ULL(31, 0); 2234 2235 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs, 2236 true); 2237} 2238 2239static int sja1105_reload_cbs(struct sja1105_private *priv) 2240{ 2241 int rc = 0, i; 2242 2243 /* The credit based shapers are only allocated if 2244 * CONFIG_NET_SCH_CBS is enabled. 2245 */ 2246 if (!priv->cbs) 2247 return 0; 2248 2249 for (i = 0; i < priv->info->num_cbs_shapers; i++) { 2250 struct sja1105_cbs_entry *cbs = &priv->cbs[i]; 2251 2252 if (!cbs->idle_slope && !cbs->send_slope) 2253 continue; 2254 2255 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs, 2256 true); 2257 if (rc) 2258 break; 2259 } 2260 2261 return rc; 2262} 2263 2264static const char * const sja1105_reset_reasons[] = { 2265 [SJA1105_VLAN_FILTERING] = "VLAN filtering", 2266 [SJA1105_AGEING_TIME] = "Ageing time", 2267 [SJA1105_SCHEDULING] = "Time-aware scheduling", 2268 [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing", 2269 [SJA1105_VIRTUAL_LINKS] = "Virtual links", 2270}; 2271 2272/* For situations where we need to change a setting at runtime that is only 2273 * available through the static configuration, resetting the switch in order 2274 * to upload the new static config is unavoidable. Back up the settings we 2275 * modify at runtime (currently only MAC) and restore them after uploading, 2276 * such that this operation is relatively seamless. 2277 */ 2278int sja1105_static_config_reload(struct sja1105_private *priv, 2279 enum sja1105_reset_reason reason) 2280{ 2281 struct ptp_system_timestamp ptp_sts_before; 2282 struct ptp_system_timestamp ptp_sts_after; 2283 u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0}; 2284 u64 mac_speed[SJA1105_MAX_NUM_PORTS]; 2285 struct sja1105_mac_config_entry *mac; 2286 struct dsa_switch *ds = priv->ds; 2287 s64 t1, t2, t3, t4; 2288 s64 t12, t34; 2289 int rc, i; 2290 s64 now; 2291 2292 mutex_lock(&priv->fdb_lock); 2293 mutex_lock(&priv->mgmt_lock); 2294 2295 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 2296 2297 /* Back up the dynamic link speed changed by sja1105_set_port_speed() 2298 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the 2299 * switch wants to see in the static config in order to allow us to 2300 * change it through the dynamic interface later. 2301 */ 2302 for (i = 0; i < ds->num_ports; i++) { 2303 mac_speed[i] = mac[i].speed; 2304 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO]; 2305 2306 if (priv->pcs[i]) 2307 bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i, 2308 MDIO_MMD_VEND2, MDIO_CTRL1); 2309 } 2310 2311 /* No PTP operations can run right now */ 2312 mutex_lock(&priv->ptp_data.lock); 2313 2314 rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before); 2315 if (rc < 0) { 2316 mutex_unlock(&priv->ptp_data.lock); 2317 goto out; 2318 } 2319 2320 /* Reset switch and send updated static configuration */ 2321 rc = sja1105_static_config_upload(priv); 2322 if (rc < 0) { 2323 mutex_unlock(&priv->ptp_data.lock); 2324 goto out; 2325 } 2326 2327 rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after); 2328 if (rc < 0) { 2329 mutex_unlock(&priv->ptp_data.lock); 2330 goto out; 2331 } 2332 2333 t1 = timespec64_to_ns(&ptp_sts_before.pre_ts); 2334 t2 = timespec64_to_ns(&ptp_sts_before.post_ts); 2335 t3 = timespec64_to_ns(&ptp_sts_after.pre_ts); 2336 t4 = timespec64_to_ns(&ptp_sts_after.post_ts); 2337 /* Mid point, corresponds to pre-reset PTPCLKVAL */ 2338 t12 = t1 + (t2 - t1) / 2; 2339 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */ 2340 t34 = t3 + (t4 - t3) / 2; 2341 /* Advance PTPCLKVAL by the time it took since its readout */ 2342 now += (t34 - t12); 2343 2344 __sja1105_ptp_adjtime(ds, now); 2345 2346 mutex_unlock(&priv->ptp_data.lock); 2347 2348 dev_info(priv->ds->dev, 2349 "Reset switch and programmed static config. Reason: %s\n", 2350 sja1105_reset_reasons[reason]); 2351 2352 /* Configure the CGU (PLLs) for MII and RMII PHYs. 2353 * For these interfaces there is no dynamic configuration 2354 * needed, since PLLs have same settings at all speeds. 2355 */ 2356 if (priv->info->clocking_setup) { 2357 rc = priv->info->clocking_setup(priv); 2358 if (rc < 0) 2359 goto out; 2360 } 2361 2362 for (i = 0; i < ds->num_ports; i++) { 2363 struct phylink_pcs *pcs = priv->pcs[i]; 2364 unsigned int neg_mode; 2365 2366 mac[i].speed = mac_speed[i]; 2367 rc = sja1105_set_port_config(priv, i); 2368 if (rc < 0) 2369 goto out; 2370 2371 if (!pcs) 2372 continue; 2373 2374 if (bmcr[i] & BMCR_ANENABLE) 2375 neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; 2376 else 2377 neg_mode = PHYLINK_PCS_NEG_OUTBAND; 2378 2379 rc = pcs->ops->pcs_config(pcs, neg_mode, priv->phy_mode[i], 2380 NULL, true); 2381 if (rc < 0) 2382 goto out; 2383 2384 if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) { 2385 int speed = SPEED_UNKNOWN; 2386 2387 if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX) 2388 speed = SPEED_2500; 2389 else if (bmcr[i] & BMCR_SPEED1000) 2390 speed = SPEED_1000; 2391 else if (bmcr[i] & BMCR_SPEED100) 2392 speed = SPEED_100; 2393 else 2394 speed = SPEED_10; 2395 2396 pcs->ops->pcs_link_up(pcs, neg_mode, priv->phy_mode[i], 2397 speed, DUPLEX_FULL); 2398 } 2399 } 2400 2401 rc = sja1105_reload_cbs(priv); 2402 if (rc < 0) 2403 goto out; 2404out: 2405 mutex_unlock(&priv->mgmt_lock); 2406 mutex_unlock(&priv->fdb_lock); 2407 2408 return rc; 2409} 2410 2411static enum dsa_tag_protocol 2412sja1105_get_tag_protocol(struct dsa_switch *ds, int port, 2413 enum dsa_tag_protocol mp) 2414{ 2415 struct sja1105_private *priv = ds->priv; 2416 2417 return priv->info->tag_proto; 2418} 2419 2420/* The TPID setting belongs to the General Parameters table, 2421 * which can only be partially reconfigured at runtime (and not the TPID). 2422 * So a switch reset is required. 2423 */ 2424int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 2425 struct netlink_ext_ack *extack) 2426{ 2427 struct sja1105_general_params_entry *general_params; 2428 struct sja1105_private *priv = ds->priv; 2429 struct sja1105_table *table; 2430 struct sja1105_rule *rule; 2431 u16 tpid, tpid2; 2432 int rc; 2433 2434 list_for_each_entry(rule, &priv->flow_block.rules, list) { 2435 if (rule->type == SJA1105_RULE_VL) { 2436 NL_SET_ERR_MSG_MOD(extack, 2437 "Cannot change VLAN filtering with active VL rules"); 2438 return -EBUSY; 2439 } 2440 } 2441 2442 if (enabled) { 2443 /* Enable VLAN filtering. */ 2444 tpid = ETH_P_8021Q; 2445 tpid2 = ETH_P_8021AD; 2446 } else { 2447 /* Disable VLAN filtering. */ 2448 tpid = ETH_P_SJA1105; 2449 tpid2 = ETH_P_SJA1105; 2450 } 2451 2452 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; 2453 general_params = table->entries; 2454 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */ 2455 general_params->tpid = tpid; 2456 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */ 2457 general_params->tpid2 = tpid2; 2458 2459 for (port = 0; port < ds->num_ports; port++) { 2460 if (dsa_is_unused_port(ds, port)) 2461 continue; 2462 2463 rc = sja1105_commit_pvid(ds, port); 2464 if (rc) 2465 return rc; 2466 } 2467 2468 rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING); 2469 if (rc) 2470 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype"); 2471 2472 return rc; 2473} 2474 2475static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid, 2476 u16 flags, bool allowed_ingress) 2477{ 2478 struct sja1105_vlan_lookup_entry *vlan; 2479 struct sja1105_table *table; 2480 int match, rc; 2481 2482 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; 2483 2484 match = sja1105_is_vlan_configured(priv, vid); 2485 if (match < 0) { 2486 rc = sja1105_table_resize(table, table->entry_count + 1); 2487 if (rc) 2488 return rc; 2489 match = table->entry_count - 1; 2490 } 2491 2492 /* Assign pointer after the resize (it's new memory) */ 2493 vlan = table->entries; 2494 2495 vlan[match].type_entry = SJA1110_VLAN_D_TAG; 2496 vlan[match].vlanid = vid; 2497 vlan[match].vlan_bc |= BIT(port); 2498 2499 if (allowed_ingress) 2500 vlan[match].vmemb_port |= BIT(port); 2501 else 2502 vlan[match].vmemb_port &= ~BIT(port); 2503 2504 if (flags & BRIDGE_VLAN_INFO_UNTAGGED) 2505 vlan[match].tag_port &= ~BIT(port); 2506 else 2507 vlan[match].tag_port |= BIT(port); 2508 2509 return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid, 2510 &vlan[match], true); 2511} 2512 2513static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid) 2514{ 2515 struct sja1105_vlan_lookup_entry *vlan; 2516 struct sja1105_table *table; 2517 bool keep = true; 2518 int match, rc; 2519 2520 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; 2521 2522 match = sja1105_is_vlan_configured(priv, vid); 2523 /* Can't delete a missing entry. */ 2524 if (match < 0) 2525 return 0; 2526 2527 /* Assign pointer after the resize (it's new memory) */ 2528 vlan = table->entries; 2529 2530 vlan[match].vlanid = vid; 2531 vlan[match].vlan_bc &= ~BIT(port); 2532 vlan[match].vmemb_port &= ~BIT(port); 2533 /* Also unset tag_port, just so we don't have a confusing bitmap 2534 * (no practical purpose). 2535 */ 2536 vlan[match].tag_port &= ~BIT(port); 2537 2538 /* If there's no port left as member of this VLAN, 2539 * it's time for it to go. 2540 */ 2541 if (!vlan[match].vmemb_port) 2542 keep = false; 2543 2544 rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid, 2545 &vlan[match], keep); 2546 if (rc < 0) 2547 return rc; 2548 2549 if (!keep) 2550 return sja1105_table_delete_entry(table, match); 2551 2552 return 0; 2553} 2554 2555static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port, 2556 const struct switchdev_obj_port_vlan *vlan, 2557 struct netlink_ext_ack *extack) 2558{ 2559 struct sja1105_private *priv = ds->priv; 2560 u16 flags = vlan->flags; 2561 int rc; 2562 2563 /* Be sure to deny alterations to the configuration done by tag_8021q. 2564 */ 2565 if (vid_is_dsa_8021q(vlan->vid)) { 2566 NL_SET_ERR_MSG_MOD(extack, 2567 "Range 3072-4095 reserved for dsa_8021q operation"); 2568 return -EBUSY; 2569 } 2570 2571 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */ 2572 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2573 flags = 0; 2574 2575 rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true); 2576 if (rc) 2577 return rc; 2578 2579 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 2580 priv->bridge_pvid[port] = vlan->vid; 2581 2582 return sja1105_commit_pvid(ds, port); 2583} 2584 2585static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port, 2586 const struct switchdev_obj_port_vlan *vlan) 2587{ 2588 struct sja1105_private *priv = ds->priv; 2589 int rc; 2590 2591 rc = sja1105_vlan_del(priv, port, vlan->vid); 2592 if (rc) 2593 return rc; 2594 2595 /* In case the pvid was deleted, make sure that untagged packets will 2596 * be dropped. 2597 */ 2598 return sja1105_commit_pvid(ds, port); 2599} 2600 2601static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 2602 u16 flags) 2603{ 2604 struct sja1105_private *priv = ds->priv; 2605 bool allowed_ingress = true; 2606 int rc; 2607 2608 /* Prevent attackers from trying to inject a DSA tag from 2609 * the outside world. 2610 */ 2611 if (dsa_is_user_port(ds, port)) 2612 allowed_ingress = false; 2613 2614 rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress); 2615 if (rc) 2616 return rc; 2617 2618 if (flags & BRIDGE_VLAN_INFO_PVID) 2619 priv->tag_8021q_pvid[port] = vid; 2620 2621 return sja1105_commit_pvid(ds, port); 2622} 2623 2624static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 2625{ 2626 struct sja1105_private *priv = ds->priv; 2627 2628 return sja1105_vlan_del(priv, port, vid); 2629} 2630 2631static int sja1105_prechangeupper(struct dsa_switch *ds, int port, 2632 struct netdev_notifier_changeupper_info *info) 2633{ 2634 struct netlink_ext_ack *extack = info->info.extack; 2635 struct net_device *upper = info->upper_dev; 2636 struct dsa_switch_tree *dst = ds->dst; 2637 struct dsa_port *dp; 2638 2639 if (is_vlan_dev(upper)) { 2640 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported"); 2641 return -EBUSY; 2642 } 2643 2644 if (netif_is_bridge_master(upper)) { 2645 list_for_each_entry(dp, &dst->ports, list) { 2646 struct net_device *br = dsa_port_bridge_dev_get(dp); 2647 2648 if (br && br != upper && br_vlan_enabled(br)) { 2649 NL_SET_ERR_MSG_MOD(extack, 2650 "Only one VLAN-aware bridge is supported"); 2651 return -EBUSY; 2652 } 2653 } 2654 } 2655 2656 return 0; 2657} 2658 2659static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot, 2660 struct sk_buff *skb, bool takets) 2661{ 2662 struct sja1105_mgmt_entry mgmt_route = {0}; 2663 struct sja1105_private *priv = ds->priv; 2664 struct ethhdr *hdr; 2665 int timeout = 10; 2666 int rc; 2667 2668 hdr = eth_hdr(skb); 2669 2670 mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest); 2671 mgmt_route.destports = BIT(port); 2672 mgmt_route.enfport = 1; 2673 mgmt_route.tsreg = 0; 2674 mgmt_route.takets = takets; 2675 2676 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE, 2677 slot, &mgmt_route, true); 2678 if (rc < 0) { 2679 kfree_skb(skb); 2680 return rc; 2681 } 2682 2683 /* Transfer skb to the host port. */ 2684 dsa_enqueue_skb(skb, dsa_to_port(ds, port)->user); 2685 2686 /* Wait until the switch has processed the frame */ 2687 do { 2688 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE, 2689 slot, &mgmt_route); 2690 if (rc < 0) { 2691 dev_err_ratelimited(priv->ds->dev, 2692 "failed to poll for mgmt route\n"); 2693 continue; 2694 } 2695 2696 /* UM10944: The ENFPORT flag of the respective entry is 2697 * cleared when a match is found. The host can use this 2698 * flag as an acknowledgment. 2699 */ 2700 cpu_relax(); 2701 } while (mgmt_route.enfport && --timeout); 2702 2703 if (!timeout) { 2704 /* Clean up the management route so that a follow-up 2705 * frame may not match on it by mistake. 2706 * This is only hardware supported on P/Q/R/S - on E/T it is 2707 * a no-op and we are silently discarding the -EOPNOTSUPP. 2708 */ 2709 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE, 2710 slot, &mgmt_route, false); 2711 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n"); 2712 } 2713 2714 return NETDEV_TX_OK; 2715} 2716 2717#define work_to_xmit_work(w) \ 2718 container_of((w), struct sja1105_deferred_xmit_work, work) 2719 2720/* Deferred work is unfortunately necessary because setting up the management 2721 * route cannot be done from atomit context (SPI transfer takes a sleepable 2722 * lock on the bus) 2723 */ 2724static void sja1105_port_deferred_xmit(struct kthread_work *work) 2725{ 2726 struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work); 2727 struct sk_buff *clone, *skb = xmit_work->skb; 2728 struct dsa_switch *ds = xmit_work->dp->ds; 2729 struct sja1105_private *priv = ds->priv; 2730 int port = xmit_work->dp->index; 2731 2732 clone = SJA1105_SKB_CB(skb)->clone; 2733 2734 mutex_lock(&priv->mgmt_lock); 2735 2736 sja1105_mgmt_xmit(ds, port, 0, skb, !!clone); 2737 2738 /* The clone, if there, was made by dsa_skb_tx_timestamp */ 2739 if (clone) 2740 sja1105_ptp_txtstamp_skb(ds, port, clone); 2741 2742 mutex_unlock(&priv->mgmt_lock); 2743 2744 kfree(xmit_work); 2745} 2746 2747static int sja1105_connect_tag_protocol(struct dsa_switch *ds, 2748 enum dsa_tag_protocol proto) 2749{ 2750 struct sja1105_private *priv = ds->priv; 2751 struct sja1105_tagger_data *tagger_data; 2752 2753 if (proto != priv->info->tag_proto) 2754 return -EPROTONOSUPPORT; 2755 2756 tagger_data = sja1105_tagger_data(ds); 2757 tagger_data->xmit_work_fn = sja1105_port_deferred_xmit; 2758 tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp; 2759 2760 return 0; 2761} 2762 2763/* The MAXAGE setting belongs to the L2 Forwarding Parameters table, 2764 * which cannot be reconfigured at runtime. So a switch reset is required. 2765 */ 2766static int sja1105_set_ageing_time(struct dsa_switch *ds, 2767 unsigned int ageing_time) 2768{ 2769 struct sja1105_l2_lookup_params_entry *l2_lookup_params; 2770 struct sja1105_private *priv = ds->priv; 2771 struct sja1105_table *table; 2772 unsigned int maxage; 2773 2774 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; 2775 l2_lookup_params = table->entries; 2776 2777 maxage = SJA1105_AGEING_TIME_MS(ageing_time); 2778 2779 if (l2_lookup_params->maxage == maxage) 2780 return 0; 2781 2782 l2_lookup_params->maxage = maxage; 2783 2784 return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME); 2785} 2786 2787static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2788{ 2789 struct sja1105_l2_policing_entry *policing; 2790 struct sja1105_private *priv = ds->priv; 2791 2792 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 2793 2794 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2795 new_mtu += VLAN_HLEN; 2796 2797 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; 2798 2799 if (policing[port].maxlen == new_mtu) 2800 return 0; 2801 2802 policing[port].maxlen = new_mtu; 2803 2804 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); 2805} 2806 2807static int sja1105_get_max_mtu(struct dsa_switch *ds, int port) 2808{ 2809 return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN; 2810} 2811 2812static int sja1105_port_setup_tc(struct dsa_switch *ds, int port, 2813 enum tc_setup_type type, 2814 void *type_data) 2815{ 2816 switch (type) { 2817 case TC_SETUP_QDISC_TAPRIO: 2818 return sja1105_setup_tc_taprio(ds, port, type_data); 2819 case TC_SETUP_QDISC_CBS: 2820 return sja1105_setup_tc_cbs(ds, port, type_data); 2821 default: 2822 return -EOPNOTSUPP; 2823 } 2824} 2825 2826/* We have a single mirror (@to) port, but can configure ingress and egress 2827 * mirroring on all other (@from) ports. 2828 * We need to allow mirroring rules only as long as the @to port is always the 2829 * same, and we need to unset the @to port from mirr_port only when there is no 2830 * mirroring rule that references it. 2831 */ 2832static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to, 2833 bool ingress, bool enabled) 2834{ 2835 struct sja1105_general_params_entry *general_params; 2836 struct sja1105_mac_config_entry *mac; 2837 struct dsa_switch *ds = priv->ds; 2838 struct sja1105_table *table; 2839 bool already_enabled; 2840 u64 new_mirr_port; 2841 int rc; 2842 2843 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; 2844 general_params = table->entries; 2845 2846 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 2847 2848 already_enabled = (general_params->mirr_port != ds->num_ports); 2849 if (already_enabled && enabled && general_params->mirr_port != to) { 2850 dev_err(priv->ds->dev, 2851 "Delete mirroring rules towards port %llu first\n", 2852 general_params->mirr_port); 2853 return -EBUSY; 2854 } 2855 2856 new_mirr_port = to; 2857 if (!enabled) { 2858 bool keep = false; 2859 int port; 2860 2861 /* Anybody still referencing mirr_port? */ 2862 for (port = 0; port < ds->num_ports; port++) { 2863 if (mac[port].ing_mirr || mac[port].egr_mirr) { 2864 keep = true; 2865 break; 2866 } 2867 } 2868 /* Unset already_enabled for next time */ 2869 if (!keep) 2870 new_mirr_port = ds->num_ports; 2871 } 2872 if (new_mirr_port != general_params->mirr_port) { 2873 general_params->mirr_port = new_mirr_port; 2874 2875 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS, 2876 0, general_params, true); 2877 if (rc < 0) 2878 return rc; 2879 } 2880 2881 if (ingress) 2882 mac[from].ing_mirr = enabled; 2883 else 2884 mac[from].egr_mirr = enabled; 2885 2886 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from, 2887 &mac[from], true); 2888} 2889 2890static int sja1105_mirror_add(struct dsa_switch *ds, int port, 2891 struct dsa_mall_mirror_tc_entry *mirror, 2892 bool ingress, struct netlink_ext_ack *extack) 2893{ 2894 return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port, 2895 ingress, true); 2896} 2897 2898static void sja1105_mirror_del(struct dsa_switch *ds, int port, 2899 struct dsa_mall_mirror_tc_entry *mirror) 2900{ 2901 sja1105_mirror_apply(ds->priv, port, mirror->to_local_port, 2902 mirror->ingress, false); 2903} 2904 2905static int sja1105_port_policer_add(struct dsa_switch *ds, int port, 2906 struct dsa_mall_policer_tc_entry *policer) 2907{ 2908 struct sja1105_l2_policing_entry *policing; 2909 struct sja1105_private *priv = ds->priv; 2910 2911 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; 2912 2913 /* In hardware, every 8 microseconds the credit level is incremented by 2914 * the value of RATE bytes divided by 64, up to a maximum of SMAX 2915 * bytes. 2916 */ 2917 policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec, 2918 1000000); 2919 policing[port].smax = policer->burst; 2920 2921 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); 2922} 2923 2924static void sja1105_port_policer_del(struct dsa_switch *ds, int port) 2925{ 2926 struct sja1105_l2_policing_entry *policing; 2927 struct sja1105_private *priv = ds->priv; 2928 2929 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; 2930 2931 policing[port].rate = SJA1105_RATE_MBPS(1000); 2932 policing[port].smax = 65535; 2933 2934 sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); 2935} 2936 2937static int sja1105_port_set_learning(struct sja1105_private *priv, int port, 2938 bool enabled) 2939{ 2940 struct sja1105_mac_config_entry *mac; 2941 2942 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 2943 2944 mac[port].dyn_learn = enabled; 2945 2946 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 2947 &mac[port], true); 2948} 2949 2950static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to, 2951 struct switchdev_brport_flags flags) 2952{ 2953 if (flags.mask & BR_FLOOD) { 2954 if (flags.val & BR_FLOOD) 2955 priv->ucast_egress_floods |= BIT(to); 2956 else 2957 priv->ucast_egress_floods &= ~BIT(to); 2958 } 2959 2960 if (flags.mask & BR_BCAST_FLOOD) { 2961 if (flags.val & BR_BCAST_FLOOD) 2962 priv->bcast_egress_floods |= BIT(to); 2963 else 2964 priv->bcast_egress_floods &= ~BIT(to); 2965 } 2966 2967 return sja1105_manage_flood_domains(priv); 2968} 2969 2970static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to, 2971 struct switchdev_brport_flags flags, 2972 struct netlink_ext_ack *extack) 2973{ 2974 struct sja1105_l2_lookup_entry *l2_lookup; 2975 struct sja1105_table *table; 2976 int match, rc; 2977 2978 mutex_lock(&priv->fdb_lock); 2979 2980 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; 2981 l2_lookup = table->entries; 2982 2983 for (match = 0; match < table->entry_count; match++) 2984 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST && 2985 l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST) 2986 break; 2987 2988 if (match == table->entry_count) { 2989 NL_SET_ERR_MSG_MOD(extack, 2990 "Could not find FDB entry for unknown multicast"); 2991 rc = -ENOSPC; 2992 goto out; 2993 } 2994 2995 if (flags.val & BR_MCAST_FLOOD) 2996 l2_lookup[match].destports |= BIT(to); 2997 else 2998 l2_lookup[match].destports &= ~BIT(to); 2999 3000 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 3001 l2_lookup[match].index, 3002 &l2_lookup[match], true); 3003out: 3004 mutex_unlock(&priv->fdb_lock); 3005 3006 return rc; 3007} 3008 3009static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3010 struct switchdev_brport_flags flags, 3011 struct netlink_ext_ack *extack) 3012{ 3013 struct sja1105_private *priv = ds->priv; 3014 3015 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 3016 BR_BCAST_FLOOD)) 3017 return -EINVAL; 3018 3019 if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) && 3020 !priv->info->can_limit_mcast_flood) { 3021 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 3022 bool unicast = !!(flags.val & BR_FLOOD); 3023 3024 if (unicast != multicast) { 3025 NL_SET_ERR_MSG_MOD(extack, 3026 "This chip cannot configure multicast flooding independently of unicast"); 3027 return -EINVAL; 3028 } 3029 } 3030 3031 return 0; 3032} 3033 3034static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port, 3035 struct switchdev_brport_flags flags, 3036 struct netlink_ext_ack *extack) 3037{ 3038 struct sja1105_private *priv = ds->priv; 3039 int rc; 3040 3041 if (flags.mask & BR_LEARNING) { 3042 bool learn_ena = !!(flags.val & BR_LEARNING); 3043 3044 rc = sja1105_port_set_learning(priv, port, learn_ena); 3045 if (rc) 3046 return rc; 3047 } 3048 3049 if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) { 3050 rc = sja1105_port_ucast_bcast_flood(priv, port, flags); 3051 if (rc) 3052 return rc; 3053 } 3054 3055 /* For chips that can't offload BR_MCAST_FLOOD independently, there 3056 * is nothing to do here, we ensured the configuration is in sync by 3057 * offloading BR_FLOOD. 3058 */ 3059 if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) { 3060 rc = sja1105_port_mcast_flood(priv, port, flags, 3061 extack); 3062 if (rc) 3063 return rc; 3064 } 3065 3066 return 0; 3067} 3068 3069/* The programming model for the SJA1105 switch is "all-at-once" via static 3070 * configuration tables. Some of these can be dynamically modified at runtime, 3071 * but not the xMII mode parameters table. 3072 * Furthermode, some PHYs may not have crystals for generating their clocks 3073 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's 3074 * ref_clk pin. So port clocking needs to be initialized early, before 3075 * connecting to PHYs is attempted, otherwise they won't respond through MDIO. 3076 * Setting correct PHY link speed does not matter now. 3077 * But dsa_user_phy_setup is called later than sja1105_setup, so the PHY 3078 * bindings are not yet parsed by DSA core. We need to parse early so that we 3079 * can populate the xMII mode parameters table. 3080 */ 3081static int sja1105_setup(struct dsa_switch *ds) 3082{ 3083 struct sja1105_private *priv = ds->priv; 3084 int rc; 3085 3086 if (priv->info->disable_microcontroller) { 3087 rc = priv->info->disable_microcontroller(priv); 3088 if (rc < 0) { 3089 dev_err(ds->dev, 3090 "Failed to disable microcontroller: %pe\n", 3091 ERR_PTR(rc)); 3092 return rc; 3093 } 3094 } 3095 3096 /* Create and send configuration down to device */ 3097 rc = sja1105_static_config_load(priv); 3098 if (rc < 0) { 3099 dev_err(ds->dev, "Failed to load static config: %d\n", rc); 3100 return rc; 3101 } 3102 3103 /* Configure the CGU (PHY link modes and speeds) */ 3104 if (priv->info->clocking_setup) { 3105 rc = priv->info->clocking_setup(priv); 3106 if (rc < 0) { 3107 dev_err(ds->dev, 3108 "Failed to configure MII clocking: %pe\n", 3109 ERR_PTR(rc)); 3110 goto out_static_config_free; 3111 } 3112 } 3113 3114 sja1105_tas_setup(ds); 3115 sja1105_flower_setup(ds); 3116 3117 rc = sja1105_ptp_clock_register(ds); 3118 if (rc < 0) { 3119 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc); 3120 goto out_flower_teardown; 3121 } 3122 3123 rc = sja1105_mdiobus_register(ds); 3124 if (rc < 0) { 3125 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n", 3126 ERR_PTR(rc)); 3127 goto out_ptp_clock_unregister; 3128 } 3129 3130 rc = sja1105_devlink_setup(ds); 3131 if (rc < 0) 3132 goto out_mdiobus_unregister; 3133 3134 rtnl_lock(); 3135 rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); 3136 rtnl_unlock(); 3137 if (rc) 3138 goto out_devlink_teardown; 3139 3140 /* On SJA1105, VLAN filtering per se is always enabled in hardware. 3141 * The only thing we can do to disable it is lie about what the 802.1Q 3142 * EtherType is. 3143 * So it will still try to apply VLAN filtering, but all ingress 3144 * traffic (except frames received with EtherType of ETH_P_SJA1105) 3145 * will be internally tagged with a distorted VLAN header where the 3146 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid. 3147 */ 3148 ds->vlan_filtering_is_global = true; 3149 ds->fdb_isolation = true; 3150 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES; 3151 3152 /* Advertise the 8 egress queues */ 3153 ds->num_tx_queues = SJA1105_NUM_TC; 3154 3155 ds->mtu_enforcement_ingress = true; 3156 ds->assisted_learning_on_cpu_port = true; 3157 3158 return 0; 3159 3160out_devlink_teardown: 3161 sja1105_devlink_teardown(ds); 3162out_mdiobus_unregister: 3163 sja1105_mdiobus_unregister(ds); 3164out_ptp_clock_unregister: 3165 sja1105_ptp_clock_unregister(ds); 3166out_flower_teardown: 3167 sja1105_flower_teardown(ds); 3168 sja1105_tas_teardown(ds); 3169out_static_config_free: 3170 sja1105_static_config_free(&priv->static_config); 3171 3172 return rc; 3173} 3174 3175static void sja1105_teardown(struct dsa_switch *ds) 3176{ 3177 struct sja1105_private *priv = ds->priv; 3178 3179 rtnl_lock(); 3180 dsa_tag_8021q_unregister(ds); 3181 rtnl_unlock(); 3182 3183 sja1105_devlink_teardown(ds); 3184 sja1105_mdiobus_unregister(ds); 3185 sja1105_ptp_clock_unregister(ds); 3186 sja1105_flower_teardown(ds); 3187 sja1105_tas_teardown(ds); 3188 sja1105_static_config_free(&priv->static_config); 3189} 3190 3191static const struct phylink_mac_ops sja1105_phylink_mac_ops = { 3192 .mac_select_pcs = sja1105_mac_select_pcs, 3193 .mac_config = sja1105_mac_config, 3194 .mac_link_up = sja1105_mac_link_up, 3195 .mac_link_down = sja1105_mac_link_down, 3196}; 3197 3198static const struct dsa_switch_ops sja1105_switch_ops = { 3199 .get_tag_protocol = sja1105_get_tag_protocol, 3200 .connect_tag_protocol = sja1105_connect_tag_protocol, 3201 .setup = sja1105_setup, 3202 .teardown = sja1105_teardown, 3203 .set_ageing_time = sja1105_set_ageing_time, 3204 .port_change_mtu = sja1105_change_mtu, 3205 .port_max_mtu = sja1105_get_max_mtu, 3206 .phylink_get_caps = sja1105_phylink_get_caps, 3207 .get_strings = sja1105_get_strings, 3208 .get_ethtool_stats = sja1105_get_ethtool_stats, 3209 .get_sset_count = sja1105_get_sset_count, 3210 .get_ts_info = sja1105_get_ts_info, 3211 .port_fdb_dump = sja1105_fdb_dump, 3212 .port_fdb_add = sja1105_fdb_add, 3213 .port_fdb_del = sja1105_fdb_del, 3214 .port_fast_age = sja1105_fast_age, 3215 .port_bridge_join = sja1105_bridge_join, 3216 .port_bridge_leave = sja1105_bridge_leave, 3217 .port_pre_bridge_flags = sja1105_port_pre_bridge_flags, 3218 .port_bridge_flags = sja1105_port_bridge_flags, 3219 .port_stp_state_set = sja1105_bridge_stp_state_set, 3220 .port_vlan_filtering = sja1105_vlan_filtering, 3221 .port_vlan_add = sja1105_bridge_vlan_add, 3222 .port_vlan_del = sja1105_bridge_vlan_del, 3223 .port_mdb_add = sja1105_mdb_add, 3224 .port_mdb_del = sja1105_mdb_del, 3225 .port_hwtstamp_get = sja1105_hwtstamp_get, 3226 .port_hwtstamp_set = sja1105_hwtstamp_set, 3227 .port_rxtstamp = sja1105_port_rxtstamp, 3228 .port_txtstamp = sja1105_port_txtstamp, 3229 .port_setup_tc = sja1105_port_setup_tc, 3230 .port_mirror_add = sja1105_mirror_add, 3231 .port_mirror_del = sja1105_mirror_del, 3232 .port_policer_add = sja1105_port_policer_add, 3233 .port_policer_del = sja1105_port_policer_del, 3234 .cls_flower_add = sja1105_cls_flower_add, 3235 .cls_flower_del = sja1105_cls_flower_del, 3236 .cls_flower_stats = sja1105_cls_flower_stats, 3237 .devlink_info_get = sja1105_devlink_info_get, 3238 .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add, 3239 .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del, 3240 .port_prechangeupper = sja1105_prechangeupper, 3241}; 3242 3243static const struct of_device_id sja1105_dt_ids[]; 3244 3245static int sja1105_check_device_id(struct sja1105_private *priv) 3246{ 3247 const struct sja1105_regs *regs = priv->info->regs; 3248 u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0}; 3249 struct device *dev = &priv->spidev->dev; 3250 const struct of_device_id *match; 3251 u32 device_id; 3252 u64 part_no; 3253 int rc; 3254 3255 rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id, 3256 NULL); 3257 if (rc < 0) 3258 return rc; 3259 3260 rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id, 3261 SJA1105_SIZE_DEVICE_ID); 3262 if (rc < 0) 3263 return rc; 3264 3265 sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID); 3266 3267 for (match = sja1105_dt_ids; match->compatible[0]; match++) { 3268 const struct sja1105_info *info = match->data; 3269 3270 /* Is what's been probed in our match table at all? */ 3271 if (info->device_id != device_id || info->part_no != part_no) 3272 continue; 3273 3274 /* But is it what's in the device tree? */ 3275 if (priv->info->device_id != device_id || 3276 priv->info->part_no != part_no) { 3277 dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n", 3278 priv->info->name, info->name); 3279 /* It isn't. No problem, pick that up. */ 3280 priv->info = info; 3281 } 3282 3283 return 0; 3284 } 3285 3286 dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n", 3287 device_id, part_no); 3288 3289 return -ENODEV; 3290} 3291 3292static int sja1105_probe(struct spi_device *spi) 3293{ 3294 struct device *dev = &spi->dev; 3295 struct sja1105_private *priv; 3296 size_t max_xfer, max_msg; 3297 struct dsa_switch *ds; 3298 int rc; 3299 3300 if (!dev->of_node) { 3301 dev_err(dev, "No DTS bindings for SJA1105 driver\n"); 3302 return -EINVAL; 3303 } 3304 3305 rc = sja1105_hw_reset(dev, 1, 1); 3306 if (rc) 3307 return rc; 3308 3309 priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL); 3310 if (!priv) 3311 return -ENOMEM; 3312 3313 /* Populate our driver private structure (priv) based on 3314 * the device tree node that was probed (spi) 3315 */ 3316 priv->spidev = spi; 3317 spi_set_drvdata(spi, priv); 3318 3319 /* Configure the SPI bus */ 3320 spi->bits_per_word = 8; 3321 rc = spi_setup(spi); 3322 if (rc < 0) { 3323 dev_err(dev, "Could not init SPI\n"); 3324 return rc; 3325 } 3326 3327 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers: 3328 * a small one for the message header and another one for the current 3329 * chunk of the packed buffer. 3330 * Check that the restrictions imposed by the SPI controller are 3331 * respected: the chunk buffer is smaller than the max transfer size, 3332 * and the total length of the chunk plus its message header is smaller 3333 * than the max message size. 3334 * We do that during probe time since the maximum transfer size is a 3335 * runtime invariant. 3336 */ 3337 max_xfer = spi_max_transfer_size(spi); 3338 max_msg = spi_max_message_size(spi); 3339 3340 /* We need to send at least one 64-bit word of SPI payload per message 3341 * in order to be able to make useful progress. 3342 */ 3343 if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) { 3344 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n"); 3345 return -EINVAL; 3346 } 3347 3348 priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN; 3349 if (priv->max_xfer_len > max_xfer) 3350 priv->max_xfer_len = max_xfer; 3351 if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER) 3352 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER; 3353 3354 priv->info = of_device_get_match_data(dev); 3355 3356 /* Detect hardware device */ 3357 rc = sja1105_check_device_id(priv); 3358 if (rc < 0) { 3359 dev_err(dev, "Device ID check failed: %d\n", rc); 3360 return rc; 3361 } 3362 3363 dev_info(dev, "Probed switch chip: %s\n", priv->info->name); 3364 3365 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 3366 if (!ds) 3367 return -ENOMEM; 3368 3369 ds->dev = dev; 3370 ds->num_ports = priv->info->num_ports; 3371 ds->ops = &sja1105_switch_ops; 3372 ds->phylink_mac_ops = &sja1105_phylink_mac_ops; 3373 ds->priv = priv; 3374 priv->ds = ds; 3375 3376 mutex_init(&priv->ptp_data.lock); 3377 mutex_init(&priv->dynamic_config_lock); 3378 mutex_init(&priv->mgmt_lock); 3379 mutex_init(&priv->fdb_lock); 3380 spin_lock_init(&priv->ts_id_lock); 3381 3382 rc = sja1105_parse_dt(priv); 3383 if (rc < 0) { 3384 dev_err(ds->dev, "Failed to parse DT: %d\n", rc); 3385 return rc; 3386 } 3387 3388 if (IS_ENABLED(CONFIG_NET_SCH_CBS)) { 3389 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers, 3390 sizeof(struct sja1105_cbs_entry), 3391 GFP_KERNEL); 3392 if (!priv->cbs) 3393 return -ENOMEM; 3394 } 3395 3396 return dsa_register_switch(priv->ds); 3397} 3398 3399static void sja1105_remove(struct spi_device *spi) 3400{ 3401 struct sja1105_private *priv = spi_get_drvdata(spi); 3402 3403 if (!priv) 3404 return; 3405 3406 dsa_unregister_switch(priv->ds); 3407} 3408 3409static void sja1105_shutdown(struct spi_device *spi) 3410{ 3411 struct sja1105_private *priv = spi_get_drvdata(spi); 3412 3413 if (!priv) 3414 return; 3415 3416 dsa_switch_shutdown(priv->ds); 3417 3418 spi_set_drvdata(spi, NULL); 3419} 3420 3421static const struct of_device_id sja1105_dt_ids[] = { 3422 { .compatible = "nxp,sja1105e", .data = &sja1105e_info }, 3423 { .compatible = "nxp,sja1105t", .data = &sja1105t_info }, 3424 { .compatible = "nxp,sja1105p", .data = &sja1105p_info }, 3425 { .compatible = "nxp,sja1105q", .data = &sja1105q_info }, 3426 { .compatible = "nxp,sja1105r", .data = &sja1105r_info }, 3427 { .compatible = "nxp,sja1105s", .data = &sja1105s_info }, 3428 { .compatible = "nxp,sja1110a", .data = &sja1110a_info }, 3429 { .compatible = "nxp,sja1110b", .data = &sja1110b_info }, 3430 { .compatible = "nxp,sja1110c", .data = &sja1110c_info }, 3431 { .compatible = "nxp,sja1110d", .data = &sja1110d_info }, 3432 { /* sentinel */ }, 3433}; 3434MODULE_DEVICE_TABLE(of, sja1105_dt_ids); 3435 3436static const struct spi_device_id sja1105_spi_ids[] = { 3437 { "sja1105e" }, 3438 { "sja1105t" }, 3439 { "sja1105p" }, 3440 { "sja1105q" }, 3441 { "sja1105r" }, 3442 { "sja1105s" }, 3443 { "sja1110a" }, 3444 { "sja1110b" }, 3445 { "sja1110c" }, 3446 { "sja1110d" }, 3447 { }, 3448}; 3449MODULE_DEVICE_TABLE(spi, sja1105_spi_ids); 3450 3451static struct spi_driver sja1105_driver = { 3452 .driver = { 3453 .name = "sja1105", 3454 .of_match_table = of_match_ptr(sja1105_dt_ids), 3455 }, 3456 .id_table = sja1105_spi_ids, 3457 .probe = sja1105_probe, 3458 .remove = sja1105_remove, 3459 .shutdown = sja1105_shutdown, 3460}; 3461 3462module_spi_driver(sja1105_driver); 3463 3464MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>"); 3465MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>"); 3466MODULE_DESCRIPTION("SJA1105 Driver"); 3467MODULE_LICENSE("GPL v2");
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