FILE
felix_vsc9959.c
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linux-6.19.14/drivers/net/dsa/ocelot/felix_vsc9959.c
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5#include <linux/fsl/enetc_mdio.h> 6#include <soc/mscc/ocelot_qsys.h> 7#include <soc/mscc/ocelot_vcap.h> 8#include <soc/mscc/ocelot_ana.h> 9#include <soc/mscc/ocelot_dev.h> 10#include <soc/mscc/ocelot_ptp.h> 11#include <soc/mscc/ocelot_sys.h> 12#include <net/tc_act/tc_gate.h> 13#include <soc/mscc/ocelot.h> 14#include <linux/dsa/ocelot.h> 15#include <linux/pcs-lynx.h> 16#include <net/pkt_sched.h> 17#include <linux/iopoll.h> 18#include <linux/mdio.h> 19#include <linux/of.h> 20#include <linux/pci.h> 21#include <linux/time.h> 22#include "felix.h" 23 24#define VSC9959_NUM_PORTS 6 25 26#define VSC9959_TAS_GCL_ENTRY_MAX 63 27#define VSC9959_TAS_MIN_GATE_LEN_NS 35 28#define VSC9959_VCAP_POLICER_BASE 63 29#define VSC9959_VCAP_POLICER_MAX 383 30#define VSC9959_SWITCH_PCI_BAR 4 31#define VSC9959_IMDIO_PCI_BAR 0 32 33#define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 34 OCELOT_PORT_MODE_QSGMII | \ 35 OCELOT_PORT_MODE_1000BASEX | \ 36 OCELOT_PORT_MODE_2500BASEX | \ 37 OCELOT_PORT_MODE_USXGMII | \ 38 OCELOT_PORT_MODE_10G_QXGMII) 39 40static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 41 VSC9959_PORT_MODE_SERDES, 42 VSC9959_PORT_MODE_SERDES, 43 VSC9959_PORT_MODE_SERDES, 44 VSC9959_PORT_MODE_SERDES, 45 OCELOT_PORT_MODE_INTERNAL, 46 OCELOT_PORT_MODE_INTERNAL, 47}; 48 49static const u32 vsc9959_ana_regmap[] = { 50 REG(ANA_ADVLEARN, 0x0089a0), 51 REG(ANA_VLANMASK, 0x0089a4), 52 REG_RESERVED(ANA_PORT_B_DOMAIN), 53 REG(ANA_ANAGEFIL, 0x0089ac), 54 REG(ANA_ANEVENTS, 0x0089b0), 55 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 56 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 57 REG(ANA_ISOLATED_PORTS, 0x0089c8), 58 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 59 REG(ANA_AUTOAGE, 0x0089d0), 60 REG(ANA_MACTOPTIONS, 0x0089d4), 61 REG(ANA_LEARNDISC, 0x0089d8), 62 REG(ANA_AGENCTRL, 0x0089dc), 63 REG(ANA_MIRRORPORTS, 0x0089e0), 64 REG(ANA_EMIRRORPORTS, 0x0089e4), 65 REG(ANA_FLOODING, 0x0089e8), 66 REG(ANA_FLOODING_IPMC, 0x008a08), 67 REG(ANA_SFLOW_CFG, 0x008a0c), 68 REG(ANA_PORT_MODE, 0x008a28), 69 REG(ANA_CUT_THRU_CFG, 0x008a48), 70 REG(ANA_PGID_PGID, 0x008400), 71 REG(ANA_TABLES_ANMOVED, 0x007f1c), 72 REG(ANA_TABLES_MACHDATA, 0x007f20), 73 REG(ANA_TABLES_MACLDATA, 0x007f24), 74 REG(ANA_TABLES_STREAMDATA, 0x007f28), 75 REG(ANA_TABLES_MACACCESS, 0x007f2c), 76 REG(ANA_TABLES_MACTINDX, 0x007f30), 77 REG(ANA_TABLES_VLANACCESS, 0x007f34), 78 REG(ANA_TABLES_VLANTIDX, 0x007f38), 79 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 80 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 81 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 82 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 83 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 84 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 85 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 86 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 87 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 88 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 89 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 90 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 91 REG(ANA_MSTI_STATE, 0x008600), 92 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 93 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 94 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 95 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 96 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 97 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 98 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 99 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 100 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 101 REG(ANA_SG_STATUS_REG_1, 0x008980), 102 REG(ANA_SG_STATUS_REG_2, 0x008984), 103 REG(ANA_SG_STATUS_REG_3, 0x008988), 104 REG(ANA_PORT_VLAN_CFG, 0x007800), 105 REG(ANA_PORT_DROP_CFG, 0x007804), 106 REG(ANA_PORT_QOS_CFG, 0x007808), 107 REG(ANA_PORT_VCAP_CFG, 0x00780c), 108 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 109 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 110 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 111 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 112 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 113 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 114 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 115 REG(ANA_PORT_PORT_CFG, 0x007870), 116 REG(ANA_PORT_POL_CFG, 0x007874), 117 REG(ANA_PORT_PTP_CFG, 0x007878), 118 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 119 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 120 REG(ANA_PORT_SFID_CFG, 0x007884), 121 REG(ANA_PFC_PFC_CFG, 0x008800), 122 REG_RESERVED(ANA_PFC_PFC_TIMER), 123 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 124 REG_RESERVED(ANA_IPT_IPT), 125 REG_RESERVED(ANA_PPT_PPT), 126 REG_RESERVED(ANA_FID_MAP_FID_MAP), 127 REG(ANA_AGGR_CFG, 0x008a68), 128 REG(ANA_CPUQ_CFG, 0x008a6c), 129 REG_RESERVED(ANA_CPUQ_CFG2), 130 REG(ANA_CPUQ_8021_CFG, 0x008a74), 131 REG(ANA_DSCP_CFG, 0x008ab4), 132 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 133 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 134 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 135 REG_RESERVED(ANA_VRAP_CFG), 136 REG_RESERVED(ANA_VRAP_HDR_DATA), 137 REG_RESERVED(ANA_VRAP_HDR_MASK), 138 REG(ANA_DISCARD_CFG, 0x008c40), 139 REG(ANA_FID_CFG, 0x008c44), 140 REG(ANA_POL_PIR_CFG, 0x004000), 141 REG(ANA_POL_CIR_CFG, 0x004004), 142 REG(ANA_POL_MODE_CFG, 0x004008), 143 REG(ANA_POL_PIR_STATE, 0x00400c), 144 REG(ANA_POL_CIR_STATE, 0x004010), 145 REG_RESERVED(ANA_POL_STATE), 146 REG(ANA_POL_FLOWC, 0x008c48), 147 REG(ANA_POL_HYST, 0x008cb4), 148 REG_RESERVED(ANA_POL_MISC_CFG), 149}; 150 151static const u32 vsc9959_qs_regmap[] = { 152 REG(QS_XTR_GRP_CFG, 0x000000), 153 REG(QS_XTR_RD, 0x000008), 154 REG(QS_XTR_FRM_PRUNING, 0x000010), 155 REG(QS_XTR_FLUSH, 0x000018), 156 REG(QS_XTR_DATA_PRESENT, 0x00001c), 157 REG(QS_XTR_CFG, 0x000020), 158 REG(QS_INJ_GRP_CFG, 0x000024), 159 REG(QS_INJ_WR, 0x00002c), 160 REG(QS_INJ_CTRL, 0x000034), 161 REG(QS_INJ_STATUS, 0x00003c), 162 REG(QS_INJ_ERR, 0x000040), 163 REG_RESERVED(QS_INH_DBG), 164}; 165 166static const u32 vsc9959_vcap_regmap[] = { 167 /* VCAP_CORE_CFG */ 168 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 169 REG(VCAP_CORE_MV_CFG, 0x000004), 170 /* VCAP_CORE_CACHE */ 171 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 172 REG(VCAP_CACHE_MASK_DAT, 0x000108), 173 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 174 REG(VCAP_CACHE_CNT_DAT, 0x000308), 175 REG(VCAP_CACHE_TG_DAT, 0x000388), 176 /* VCAP_CONST */ 177 REG(VCAP_CONST_VCAP_VER, 0x000398), 178 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 179 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 180 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 181 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 182 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 183 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 184 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 185 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 186 REG(VCAP_CONST_IF_CNT, 0x0003bc), 187}; 188 189static const u32 vsc9959_qsys_regmap[] = { 190 REG(QSYS_PORT_MODE, 0x00f460), 191 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 192 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 193 REG(QSYS_EEE_CFG, 0x00f4a0), 194 REG(QSYS_EEE_THRES, 0x00f4b8), 195 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 196 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 197 REG(QSYS_SW_STATUS, 0x00f4c4), 198 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 199 REG_RESERVED(QSYS_PAD_CFG), 200 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 201 REG_RESERVED(QSYS_QMAP), 202 REG_RESERVED(QSYS_ISDX_SGRP), 203 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 204 REG(QSYS_TFRM_MISC, 0x00f50c), 205 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 206 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 207 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 208 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 209 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 210 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 211 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 212 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 213 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 214 REG(QSYS_RED_PROFILE, 0x00f534), 215 REG(QSYS_RES_QOS_MODE, 0x00f574), 216 REG(QSYS_RES_CFG, 0x00c000), 217 REG(QSYS_RES_STAT, 0x00c004), 218 REG(QSYS_EGR_DROP_MODE, 0x00f578), 219 REG(QSYS_EQ_CTRL, 0x00f57c), 220 REG_RESERVED(QSYS_EVENTS_CORE), 221 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 222 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 223 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 224 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 225 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 226 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 227 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 228 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 229 REG(QSYS_PREEMPTION_CFG, 0x00f664), 230 REG(QSYS_CIR_CFG, 0x000000), 231 REG(QSYS_EIR_CFG, 0x000004), 232 REG(QSYS_SE_CFG, 0x000008), 233 REG(QSYS_SE_DWRR_CFG, 0x00000c), 234 REG_RESERVED(QSYS_SE_CONNECT), 235 REG(QSYS_SE_DLB_SENSE, 0x000040), 236 REG(QSYS_CIR_STATE, 0x000044), 237 REG(QSYS_EIR_STATE, 0x000048), 238 REG_RESERVED(QSYS_SE_STATE), 239 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 240 REG(QSYS_TAG_CONFIG, 0x00f680), 241 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 242 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 243 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 244 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 245 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 246 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 247 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 248 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 249 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 250 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 251 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 252 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 253 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 254 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 255 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 256 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 257 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 258 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 259 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 260 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 261}; 262 263static const u32 vsc9959_rew_regmap[] = { 264 REG(REW_PORT_VLAN_CFG, 0x000000), 265 REG(REW_TAG_CFG, 0x000004), 266 REG(REW_PORT_CFG, 0x000008), 267 REG(REW_DSCP_CFG, 0x00000c), 268 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 269 REG(REW_PTP_CFG, 0x000050), 270 REG(REW_PTP_DLY1_CFG, 0x000054), 271 REG(REW_RED_TAG_CFG, 0x000058), 272 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 273 REG(REW_DSCP_REMAP_CFG, 0x000510), 274 REG_RESERVED(REW_STAT_CFG), 275 REG_RESERVED(REW_REW_STICKY), 276 REG_RESERVED(REW_PPT), 277}; 278 279static const u32 vsc9959_sys_regmap[] = { 280 REG(SYS_COUNT_RX_OCTETS, 0x000000), 281 REG(SYS_COUNT_RX_UNICAST, 0x000004), 282 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 283 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 284 REG(SYS_COUNT_RX_SHORTS, 0x000010), 285 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 286 REG(SYS_COUNT_RX_JABBERS, 0x000018), 287 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 288 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 289 REG(SYS_COUNT_RX_64, 0x000024), 290 REG(SYS_COUNT_RX_65_127, 0x000028), 291 REG(SYS_COUNT_RX_128_255, 0x00002c), 292 REG(SYS_COUNT_RX_256_511, 0x000030), 293 REG(SYS_COUNT_RX_512_1023, 0x000034), 294 REG(SYS_COUNT_RX_1024_1526, 0x000038), 295 REG(SYS_COUNT_RX_1527_MAX, 0x00003c), 296 REG(SYS_COUNT_RX_PAUSE, 0x000040), 297 REG(SYS_COUNT_RX_CONTROL, 0x000044), 298 REG(SYS_COUNT_RX_LONGS, 0x000048), 299 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), 300 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), 301 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), 302 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), 303 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), 304 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), 305 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), 306 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), 307 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), 308 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), 309 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), 310 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), 311 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), 312 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), 313 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), 314 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), 315 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), 316 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), 317 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), 318 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), 319 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), 320 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), 321 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), 322 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), 323 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), 324 REG(SYS_COUNT_RX_ASSEMBLY_ERRS, 0x0000b0), 325 REG(SYS_COUNT_RX_SMD_ERRS, 0x0000b4), 326 REG(SYS_COUNT_RX_ASSEMBLY_OK, 0x0000b8), 327 REG(SYS_COUNT_RX_MERGE_FRAGMENTS, 0x0000bc), 328 REG(SYS_COUNT_RX_PMAC_OCTETS, 0x0000c0), 329 REG(SYS_COUNT_RX_PMAC_UNICAST, 0x0000c4), 330 REG(SYS_COUNT_RX_PMAC_MULTICAST, 0x0000c8), 331 REG(SYS_COUNT_RX_PMAC_BROADCAST, 0x0000cc), 332 REG(SYS_COUNT_RX_PMAC_SHORTS, 0x0000d0), 333 REG(SYS_COUNT_RX_PMAC_FRAGMENTS, 0x0000d4), 334 REG(SYS_COUNT_RX_PMAC_JABBERS, 0x0000d8), 335 REG(SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 0x0000dc), 336 REG(SYS_COUNT_RX_PMAC_SYM_ERRS, 0x0000e0), 337 REG(SYS_COUNT_RX_PMAC_64, 0x0000e4), 338 REG(SYS_COUNT_RX_PMAC_65_127, 0x0000e8), 339 REG(SYS_COUNT_RX_PMAC_128_255, 0x0000ec), 340 REG(SYS_COUNT_RX_PMAC_256_511, 0x0000f0), 341 REG(SYS_COUNT_RX_PMAC_512_1023, 0x0000f4), 342 REG(SYS_COUNT_RX_PMAC_1024_1526, 0x0000f8), 343 REG(SYS_COUNT_RX_PMAC_1527_MAX, 0x0000fc), 344 REG(SYS_COUNT_RX_PMAC_PAUSE, 0x000100), 345 REG(SYS_COUNT_RX_PMAC_CONTROL, 0x000104), 346 REG(SYS_COUNT_RX_PMAC_LONGS, 0x000108), 347 REG(SYS_COUNT_TX_OCTETS, 0x000200), 348 REG(SYS_COUNT_TX_UNICAST, 0x000204), 349 REG(SYS_COUNT_TX_MULTICAST, 0x000208), 350 REG(SYS_COUNT_TX_BROADCAST, 0x00020c), 351 REG(SYS_COUNT_TX_COLLISION, 0x000210), 352 REG(SYS_COUNT_TX_DROPS, 0x000214), 353 REG(SYS_COUNT_TX_PAUSE, 0x000218), 354 REG(SYS_COUNT_TX_64, 0x00021c), 355 REG(SYS_COUNT_TX_65_127, 0x000220), 356 REG(SYS_COUNT_TX_128_255, 0x000224), 357 REG(SYS_COUNT_TX_256_511, 0x000228), 358 REG(SYS_COUNT_TX_512_1023, 0x00022c), 359 REG(SYS_COUNT_TX_1024_1526, 0x000230), 360 REG(SYS_COUNT_TX_1527_MAX, 0x000234), 361 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), 362 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), 363 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), 364 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), 365 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), 366 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), 367 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), 368 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), 369 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), 370 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), 371 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), 372 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), 373 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), 374 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), 375 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), 376 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), 377 REG(SYS_COUNT_TX_AGED, 0x000278), 378 REG(SYS_COUNT_TX_MM_HOLD, 0x00027c), 379 REG(SYS_COUNT_TX_MERGE_FRAGMENTS, 0x000280), 380 REG(SYS_COUNT_TX_PMAC_OCTETS, 0x000284), 381 REG(SYS_COUNT_TX_PMAC_UNICAST, 0x000288), 382 REG(SYS_COUNT_TX_PMAC_MULTICAST, 0x00028c), 383 REG(SYS_COUNT_TX_PMAC_BROADCAST, 0x000290), 384 REG(SYS_COUNT_TX_PMAC_PAUSE, 0x000294), 385 REG(SYS_COUNT_TX_PMAC_64, 0x000298), 386 REG(SYS_COUNT_TX_PMAC_65_127, 0x00029c), 387 REG(SYS_COUNT_TX_PMAC_128_255, 0x0002a0), 388 REG(SYS_COUNT_TX_PMAC_256_511, 0x0002a4), 389 REG(SYS_COUNT_TX_PMAC_512_1023, 0x0002a8), 390 REG(SYS_COUNT_TX_PMAC_1024_1526, 0x0002ac), 391 REG(SYS_COUNT_TX_PMAC_1527_MAX, 0x0002b0), 392 REG(SYS_COUNT_DROP_LOCAL, 0x000400), 393 REG(SYS_COUNT_DROP_TAIL, 0x000404), 394 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), 395 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), 396 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), 397 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), 398 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), 399 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), 400 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), 401 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), 402 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), 403 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), 404 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), 405 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), 406 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), 407 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), 408 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), 409 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), 410 REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800), 411 REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804), 412 REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808), 413 REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c), 414 REG(SYS_RESET_CFG, 0x000e00), 415 REG(SYS_SR_ETYPE_CFG, 0x000e04), 416 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 417 REG(SYS_PORT_MODE, 0x000e0c), 418 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 419 REG(SYS_FRM_AGING, 0x000e44), 420 REG(SYS_STAT_CFG, 0x000e48), 421 REG(SYS_SW_STATUS, 0x000e4c), 422 REG_RESERVED(SYS_MISC_CFG), 423 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 424 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 425 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 426 REG(SYS_PAUSE_CFG, 0x000ea0), 427 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 428 REG(SYS_ATOP, 0x000ec0), 429 REG(SYS_ATOP_TOT_CFG, 0x000edc), 430 REG(SYS_MAC_FC_CFG, 0x000ee0), 431 REG(SYS_MMGT, 0x000ef8), 432 REG_RESERVED(SYS_MMGT_FAST), 433 REG_RESERVED(SYS_EVENTS_DIF), 434 REG_RESERVED(SYS_EVENTS_CORE), 435 REG(SYS_PTP_STATUS, 0x000f14), 436 REG(SYS_PTP_TXSTAMP, 0x000f18), 437 REG(SYS_PTP_NXT, 0x000f1c), 438 REG(SYS_PTP_CFG, 0x000f20), 439 REG(SYS_RAM_INIT, 0x000f24), 440 REG_RESERVED(SYS_CM_ADDR), 441 REG_RESERVED(SYS_CM_DATA_WR), 442 REG_RESERVED(SYS_CM_DATA_RD), 443 REG_RESERVED(SYS_CM_OP), 444 REG_RESERVED(SYS_CM_DATA), 445}; 446 447static const u32 vsc9959_ptp_regmap[] = { 448 REG(PTP_PIN_CFG, 0x000000), 449 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 450 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 451 REG(PTP_PIN_TOD_NSEC, 0x00000c), 452 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 453 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 454 REG(PTP_CFG_MISC, 0x0000a0), 455 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 456 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 457}; 458 459static const u32 vsc9959_gcb_regmap[] = { 460 REG(GCB_SOFT_RST, 0x000004), 461}; 462 463static const u32 vsc9959_dev_gmii_regmap[] = { 464 REG(DEV_CLOCK_CFG, 0x0), 465 REG(DEV_PORT_MISC, 0x4), 466 REG(DEV_EVENTS, 0x8), 467 REG(DEV_EEE_CFG, 0xc), 468 REG(DEV_RX_PATH_DELAY, 0x10), 469 REG(DEV_TX_PATH_DELAY, 0x14), 470 REG(DEV_PTP_PREDICT_CFG, 0x18), 471 REG(DEV_MAC_ENA_CFG, 0x1c), 472 REG(DEV_MAC_MODE_CFG, 0x20), 473 REG(DEV_MAC_MAXLEN_CFG, 0x24), 474 REG(DEV_MAC_TAGS_CFG, 0x28), 475 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 476 REG(DEV_MAC_IFG_CFG, 0x30), 477 REG(DEV_MAC_HDX_CFG, 0x34), 478 REG(DEV_MAC_DBG_CFG, 0x38), 479 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 480 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 481 REG(DEV_MAC_STICKY, 0x44), 482 REG(DEV_MM_ENABLE_CONFIG, 0x48), 483 REG(DEV_MM_VERIF_CONFIG, 0x4C), 484 REG(DEV_MM_STATUS, 0x50), 485 REG_RESERVED(PCS1G_CFG), 486 REG_RESERVED(PCS1G_MODE_CFG), 487 REG_RESERVED(PCS1G_SD_CFG), 488 REG_RESERVED(PCS1G_ANEG_CFG), 489 REG_RESERVED(PCS1G_ANEG_NP_CFG), 490 REG_RESERVED(PCS1G_LB_CFG), 491 REG_RESERVED(PCS1G_DBG_CFG), 492 REG_RESERVED(PCS1G_CDET_CFG), 493 REG_RESERVED(PCS1G_ANEG_STATUS), 494 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 495 REG_RESERVED(PCS1G_LINK_STATUS), 496 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 497 REG_RESERVED(PCS1G_STICKY), 498 REG_RESERVED(PCS1G_DEBUG_STATUS), 499 REG_RESERVED(PCS1G_LPI_CFG), 500 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 501 REG_RESERVED(PCS1G_LPI_STATUS), 502 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 503 REG_RESERVED(PCS1G_TSTPAT_STATUS), 504 REG_RESERVED(DEV_PCS_FX100_CFG), 505 REG_RESERVED(DEV_PCS_FX100_STATUS), 506}; 507 508static const u32 *vsc9959_regmap[TARGET_MAX] = { 509 [ANA] = vsc9959_ana_regmap, 510 [QS] = vsc9959_qs_regmap, 511 [QSYS] = vsc9959_qsys_regmap, 512 [REW] = vsc9959_rew_regmap, 513 [SYS] = vsc9959_sys_regmap, 514 [S0] = vsc9959_vcap_regmap, 515 [S1] = vsc9959_vcap_regmap, 516 [S2] = vsc9959_vcap_regmap, 517 [PTP] = vsc9959_ptp_regmap, 518 [GCB] = vsc9959_gcb_regmap, 519 [DEV_GMII] = vsc9959_dev_gmii_regmap, 520}; 521 522/* Addresses are relative to the PCI device's base address */ 523static const struct resource vsc9959_resources[] = { 524 DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"), 525 DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"), 526 DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"), 527 DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"), 528 DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"), 529 DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"), 530 DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"), 531 DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"), 532 DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"), 533 DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"), 534 DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"), 535 DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"), 536 DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"), 537 DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"), 538 DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"), 539 DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"), 540}; 541 542static const char * const vsc9959_resource_names[TARGET_MAX] = { 543 [SYS] = "sys", 544 [REW] = "rew", 545 [S0] = "s0", 546 [S1] = "s1", 547 [S2] = "s2", 548 [GCB] = "devcpu_gcb", 549 [QS] = "qs", 550 [PTP] = "ptp", 551 [QSYS] = "qsys", 552 [ANA] = "ana", 553}; 554 555/* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 556 * SGMII/QSGMII MAC PCS can be found. 557 */ 558static const struct resource vsc9959_imdio_res = 559 DEFINE_RES_MEM_NAMED(0x8030, 0x10, "imdio"); 560 561static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 562 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 563 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 564 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 565 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 566 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 567 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 568 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 569 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 570 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 571 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 572 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 573 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 574 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 575 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 576 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 577 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 578 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 579 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 580 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 581 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 582 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 583 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 584 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 585 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 586 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 587 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 588 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 589 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 590 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 591 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 592 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 593 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 594 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 595 /* Replicated per number of ports (7), register size 4 per port */ 596 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 597 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 598 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 599 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 600 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 601 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 602 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 603 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 604 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 605 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 606 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 607 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 608 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 609}; 610 611static const struct vcap_field vsc9959_vcap_es0_keys[] = { 612 [VCAP_ES0_EGR_PORT] = { 0, 3}, 613 [VCAP_ES0_IGR_PORT] = { 3, 3}, 614 [VCAP_ES0_RSV] = { 6, 2}, 615 [VCAP_ES0_L2_MC] = { 8, 1}, 616 [VCAP_ES0_L2_BC] = { 9, 1}, 617 [VCAP_ES0_VID] = { 10, 12}, 618 [VCAP_ES0_DP] = { 22, 1}, 619 [VCAP_ES0_PCP] = { 23, 3}, 620}; 621 622static const struct vcap_field vsc9959_vcap_es0_actions[] = { 623 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 624 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 625 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 626 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 627 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 628 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 629 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 630 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 631 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 632 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 633 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 634 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 635 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 636 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 637 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 638 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 639 [VCAP_ES0_ACT_RSV] = { 49, 23}, 640 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 641}; 642 643static const struct vcap_field vsc9959_vcap_is1_keys[] = { 644 [VCAP_IS1_HK_TYPE] = { 0, 1}, 645 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 646 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 647 [VCAP_IS1_HK_RSV] = { 10, 9}, 648 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 649 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 650 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 651 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 652 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 653 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 654 [VCAP_IS1_HK_TPID] = { 25, 1}, 655 [VCAP_IS1_HK_VID] = { 26, 12}, 656 [VCAP_IS1_HK_DEI] = { 38, 1}, 657 [VCAP_IS1_HK_PCP] = { 39, 3}, 658 /* Specific Fields for IS1 Half Key S1_NORMAL */ 659 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 660 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 661 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 662 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 663 [VCAP_IS1_HK_IP4] = {108, 1}, 664 /* Layer-3 Information */ 665 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 666 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 667 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 668 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 669 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 670 /* Layer-4 Information */ 671 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 672 [VCAP_IS1_HK_TCP] = {151, 1}, 673 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 674 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 675 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 676 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 677 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 678 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 679 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 680 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 681 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 682 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 683 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 684 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 685 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 686 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 687 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 688 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 689 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 690 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 691 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 692}; 693 694static const struct vcap_field vsc9959_vcap_is1_actions[] = { 695 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 696 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 697 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 698 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 699 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 700 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 701 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 702 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 703 [VCAP_IS1_ACT_RSV] = { 29, 9}, 704 /* The fields below are incorrectly shifted by 2 in the manual */ 705 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 706 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 707 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 708 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 709 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 710 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 711 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 712 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 713 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 714 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 715 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 716}; 717 718static struct vcap_field vsc9959_vcap_is2_keys[] = { 719 /* Common: 41 bits */ 720 [VCAP_IS2_TYPE] = { 0, 4}, 721 [VCAP_IS2_HK_FIRST] = { 4, 1}, 722 [VCAP_IS2_HK_PAG] = { 5, 8}, 723 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 724 [VCAP_IS2_HK_RSV2] = { 20, 1}, 725 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 726 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 727 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 728 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 729 [VCAP_IS2_HK_VID] = { 25, 12}, 730 [VCAP_IS2_HK_DEI] = { 37, 1}, 731 [VCAP_IS2_HK_PCP] = { 38, 3}, 732 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 733 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 734 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 735 /* MAC_ETYPE (TYPE=000) */ 736 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 737 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 738 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 739 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 740 /* MAC_LLC (TYPE=001) */ 741 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 742 /* MAC_SNAP (TYPE=010) */ 743 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 744 /* MAC_ARP (TYPE=011) */ 745 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 746 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 747 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 748 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 749 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 750 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 751 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 752 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 753 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 754 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 755 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 756 /* IP4_TCP_UDP / IP4_OTHER common */ 757 [VCAP_IS2_HK_IP4] = { 41, 1}, 758 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 759 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 760 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 761 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 762 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 763 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 764 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 765 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 766 /* IP4_TCP_UDP (TYPE=100) */ 767 [VCAP_IS2_HK_TCP] = {119, 1}, 768 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 769 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 770 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 771 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 772 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 773 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 774 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 775 [VCAP_IS2_HK_L4_RST] = {164, 1}, 776 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 777 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 778 [VCAP_IS2_HK_L4_URG] = {167, 1}, 779 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 780 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 781 /* IP4_OTHER (TYPE=101) */ 782 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 783 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 784 /* IP6_STD (TYPE=110) */ 785 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 786 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 787 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 788 /* OAM (TYPE=111) */ 789 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 790 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 791 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 792 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 793 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 794 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 795 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 796}; 797 798static struct vcap_field vsc9959_vcap_is2_actions[] = { 799 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 800 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 801 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 802 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 803 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 804 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 805 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 806 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 807 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 808 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 809 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 810 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 811 [VCAP_IS2_ACT_RSV] = { 36, 2}, 812 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 813 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 814}; 815 816static struct vcap_props vsc9959_vcap_props[] = { 817 [VCAP_ES0] = { 818 .action_type_width = 0, 819 .action_table = { 820 [ES0_ACTION_TYPE_NORMAL] = { 821 .width = 72, /* HIT_STICKY not included */ 822 .count = 1, 823 }, 824 }, 825 .target = S0, 826 .keys = vsc9959_vcap_es0_keys, 827 .actions = vsc9959_vcap_es0_actions, 828 }, 829 [VCAP_IS1] = { 830 .action_type_width = 0, 831 .action_table = { 832 [IS1_ACTION_TYPE_NORMAL] = { 833 .width = 78, /* HIT_STICKY not included */ 834 .count = 4, 835 }, 836 }, 837 .target = S1, 838 .keys = vsc9959_vcap_is1_keys, 839 .actions = vsc9959_vcap_is1_actions, 840 }, 841 [VCAP_IS2] = { 842 .action_type_width = 1, 843 .action_table = { 844 [IS2_ACTION_TYPE_NORMAL] = { 845 .width = 44, 846 .count = 2 847 }, 848 [IS2_ACTION_TYPE_SMAC_SIP] = { 849 .width = 6, 850 .count = 4 851 }, 852 }, 853 .target = S2, 854 .keys = vsc9959_vcap_is2_keys, 855 .actions = vsc9959_vcap_is2_actions, 856 }, 857}; 858 859static const struct ptp_clock_info vsc9959_ptp_caps = { 860 .owner = THIS_MODULE, 861 .name = "felix ptp", 862 .max_adj = 0x7fffffff, 863 .n_alarm = 0, 864 .n_ext_ts = 0, 865 .n_per_out = OCELOT_PTP_PINS_NUM, 866 .n_pins = OCELOT_PTP_PINS_NUM, 867 .pps = 0, 868 .gettime64 = ocelot_ptp_gettime64, 869 .settime64 = ocelot_ptp_settime64, 870 .adjtime = ocelot_ptp_adjtime, 871 .adjfine = ocelot_ptp_adjfine, 872 .verify = ocelot_ptp_verify, 873 .enable = ocelot_ptp_enable, 874}; 875 876#define VSC9959_INIT_TIMEOUT 50000 877#define VSC9959_GCB_RST_SLEEP 100 878#define VSC9959_SYS_RAMINIT_SLEEP 80 879 880static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 881{ 882 int val; 883 884 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 885 886 return val; 887} 888 889static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 890{ 891 return ocelot_read(ocelot, SYS_RAM_INIT); 892} 893 894/* CORE_ENA is in SYS:SYSTEM:RESET_CFG 895 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 896 */ 897static int vsc9959_reset(struct ocelot *ocelot) 898{ 899 int val, err; 900 901 /* soft-reset the switch core */ 902 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 903 904 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 905 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 906 if (err) { 907 dev_err(ocelot->dev, "timeout: switch core reset\n"); 908 return err; 909 } 910 911 /* initialize switch mem ~40us */ 912 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 913 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 914 VSC9959_SYS_RAMINIT_SLEEP, 915 VSC9959_INIT_TIMEOUT); 916 if (err) { 917 dev_err(ocelot->dev, "timeout: switch sram init\n"); 918 return err; 919 } 920 921 /* enable switch core */ 922 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 923 924 return 0; 925} 926 927/* Watermark encode 928 * Bit 8: Unit; 0:1, 1:16 929 * Bit 7-0: Value to be multiplied with unit 930 */ 931static u16 vsc9959_wm_enc(u16 value) 932{ 933 WARN_ON(value >= 16 * BIT(8)); 934 935 if (value >= BIT(8)) 936 return BIT(8) | (value / 16); 937 938 return value; 939} 940 941static u16 vsc9959_wm_dec(u16 wm) 942{ 943 WARN_ON(wm & ~GENMASK(8, 0)); 944 945 if (wm & BIT(8)) 946 return (wm & GENMASK(7, 0)) * 16; 947 948 return wm; 949} 950 951static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 952{ 953 *inuse = (val & GENMASK(23, 12)) >> 12; 954 *maxuse = val & GENMASK(11, 0); 955} 956 957static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 958{ 959 struct pci_dev *pdev = to_pci_dev(ocelot->dev); 960 struct felix *felix = ocelot_to_felix(ocelot); 961 struct enetc_mdio_priv *mdio_priv; 962 struct device *dev = ocelot->dev; 963 resource_size_t imdio_base; 964 void __iomem *imdio_regs; 965 struct resource res; 966 struct enetc_hw *hw; 967 struct mii_bus *bus; 968 int port; 969 int rc; 970 971 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 972 sizeof(struct phylink_pcs *), 973 GFP_KERNEL); 974 if (!felix->pcs) { 975 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 976 return -ENOMEM; 977 } 978 979 imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 980 981 memcpy(&res, &vsc9959_imdio_res, sizeof(res)); 982 res.start += imdio_base; 983 res.end += imdio_base; 984 985 imdio_regs = devm_ioremap_resource(dev, &res); 986 if (IS_ERR(imdio_regs)) 987 return PTR_ERR(imdio_regs); 988 989 hw = enetc_hw_alloc(dev, imdio_regs); 990 if (IS_ERR(hw)) { 991 dev_err(dev, "failed to allocate ENETC HW structure\n"); 992 return PTR_ERR(hw); 993 } 994 995 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 996 if (!bus) 997 return -ENOMEM; 998 999 bus->name = "VSC9959 internal MDIO bus"; 1000 bus->read = enetc_mdio_read_c22; 1001 bus->write = enetc_mdio_write_c22; 1002 bus->read_c45 = enetc_mdio_read_c45; 1003 bus->write_c45 = enetc_mdio_write_c45; 1004 bus->parent = dev; 1005 mdio_priv = bus->priv; 1006 mdio_priv->hw = hw; 1007 /* This gets added to imdio_regs, which already maps addresses 1008 * starting with the proper offset. 1009 */ 1010 mdio_priv->mdio_base = 0; 1011 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1012 1013 /* Needed in order to initialize the bus mutex lock */ 1014 rc = mdiobus_register(bus); 1015 if (rc < 0) { 1016 dev_err(dev, "failed to register MDIO bus\n"); 1017 mdiobus_free(bus); 1018 return rc; 1019 } 1020 1021 felix->imdio = bus; 1022 1023 for (port = 0; port < felix->info->num_ports; port++) { 1024 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1025 struct phylink_pcs *phylink_pcs; 1026 1027 if (dsa_is_unused_port(felix->ds, port)) 1028 continue; 1029 1030 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1031 continue; 1032 1033 phylink_pcs = lynx_pcs_create_mdiodev(felix->imdio, port); 1034 if (IS_ERR(phylink_pcs)) 1035 continue; 1036 1037 felix->pcs[port] = phylink_pcs; 1038 1039 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1040 } 1041 1042 return 0; 1043} 1044 1045static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1046{ 1047 struct felix *felix = ocelot_to_felix(ocelot); 1048 int port; 1049 1050 for (port = 0; port < ocelot->num_phys_ports; port++) { 1051 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1052 1053 if (phylink_pcs) 1054 lynx_pcs_destroy(phylink_pcs); 1055 } 1056 mdiobus_unregister(felix->imdio); 1057 mdiobus_free(felix->imdio); 1058} 1059 1060/* The switch considers any frame (regardless of size) as eligible 1061 * for transmission if the traffic class gate is open for at least 1062 * VSC9959_TAS_MIN_GATE_LEN_NS. 1063 * 1064 * Overruns are prevented by cropping an interval at the end of the gate time 1065 * slot for which egress scheduling is blocked, but we need to still keep 1066 * VSC9959_TAS_MIN_GATE_LEN_NS available for one packet to be transmitted, 1067 * otherwise the port tc will hang. 1068 * 1069 * This function returns the size of a gate interval that remains available for 1070 * setting the guard band, after reserving the space for one egress frame. 1071 */ 1072static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns) 1073{ 1074 /* Gate always open */ 1075 if (gate_len_ns == U64_MAX) 1076 return U64_MAX; 1077 1078 if (gate_len_ns < VSC9959_TAS_MIN_GATE_LEN_NS) 1079 return 0; 1080 1081 return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC; 1082} 1083 1084/* Extract shortest continuous gate open intervals in ns for each traffic class 1085 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 1086 * considered U64_MAX. If the gate is always closed, it is considered 0. 1087 */ 1088static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 1089 u64 min_gate_len[OCELOT_NUM_TC]) 1090{ 1091 struct tc_taprio_sched_entry *entry; 1092 u64 gate_len[OCELOT_NUM_TC]; 1093 u8 gates_ever_opened = 0; 1094 int tc, i, n; 1095 1096 /* Initialize arrays */ 1097 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1098 min_gate_len[tc] = U64_MAX; 1099 gate_len[tc] = 0; 1100 } 1101 1102 /* If we don't have taprio, consider all gates as permanently open */ 1103 if (!taprio) 1104 return; 1105 1106 n = taprio->num_entries; 1107 1108 /* Walk through the gate list twice to determine the length 1109 * of consecutively open gates for a traffic class, including 1110 * open gates that wrap around. We are just interested in the 1111 * minimum window size, and this doesn't change what the 1112 * minimum is (if the gate never closes, min_gate_len will 1113 * remain U64_MAX). 1114 */ 1115 for (i = 0; i < 2 * n; i++) { 1116 entry = &taprio->entries[i % n]; 1117 1118 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1119 if (entry->gate_mask & BIT(tc)) { 1120 gate_len[tc] += entry->interval; 1121 gates_ever_opened |= BIT(tc); 1122 } else { 1123 /* Gate closes now, record a potential new 1124 * minimum and reinitialize length 1125 */ 1126 if (min_gate_len[tc] > gate_len[tc] && 1127 gate_len[tc]) 1128 min_gate_len[tc] = gate_len[tc]; 1129 gate_len[tc] = 0; 1130 } 1131 } 1132 } 1133 1134 /* min_gate_len[tc] actually tracks minimum *open* gate time, so for 1135 * permanently closed gates, min_gate_len[tc] will still be U64_MAX. 1136 * Therefore they are currently indistinguishable from permanently 1137 * open gates. Overwrite the gate len with 0 when we know they're 1138 * actually permanently closed, i.e. after the loop above. 1139 */ 1140 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 1141 if (!(gates_ever_opened & BIT(tc))) 1142 min_gate_len[tc] = 0; 1143} 1144 1145/* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ, 1146 * so we need to spell out the register access to each traffic class in helper 1147 * functions, to simplify callers 1148 */ 1149static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc, 1150 u32 max_sdu) 1151{ 1152 switch (tc) { 1153 case 0: 1154 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 1155 port); 1156 break; 1157 case 1: 1158 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 1159 port); 1160 break; 1161 case 2: 1162 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 1163 port); 1164 break; 1165 case 3: 1166 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 1167 port); 1168 break; 1169 case 4: 1170 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 1171 port); 1172 break; 1173 case 5: 1174 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 1175 port); 1176 break; 1177 case 6: 1178 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 1179 port); 1180 break; 1181 case 7: 1182 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 1183 port); 1184 break; 1185 } 1186} 1187 1188static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc) 1189{ 1190 switch (tc) { 1191 case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port); 1192 case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port); 1193 case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port); 1194 case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port); 1195 case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port); 1196 case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port); 1197 case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port); 1198 case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port); 1199 default: 1200 return 0; 1201 } 1202} 1203 1204static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc) 1205{ 1206 if (!taprio || !taprio->max_sdu[tc]) 1207 return 0; 1208 1209 return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN; 1210} 1211 1212/* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 1213 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 1214 * values (the default value is 1518). Also, for traffic class windows smaller 1215 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 1216 * dropping, such that these won't hang the port, as they will never be sent. 1217 */ 1218static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 1219{ 1220 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1221 struct ocelot_mm_state *mm = &ocelot->mm[port]; 1222 struct tc_taprio_qopt_offload *taprio; 1223 u64 min_gate_len[OCELOT_NUM_TC]; 1224 u32 val, maxlen, add_frag_size; 1225 u64 needed_min_frag_time_ps; 1226 int speed, picos_per_byte; 1227 u64 needed_bit_time_ps; 1228 u8 tas_speed; 1229 int tc; 1230 1231 lockdep_assert_held(&ocelot->fwd_domain_lock); 1232 1233 taprio = ocelot_port->taprio; 1234 1235 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1236 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 1237 1238 switch (tas_speed) { 1239 case OCELOT_SPEED_10: 1240 speed = SPEED_10; 1241 break; 1242 case OCELOT_SPEED_100: 1243 speed = SPEED_100; 1244 break; 1245 case OCELOT_SPEED_1000: 1246 speed = SPEED_1000; 1247 break; 1248 case OCELOT_SPEED_2500: 1249 speed = SPEED_2500; 1250 break; 1251 default: 1252 return; 1253 } 1254 1255 picos_per_byte = (USEC_PER_SEC * 8) / speed; 1256 1257 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 1258 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 1259 * manually in the bit time calculation, plus the preamble and SFD. 1260 */ 1261 maxlen = val + 2 * VLAN_HLEN; 1262 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 1263 * 4 octets FCS, 12 octets IFG. 1264 */ 1265 needed_bit_time_ps = (u64)(maxlen + 24) * picos_per_byte; 1266 1267 /* Preemptible TCs don't need to pass a full MTU, the port will 1268 * automatically emit a HOLD request when a preemptible TC gate closes 1269 */ 1270 val = ocelot_read_rix(ocelot, QSYS_PREEMPTION_CFG, port); 1271 add_frag_size = QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(val); 1272 needed_min_frag_time_ps = picos_per_byte * 1273 (u64)(24 + 2 * ethtool_mm_frag_size_add_to_min(add_frag_size)); 1274 1275 dev_dbg(ocelot->dev, 1276 "port %d: max frame size %d needs %llu ps, %llu ps for mPackets at speed %d\n", 1277 port, maxlen, needed_bit_time_ps, needed_min_frag_time_ps, 1278 speed); 1279 1280 vsc9959_tas_min_gate_lengths(taprio, min_gate_len); 1281 1282 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1283 u32 requested_max_sdu = vsc9959_tas_tc_max_sdu(taprio, tc); 1284 u64 remaining_gate_len_ps; 1285 u32 max_sdu; 1286 1287 remaining_gate_len_ps = 1288 vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]); 1289 1290 if ((mm->active_preemptible_tcs & BIT(tc)) ? 1291 remaining_gate_len_ps > needed_min_frag_time_ps : 1292 remaining_gate_len_ps > needed_bit_time_ps) { 1293 /* Setting QMAXSDU_CFG to 0 disables oversized frame 1294 * dropping. 1295 */ 1296 max_sdu = requested_max_sdu; 1297 dev_dbg(ocelot->dev, 1298 "port %d tc %d min gate len %llu" 1299 ", sending all frames\n", 1300 port, tc, min_gate_len[tc]); 1301 } else { 1302 /* If traffic class doesn't support a full MTU sized 1303 * frame, make sure to enable oversize frame dropping 1304 * for frames larger than the smallest that would fit. 1305 * 1306 * However, the exact same register, QSYS_QMAXSDU_CFG_*, 1307 * controls not only oversized frame dropping, but also 1308 * per-tc static guard band lengths, so it reduces the 1309 * useful gate interval length. Therefore, be careful 1310 * to calculate a guard band (and therefore max_sdu) 1311 * that still leaves VSC9959_TAS_MIN_GATE_LEN_NS 1312 * available in the time slot. 1313 */ 1314 max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte); 1315 /* A TC gate may be completely closed, which is a 1316 * special case where all packets are oversized. 1317 * Any limit smaller than 64 octets accomplishes this 1318 */ 1319 if (!max_sdu) 1320 max_sdu = 1; 1321 /* Take L1 overhead into account, but just don't allow 1322 * max_sdu to go negative or to 0. Here we use 20 1323 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 1324 * octets as part of packet size. 1325 */ 1326 if (max_sdu > 20) 1327 max_sdu -= 20; 1328 1329 if (requested_max_sdu && requested_max_sdu < max_sdu) 1330 max_sdu = requested_max_sdu; 1331 1332 dev_info(ocelot->dev, 1333 "port %d tc %d min gate length %llu" 1334 " ns not enough for max frame size %d at %d" 1335 " Mbps, dropping frames over %d" 1336 " octets including FCS\n", 1337 port, tc, min_gate_len[tc], maxlen, speed, 1338 max_sdu); 1339 } 1340 1341 vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu); 1342 } 1343 1344 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 1345 1346 ocelot->ops->cut_through_fwd(ocelot); 1347} 1348 1349static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1350 u32 speed) 1351{ 1352 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1353 u8 tas_speed; 1354 1355 switch (speed) { 1356 case SPEED_10: 1357 tas_speed = OCELOT_SPEED_10; 1358 break; 1359 case SPEED_100: 1360 tas_speed = OCELOT_SPEED_100; 1361 break; 1362 case SPEED_1000: 1363 tas_speed = OCELOT_SPEED_1000; 1364 break; 1365 case SPEED_2500: 1366 tas_speed = OCELOT_SPEED_2500; 1367 break; 1368 default: 1369 tas_speed = OCELOT_SPEED_1000; 1370 break; 1371 } 1372 1373 mutex_lock(&ocelot->fwd_domain_lock); 1374 1375 ocelot_rmw_rix(ocelot, 1376 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1377 QSYS_TAG_CONFIG_LINK_SPEED_M, 1378 QSYS_TAG_CONFIG, port); 1379 1380 if (ocelot_port->taprio) 1381 vsc9959_tas_guard_bands_update(ocelot, port); 1382 1383 mutex_unlock(&ocelot->fwd_domain_lock); 1384} 1385 1386static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1387 u64 cycle_time, 1388 struct timespec64 *new_base_ts) 1389{ 1390 struct timespec64 ts; 1391 ktime_t new_base_time; 1392 ktime_t current_time; 1393 1394 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1395 current_time = timespec64_to_ktime(ts); 1396 new_base_time = base_time; 1397 1398 if (base_time < current_time) { 1399 u64 nr_of_cycles = current_time - base_time; 1400 1401 do_div(nr_of_cycles, cycle_time); 1402 new_base_time += cycle_time * (nr_of_cycles + 1); 1403 } 1404 1405 *new_base_ts = ktime_to_timespec64(new_base_time); 1406} 1407 1408static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1409{ 1410 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1411} 1412 1413static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1414 struct tc_taprio_sched_entry *entry) 1415{ 1416 ocelot_write(ocelot, 1417 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1418 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1419 QSYS_GCL_CFG_REG_1); 1420 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1421} 1422 1423static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1424 struct tc_taprio_qopt_offload *taprio) 1425{ 1426 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1427 struct timespec64 base_ts; 1428 int ret, i; 1429 u32 val; 1430 1431 mutex_lock(&ocelot->fwd_domain_lock); 1432 1433 if (taprio->cmd == TAPRIO_CMD_DESTROY) { 1434 ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1435 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1436 QSYS_TAG_CONFIG, port); 1437 1438 taprio_offload_free(ocelot_port->taprio); 1439 ocelot_port->taprio = NULL; 1440 1441 vsc9959_tas_guard_bands_update(ocelot, port); 1442 1443 mutex_unlock(&ocelot->fwd_domain_lock); 1444 return 0; 1445 } else if (taprio->cmd != TAPRIO_CMD_REPLACE) { 1446 ret = -EOPNOTSUPP; 1447 goto err_unlock; 1448 } 1449 1450 ret = ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1451 if (ret) 1452 goto err_unlock; 1453 1454 if (taprio->cycle_time > NSEC_PER_SEC || 1455 taprio->cycle_time_extension >= NSEC_PER_SEC) { 1456 ret = -EINVAL; 1457 goto err_reset_tc; 1458 } 1459 1460 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 1461 ret = -ERANGE; 1462 goto err_reset_tc; 1463 } 1464 1465 /* Enable guard band. The switch will schedule frames without taking 1466 * their length into account. Thus we'll always need to enable the 1467 * guard band which reserves the time of a maximum sized frame at the 1468 * end of the time window. 1469 * 1470 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1471 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1472 * operate on the port number. 1473 */ 1474 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1475 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1476 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1477 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1478 QSYS_TAS_PARAM_CFG_CTRL); 1479 1480 /* Hardware errata - Admin config could not be overwritten if 1481 * config is pending, need reset the TAS module 1482 */ 1483 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1484 if (val & QSYS_TAG_CONFIG_ENABLE) { 1485 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1486 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 1487 ret = -EBUSY; 1488 goto err_reset_tc; 1489 } 1490 } 1491 1492 ocelot_rmw_rix(ocelot, 1493 QSYS_TAG_CONFIG_ENABLE | 1494 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1495 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1496 QSYS_TAG_CONFIG_ENABLE | 1497 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1498 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1499 QSYS_TAG_CONFIG, port); 1500 1501 vsc9959_new_base_time(ocelot, taprio->base_time, 1502 taprio->cycle_time, &base_ts); 1503 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1504 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1505 val = upper_32_bits(base_ts.tv_sec); 1506 ocelot_write(ocelot, 1507 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1508 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1509 QSYS_PARAM_CFG_REG_3); 1510 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1511 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1512 1513 for (i = 0; i < taprio->num_entries; i++) 1514 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1515 1516 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1517 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1518 QSYS_TAS_PARAM_CFG_CTRL); 1519 1520 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1521 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1522 10, 100000); 1523 if (ret) 1524 goto err_reset_tc; 1525 1526 ocelot_port->taprio = taprio_offload_get(taprio); 1527 vsc9959_tas_guard_bands_update(ocelot, port); 1528 1529 mutex_unlock(&ocelot->fwd_domain_lock); 1530 1531 return 0; 1532 1533err_reset_tc: 1534 taprio->mqprio.qopt.num_tc = 0; 1535 ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1536err_unlock: 1537 mutex_unlock(&ocelot->fwd_domain_lock); 1538 1539 return ret; 1540} 1541 1542static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 1543{ 1544 struct tc_taprio_qopt_offload *taprio; 1545 struct ocelot_port *ocelot_port; 1546 struct timespec64 base_ts; 1547 int i, port; 1548 u32 val; 1549 1550 mutex_lock(&ocelot->fwd_domain_lock); 1551 1552 for (port = 0; port < ocelot->num_phys_ports; port++) { 1553 ocelot_port = ocelot->ports[port]; 1554 taprio = ocelot_port->taprio; 1555 if (!taprio) 1556 continue; 1557 1558 ocelot_rmw(ocelot, 1559 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 1560 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 1561 QSYS_TAS_PARAM_CFG_CTRL); 1562 1563 /* Disable time-aware shaper */ 1564 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1565 QSYS_TAG_CONFIG, port); 1566 1567 vsc9959_new_base_time(ocelot, taprio->base_time, 1568 taprio->cycle_time, &base_ts); 1569 1570 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1571 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 1572 QSYS_PARAM_CFG_REG_2); 1573 val = upper_32_bits(base_ts.tv_sec); 1574 ocelot_rmw(ocelot, 1575 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 1576 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 1577 QSYS_PARAM_CFG_REG_3); 1578 1579 for (i = 0; i < taprio->num_entries; i++) 1580 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1581 1582 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1583 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1584 QSYS_TAS_PARAM_CFG_CTRL); 1585 1586 /* Re-enable time-aware shaper */ 1587 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 1588 QSYS_TAG_CONFIG_ENABLE, 1589 QSYS_TAG_CONFIG, port); 1590 } 1591 mutex_unlock(&ocelot->fwd_domain_lock); 1592} 1593 1594static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1595 struct tc_cbs_qopt_offload *cbs_qopt) 1596{ 1597 struct ocelot *ocelot = ds->priv; 1598 int port_ix = port * 8 + cbs_qopt->queue; 1599 u32 rate, burst; 1600 1601 if (cbs_qopt->queue >= ds->num_tx_queues) 1602 return -EINVAL; 1603 1604 if (!cbs_qopt->enable) { 1605 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1606 QSYS_CIR_CFG_CIR_BURST(0), 1607 QSYS_CIR_CFG, port_ix); 1608 1609 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1610 QSYS_SE_CFG, port_ix); 1611 1612 return 0; 1613 } 1614 1615 /* Rate unit is 100 kbps */ 1616 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1617 /* Avoid using zero rate */ 1618 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1619 /* Burst unit is 4kB */ 1620 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1621 /* Avoid using zero burst size */ 1622 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1623 ocelot_write_gix(ocelot, 1624 QSYS_CIR_CFG_CIR_RATE(rate) | 1625 QSYS_CIR_CFG_CIR_BURST(burst), 1626 QSYS_CIR_CFG, 1627 port_ix); 1628 1629 ocelot_rmw_gix(ocelot, 1630 QSYS_SE_CFG_SE_FRM_MODE(0) | 1631 QSYS_SE_CFG_SE_AVB_ENA, 1632 QSYS_SE_CFG_SE_AVB_ENA | 1633 QSYS_SE_CFG_SE_FRM_MODE_M, 1634 QSYS_SE_CFG, 1635 port_ix); 1636 1637 return 0; 1638} 1639 1640static int vsc9959_qos_query_caps(struct tc_query_caps_base *base) 1641{ 1642 switch (base->type) { 1643 case TC_SETUP_QDISC_MQPRIO: { 1644 struct tc_mqprio_caps *caps = base->caps; 1645 1646 caps->validate_queue_counts = true; 1647 1648 return 0; 1649 } 1650 case TC_SETUP_QDISC_TAPRIO: { 1651 struct tc_taprio_caps *caps = base->caps; 1652 1653 caps->supports_queue_max_sdu = true; 1654 1655 return 0; 1656 } 1657 default: 1658 return -EOPNOTSUPP; 1659 } 1660} 1661 1662static int vsc9959_qos_port_mqprio(struct ocelot *ocelot, int port, 1663 struct tc_mqprio_qopt_offload *mqprio) 1664{ 1665 int ret; 1666 1667 mutex_lock(&ocelot->fwd_domain_lock); 1668 ret = ocelot_port_mqprio(ocelot, port, mqprio); 1669 mutex_unlock(&ocelot->fwd_domain_lock); 1670 1671 return ret; 1672} 1673 1674static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1675 enum tc_setup_type type, 1676 void *type_data) 1677{ 1678 struct ocelot *ocelot = ds->priv; 1679 1680 switch (type) { 1681 case TC_QUERY_CAPS: 1682 return vsc9959_qos_query_caps(type_data); 1683 case TC_SETUP_QDISC_TAPRIO: 1684 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1685 case TC_SETUP_QDISC_MQPRIO: 1686 return vsc9959_qos_port_mqprio(ocelot, port, type_data); 1687 case TC_SETUP_QDISC_CBS: 1688 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1689 default: 1690 return -EOPNOTSUPP; 1691 } 1692} 1693 1694#define VSC9959_PSFP_SFID_MAX 175 1695#define VSC9959_PSFP_GATE_ID_MAX 183 1696#define VSC9959_PSFP_POLICER_BASE 63 1697#define VSC9959_PSFP_POLICER_MAX 383 1698#define VSC9959_PSFP_GATE_LIST_NUM 4 1699#define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1700 1701struct felix_stream { 1702 struct list_head list; 1703 unsigned long id; 1704 bool dummy; 1705 int ports; 1706 int port; 1707 u8 dmac[ETH_ALEN]; 1708 u16 vid; 1709 s8 prio; 1710 u8 sfid_valid; 1711 u8 ssid_valid; 1712 u32 sfid; 1713 u32 ssid; 1714}; 1715 1716struct felix_stream_filter_counters { 1717 u64 match; 1718 u64 not_pass_gate; 1719 u64 not_pass_sdu; 1720 u64 red; 1721}; 1722 1723struct felix_stream_filter { 1724 struct felix_stream_filter_counters stats; 1725 struct list_head list; 1726 refcount_t refcount; 1727 u32 index; 1728 u8 enable; 1729 int portmask; 1730 u8 sg_valid; 1731 u32 sgid; 1732 u8 fm_valid; 1733 u32 fmid; 1734 u8 prio_valid; 1735 u8 prio; 1736 u32 maxsdu; 1737}; 1738 1739struct felix_stream_gate { 1740 u32 index; 1741 u8 enable; 1742 u8 ipv_valid; 1743 u8 init_ipv; 1744 u64 basetime; 1745 u64 cycletime; 1746 u64 cycletime_ext; 1747 u32 num_entries; 1748 struct action_gate_entry entries[] __counted_by(num_entries); 1749}; 1750 1751struct felix_stream_gate_entry { 1752 struct list_head list; 1753 refcount_t refcount; 1754 u32 index; 1755}; 1756 1757static int vsc9959_stream_identify(struct flow_cls_offload *f, 1758 struct felix_stream *stream) 1759{ 1760 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 1761 struct flow_dissector *dissector = rule->match.dissector; 1762 1763 if (dissector->used_keys & 1764 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 1765 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 1766 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 1767 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 1768 return -EOPNOTSUPP; 1769 1770 if (flow_rule_match_has_control_flags(rule, f->common.extack)) 1771 return -EOPNOTSUPP; 1772 1773 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1774 struct flow_match_eth_addrs match; 1775 1776 flow_rule_match_eth_addrs(rule, &match); 1777 ether_addr_copy(stream->dmac, match.key->dst); 1778 if (!is_zero_ether_addr(match.mask->src)) 1779 return -EOPNOTSUPP; 1780 } else { 1781 return -EOPNOTSUPP; 1782 } 1783 1784 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 1785 struct flow_match_vlan match; 1786 1787 flow_rule_match_vlan(rule, &match); 1788 if (match.mask->vlan_priority) 1789 stream->prio = match.key->vlan_priority; 1790 else 1791 stream->prio = -1; 1792 1793 if (!match.mask->vlan_id) 1794 return -EOPNOTSUPP; 1795 stream->vid = match.key->vlan_id; 1796 } else { 1797 return -EOPNOTSUPP; 1798 } 1799 1800 stream->id = f->cookie; 1801 1802 return 0; 1803} 1804 1805static int vsc9959_mact_stream_set(struct ocelot *ocelot, 1806 struct felix_stream *stream, 1807 struct netlink_ext_ack *extack) 1808{ 1809 enum macaccess_entry_type type; 1810 int ret, sfid, ssid; 1811 u32 vid, dst_idx; 1812 u8 mac[ETH_ALEN]; 1813 1814 ether_addr_copy(mac, stream->dmac); 1815 vid = stream->vid; 1816 1817 /* Stream identification desn't support to add a stream with non 1818 * existent MAC (The MAC entry has not been learned in MAC table). 1819 */ 1820 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 1821 if (ret) { 1822 if (extack) 1823 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 1824 return -EOPNOTSUPP; 1825 } 1826 1827 if ((stream->sfid_valid || stream->ssid_valid) && 1828 type == ENTRYTYPE_NORMAL) 1829 type = ENTRYTYPE_LOCKED; 1830 1831 sfid = stream->sfid_valid ? stream->sfid : -1; 1832 ssid = stream->ssid_valid ? stream->ssid : -1; 1833 1834 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 1835 sfid, ssid); 1836 1837 return ret; 1838} 1839 1840static struct felix_stream * 1841vsc9959_stream_table_lookup(struct list_head *stream_list, 1842 struct felix_stream *stream) 1843{ 1844 struct felix_stream *tmp; 1845 1846 list_for_each_entry(tmp, stream_list, list) 1847 if (ether_addr_equal(tmp->dmac, stream->dmac) && 1848 tmp->vid == stream->vid) 1849 return tmp; 1850 1851 return NULL; 1852} 1853 1854static int vsc9959_stream_table_add(struct ocelot *ocelot, 1855 struct list_head *stream_list, 1856 struct felix_stream *stream, 1857 struct netlink_ext_ack *extack) 1858{ 1859 struct felix_stream *stream_entry; 1860 int ret; 1861 1862 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 1863 if (!stream_entry) 1864 return -ENOMEM; 1865 1866 if (!stream->dummy) { 1867 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 1868 if (ret) { 1869 kfree(stream_entry); 1870 return ret; 1871 } 1872 } 1873 1874 list_add_tail(&stream_entry->list, stream_list); 1875 1876 return 0; 1877} 1878 1879static struct felix_stream * 1880vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 1881{ 1882 struct felix_stream *tmp; 1883 1884 list_for_each_entry(tmp, stream_list, list) 1885 if (tmp->id == id) 1886 return tmp; 1887 1888 return NULL; 1889} 1890 1891static void vsc9959_stream_table_del(struct ocelot *ocelot, 1892 struct felix_stream *stream) 1893{ 1894 if (!stream->dummy) 1895 vsc9959_mact_stream_set(ocelot, stream, NULL); 1896 1897 list_del(&stream->list); 1898 kfree(stream); 1899} 1900 1901static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 1902{ 1903 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 1904} 1905 1906static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 1907 struct felix_stream_filter *sfi) 1908{ 1909 u32 val; 1910 1911 if (sfi->index > VSC9959_PSFP_SFID_MAX) 1912 return -EINVAL; 1913 1914 if (!sfi->enable) { 1915 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1916 ANA_TABLES_SFIDTIDX); 1917 1918 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 1919 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 1920 1921 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1922 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1923 10, 100000); 1924 } 1925 1926 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 1927 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 1928 return -EINVAL; 1929 1930 ocelot_write(ocelot, 1931 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 1932 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 1933 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 1934 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 1935 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1936 ANA_TABLES_SFIDTIDX); 1937 1938 ocelot_write(ocelot, 1939 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 1940 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 1941 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 1942 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1943 ANA_TABLES_SFIDACCESS); 1944 1945 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1946 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1947 10, 100000); 1948} 1949 1950static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 1951{ 1952 u32 val; 1953 1954 ocelot_rmw(ocelot, 1955 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1956 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1957 ANA_TABLES_SFIDTIDX); 1958 1959 ocelot_write(ocelot, 1960 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1961 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1962 ANA_TABLES_SFID_MASK); 1963 1964 ocelot_rmw(ocelot, 1965 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1966 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1967 ANA_TABLES_SFIDACCESS); 1968 1969 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1970 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1971 10, 100000); 1972} 1973 1974static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1975 struct felix_stream_filter *sfi, 1976 struct list_head *pos) 1977{ 1978 struct felix_stream_filter *sfi_entry; 1979 int ret; 1980 1981 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 1982 if (!sfi_entry) 1983 return -ENOMEM; 1984 1985 refcount_set(&sfi_entry->refcount, 1); 1986 1987 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 1988 if (ret) { 1989 kfree(sfi_entry); 1990 return ret; 1991 } 1992 1993 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1994 1995 list_add(&sfi_entry->list, pos); 1996 1997 return 0; 1998} 1999 2000static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 2001 struct felix_stream_filter *sfi) 2002{ 2003 struct list_head *pos, *q, *last; 2004 struct felix_stream_filter *tmp; 2005 struct ocelot_psfp_list *psfp; 2006 u32 insert = 0; 2007 2008 psfp = &ocelot->psfp; 2009 last = &psfp->sfi_list; 2010 2011 list_for_each_safe(pos, q, &psfp->sfi_list) { 2012 tmp = list_entry(pos, struct felix_stream_filter, list); 2013 if (sfi->sg_valid == tmp->sg_valid && 2014 sfi->fm_valid == tmp->fm_valid && 2015 sfi->portmask == tmp->portmask && 2016 tmp->sgid == sfi->sgid && 2017 tmp->fmid == sfi->fmid) { 2018 sfi->index = tmp->index; 2019 refcount_inc(&tmp->refcount); 2020 return 0; 2021 } 2022 /* Make sure that the index is increasing in order. */ 2023 if (tmp->index == insert) { 2024 last = pos; 2025 insert++; 2026 } 2027 } 2028 sfi->index = insert; 2029 2030 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 2031} 2032 2033static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 2034 struct felix_stream_filter *sfi, 2035 struct felix_stream_filter *sfi2) 2036{ 2037 struct felix_stream_filter *tmp; 2038 struct list_head *pos, *q, *last; 2039 struct ocelot_psfp_list *psfp; 2040 u32 insert = 0; 2041 int ret; 2042 2043 psfp = &ocelot->psfp; 2044 last = &psfp->sfi_list; 2045 2046 list_for_each_safe(pos, q, &psfp->sfi_list) { 2047 tmp = list_entry(pos, struct felix_stream_filter, list); 2048 /* Make sure that the index is increasing in order. */ 2049 if (tmp->index >= insert + 2) 2050 break; 2051 2052 insert = tmp->index + 1; 2053 last = pos; 2054 } 2055 sfi->index = insert; 2056 2057 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 2058 if (ret) 2059 return ret; 2060 2061 sfi2->index = insert + 1; 2062 2063 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 2064} 2065 2066static struct felix_stream_filter * 2067vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 2068{ 2069 struct felix_stream_filter *tmp; 2070 2071 list_for_each_entry(tmp, sfi_list, list) 2072 if (tmp->index == index) 2073 return tmp; 2074 2075 return NULL; 2076} 2077 2078static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 2079{ 2080 struct felix_stream_filter *tmp, *n; 2081 struct ocelot_psfp_list *psfp; 2082 u8 z; 2083 2084 psfp = &ocelot->psfp; 2085 2086 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 2087 if (tmp->index == index) { 2088 z = refcount_dec_and_test(&tmp->refcount); 2089 if (z) { 2090 tmp->enable = 0; 2091 vsc9959_psfp_sfi_set(ocelot, tmp); 2092 list_del(&tmp->list); 2093 kfree(tmp); 2094 } 2095 break; 2096 } 2097} 2098 2099static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 2100 struct felix_stream_gate *sgi) 2101{ 2102 sgi->index = entry->hw_index; 2103 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 2104 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 2105 sgi->basetime = entry->gate.basetime; 2106 sgi->cycletime = entry->gate.cycletime; 2107 sgi->num_entries = entry->gate.num_entries; 2108 sgi->enable = 1; 2109 2110 memcpy(sgi->entries, entry->gate.entries, 2111 entry->gate.num_entries * sizeof(struct action_gate_entry)); 2112} 2113 2114static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 2115{ 2116 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 2117} 2118 2119static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 2120 struct felix_stream_gate *sgi) 2121{ 2122 struct action_gate_entry *e; 2123 struct timespec64 base_ts; 2124 u32 interval_sum = 0; 2125 u32 val; 2126 int i; 2127 2128 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 2129 return -EINVAL; 2130 2131 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 2132 ANA_SG_ACCESS_CTRL); 2133 2134 if (!sgi->enable) { 2135 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 2136 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2137 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 2138 ANA_SG_CONFIG_REG_3); 2139 2140 return 0; 2141 } 2142 2143 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 2144 sgi->cycletime > NSEC_PER_SEC) 2145 return -EINVAL; 2146 2147 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 2148 return -EINVAL; 2149 2150 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 2151 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 2152 val = lower_32_bits(base_ts.tv_sec); 2153 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 2154 2155 val = upper_32_bits(base_ts.tv_sec); 2156 ocelot_write(ocelot, 2157 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 2158 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 2159 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 2160 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 2161 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2162 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 2163 ANA_SG_CONFIG_REG_3); 2164 2165 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 2166 2167 e = sgi->entries; 2168 for (i = 0; i < sgi->num_entries; i++) { 2169 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 2170 2171 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 2172 (e[i].gate_state ? 2173 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 2174 ANA_SG_GCL_GS_CONFIG, i); 2175 2176 interval_sum += e[i].interval; 2177 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 2178 } 2179 2180 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2181 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2182 ANA_SG_ACCESS_CTRL); 2183 2184 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 2185 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 2186 10, 100000); 2187} 2188 2189static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 2190 struct felix_stream_gate *sgi) 2191{ 2192 struct felix_stream_gate_entry *tmp; 2193 struct ocelot_psfp_list *psfp; 2194 int ret; 2195 2196 psfp = &ocelot->psfp; 2197 2198 list_for_each_entry(tmp, &psfp->sgi_list, list) 2199 if (tmp->index == sgi->index) { 2200 refcount_inc(&tmp->refcount); 2201 return 0; 2202 } 2203 2204 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 2205 if (!tmp) 2206 return -ENOMEM; 2207 2208 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 2209 if (ret) { 2210 kfree(tmp); 2211 return ret; 2212 } 2213 2214 tmp->index = sgi->index; 2215 refcount_set(&tmp->refcount, 1); 2216 list_add_tail(&tmp->list, &psfp->sgi_list); 2217 2218 return 0; 2219} 2220 2221static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 2222 u32 index) 2223{ 2224 struct felix_stream_gate_entry *tmp, *n; 2225 struct felix_stream_gate sgi = {0}; 2226 struct ocelot_psfp_list *psfp; 2227 u8 z; 2228 2229 psfp = &ocelot->psfp; 2230 2231 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 2232 if (tmp->index == index) { 2233 z = refcount_dec_and_test(&tmp->refcount); 2234 if (z) { 2235 sgi.index = index; 2236 sgi.enable = 0; 2237 vsc9959_psfp_sgi_set(ocelot, &sgi); 2238 list_del(&tmp->list); 2239 kfree(tmp); 2240 } 2241 break; 2242 } 2243} 2244 2245static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 2246 struct flow_cls_offload *f) 2247{ 2248 struct netlink_ext_ack *extack = f->common.extack; 2249 struct felix_stream_filter old_sfi, *sfi_entry; 2250 struct felix_stream_filter sfi = {0}; 2251 const struct flow_action_entry *a; 2252 struct felix_stream *stream_entry; 2253 struct felix_stream stream = {0}; 2254 struct felix_stream_gate *sgi; 2255 struct ocelot_psfp_list *psfp; 2256 struct ocelot_policer pol; 2257 int ret, i, size; 2258 u64 rate, burst; 2259 u32 index; 2260 2261 psfp = &ocelot->psfp; 2262 2263 ret = vsc9959_stream_identify(f, &stream); 2264 if (ret) { 2265 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 2266 return ret; 2267 } 2268 2269 mutex_lock(&psfp->lock); 2270 2271 flow_action_for_each(i, a, &f->rule->action) { 2272 switch (a->id) { 2273 case FLOW_ACTION_GATE: 2274 size = struct_size(sgi, entries, a->gate.num_entries); 2275 sgi = kzalloc(size, GFP_KERNEL); 2276 if (!sgi) { 2277 ret = -ENOMEM; 2278 goto err; 2279 } 2280 vsc9959_psfp_parse_gate(a, sgi); 2281 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 2282 if (ret) { 2283 kfree(sgi); 2284 goto err; 2285 } 2286 sfi.sg_valid = 1; 2287 sfi.sgid = sgi->index; 2288 kfree(sgi); 2289 break; 2290 case FLOW_ACTION_POLICE: 2291 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 2292 if (index > VSC9959_PSFP_POLICER_MAX) { 2293 ret = -EINVAL; 2294 goto err; 2295 } 2296 2297 rate = a->police.rate_bytes_ps; 2298 burst = rate * PSCHED_NS2TICKS(a->police.burst); 2299 pol = (struct ocelot_policer) { 2300 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 2301 .rate = div_u64(rate, 1000) * 8, 2302 }; 2303 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 2304 if (ret) 2305 goto err; 2306 2307 sfi.fm_valid = 1; 2308 sfi.fmid = index; 2309 sfi.maxsdu = a->police.mtu; 2310 break; 2311 default: 2312 mutex_unlock(&psfp->lock); 2313 return -EOPNOTSUPP; 2314 } 2315 } 2316 2317 stream.ports = BIT(port); 2318 stream.port = port; 2319 2320 sfi.portmask = stream.ports; 2321 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 2322 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 2323 sfi.enable = 1; 2324 2325 /* Check if stream is set. */ 2326 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2327 if (stream_entry) { 2328 if (stream_entry->ports & BIT(port)) { 2329 NL_SET_ERR_MSG_MOD(extack, 2330 "The stream is added on this port"); 2331 ret = -EEXIST; 2332 goto err; 2333 } 2334 2335 if (stream_entry->ports != BIT(stream_entry->port)) { 2336 NL_SET_ERR_MSG_MOD(extack, 2337 "The stream is added on two ports"); 2338 ret = -EEXIST; 2339 goto err; 2340 } 2341 2342 stream_entry->ports |= BIT(port); 2343 stream.ports = stream_entry->ports; 2344 2345 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2346 stream_entry->sfid); 2347 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2348 2349 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2350 2351 old_sfi.portmask = stream_entry->ports; 2352 sfi.portmask = stream.ports; 2353 2354 if (stream_entry->port > port) { 2355 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2356 &old_sfi); 2357 stream_entry->dummy = true; 2358 } else { 2359 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2360 &sfi); 2361 stream.dummy = true; 2362 } 2363 if (ret) 2364 goto err; 2365 2366 stream_entry->sfid = old_sfi.index; 2367 } else { 2368 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2369 if (ret) 2370 goto err; 2371 } 2372 2373 stream.sfid = sfi.index; 2374 stream.sfid_valid = 1; 2375 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2376 &stream, extack); 2377 if (ret) { 2378 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2379 goto err; 2380 } 2381 2382 mutex_unlock(&psfp->lock); 2383 2384 return 0; 2385 2386err: 2387 if (sfi.sg_valid) 2388 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2389 2390 if (sfi.fm_valid) 2391 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2392 2393 mutex_unlock(&psfp->lock); 2394 2395 return ret; 2396} 2397 2398static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2399 struct flow_cls_offload *f) 2400{ 2401 struct felix_stream *stream, tmp, *stream_entry; 2402 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2403 static struct felix_stream_filter *sfi; 2404 2405 mutex_lock(&psfp->lock); 2406 2407 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2408 if (!stream) { 2409 mutex_unlock(&psfp->lock); 2410 return -ENOMEM; 2411 } 2412 2413 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2414 if (!sfi) { 2415 mutex_unlock(&psfp->lock); 2416 return -ENOMEM; 2417 } 2418 2419 if (sfi->sg_valid) 2420 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2421 2422 if (sfi->fm_valid) 2423 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2424 2425 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2426 2427 memcpy(&tmp, stream, sizeof(tmp)); 2428 2429 stream->sfid_valid = 0; 2430 vsc9959_stream_table_del(ocelot, stream); 2431 2432 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2433 if (stream_entry) { 2434 stream_entry->ports = BIT(stream_entry->port); 2435 if (stream_entry->dummy) { 2436 stream_entry->dummy = false; 2437 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2438 } 2439 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2440 stream_entry->ports); 2441 } 2442 2443 mutex_unlock(&psfp->lock); 2444 2445 return 0; 2446} 2447 2448static void vsc9959_update_sfid_stats(struct ocelot *ocelot, 2449 struct felix_stream_filter *sfi) 2450{ 2451 struct felix_stream_filter_counters *s = &sfi->stats; 2452 u32 match, not_pass_gate, not_pass_sdu, red; 2453 u32 sfid = sfi->index; 2454 2455 lockdep_assert_held(&ocelot->stat_view_lock); 2456 2457 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid), 2458 SYS_STAT_CFG_STAT_VIEW_M, 2459 SYS_STAT_CFG); 2460 2461 match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES); 2462 not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES); 2463 not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU); 2464 red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES); 2465 2466 /* Clear the PSFP counter. */ 2467 ocelot_write(ocelot, 2468 SYS_STAT_CFG_STAT_VIEW(sfid) | 2469 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 2470 SYS_STAT_CFG); 2471 2472 s->match += match; 2473 s->not_pass_gate += not_pass_gate; 2474 s->not_pass_sdu += not_pass_sdu; 2475 s->red += red; 2476} 2477 2478/* Caller must hold &ocelot->stat_view_lock */ 2479static void vsc9959_update_stats(struct ocelot *ocelot) 2480{ 2481 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2482 struct felix_stream_filter *sfi; 2483 2484 mutex_lock(&psfp->lock); 2485 2486 list_for_each_entry(sfi, &psfp->sfi_list, list) 2487 vsc9959_update_sfid_stats(ocelot, sfi); 2488 2489 mutex_unlock(&psfp->lock); 2490} 2491 2492static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2493 struct flow_cls_offload *f, 2494 struct flow_stats *stats) 2495{ 2496 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2497 struct felix_stream_filter_counters *s; 2498 static struct felix_stream_filter *sfi; 2499 struct felix_stream *stream; 2500 2501 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2502 if (!stream) 2503 return -ENOMEM; 2504 2505 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2506 if (!sfi) 2507 return -EINVAL; 2508 2509 mutex_lock(&ocelot->stat_view_lock); 2510 2511 vsc9959_update_sfid_stats(ocelot, sfi); 2512 2513 s = &sfi->stats; 2514 stats->pkts = s->match; 2515 stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red; 2516 2517 memset(s, 0, sizeof(*s)); 2518 2519 mutex_unlock(&ocelot->stat_view_lock); 2520 2521 return 0; 2522} 2523 2524static void vsc9959_psfp_init(struct ocelot *ocelot) 2525{ 2526 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2527 2528 INIT_LIST_HEAD(&psfp->stream_list); 2529 INIT_LIST_HEAD(&psfp->sfi_list); 2530 INIT_LIST_HEAD(&psfp->sgi_list); 2531 mutex_init(&psfp->lock); 2532} 2533 2534/* When using cut-through forwarding and the egress port runs at a higher data 2535 * rate than the ingress port, the packet currently under transmission would 2536 * suffer an underrun since it would be transmitted faster than it is received. 2537 * The Felix switch implementation of cut-through forwarding does not check in 2538 * hardware whether this condition is satisfied or not, so we must restrict the 2539 * list of ports that have cut-through forwarding enabled on egress to only be 2540 * the ports operating at the lowest link speed within their respective 2541 * forwarding domain. 2542 */ 2543static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2544{ 2545 struct felix *felix = ocelot_to_felix(ocelot); 2546 struct dsa_switch *ds = felix->ds; 2547 int tc, port, other_port; 2548 2549 lockdep_assert_held(&ocelot->fwd_domain_lock); 2550 2551 for (port = 0; port < ocelot->num_phys_ports; port++) { 2552 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2553 struct ocelot_mm_state *mm = &ocelot->mm[port]; 2554 int min_speed = ocelot_port->speed; 2555 unsigned long mask = 0; 2556 u32 tmp, val = 0; 2557 2558 /* Disable cut-through on ports that are down */ 2559 if (ocelot_port->speed <= 0) 2560 goto set; 2561 2562 if (dsa_is_cpu_port(ds, port)) { 2563 /* Ocelot switches forward from the NPI port towards 2564 * any port, regardless of it being in the NPI port's 2565 * forwarding domain or not. 2566 */ 2567 mask = dsa_user_ports(ds); 2568 } else { 2569 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2570 mask &= ~BIT(port); 2571 if (ocelot->npi >= 0) 2572 mask |= BIT(ocelot->npi); 2573 else 2574 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2575 port); 2576 } 2577 2578 /* Calculate the minimum link speed, among the ports that are 2579 * up, of this source port's forwarding domain. 2580 */ 2581 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2582 struct ocelot_port *other_ocelot_port; 2583 2584 other_ocelot_port = ocelot->ports[other_port]; 2585 if (other_ocelot_port->speed <= 0) 2586 continue; 2587 2588 if (min_speed > other_ocelot_port->speed) 2589 min_speed = other_ocelot_port->speed; 2590 } 2591 2592 /* Enable cut-through forwarding for all traffic classes that 2593 * don't have oversized dropping enabled, since this check is 2594 * bypassed in cut-through mode. Also exclude preemptible 2595 * traffic classes, since these would hang the port for some 2596 * reason, if sent as cut-through. 2597 */ 2598 if (ocelot_port->speed == min_speed) { 2599 val = GENMASK(7, 0) & ~mm->active_preemptible_tcs; 2600 2601 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 2602 if (vsc9959_port_qmaxsdu_get(ocelot, port, tc)) 2603 val &= ~BIT(tc); 2604 } 2605 2606set: 2607 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2608 if (tmp == val) 2609 continue; 2610 2611 dev_dbg(ocelot->dev, 2612 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n", 2613 port, mask, ocelot_port->speed, min_speed, 2614 val ? "enabling" : "disabling", val); 2615 2616 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2617 } 2618} 2619 2620/* The INTB interrupt is shared between for PTP TX timestamp availability 2621 * notification and MAC Merge status change on each port. 2622 */ 2623static irqreturn_t vsc9959_irq_handler(int irq, void *data) 2624{ 2625 struct ocelot *ocelot = data; 2626 2627 ocelot_get_txtstamp(ocelot); 2628 ocelot_mm_irq(ocelot); 2629 2630 return IRQ_HANDLED; 2631} 2632 2633static int vsc9959_request_irq(struct ocelot *ocelot) 2634{ 2635 struct pci_dev *pdev = to_pci_dev(ocelot->dev); 2636 2637 return devm_request_threaded_irq(ocelot->dev, pdev->irq, NULL, 2638 &vsc9959_irq_handler, IRQF_ONESHOT, 2639 "felix-intb", ocelot); 2640} 2641 2642static const struct ocelot_ops vsc9959_ops = { 2643 .reset = vsc9959_reset, 2644 .wm_enc = vsc9959_wm_enc, 2645 .wm_dec = vsc9959_wm_dec, 2646 .wm_stat = vsc9959_wm_stat, 2647 .port_to_netdev = felix_port_to_netdev, 2648 .netdev_to_port = felix_netdev_to_port, 2649 .psfp_init = vsc9959_psfp_init, 2650 .psfp_filter_add = vsc9959_psfp_filter_add, 2651 .psfp_filter_del = vsc9959_psfp_filter_del, 2652 .psfp_stats_get = vsc9959_psfp_stats_get, 2653 .cut_through_fwd = vsc9959_cut_through_fwd, 2654 .tas_clock_adjust = vsc9959_tas_clock_adjust, 2655 .update_stats = vsc9959_update_stats, 2656 .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2657}; 2658 2659static const struct felix_info felix_info_vsc9959 = { 2660 .resources = vsc9959_resources, 2661 .num_resources = ARRAY_SIZE(vsc9959_resources), 2662 .resource_names = vsc9959_resource_names, 2663 .regfields = vsc9959_regfields, 2664 .map = vsc9959_regmap, 2665 .ops = &vsc9959_ops, 2666 .vcap = vsc9959_vcap_props, 2667 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2668 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2669 .vcap_pol_base2 = 0, 2670 .vcap_pol_max2 = 0, 2671 .num_mact_rows = 2048, 2672 .num_ports = VSC9959_NUM_PORTS, 2673 .quirks = FELIX_MAC_QUIRKS, 2674 .quirk_no_xtr_irq = true, 2675 .ptp_caps = &vsc9959_ptp_caps, 2676 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2677 .mdio_bus_free = vsc9959_mdio_bus_free, 2678 .port_modes = vsc9959_port_modes, 2679 .port_setup_tc = vsc9959_port_setup_tc, 2680 .port_sched_speed_set = vsc9959_sched_speed_set, 2681 .request_irq = vsc9959_request_irq, 2682}; 2683 2684static int felix_pci_probe(struct pci_dev *pdev, 2685 const struct pci_device_id *id) 2686{ 2687 struct device *dev = &pdev->dev; 2688 resource_size_t switch_base; 2689 int err; 2690 2691 err = pci_enable_device(pdev); 2692 if (err) { 2693 dev_err(dev, "device enable failed: %pe\n", ERR_PTR(err)); 2694 return err; 2695 } 2696 2697 pci_set_master(pdev); 2698 2699 switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2700 2701 err = felix_register_switch(dev, switch_base, OCELOT_NUM_TC, 2702 true, true, DSA_TAG_PROTO_OCELOT, 2703 &felix_info_vsc9959); 2704 if (err) 2705 goto out_disable; 2706 2707 return 0; 2708 2709out_disable: 2710 pci_disable_device(pdev); 2711 return err; 2712} 2713 2714static void felix_pci_remove(struct pci_dev *pdev) 2715{ 2716 struct felix *felix = pci_get_drvdata(pdev); 2717 2718 if (!felix) 2719 return; 2720 2721 dsa_unregister_switch(felix->ds); 2722 2723 pci_disable_device(pdev); 2724} 2725 2726static void felix_pci_shutdown(struct pci_dev *pdev) 2727{ 2728 struct felix *felix = pci_get_drvdata(pdev); 2729 2730 if (!felix) 2731 return; 2732 2733 dsa_switch_shutdown(felix->ds); 2734 2735 pci_set_drvdata(pdev, NULL); 2736} 2737 2738static struct pci_device_id felix_ids[] = { 2739 { 2740 /* NXP LS1028A */ 2741 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2742 }, 2743 { 0, } 2744}; 2745MODULE_DEVICE_TABLE(pci, felix_ids); 2746 2747static struct pci_driver felix_vsc9959_pci_driver = { 2748 .name = "mscc_felix", 2749 .id_table = felix_ids, 2750 .probe = felix_pci_probe, 2751 .remove = felix_pci_remove, 2752 .shutdown = felix_pci_shutdown, 2753}; 2754module_pci_driver(felix_vsc9959_pci_driver); 2755 2756MODULE_DESCRIPTION("Felix Switch driver"); 2757MODULE_LICENSE("GPL v2");
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