FILE
port.h
File preview with syntax highlighting.
linux-6.19.14/drivers/net/dsa/mv88e6xxx/port.h
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11#ifndef _MV88E6XXX_PORT_H 12#define _MV88E6XXX_PORT_H 13 14#include "chip.h" 15 16/* Offset 0x00: Port Status Register */ 17#define MV88E6XXX_PORT_STS 0x00 18#define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 19#define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 20#define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 21#define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 22#define MV88E6250_PORT_STS_LINK 0x1000 23#define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00 24#define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800 25#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900 26#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00 27#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00 28/* - Modes with PHY suffix use output instead of input clock 29 * - Modes without RMII or RGMII use MII 30 * - Modes without speed do not have a fixed speed specified in the manual 31 * ("DC to x MHz" - variable clock support?) 32 */ 33#define MV88E6250_PORT_STS_PORTMODE_MII_DISABLED 0x0000 34#define MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII 0x0100 35#define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY 0x0200 36#define MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY 0x0400 37#define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL 0x0600 38#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL 0x0700 39#define MV88E6250_PORT_STS_PORTMODE_MII_HALF 0x0800 40#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY 0x0900 41#define MV88E6250_PORT_STS_PORTMODE_MII_FULL 0x0a00 42#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY 0x0b00 43#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY 0x0c00 44#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY 0x0d00 45#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY 0x0e00 46#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY 0x0f00 47#define MV88E6XXX_PORT_STS_LINK 0x0800 48#define MV88E6XXX_PORT_STS_DUPLEX 0x0400 49#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 50#define MV88E6XXX_PORT_STS_SPEED_10 0x0000 51#define MV88E6XXX_PORT_STS_SPEED_100 0x0100 52#define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 53#define MV88E6XXX_PORT_STS_SPEED_10000 0x0300 54#define MV88E6352_PORT_STS_EEE 0x0040 55#define MV88E6165_PORT_STS_AM_DIS 0x0040 56#define MV88E6185_PORT_STS_MGMII 0x0040 57#define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 58#define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 59#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 60#define MV88E6XXX_PORT_STS_CMODE_MII_PHY 0x0001 61#define MV88E6XXX_PORT_STS_CMODE_MII 0x0002 62#define MV88E6XXX_PORT_STS_CMODE_GMII 0x0003 63#define MV88E6XXX_PORT_STS_CMODE_RMII_PHY 0x0004 64#define MV88E6XXX_PORT_STS_CMODE_RMII 0x0005 65#define MV88E6XXX_PORT_STS_CMODE_RGMII 0x0007 66#define MV88E6XXX_PORT_STS_CMODE_100BASEX 0x0008 67#define MV88E6XXX_PORT_STS_CMODE_1000BASEX 0x0009 68#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 69#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 70#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 71#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 72#define MV88E6393X_PORT_STS_CMODE_5GBASER 0x000c 73#define MV88E6393X_PORT_STS_CMODE_10GBASER 0x000d 74#define MV88E6393X_PORT_STS_CMODE_USXGMII 0x000e 75#define MV88E6185_PORT_STS_CDUPLEX 0x0008 76#define MV88E6185_PORT_STS_CMODE_MASK 0x0007 77#define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000 78#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001 79#define MV88E6185_PORT_STS_CMODE_MII_100 0x0002 80#define MV88E6185_PORT_STS_CMODE_MII_10 0x0003 81#define MV88E6185_PORT_STS_CMODE_SERDES 0x0004 82#define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005 83#define MV88E6185_PORT_STS_CMODE_PHY 0x0006 84#define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007 85 86/* Offset 0x01: MAC (or PCS or Physical) Control Register */ 87#define MV88E6XXX_PORT_MAC_CTL 0x01 88#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 89#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 90#define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000 91#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 92#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 93#define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 94#define MV88E6XXX_PORT_MAC_CTL_EEE 0x0200 95#define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE 0x0100 96#define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400 97#define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200 98#define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100 99#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 100#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 101#define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 102#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 103#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 104#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 105#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 106#define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 107#define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 108#define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 109#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 110#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 111#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 112 113/* Offset 0x02: Jamming Control Register */ 114#define MV88E6097_PORT_JAM_CTL 0x02 115#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 116#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 117 118/* Offset 0x02: Flow Control Register */ 119#define MV88E6390_PORT_FLOW_CTL 0x02 120#define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 121#define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 122#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 123#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 124#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 125 126/* Offset 0x03: Switch Identifier Register */ 127#define MV88E6XXX_PORT_SWITCH_ID 0x03 128#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 129#define MV88E6XXX_PORT_SWITCH_ID_PROD_6020 0x0200 130#define MV88E6XXX_PORT_SWITCH_ID_PROD_6071 0x0710 131#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 132#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 133#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 134#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 135#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 136#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 137#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 138#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 139#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 140#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 141#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 142#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 143#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 144#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 145#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 146#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 147#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920 148#define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930 149#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 150#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200 151#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 152#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500 153#define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610 154#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 155#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 156#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 157#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 158#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 159#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 160#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 161#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 162#define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930 163#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 164 165/* Offset 0x04: Port Control Register */ 166#define MV88E6XXX_PORT_CTL0 0x04 167#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 168#define MV88E6XXX_PORT_CTL0_SA_FILT_MASK 0xc000 169#define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED 0x0000 170#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK 0x4000 171#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK 0x8000 172#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU 0xc000 173#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 174#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 175#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 176#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 177#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 178#define MV88E6XXX_PORT_CTL0_HEADER 0x0800 179#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 180#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 181#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 182#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 183#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 184#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 185#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 186#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 187#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 188#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 189#define MV88E6185_PORT_CTL0_USE_IP 0x0020 190#define MV88E6185_PORT_CTL0_USE_TAG 0x0010 191#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 192#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC 0x0004 193#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC 0x0008 194#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 195#define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 196#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 197#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 198#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 199 200/* Offset 0x05: Port Control 1 */ 201#define MV88E6XXX_PORT_CTL1 0x05 202#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 203#define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000 204#define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00 205#define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8 206#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff 207 208/* Offset 0x06: Port Based VLAN Map */ 209#define MV88E6XXX_PORT_BASE_VLAN 0x06 210#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 211 212/* Offset 0x07: Default Port VLAN ID & Priority */ 213#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 214#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff 215 216/* Offset 0x08: Port Control 2 Register */ 217#define MV88E6XXX_PORT_CTL2 0x08 218#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 219#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000 220#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000 221#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 222#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 223#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 224#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 225#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 226#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 227#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000 228#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400 229#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800 230#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00 231#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200 232#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100 233#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 234#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 235#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 236#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 237#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f 238 239/* Offset 0x09: Egress Rate Control */ 240#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 241 242/* Offset 0x0A: Egress Rate Control 2 */ 243#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a 244 245/* Offset 0x0B: Port Association Vector */ 246#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b 247#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 248#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 249#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 250#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 251#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 252 253/* Offset 0x0C: Port ATU Control */ 254#define MV88E6XXX_PORT_ATU_CTL 0x0c 255 256/* Offset 0x0D: Priority Override Register */ 257#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d 258 259/* Offset 0x0E: Policy Control Register */ 260#define MV88E6XXX_PORT_POLICY_CTL 0x0e 261#define MV88E6XXX_PORT_POLICY_CTL_DA_MASK 0xc000 262#define MV88E6XXX_PORT_POLICY_CTL_SA_MASK 0x3000 263#define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK 0x0c00 264#define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK 0x0300 265#define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK 0x00c0 266#define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030 267#define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK 0x000c 268#define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK 0x0003 269#define MV88E6XXX_PORT_POLICY_CTL_NORMAL 0x0000 270#define MV88E6XXX_PORT_POLICY_CTL_MIRROR 0x0001 271#define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002 272#define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003 273 274/* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */ 275#define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e 276#define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000 277#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00 278#define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff 279#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000 280#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100 281#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400 282#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500 283#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000 284#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800 285#define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0 286 287/* Offset 0x0F: Port Special Ether Type */ 288#define MV88E6XXX_PORT_ETH_TYPE 0x0f 289#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 290 291/* Offset 0x10: InDiscards Low Counter */ 292#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 293 294/* Offset 0x10: Extended Port Control Command */ 295#define MV88E6393X_PORT_EPC_CMD 0x10 296#define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000 297#define MV88E6393X_PORT_EPC_CMD_WRITE 0x3000 298#define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02 299 300/* Offset 0x11: Extended Port Control Data */ 301#define MV88E6393X_PORT_EPC_DATA 0x11 302 303/* Offset 0x11: InDiscards High Counter */ 304#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 305 306/* Offset 0x12: InFiltered Counter */ 307#define MV88E6XXX_PORT_IN_FILTERED 0x12 308 309/* Offset 0x13: OutFiltered Counter */ 310#define MV88E6XXX_PORT_OUT_FILTERED 0x13 311 312/* Offset 0x16: LED Control */ 313#define MV88E6XXX_PORT_LED_CONTROL 0x16 314#define MV88E6XXX_PORT_LED_CONTROL_UPDATE BIT(15) 315#define MV88E6XXX_PORT_LED_CONTROL_POINTER_MASK GENMASK(14, 12) 316#define MV88E6XXX_PORT_LED_CONTROL_POINTER_LED01_CTRL (0x00 << 12) /* Control for LED 0 and 1 */ 317#define MV88E6XXX_PORT_LED_CONTROL_POINTER_STRETCH_BLINK (0x06 << 12) /* Stetch and Blink Rate */ 318#define MV88E6XXX_PORT_LED_CONTROL_POINTER_CNTL_SPECIAL (0x07 << 12) /* Control for the Port's Special LED */ 319#define MV88E6XXX_PORT_LED_CONTROL_DATA_MASK GENMASK(10, 0) 320/* Selection masks valid for either port 1,2,3,4 or 5 */ 321#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL_MASK GENMASK(3, 0) 322#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL_MASK GENMASK(7, 4) 323/* Selection control for LED 0 and 1, ports 5 and 6 only has LED 0 324 * Bits Function 325 * 0..3 LED 0 control selector on ports 1-5 326 * 4..7 LED 1 control selector on ports 1-4 on port 5 this controls LED 0 of port 6 327 * 328 * Sel Port LED Function for the 6352 family: 329 * 0 1-4 0 Link/Act/Speed by Blink Rate (off=no link, on=link, blink=activity, blink speed=link speed) 330 * 1-4 1 Port 2's Special LED 331 * 5-6 0 Port 5 Link/Act (off=no link, on=link, blink=activity) 332 * 5-6 1 Port 6 Link/Act (off=no link, on=link 1000, blink=activity) 333 * 1 1-4 0 100/1000 Link/Act (off=no link, on=100 or 1000 link, blink=activity) 334 * 1-4 1 10/100 Link Act (off=no link, on=10 or 100 link, blink=activity) 335 * 5-6 0 Fiber 100 Link/Act (off=no link, on=link 100, blink=activity) 336 * 5-6 1 Fiber 1000 Link/Act (off=no link, on=link 1000, blink=activity) 337 * 2 1-4 0 1000 Link/Act (off=no link, on=link 1000, blink=activity) 338 * 1-4 1 10/100 Link/Act (off=no link, on=10 or 100 link, blink=activity) 339 * 5-6 0 Fiber 1000 Link/Act (off=no link, on=link 1000, blink=activity) 340 * 5-6 1 Fiber 100 Link/Act (off=no link, on=link 100, blink=activity) 341 * 3 1-4 0 Link/Act (off=no link, on=link, blink=activity) 342 * 1-4 1 1000 Link (off=no link, on=1000 link) 343 * 5-6 0 Port 0's Special LED 344 * 5-6 1 Fiber Link (off=no link, on=link) 345 * 4 1-4 0 Port 0's Special LED 346 * 1-4 1 Port 1's Special LED 347 * 5-6 0 Port 1's Special LED 348 * 5-6 1 Port 5 Link/Act (off=no link, on=link, blink=activity) 349 * 5 1-4 0 Reserved 350 * 1-4 1 Reserved 351 * 5-6 0 Port 2's Special LED 352 * 5-6 1 Port 6 Link (off=no link, on=link) 353 * 6 1-4 0 Duplex/Collision (off=half-duplex,on=full-duplex,blink=collision) 354 * 1-4 1 10/1000 Link/Act (off=no link, on=10 or 1000 link, blink=activity) 355 * 5-6 0 Port 5 Duplex/Collision (off=half-duplex, on=full-duplex, blink=col) 356 * 5-6 1 Port 6 Duplex/Collision (off=half-duplex, on=full-duplex, blink=col) 357 * 7 1-4 0 10/1000 Link/Act (off=no link, on=10 or 1000 link, blink=activity) 358 * 1-4 1 10/1000 Link (off=no link, on=10 or 1000 link) 359 * 5-6 0 Port 5 Link/Act/Speed by Blink rate (off=no link, on=link, blink=activity, blink speed=link speed) 360 * 5-6 1 Port 6 Link/Act/Speed by Blink rate (off=no link, on=link, blink=activity, blink speed=link speed) 361 * 8 1-4 0 Link (off=no link, on=link) 362 * 1-4 1 Activity (off=no link, blink on=activity) 363 * 5-6 0 Port 6 Link/Act (off=no link, on=link, blink=activity) 364 * 5-6 1 Port 0's Special LED 365 * 9 1-4 0 10 Link (off=no link, on=10 link) 366 * 1-4 1 100 Link (off=no link, on=100 link) 367 * 5-6 0 Reserved 368 * 5-6 1 Port 1's Special LED 369 * a 1-4 0 10 Link/Act (off=no link, on=10 link, blink=activity) 370 * 1-4 1 100 Link/Act (off=no link, on=100 link, blink=activity) 371 * 5-6 0 Reserved 372 * 5-6 1 Port 2's Special LED 373 * b 1-4 0 100/1000 Link (off=no link, on=100 or 1000 link) 374 * 1-4 1 10/100 Link (off=no link, on=100 link, blink=activity) 375 * 5-6 0 Reserved 376 * 5-6 1 Reserved 377 * c * * PTP Act (blink on=PTP activity) 378 * d * * Force Blink 379 * e * * Force Off 380 * f * * Force On 381 */ 382/* Select LED0 output */ 383#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL0 0x0 384#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL1 0x1 385#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL2 0x2 386#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL3 0x3 387#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL4 0x4 388#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL5 0x5 389#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL6 0x6 390#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL7 0x7 391#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL8 0x8 392#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL9 0x9 393#define MV88E6XXX_PORT_LED_CONTROL_LED0_SELA 0xa 394#define MV88E6XXX_PORT_LED_CONTROL_LED0_SELB 0xb 395#define MV88E6XXX_PORT_LED_CONTROL_LED0_SELC 0xc 396#define MV88E6XXX_PORT_LED_CONTROL_LED0_SELD 0xd 397#define MV88E6XXX_PORT_LED_CONTROL_LED0_SELE 0xe 398#define MV88E6XXX_PORT_LED_CONTROL_LED0_SELF 0xf 399#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL0 (0x0 << 4) 400#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL1 (0x1 << 4) 401#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL2 (0x2 << 4) 402#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL3 (0x3 << 4) 403#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL4 (0x4 << 4) 404#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL5 (0x5 << 4) 405#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL6 (0x6 << 4) 406#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL7 (0x7 << 4) 407#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL8 (0x8 << 4) 408#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL9 (0x9 << 4) 409#define MV88E6XXX_PORT_LED_CONTROL_LED1_SELA (0xa << 4) 410#define MV88E6XXX_PORT_LED_CONTROL_LED1_SELB (0xb << 4) 411#define MV88E6XXX_PORT_LED_CONTROL_LED1_SELC (0xc << 4) 412#define MV88E6XXX_PORT_LED_CONTROL_LED1_SELD (0xd << 4) 413#define MV88E6XXX_PORT_LED_CONTROL_LED1_SELE (0xe << 4) 414#define MV88E6XXX_PORT_LED_CONTROL_LED1_SELF (0xf << 4) 415/* Stretch and Blink Rate Control (Index 0x06 of LED Control) */ 416/* Pulse Stretch Selection for all LED's on this port */ 417#define MV88E6XXX_PORT_LED_CONTROL_0x06_PULSE_STRETCH_NONE (0 << 4) 418#define MV88E6XXX_PORT_LED_CONTROL_0x06_PULSE_STRETCH_21MS (1 << 4) 419#define MV88E6XXX_PORT_LED_CONTROL_0x06_PULSE_STRETCH_42MS (2 << 4) 420#define MV88E6XXX_PORT_LED_CONTROL_0x06_PULSE_STRETCH_84MS (3 << 4) 421#define MV88E6XXX_PORT_LED_CONTROL_0x06_PULSE_STRETCH_168MS (4 << 4) 422/* Blink Rate Selection for all LEDs on this port */ 423#define MV88E6XXX_PORT_LED_CONTROL_0x06_BLINK_RATE_21MS 0 424#define MV88E6XXX_PORT_LED_CONTROL_0x06_BLINK_RATE_42MS 1 425#define MV88E6XXX_PORT_LED_CONTROL_0x06_BLINK_RATE_84MS 2 426#define MV88E6XXX_PORT_LED_CONTROL_0x06_BLINK_RATE_168MS 3 427#define MV88E6XXX_PORT_LED_CONTROL_0x06_BLINK_RATE_336MS 4 428#define MV88E6XXX_PORT_LED_CONTROL_0x06_BLINK_RATE_672MS 5 429 /* Control for Special LED (Index 0x7 of LED Control on Port0) */ 430#define MV88E6XXX_PORT_LED_CONTROL_0x07_P0_LAN_LINKACT_SHIFT 0 /* bits 6:0 LAN Link Activity LED */ 431/* Control for Special LED (Index 0x7 of LED Control on Port 1) */ 432#define MV88E6XXX_PORT_LED_CONTROL_0x07_P1_WAN_LINKACT_SHIFT 0 /* bits 6:0 WAN Link Activity LED */ 433/* Control for Special LED (Index 0x7 of LED Control on Port 2) */ 434#define MV88E6XXX_PORT_LED_CONTROL_0x07_P2_PTP_ACT 0 /* bits 6:0 PTP Activity */ 435 436/* Offset 0x18: IEEE Priority Mapping Table */ 437#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 438#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 439#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 440#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 441#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 442#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 443#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 444#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 445#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 446#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 447#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 448#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff 449 450/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ 451#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 452 453/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ 454#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 455 456/* Offset 0x1a: Magic undocumented errata register */ 457#define MV88E6XXX_PORT_RESERVED_1A 0x1a 458#define MV88E6XXX_PORT_RESERVED_1A_BUSY 0x8000 459#define MV88E6XXX_PORT_RESERVED_1A_WRITE 0x4000 460#define MV88E6XXX_PORT_RESERVED_1A_READ 0x0000 461#define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT 5 462#define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT 10 463#define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT 0x04 464#define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT 0x05 465#define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE 0x8000 466#define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000 467 468int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 469 u16 *val); 470int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 471 u16 val); 472int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 473 int bit, int val); 474 475int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 476 int pause); 477int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 478 phy_interface_t mode); 479int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 480 phy_interface_t mode); 481int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 482 phy_interface_t mode); 483 484int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 485 486int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 487int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 488 489int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 490 int speed, int duplex); 491int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 492 int speed, int duplex); 493int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 494 int speed, int duplex); 495int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 496 int speed, int duplex); 497int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 498 int speed, int duplex); 499int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 500 int speed, int duplex); 501int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 502 int speed, int duplex); 503 504phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip, 505 int port); 506phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip, 507 int port); 508phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 509 int port); 510phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 511 int port); 512 513int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 514 515int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 516 517int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 518int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 519 520int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 521int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 522 523int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 524 bool locked); 525 526int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 527 u16 mode); 528int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 529int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 530int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 531 enum mv88e6xxx_egress_mode mode); 532int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 533 enum mv88e6xxx_frame_mode mode); 534int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 535 enum mv88e6xxx_frame_mode mode); 536int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 537 int port, bool unicast); 538int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 539 int port, bool multicast); 540int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 541 bool unicast); 542int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 543 bool multicast); 544int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 545 enum mv88e6xxx_policy_mapping mapping, 546 enum mv88e6xxx_policy_action action); 547int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 548 enum mv88e6xxx_policy_mapping mapping, 549 enum mv88e6xxx_policy_action action); 550int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 551 u16 etype); 552int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 553 enum mv88e6xxx_egress_direction direction, 554 int port); 555int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 556 int upstream_port); 557int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 558int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 559 u16 etype); 560int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 561 bool message_port); 562int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 563 bool trunk, u8 id); 564int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 565 size_t size); 566int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 567int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 568int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 569 u16 pav); 570int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 571 u8 out); 572int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 573 u8 out); 574int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 575 phy_interface_t mode); 576int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 577 phy_interface_t mode); 578int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 579 phy_interface_t mode); 580int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 581 phy_interface_t mode); 582int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 583int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 584#ifdef CONFIG_NET_DSA_MV88E6XXX_LEDS 585int mv88e6xxx_port_setup_leds(struct mv88e6xxx_chip *chip, int port); 586#else 587static inline int mv88e6xxx_port_setup_leds(struct mv88e6xxx_chip *chip, 588 int port) 589{ 590 return 0; 591} 592#endif 593int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 594 bool drop_untagged); 595int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map); 596int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 597 int upstream_port); 598int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 599 enum mv88e6xxx_egress_direction direction, 600 bool mirror); 601 602int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 603int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 604 605int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block, 606 int port, int reg, u16 val); 607int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip); 608int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port, 609 int reg, u16 *val); 610 611#endif /* _MV88E6XXX_PORT_H */
~/
Read-only file preview.