FILE
mt7530.h
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linux-6.19.14/drivers/net/dsa/mt7530.h
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6#ifndef __MT7530_H 7#define __MT7530_H 8 9#define MT7530_NUM_PORTS 7 10#define MT7530_NUM_PHYS 5 11#define MT7530_NUM_FDB_RECORDS 2048 12#define MT7530_ALL_MEMBERS 0xff 13 14#define MTK_HDR_LEN 4 15#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 ID_MT7988 = 3, 22 ID_EN7581 = 4, 23 ID_AN7583 = 5, 24}; 25 26#define NUM_TRGMII_CTRL 5 27 28#define TRGMII_BASE(x) (0x10000 + (x)) 29 30/* Registers to ethsys access */ 31#define ETHSYS_CLKCFG0 0x2c 32#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 33 34#define SYSC_REG_RSTCTRL 0x34 35#define RESET_MCM BIT(2) 36 37/* Register for ARL global control */ 38#define MT753X_AGC 0xc 39#define LOCAL_EN BIT(7) 40 41/* Register for MAC forward control */ 42#define MT753X_MFC 0x10 43#define BC_FFP_MASK GENMASK(31, 24) 44#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) 45#define UNM_FFP_MASK GENMASK(23, 16) 46#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) 47#define UNU_FFP_MASK GENMASK(15, 8) 48#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) 49#define MT7530_CPU_EN BIT(7) 50#define MT7530_CPU_PORT_MASK GENMASK(6, 4) 51#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) 52#define MT7530_MIRROR_EN BIT(3) 53#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0) 54#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) 55#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) 56#define MT7531_QRY_FFP_MASK GENMASK(7, 0) 57#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) 58 59/* Register for CPU forward control */ 60#define MT7531_CFC 0x4 61#define MT7531_MIRROR_EN BIT(19) 62#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16) 63#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) 64#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) 65#define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 66#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) 67 68#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \ 69 id == ID_MT7988 || \ 70 id == ID_EN7581 || \ 71 id == ID_AN7583) ? \ 72 MT7531_CFC : MT753X_MFC) 73 74#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \ 75 id == ID_MT7988 || \ 76 id == ID_EN7581) ? \ 77 MT7531_MIRROR_EN : MT7530_MIRROR_EN) 78 79#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \ 80 id == ID_MT7988 || \ 81 id == ID_EN7581 || \ 82 id == ID_AN7583) ? \ 83 MT7531_MIRROR_PORT_MASK : \ 84 MT7530_MIRROR_PORT_MASK) 85 86#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \ 87 id == ID_MT7988 || \ 88 id == ID_EN7581 || \ 89 id == ID_AN7583) ? \ 90 MT7531_MIRROR_PORT_GET(val) : \ 91 MT7530_MIRROR_PORT_GET(val)) 92 93#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \ 94 id == ID_MT7988 || \ 95 id == ID_EN7581 || \ 96 id == ID_AN7583) ? \ 97 MT7531_MIRROR_PORT_SET(val) : \ 98 MT7530_MIRROR_PORT_SET(val)) 99 100/* Register for BPDU and PAE frame control */ 101#define MT753X_BPC 0x24 102#define PAE_BPDU_FR BIT(25) 103#define PAE_EG_TAG_MASK GENMASK(24, 22) 104#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) 105#define PAE_PORT_FW_MASK GENMASK(18, 16) 106#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) 107#define BPDU_EG_TAG_MASK GENMASK(8, 6) 108#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) 109#define BPDU_PORT_FW_MASK GENMASK(2, 0) 110 111/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ 112#define MT753X_RGAC1 0x28 113#define R02_BPDU_FR BIT(25) 114#define R02_EG_TAG_MASK GENMASK(24, 22) 115#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) 116#define R02_PORT_FW_MASK GENMASK(18, 16) 117#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) 118#define R01_BPDU_FR BIT(9) 119#define R01_EG_TAG_MASK GENMASK(8, 6) 120#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) 121#define R01_PORT_FW_MASK GENMASK(2, 0) 122 123/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ 124#define MT753X_RGAC2 0x2c 125#define R0E_BPDU_FR BIT(25) 126#define R0E_EG_TAG_MASK GENMASK(24, 22) 127#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) 128#define R0E_PORT_FW_MASK GENMASK(18, 16) 129#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) 130#define R03_BPDU_FR BIT(9) 131#define R03_EG_TAG_MASK GENMASK(8, 6) 132#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) 133#define R03_PORT_FW_MASK GENMASK(2, 0) 134 135enum mt753x_to_cpu_fw { 136 TO_CPU_FW_SYSTEM_DEFAULT, 137 TO_CPU_FW_CPU_EXCLUDE = 4, 138 TO_CPU_FW_CPU_INCLUDE = 5, 139 TO_CPU_FW_CPU_ONLY = 6, 140 TO_CPU_FW_DROP = 7, 141}; 142 143/* Registers for address table access */ 144#define MT7530_ATA1 0x74 145#define STATIC_EMP 0 146#define STATIC_ENT 3 147#define MT7530_ATA2 0x78 148#define ATA2_IVL BIT(15) 149#define ATA2_FID(x) (((x) & 0x7) << 12) 150 151/* Register for address table write data */ 152#define MT7530_ATWD 0x7c 153 154/* Register for address table control */ 155#define MT7530_ATC 0x80 156#define ATC_HASH (((x) & 0xfff) << 16) 157#define ATC_BUSY BIT(15) 158#define ATC_SRCH_END BIT(14) 159#define ATC_SRCH_HIT BIT(13) 160#define ATC_INVALID BIT(12) 161#define ATC_MAT(x) (((x) & 0xf) << 8) 162#define ATC_MAT_MACTAB ATC_MAT(0) 163 164enum mt7530_fdb_cmd { 165 MT7530_FDB_READ = 0, 166 MT7530_FDB_WRITE = 1, 167 MT7530_FDB_FLUSH = 2, 168 MT7530_FDB_START = 4, 169 MT7530_FDB_NEXT = 5, 170}; 171 172/* Registers for table search read address */ 173#define MT7530_TSRA1 0x84 174#define MAC_BYTE_0 24 175#define MAC_BYTE_1 16 176#define MAC_BYTE_2 8 177#define MAC_BYTE_3 0 178#define MAC_BYTE_MASK 0xff 179 180#define MT7530_TSRA2 0x88 181#define MAC_BYTE_4 24 182#define MAC_BYTE_5 16 183#define CVID 0 184#define CVID_MASK 0xfff 185 186#define MT7530_ATRD 0x8C 187#define AGE_TIMER 24 188#define AGE_TIMER_MASK 0xff 189#define PORT_MAP 4 190#define PORT_MAP_MASK 0xff 191#define ENT_STATUS 2 192#define ENT_STATUS_MASK 0x3 193 194/* Register for vlan table control */ 195#define MT7530_VTCR 0x90 196#define VTCR_BUSY BIT(31) 197#define VTCR_INVALID BIT(16) 198#define VTCR_FUNC(x) (((x) & 0xf) << 12) 199#define VTCR_VID ((x) & 0xfff) 200 201enum mt7530_vlan_cmd { 202 /* Read/Write the specified VID entry from VAWD register based 203 * on VID. 204 */ 205 MT7530_VTCR_RD_VID = 0, 206 MT7530_VTCR_WR_VID = 1, 207}; 208 209/* Register for setup vlan and acl write data */ 210#define MT7530_VAWD1 0x94 211#define PORT_STAG BIT(31) 212/* Independent VLAN Learning */ 213#define IVL_MAC BIT(30) 214/* Egress Tag Consistent */ 215#define EG_CON BIT(29) 216/* Per VLAN Egress Tag Control */ 217#define VTAG_EN BIT(28) 218/* VLAN Member Control */ 219#define PORT_MEM(x) (((x) & 0xff) << 16) 220/* Filter ID */ 221#define FID(x) (((x) & 0x7) << 1) 222/* VLAN Entry Valid */ 223#define VLAN_VALID BIT(0) 224#define PORT_MEM_SHFT 16 225#define PORT_MEM_MASK 0xff 226 227enum mt7530_fid { 228 FID_STANDALONE = 0, 229 FID_BRIDGED = 1, 230}; 231 232#define MT7530_VAWD2 0x98 233/* Egress Tag Control */ 234#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 235#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 236 237enum mt7530_vlan_egress_attr { 238 MT7530_VLAN_EGRESS_UNTAG = 0, 239 MT7530_VLAN_EGRESS_TAG = 2, 240 MT7530_VLAN_EGRESS_STACK = 3, 241}; 242 243/* Register for address age control */ 244#define MT7530_AAC 0xa0 245/* Disable ageing */ 246#define AGE_DIS BIT(20) 247/* Age count */ 248#define AGE_CNT_MASK GENMASK(19, 12) 249#define AGE_CNT_MAX 0xff 250#define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 251/* Age unit */ 252#define AGE_UNIT_MASK GENMASK(11, 0) 253#define AGE_UNIT_MAX 0xfff 254#define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 255 256#define MT753X_ERLCR_P(x) (0x1040 + ((x) * 0x100)) 257#define ERLCR_CIR_MASK GENMASK(31, 16) 258#define ERLCR_EN_MASK BIT(15) 259#define ERLCR_EXP_MASK GENMASK(11, 8) 260#define ERLCR_TBF_MODE_MASK BIT(7) 261#define ERLCR_MANT_MASK GENMASK(6, 0) 262 263#define MT753X_GERLCR 0x10e0 264#define EGR_BC_MASK GENMASK(7, 0) 265#define EGR_BC_CRC 0x4 /* crc */ 266#define EGR_BC_CRC_IPG_PREAMBLE 0x18 /* crc + ipg + preamble */ 267 268/* Register for port STP state control */ 269#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 270#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) 271#define FID_PST_MASK(fid) FID_PST(fid, 0x3) 272 273enum mt7530_stp_state { 274 MT7530_STP_DISABLED = 0, 275 MT7530_STP_BLOCKING = 1, 276 MT7530_STP_LISTENING = 1, 277 MT7530_STP_LEARNING = 2, 278 MT7530_STP_FORWARDING = 3 279}; 280 281/* Register for port control */ 282#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 283#define PORT_TX_MIR BIT(9) 284#define PORT_RX_MIR BIT(8) 285#define PORT_VLAN(x) ((x) & 0x3) 286 287enum mt7530_port_mode { 288 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 289 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 290 291 /* Fallback Mode: Forward received frames with ingress ports that do 292 * not belong to the VLAN member. Frames whose VID is not listed on 293 * the VLAN table are forwarded by the PCR_MATRIX members. 294 */ 295 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 296 297 /* Security Mode: Discard any frame due to ingress membership 298 * violation or VID missed on the VLAN table. 299 */ 300 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 301}; 302 303#define PCR_MATRIX(x) (((x) & 0xff) << 16) 304#define PORT_PRI(x) (((x) & 0x7) << 24) 305#define EG_TAG(x) (((x) & 0x3) << 28) 306#define PCR_MATRIX_MASK PCR_MATRIX(0xff) 307#define PCR_MATRIX_CLR PCR_MATRIX(0) 308#define PCR_PORT_VLAN_MASK PORT_VLAN(3) 309 310/* Register for port security control */ 311#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 312#define SA_DIS BIT(4) 313 314/* Register for port vlan control */ 315#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 316#define PORT_SPEC_TAG BIT(5) 317#define PVC_EG_TAG(x) (((x) & 0x7) << 8) 318#define PVC_EG_TAG_MASK PVC_EG_TAG(7) 319#define VLAN_ATTR(x) (((x) & 0x3) << 6) 320#define VLAN_ATTR_MASK VLAN_ATTR(3) 321#define ACC_FRM_MASK GENMASK(1, 0) 322 323enum mt7530_vlan_port_eg_tag { 324 MT7530_VLAN_EG_DISABLED = 0, 325 MT7530_VLAN_EG_CONSISTENT = 1, 326 MT7530_VLAN_EG_UNTAGGED = 4, 327}; 328 329enum mt7530_vlan_port_attr { 330 MT7530_VLAN_USER = 0, 331 MT7530_VLAN_TRANSPARENT = 3, 332}; 333 334enum mt7530_vlan_port_acc_frm { 335 MT7530_VLAN_ACC_ALL = 0, 336 MT7530_VLAN_ACC_TAGGED = 1, 337 MT7530_VLAN_ACC_UNTAGGED = 2, 338}; 339 340#define STAG_VPID (((x) & 0xffff) << 16) 341 342/* Register for port port-and-protocol based vlan 1 control */ 343#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 344#define G0_PORT_VID(x) (((x) & 0xfff) << 0) 345#define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 346#define G0_PORT_VID_DEF G0_PORT_VID(0) 347 348/* Register for port MAC control register */ 349#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) 350#define PMCR_IFG_XMIT_MASK GENMASK(19, 18) 351#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) 352#define PMCR_EXT_PHY BIT(17) 353#define PMCR_MAC_MODE BIT(16) 354#define MT7530_FORCE_MODE BIT(15) 355#define PMCR_MAC_TX_EN BIT(14) 356#define PMCR_MAC_RX_EN BIT(13) 357#define PMCR_BACKOFF_EN BIT(9) 358#define PMCR_BACKPR_EN BIT(8) 359#define PMCR_FORCE_EEE1G BIT(7) 360#define PMCR_FORCE_EEE100 BIT(6) 361#define PMCR_FORCE_RX_FC_EN BIT(5) 362#define PMCR_FORCE_TX_FC_EN BIT(4) 363#define PMCR_FORCE_SPEED_1000 BIT(3) 364#define PMCR_FORCE_SPEED_100 BIT(2) 365#define PMCR_FORCE_FDX BIT(1) 366#define PMCR_FORCE_LNK BIT(0) 367#define MT7531_FORCE_MODE_LNK BIT(31) 368#define MT7531_FORCE_MODE_SPD BIT(30) 369#define MT7531_FORCE_MODE_DPX BIT(29) 370#define MT7531_FORCE_MODE_RX_FC BIT(28) 371#define MT7531_FORCE_MODE_TX_FC BIT(27) 372#define MT7531_FORCE_MODE_EEE100 BIT(26) 373#define MT7531_FORCE_MODE_EEE1G BIT(25) 374#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \ 375 MT7531_FORCE_MODE_SPD | \ 376 MT7531_FORCE_MODE_DPX | \ 377 MT7531_FORCE_MODE_RX_FC | \ 378 MT7531_FORCE_MODE_TX_FC | \ 379 MT7531_FORCE_MODE_EEE100 | \ 380 MT7531_FORCE_MODE_EEE1G) 381#define MT753X_FORCE_MODE(id) ((id == ID_MT7531 || \ 382 id == ID_MT7988) ? \ 383 MT7531_FORCE_MODE_MASK : \ 384 MT7530_FORCE_MODE) 385#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \ 386 PMCR_FORCE_EEE1G | \ 387 PMCR_FORCE_EEE100 | \ 388 PMCR_FORCE_RX_FC_EN | \ 389 PMCR_FORCE_TX_FC_EN | \ 390 PMCR_FORCE_SPEED_1000 | \ 391 PMCR_FORCE_SPEED_100 | \ 392 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 393 394#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) 395#define WAKEUP_TIME_1000_MASK GENMASK(31, 24) 396#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) 397#define WAKEUP_TIME_100_MASK GENMASK(23, 16) 398#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) 399#define LPI_THRESH_MASK GENMASK(15, 4) 400#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) 401#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) 402#define LPI_MODE_EN BIT(0) 403 404#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 405#define PMSR_EEE1G BIT(7) 406#define PMSR_EEE100M BIT(6) 407#define PMSR_RX_FC BIT(5) 408#define PMSR_TX_FC BIT(4) 409#define PMSR_SPEED_1000 BIT(3) 410#define PMSR_SPEED_100 BIT(2) 411#define PMSR_SPEED_10 0x00 412#define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 413#define PMSR_DPX BIT(1) 414#define PMSR_LINK BIT(0) 415 416/* Register for port debug count */ 417#define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 418#define MT7531_DIS_CLR BIT(31) 419 420#define MT7530_GMACCR 0x30e0 421#define MAX_RX_JUMBO(x) ((x) << 2) 422#define MAX_RX_JUMBO_MASK GENMASK(5, 2) 423#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 424#define MAX_RX_PKT_LEN_1522 0x0 425#define MAX_RX_PKT_LEN_1536 0x1 426#define MAX_RX_PKT_LEN_1552 0x2 427#define MAX_RX_PKT_LEN_JUMBO 0x3 428 429/* Register for MIB */ 430#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 431/* Each define is an offset of MT7530_PORT_MIB_COUNTER */ 432#define MT7530_PORT_MIB_TX_DROP 0x00 433#define MT7530_PORT_MIB_TX_CRC_ERR 0x04 434#define MT7530_PORT_MIB_TX_UNICAST 0x08 435#define MT7530_PORT_MIB_TX_MULTICAST 0x0c 436#define MT7530_PORT_MIB_TX_BROADCAST 0x10 437#define MT7530_PORT_MIB_TX_COLLISION 0x14 438#define MT7530_PORT_MIB_TX_SINGLE_COLLISION 0x18 439#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c 440#define MT7530_PORT_MIB_TX_DEFERRED 0x20 441#define MT7530_PORT_MIB_TX_LATE_COLLISION 0x24 442#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28 443#define MT7530_PORT_MIB_TX_PAUSE 0x2c 444#define MT7530_PORT_MIB_TX_PKT_SZ_64 0x30 445#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34 446#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38 447#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3c 448#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40 449#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX 0x44 450#define MT7530_PORT_MIB_TX_BYTES 0x48 /* 64 bytes */ 451#define MT7530_PORT_MIB_RX_DROP 0x60 452#define MT7530_PORT_MIB_RX_FILTERING 0x64 453#define MT7530_PORT_MIB_RX_UNICAST 0x68 454#define MT7530_PORT_MIB_RX_MULTICAST 0x6c 455#define MT7530_PORT_MIB_RX_BROADCAST 0x70 456#define MT7530_PORT_MIB_RX_ALIGN_ERR 0x74 457#define MT7530_PORT_MIB_RX_CRC_ERR 0x78 458#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR 0x7c 459#define MT7530_PORT_MIB_RX_FRAG_ERR 0x80 460#define MT7530_PORT_MIB_RX_OVER_SZ_ERR 0x84 461#define MT7530_PORT_MIB_RX_JABBER_ERR 0x88 462#define MT7530_PORT_MIB_RX_PAUSE 0x8c 463#define MT7530_PORT_MIB_RX_PKT_SZ_64 0x90 464#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 0x94 465#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 0x98 466#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 0x9c 467#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xa0 468#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX 0xa4 469#define MT7530_PORT_MIB_RX_BYTES 0xa8 /* 64 bytes */ 470#define MT7530_PORT_MIB_RX_CTRL_DROP 0xb0 471#define MT7530_PORT_MIB_RX_INGRESS_DROP 0xb4 472#define MT7530_PORT_MIB_RX_ARL_DROP 0xb8 473#define MT7530_MIB_CCR 0x4fe0 474#define CCR_MIB_ENABLE BIT(31) 475#define CCR_RX_OCT_CNT_GOOD BIT(7) 476#define CCR_RX_OCT_CNT_BAD BIT(6) 477#define CCR_TX_OCT_CNT_GOOD BIT(5) 478#define CCR_TX_OCT_CNT_BAD BIT(4) 479#define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 480 CCR_RX_OCT_CNT_BAD | \ 481 CCR_TX_OCT_CNT_GOOD | \ 482 CCR_TX_OCT_CNT_BAD) 483#define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 484 CCR_RX_OCT_CNT_GOOD | \ 485 CCR_RX_OCT_CNT_BAD | \ 486 CCR_TX_OCT_CNT_GOOD | \ 487 CCR_TX_OCT_CNT_BAD) 488 489/* MT7531 SGMII register group */ 490#define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000) 491#define MT7531_PHYA_CTRL_SIGNAL3 0x128 492 493/* Register for system reset */ 494#define MT7530_SYS_CTRL 0x7000 495#define SYS_CTRL_PHY_RST BIT(2) 496#define SYS_CTRL_SW_RST BIT(1) 497#define SYS_CTRL_REG_RST BIT(0) 498 499/* Register for system interrupt */ 500#define MT7530_SYS_INT_EN 0x7008 501 502/* Register for system interrupt status */ 503#define MT7530_SYS_INT_STS 0x700c 504 505/* Register for PHY Indirect Access Control */ 506#define MT7531_PHY_IAC 0x701C 507#define MT7531_PHY_ACS_ST BIT(31) 508#define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 509#define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 510#define MT7531_MDIO_CMD_MASK (0x3 << 18) 511#define MT7531_MDIO_ST_MASK (0x3 << 16) 512#define MT7531_MDIO_RW_DATA_MASK (0xffff) 513#define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 514#define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 515#define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 516#define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 517#define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 518 519enum mt7531_phy_iac_cmd { 520 MT7531_MDIO_ADDR = 0, 521 MT7531_MDIO_WRITE = 1, 522 MT7531_MDIO_READ = 2, 523 MT7531_MDIO_READ_CL45 = 3, 524}; 525 526/* MDIO_ST: MDIO start field */ 527enum mt7531_mdio_st { 528 MT7531_MDIO_ST_CL45 = 0, 529 MT7531_MDIO_ST_CL22 = 1, 530}; 531 532#define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 533 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 534#define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 535 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 536#define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 537 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 538#define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 539 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 540#define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 541 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 542 543/* Register for RGMII clock phase */ 544#define MT7531_CLKGEN_CTRL 0x7500 545#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 546#define CLK_SKEW_OUT_MASK GENMASK(9, 8) 547#define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 548#define CLK_SKEW_IN_MASK GENMASK(7, 6) 549#define RXCLK_NO_DELAY BIT(5) 550#define TXCLK_NO_REVERSE BIT(4) 551#define GP_MODE(x) (((x) & 0x3) << 1) 552#define GP_MODE_MASK GENMASK(2, 1) 553#define GP_CLK_EN BIT(0) 554 555enum mt7531_gp_mode { 556 MT7531_GP_MODE_RGMII = 0, 557 MT7531_GP_MODE_MII = 1, 558 MT7531_GP_MODE_REV_MII = 2 559}; 560 561enum mt7531_clk_skew { 562 MT7531_CLK_SKEW_NO_CHG = 0, 563 MT7531_CLK_SKEW_DLY_100PPS = 1, 564 MT7531_CLK_SKEW_DLY_200PPS = 2, 565 MT7531_CLK_SKEW_REVERSE = 3, 566}; 567 568/* Register for trap status */ 569#define MT753X_TRAP 0x7800 570#define MT7530_XTAL_MASK (BIT(10) | BIT(9)) 571#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9)) 572#define MT7530_XTAL_40MHZ BIT(10) 573#define MT7530_XTAL_20MHZ BIT(9) 574#define MT7531_XTAL25 BIT(7) 575 576/* Register for trap modification */ 577#define MT753X_MTRAP 0x7804 578#define MT7530_P5_PHY0_SEL BIT(20) 579#define MT7530_CHG_TRAP BIT(16) 580#define MT7530_P5_MAC_SEL BIT(13) 581#define MT7530_P6_DIS BIT(8) 582#define MT7530_P5_RGMII_MODE BIT(7) 583#define MT7530_P5_DIS BIT(6) 584#define MT7530_PHY_INDIRECT_ACCESS BIT(5) 585#define MT7531_CHG_STRAP BIT(8) 586#define MT7531_PHY_EN BIT(6) 587 588enum mt7531_xtal_fsel { 589 MT7531_XTAL_FSEL_25MHZ, 590 MT7531_XTAL_FSEL_40MHZ, 591}; 592 593/* Register for TOP signal control */ 594#define MT7530_TOP_SIG_CTRL 0x7808 595#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 596 597#define MT7531_TOP_SIG_SR 0x780c 598#define PAD_DUAL_SGMII_EN BIT(1) 599#define PAD_MCM_SMI_EN BIT(0) 600 601#define MT7530_IO_DRV_CR 0x7810 602#define P5_IO_CLK_DRV(x) ((x) & 0x3) 603#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 604 605#define MT7531_CHIP_REV 0x781C 606 607#define MT7531_PLLGP_EN 0x7820 608#define EN_COREPLL BIT(2) 609#define SW_CLKSW BIT(1) 610#define SW_PLLGP BIT(0) 611 612#define MT7530_P6ECR 0x7830 613#define P6_INTF_MODE_MASK 0x3 614#define P6_INTF_MODE(x) ((x) & 0x3) 615 616#define MT7531_PLLGP_CR0 0x78a8 617#define RG_COREPLL_EN BIT(22) 618#define RG_COREPLL_POSDIV_S 23 619#define RG_COREPLL_POSDIV_M 0x3800000 620#define RG_COREPLL_SDM_PCW_S 1 621#define RG_COREPLL_SDM_PCW_M 0x3ffffe 622#define RG_COREPLL_SDM_PCW_CHG BIT(0) 623 624/* Registers for RGMII and SGMII PLL clock */ 625#define MT7531_ANA_PLLGP_CR2 0x78b0 626#define MT7531_ANA_PLLGP_CR5 0x78bc 627 628/* Registers for TRGMII on the both side */ 629#define MT7530_TRGMII_RCK_CTRL 0x7a00 630#define RX_RST BIT(31) 631#define RXC_DQSISEL BIT(30) 632#define DQSI1_TAP_MASK (0x7f << 8) 633#define DQSI0_TAP_MASK 0x7f 634#define DQSI1_TAP(x) (((x) & 0x7f) << 8) 635#define DQSI0_TAP(x) ((x) & 0x7f) 636 637#define MT7530_TRGMII_RCK_RTT 0x7a04 638#define DQS1_GATE BIT(31) 639#define DQS0_GATE BIT(30) 640 641#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 642#define BSLIP_EN BIT(31) 643#define EDGE_CHK BIT(30) 644#define RD_TAP_MASK 0x7f 645#define RD_TAP(x) ((x) & 0x7f) 646 647#define MT7530_TRGMII_TXCTRL 0x7a40 648#define TRAIN_TXEN BIT(31) 649#define TXC_INV BIT(30) 650#define TX_RST BIT(28) 651 652#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 653#define TD_DM_DRVP(x) ((x) & 0xf) 654#define TD_DM_DRVN(x) (((x) & 0xf) << 4) 655 656#define MT7530_TRGMII_TCK_CTRL 0x7a78 657#define TCK_TAP(x) (((x) & 0xf) << 8) 658 659#define MT7530_P5RGMIIRXCR 0x7b00 660#define CSR_RGMII_EDGE_ALIGN BIT(8) 661#define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 662 663#define MT7530_P5RGMIITXCR 0x7b04 664#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 665 666/* Registers for GPIO mode */ 667#define MT7531_GPIO_MODE0 0x7c0c 668#define MT7531_GPIO0_MASK GENMASK(3, 0) 669#define MT7531_GPIO0_INTERRUPT 1 670 671#define MT7531_GPIO_MODE1 0x7c10 672#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 673#define MT7531_EXT_P_MDC_11 (2 << 12) 674#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 675#define MT7531_EXT_P_MDIO_12 (2 << 16) 676 677#define MT753X_CPORT_SPTAG_CFG 0x7c10 678#define CPORT_SW2FE_STAG_EN BIT(1) 679#define CPORT_FE2SW_STAG_EN BIT(0) 680 681#define AN7583_GEPHY_CONN_CFG 0x7c14 682#define AN7583_CSR_DPHY_CKIN_SEL BIT(31) 683#define AN7583_CSR_PHY_CORE_REG_CLK_SEL BIT(30) 684#define AN7583_CSR_ETHER_AFE_PWD GENMASK(28, 24) 685 686/* Registers for LED GPIO control (MT7530 only) 687 * All registers follow this pattern: 688 * [ 2: 0] port 0 689 * [ 6: 4] port 1 690 * [10: 8] port 2 691 * [14:12] port 3 692 * [18:16] port 4 693 */ 694 695/* LED enable, 0: Disable, 1: Enable (Default) */ 696#define MT7530_LED_EN 0x7d00 697/* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 698#define MT7530_LED_IO_MODE 0x7d04 699/* GPIO direction, 0: Input, 1: Output */ 700#define MT7530_LED_GPIO_DIR 0x7d10 701/* GPIO output enable, 0: Disable, 1: Enable */ 702#define MT7530_LED_GPIO_OE 0x7d14 703/* GPIO value, 0: Low, 1: High */ 704#define MT7530_LED_GPIO_DATA 0x7d18 705 706#define MT7530_CREV 0x7ffc 707#define CHIP_NAME_SHIFT 16 708#define MT7530_ID 0x7530 709 710#define MT7531_CREV 0x781C 711#define CHIP_REV_M 0x0f 712#define MT7531_ID 0x7531 713 714/* Registers for core PLL access through mmd indirect */ 715#define CORE_PLL_GROUP2 0x401 716#define RG_SYSPLL_EN_NORMAL BIT(15) 717#define RG_SYSPLL_VODEN BIT(14) 718#define RG_SYSPLL_LF BIT(13) 719#define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 720#define RG_SYSPLL_LVROD_EN BIT(10) 721#define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 722#define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 723#define RG_SYSPLL_FBKSEL BIT(4) 724#define RT_SYSPLL_EN_AFE_OLT BIT(0) 725 726#define CORE_PLL_GROUP4 0x403 727#define RG_SYSPLL_DDSFBK_EN BIT(12) 728#define RG_SYSPLL_BIAS_EN BIT(11) 729#define RG_SYSPLL_BIAS_LPF_EN BIT(10) 730#define MT7531_RG_SYSPLL_DMY2 BIT(6) 731#define MT7531_PHY_PLL_OFF BIT(5) 732#define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 733 734#define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f) 735 736#define CORE_PLL_GROUP5 0x404 737#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 738 739#define CORE_PLL_GROUP6 0x405 740#define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 741 742#define CORE_PLL_GROUP7 0x406 743#define RG_LCDDS_PWDB BIT(15) 744#define RG_LCDDS_ISO_EN BIT(13) 745#define RG_LCCDS_C(x) (((x) & 0x7) << 4) 746#define RG_LCDDS_PCW_NCPO_CHG BIT(3) 747 748#define CORE_PLL_GROUP10 0x409 749#define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 750 751#define CORE_PLL_GROUP11 0x40a 752#define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 753 754#define CORE_GSWPLL_GRP1 0x40d 755#define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 756#define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 757#define RG_GSWPLL_EN_PRE BIT(11) 758#define RG_GSWPLL_FBKSEL BIT(10) 759#define RG_GSWPLL_BP BIT(9) 760#define RG_GSWPLL_BR BIT(8) 761#define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 762 763#define CORE_GSWPLL_GRP2 0x40e 764#define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 765#define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 766 767#define CORE_TRGMII_GSW_CLK_CG 0x410 768#define REG_GSWCK_EN BIT(0) 769#define REG_TRGMIICK_EN BIT(1) 770 771#define MIB_DESC(_s, _o, _n) \ 772 { \ 773 .size = (_s), \ 774 .offset = (_o), \ 775 .name = (_n), \ 776 } 777 778struct mt7530_mib_desc { 779 unsigned int size; 780 unsigned int offset; 781 const char *name; 782}; 783 784struct mt7530_fdb { 785 u16 vid; 786 u8 port_mask; 787 u8 aging; 788 u8 mac[6]; 789 bool noarp; 790}; 791 792/* struct mt7530_port - This is the main data structure for holding the state 793 * of the port. 794 * @enable: The status used for show port is enabled or not. 795 * @pm: The matrix used to show all connections with the port. 796 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 797 * untagged frames will be assigned to the related VLAN. 798 * @sgmii_pcs: Pointer to PCS instance for SerDes ports 799 */ 800struct mt7530_port { 801 bool enable; 802 bool isolated; 803 u32 pm; 804 u16 pvid; 805 struct phylink_pcs *sgmii_pcs; 806}; 807 808/* Port 5 mode definitions of the MT7530 switch */ 809enum mt7530_p5_mode { 810 GMAC5, 811 MUX_PHY_P0, 812 MUX_PHY_P4, 813}; 814 815struct mt7530_priv; 816 817struct mt753x_pcs { 818 struct phylink_pcs pcs; 819 struct mt7530_priv *priv; 820 int port; 821}; 822 823/* struct mt753x_info - This is the main data structure for holding the specific 824 * part for each supported device 825 * @id: Holding the identifier to a switch model 826 * @pcs_ops: Holding the pointer to the MAC PCS operations structure 827 * @sw_setup: Holding the handler to a device initialization 828 * @phy_read_c22: Holding the way reading PHY port using C22 829 * @phy_write_c22: Holding the way writing PHY port using C22 830 * @phy_read_c45: Holding the way reading PHY port using C45 831 * @phy_write_c45: Holding the way writing PHY port using C45 832 * @mac_port_get_caps: Holding the handler that provides MAC capabilities 833 * @mac_port_config: Holding the way setting up the PHY attribute to a 834 * certain MAC port 835 */ 836struct mt753x_info { 837 enum mt753x_id id; 838 839 const struct phylink_pcs_ops *pcs_ops; 840 841 int (*sw_setup)(struct dsa_switch *ds); 842 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); 843 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, 844 u16 val); 845 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, 846 int regnum); 847 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, 848 int regnum, u16 val); 849 void (*mac_port_get_caps)(struct dsa_switch *ds, int port, 850 struct phylink_config *config); 851 void (*mac_port_config)(struct dsa_switch *ds, int port, 852 unsigned int mode, 853 phy_interface_t interface); 854}; 855 856/* struct mt7530_priv - This is the main data structure for holding the state 857 * of the driver 858 * @dev: The device pointer 859 * @ds: The pointer to the dsa core structure 860 * @bus: The bus used for the device and built-in PHY 861 * @regmap: The regmap instance representing all switch registers 862 * @rstc: The pointer to reset control used by MCM 863 * @core_pwr: The power supplied into the core 864 * @io_pwr: The power supplied into the I/O 865 * @reset: The descriptor for GPIO line tied to its reset pin 866 * @mcm: Flag for distinguishing if standalone IC or module 867 * coupling 868 * @ports: Holding the state among ports 869 * @reg_mutex: The lock for protecting among process accessing 870 * registers 871 * @p5_mode: Holding the current mode of port 5 of the MT7530 switch 872 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch 873 * has got SGMII 874 * @irq_domain: IRQ domain of the switch irq_chip 875 * @create_sgmii: Pointer to function creating SGMII PCS instance(s) 876 * @active_cpu_ports: Holding the active CPU ports 877 * @mdiodev: The pointer to the MDIO device structure 878 */ 879struct mt7530_priv { 880 struct device *dev; 881 struct dsa_switch *ds; 882 struct mii_bus *bus; 883 struct regmap *regmap; 884 struct reset_control *rstc; 885 struct regulator *core_pwr; 886 struct regulator *io_pwr; 887 struct gpio_desc *reset; 888 const struct mt753x_info *info; 889 unsigned int id; 890 bool mcm; 891 enum mt7530_p5_mode p5_mode; 892 bool p5_sgmii; 893 u8 mirror_rx; 894 u8 mirror_tx; 895 struct mt7530_port ports[MT7530_NUM_PORTS]; 896 struct mt753x_pcs pcs[MT7530_NUM_PORTS]; 897 /* protect among processes for registers access*/ 898 struct mutex reg_mutex; 899 struct irq_domain *irq_domain; 900 int (*create_sgmii)(struct mt7530_priv *priv); 901 u8 active_cpu_ports; 902 struct mdio_device *mdiodev; 903}; 904 905struct mt7530_hw_vlan_entry { 906 int port; 907 u8 old_members; 908 bool untagged; 909}; 910 911static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 912 int port, bool untagged) 913{ 914 e->port = port; 915 e->untagged = untagged; 916} 917 918typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 919 struct mt7530_hw_vlan_entry *); 920 921struct mt7530_hw_stats { 922 const char *string; 923 u16 reg; 924 u8 sizeof_stat; 925}; 926 927struct mt7530_dummy_poll { 928 struct mt7530_priv *priv; 929 u32 reg; 930}; 931 932static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 933 struct mt7530_priv *priv, u32 reg) 934{ 935 p->priv = priv; 936 p->reg = reg; 937} 938 939int mt7530_probe_common(struct mt7530_priv *priv); 940void mt7530_remove_common(struct mt7530_priv *priv); 941 942extern const struct mt753x_info mt753x_table[]; 943 944#endif /* __MT7530_H */
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