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ksz_common.h
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linux-6.19.14/drivers/net/dsa/microchip/ksz_common.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2025 Microchip Technology Inc. 5 */ 6 7#ifndef __KSZ_COMMON_H 8#define __KSZ_COMMON_H 9 10#include <linux/etherdevice.h> 11#include <linux/kernel.h> 12#include <linux/mutex.h> 13#include <linux/pcs/pcs-xpcs.h> 14#include <linux/phy.h> 15#include <linux/regmap.h> 16#include <net/dsa.h> 17#include <linux/irq.h> 18#include <linux/platform_data/microchip-ksz.h> 19 20#include "ksz_ptp.h" 21 22#define KSZ_MAX_NUM_PORTS 8 23/* all KSZ switches count ports from 1 */ 24#define KSZ_PORT_1 0 25#define KSZ_PORT_2 1 26#define KSZ_PORT_4 3 27 28struct ksz_device; 29struct ksz_port; 30struct phylink_mac_ops; 31 32enum ksz_regmap_width { 33 KSZ_REGMAP_8, 34 KSZ_REGMAP_16, 35 KSZ_REGMAP_32, 36 __KSZ_NUM_REGMAPS, 37}; 38 39struct vlan_table { 40 u32 table[3]; 41}; 42 43struct ksz_port_mib { 44 struct mutex cnt_mutex; /* structure access */ 45 u8 cnt_ptr; 46 u64 *counters; 47 struct rtnl_link_stats64 stats64; 48 struct ethtool_pause_stats pause_stats; 49 struct spinlock stats64_lock; 50}; 51 52struct ksz_mib_names { 53 int index; 54 char string[ETH_GSTRING_LEN]; 55}; 56 57struct ksz_chip_data { 58 u32 chip_id; 59 const char *dev_name; 60 int num_vlans; 61 int num_alus; 62 int num_statics; 63 int cpu_ports; 64 int port_cnt; 65 u8 port_nirqs; 66 u8 num_tx_queues; 67 u8 num_ipms; /* number of Internal Priority Maps */ 68 bool tc_cbs_supported; 69 70 /** 71 * @phy_side_mdio_supported: Indicates if the chip supports an additional 72 * side MDIO channel for accessing integrated PHYs. 73 */ 74 bool phy_side_mdio_supported; 75 const struct ksz_dev_ops *ops; 76 const struct phylink_mac_ops *phylink_mac_ops; 77 bool phy_errata_9477; 78 bool ksz87xx_eee_link_erratum; 79 const struct ksz_mib_names *mib_names; 80 int mib_cnt; 81 u8 reg_mib_cnt; 82 const u16 *regs; 83 const u32 *masks; 84 const u8 *shifts; 85 const u8 *xmii_ctrl0; 86 const u8 *xmii_ctrl1; 87 int stp_ctrl_reg; 88 int broadcast_ctrl_reg; 89 int multicast_ctrl_reg; 90 int start_ctrl_reg; 91 bool supports_mii[KSZ_MAX_NUM_PORTS]; 92 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 93 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 94 bool internal_phy[KSZ_MAX_NUM_PORTS]; 95 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 96 bool ptp_capable; 97 u8 sgmii_port; 98 const struct regmap_access_table *wr_table; 99 const struct regmap_access_table *rd_table; 100}; 101 102struct ksz_irq { 103 u16 masked; 104 u16 reg_mask; 105 u16 reg_status; 106 struct irq_domain *domain; 107 int nirqs; 108 int irq_num; 109 char name[16]; 110 struct ksz_device *dev; 111}; 112 113struct ksz_ptp_irq { 114 struct ksz_port *port; 115 u16 ts_reg; 116 bool ts_en; 117 char name[16]; 118 int num; 119}; 120 121struct ksz_switch_macaddr { 122 unsigned char addr[ETH_ALEN]; 123 refcount_t refcount; 124}; 125 126struct ksz_port { 127 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 128 bool learning; 129 bool isolated; 130 int stp_state; 131 struct phy_device phydev; 132 133 u32 fiber:1; /* port is fiber */ 134 u32 force:1; 135 u32 read:1; /* read MIB counters in background */ 136 u32 freeze:1; /* MIB counter freeze is enabled */ 137 u32 sgmii_adv_write:1; 138 139 struct ksz_port_mib mib; 140 phy_interface_t interface; 141 u32 rgmii_tx_val; 142 u32 rgmii_rx_val; 143 struct ksz_device *ksz_dev; 144 void *acl_priv; 145 struct ksz_irq pirq; 146 u8 num; 147 struct phylink_pcs *pcs; 148#if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 149 struct kernel_hwtstamp_config tstamp_config; 150 bool hwts_tx_en; 151 bool hwts_rx_en; 152 struct ksz_irq ptpirq; 153 struct ksz_ptp_irq ptpmsg_irq[3]; 154 ktime_t tstamp_msg; 155 struct completion tstamp_msg_comp; 156#endif 157 bool manual_flow; 158}; 159 160struct ksz_device { 161 struct dsa_switch *ds; 162 struct ksz_platform_data *pdata; 163 const struct ksz_chip_data *info; 164 165 struct mutex dev_mutex; /* device access */ 166 struct mutex regmap_mutex; /* regmap access */ 167 struct mutex alu_mutex; /* ALU access */ 168 struct mutex vlan_mutex; /* vlan access */ 169 const struct ksz_dev_ops *dev_ops; 170 171 struct device *dev; 172 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 173 174 void *priv; 175 int irq; 176 177 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 178 179 /* chip specific data */ 180 u32 chip_id; 181 u8 chip_rev; 182 int cpu_port; /* port connected to CPU */ 183 int phy_port_cnt; 184 phy_interface_t compat_interface; 185 bool synclko_125; 186 bool synclko_disable; 187 bool wakeup_source; 188 bool pme_active_high; 189 190 struct vlan_table *vlan_cache; 191 192 struct ksz_port *ports; 193 struct delayed_work mib_read; 194 unsigned long mib_read_interval; 195 u16 mirror_rx; 196 u16 mirror_tx; 197 u16 port_mask; 198 struct mutex lock_irq; /* IRQ Access */ 199 struct ksz_irq girq; 200 struct ksz_ptp_data ptp_data; 201 202 struct ksz_switch_macaddr *switch_macaddr; 203 struct net_device *hsr_dev; /* HSR */ 204 u8 hsr_ports; 205 206 /** 207 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 208 * addresses. 209 */ 210 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 211 212 /** 213 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 214 * 215 * This points to an external MDIO bus controller that is used to access 216 * the PHYs integrated within the switch. Unlike an integrated MDIO 217 * bus, this external controller provides a direct path for managing 218 * the switch’s internal PHYs, bypassing the main SPI interface. 219 */ 220 struct mii_bus *parent_mdio_bus; 221}; 222 223/* List of supported models */ 224enum ksz_model { 225 KSZ8463, 226 KSZ8563, 227 KSZ8567, 228 KSZ8795, 229 KSZ8794, 230 KSZ8765, 231 KSZ88X3, 232 KSZ8864, 233 KSZ8895, 234 KSZ9477, 235 KSZ9896, 236 KSZ9897, 237 KSZ9893, 238 KSZ9563, 239 KSZ9567, 240 LAN9370, 241 LAN9371, 242 LAN9372, 243 LAN9373, 244 LAN9374, 245 LAN9646, 246}; 247 248enum ksz_regs { 249 REG_SW_MAC_ADDR, 250 REG_IND_CTRL_0, 251 REG_IND_DATA_8, 252 REG_IND_DATA_CHECK, 253 REG_IND_DATA_HI, 254 REG_IND_DATA_LO, 255 REG_IND_MIB_CHECK, 256 REG_IND_BYTE, 257 P_FORCE_CTRL, 258 P_LINK_STATUS, 259 P_LOCAL_CTRL, 260 P_NEG_RESTART_CTRL, 261 P_REMOTE_STATUS, 262 P_SPEED_STATUS, 263 S_TAIL_TAG_CTRL, 264 P_STP_CTRL, 265 S_START_CTRL, 266 S_BROADCAST_CTRL, 267 S_MULTICAST_CTRL, 268 P_XMII_CTRL_0, 269 P_XMII_CTRL_1, 270 REG_SW_PME_CTRL, 271 REG_PORT_PME_STATUS, 272 REG_PORT_PME_CTRL, 273}; 274 275enum ksz_masks { 276 PORT_802_1P_REMAPPING, 277 SW_TAIL_TAG_ENABLE, 278 MIB_COUNTER_OVERFLOW, 279 MIB_COUNTER_VALID, 280 VLAN_TABLE_FID, 281 VLAN_TABLE_MEMBERSHIP, 282 VLAN_TABLE_VALID, 283 STATIC_MAC_TABLE_VALID, 284 STATIC_MAC_TABLE_USE_FID, 285 STATIC_MAC_TABLE_FID, 286 STATIC_MAC_TABLE_OVERRIDE, 287 STATIC_MAC_TABLE_FWD_PORTS, 288 DYNAMIC_MAC_TABLE_ENTRIES_H, 289 DYNAMIC_MAC_TABLE_MAC_EMPTY, 290 DYNAMIC_MAC_TABLE_NOT_READY, 291 DYNAMIC_MAC_TABLE_ENTRIES, 292 DYNAMIC_MAC_TABLE_FID, 293 DYNAMIC_MAC_TABLE_SRC_PORT, 294 DYNAMIC_MAC_TABLE_TIMESTAMP, 295 ALU_STAT_WRITE, 296 ALU_STAT_READ, 297 ALU_STAT_DIRECT, 298 ALU_RESV_MCAST_ADDR, 299 P_MII_TX_FLOW_CTRL, 300 P_MII_RX_FLOW_CTRL, 301}; 302 303enum ksz_shifts { 304 VLAN_TABLE_MEMBERSHIP_S, 305 VLAN_TABLE, 306 STATIC_MAC_FWD_PORTS, 307 STATIC_MAC_FID, 308 DYNAMIC_MAC_ENTRIES_H, 309 DYNAMIC_MAC_ENTRIES, 310 DYNAMIC_MAC_FID, 311 DYNAMIC_MAC_TIMESTAMP, 312 DYNAMIC_MAC_SRC_PORT, 313 ALU_STAT_INDEX, 314}; 315 316enum ksz_xmii_ctrl0 { 317 P_MII_100MBIT, 318 P_MII_10MBIT, 319 P_MII_FULL_DUPLEX, 320 P_MII_HALF_DUPLEX, 321}; 322 323enum ksz_xmii_ctrl1 { 324 P_RGMII_SEL, 325 P_RMII_SEL, 326 P_GMII_SEL, 327 P_MII_SEL, 328 P_GMII_1GBIT, 329 P_GMII_NOT_1GBIT, 330}; 331 332struct alu_struct { 333 /* entry 1 */ 334 u8 is_static:1; 335 u8 is_src_filter:1; 336 u8 is_dst_filter:1; 337 u8 prio_age:3; 338 u32 _reserv_0_1:23; 339 u8 mstp:3; 340 /* entry 2 */ 341 u8 is_override:1; 342 u8 is_use_fid:1; 343 u32 _reserv_1_1:23; 344 u8 port_forward:7; 345 /* entry 3 & 4*/ 346 u32 _reserv_2_1:9; 347 u8 fid:7; 348 u8 mac[ETH_ALEN]; 349}; 350 351struct ksz_dev_ops { 352 int (*setup)(struct dsa_switch *ds); 353 void (*teardown)(struct dsa_switch *ds); 354 u32 (*get_port_addr)(int port, int offset); 355 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 356 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 357 void (*port_cleanup)(struct ksz_device *dev, int port); 358 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 359 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 360 361 /** 362 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus 363 * for accessing PHYs. 364 * @dev: Pointer to device structure. 365 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 366 * MDIO bus. 367 * 368 * This function pointer is used to configure the MDIO bus for PHY 369 * access before initiating regular PHY operations. It enables either 370 * SPI/I2C or side MDIO access modes by unlocking necessary registers 371 * and setting up access permissions for the selected mode. 372 * 373 * Return: 374 * - 0 on success. 375 * - Negative error code on failure. 376 */ 377 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); 378 379 /** 380 * @create_phy_addr_map: Function pointer to create a port-to-PHY 381 * address map. 382 * @dev: Pointer to device structure. 383 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 384 * MDIO bus. 385 * 386 * This function pointer is responsible for mapping switch ports to PHY 387 * addresses according to the configured access mode (SPI or side MDIO) 388 * and the device’s strap configuration. The mapping setup may vary 389 * depending on the chip variant and configuration. Ensures the correct 390 * address mapping for PHY communication. 391 * 392 * Return: 393 * - 0 on success. 394 * - Negative error code on failure (e.g., invalid configuration). 395 */ 396 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); 397 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 398 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 399 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 400 u64 *cnt); 401 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 402 u64 *dropped, u64 *cnt); 403 void (*r_mib_stat64)(struct ksz_device *dev, int port); 404 int (*vlan_filtering)(struct ksz_device *dev, int port, 405 bool flag, struct netlink_ext_ack *extack); 406 int (*vlan_add)(struct ksz_device *dev, int port, 407 const struct switchdev_obj_port_vlan *vlan, 408 struct netlink_ext_ack *extack); 409 int (*vlan_del)(struct ksz_device *dev, int port, 410 const struct switchdev_obj_port_vlan *vlan); 411 int (*mirror_add)(struct ksz_device *dev, int port, 412 struct dsa_mall_mirror_tc_entry *mirror, 413 bool ingress, struct netlink_ext_ack *extack); 414 void (*mirror_del)(struct ksz_device *dev, int port, 415 struct dsa_mall_mirror_tc_entry *mirror); 416 int (*fdb_add)(struct ksz_device *dev, int port, 417 const unsigned char *addr, u16 vid, struct dsa_db db); 418 int (*fdb_del)(struct ksz_device *dev, int port, 419 const unsigned char *addr, u16 vid, struct dsa_db db); 420 int (*fdb_dump)(struct ksz_device *dev, int port, 421 dsa_fdb_dump_cb_t *cb, void *data); 422 int (*mdb_add)(struct ksz_device *dev, int port, 423 const struct switchdev_obj_port_mdb *mdb, 424 struct dsa_db db); 425 int (*mdb_del)(struct ksz_device *dev, int port, 426 const struct switchdev_obj_port_mdb *mdb, 427 struct dsa_db db); 428 void (*get_caps)(struct ksz_device *dev, int port, 429 struct phylink_config *config); 430 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 431 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 432 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 433 u8 *data); 434 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 435 u8 data); 436 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 437 void (*port_init_cnt)(struct ksz_device *dev, int port); 438 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 439 unsigned int mode, 440 phy_interface_t interface, 441 struct phy_device *phydev, int speed, 442 int duplex, bool tx_pause, bool rx_pause); 443 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 444 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 445 void (*config_cpu_port)(struct dsa_switch *ds); 446 int (*enable_stp_addr)(struct ksz_device *dev); 447 int (*reset)(struct ksz_device *dev); 448 int (*init)(struct ksz_device *dev); 449 void (*exit)(struct ksz_device *dev); 450 451 int (*pcs_create)(struct ksz_device *dev); 452}; 453 454struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 455int ksz_switch_register(struct ksz_device *dev); 456void ksz_switch_remove(struct ksz_device *dev); 457int ksz_switch_suspend(struct device *dev); 458int ksz_switch_resume(struct device *dev); 459 460void ksz_init_mib_timer(struct ksz_device *dev); 461bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 462void ksz_r_mib_stats64(struct ksz_device *dev, int port); 463void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 464void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 465bool ksz_get_gbit(struct ksz_device *dev, int port); 466phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 467extern const struct ksz_chip_data ksz_switch_chips[]; 468int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 469 struct netlink_ext_ack *extack); 470void ksz_switch_macaddr_put(struct dsa_switch *ds); 471void ksz_switch_shutdown(struct ksz_device *dev); 472int ksz_handle_wake_reason(struct ksz_device *dev, int port); 473 474/* Common register access functions */ 475static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 476{ 477 return dev->regmap[KSZ_REGMAP_8]; 478} 479 480static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 481{ 482 return dev->regmap[KSZ_REGMAP_16]; 483} 484 485static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 486{ 487 return dev->regmap[KSZ_REGMAP_32]; 488} 489 490static inline bool ksz_is_ksz8463(struct ksz_device *dev) 491{ 492 return dev->chip_id == KSZ8463_CHIP_ID; 493} 494 495static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 496{ 497 unsigned int value; 498 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 499 500 if (ret) 501 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 502 ERR_PTR(ret)); 503 504 *val = value; 505 return ret; 506} 507 508static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 509{ 510 unsigned int value; 511 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 512 513 if (ret) 514 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 515 ERR_PTR(ret)); 516 517 *val = value; 518 return ret; 519} 520 521static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 522{ 523 unsigned int value; 524 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 525 526 if (ret) 527 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 528 ERR_PTR(ret)); 529 530 *val = value; 531 return ret; 532} 533 534static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 535{ 536 u32 value[2]; 537 int ret; 538 539 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 540 if (ret) 541 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 542 ERR_PTR(ret)); 543 else 544 *val = (u64)value[0] << 32 | value[1]; 545 546 return ret; 547} 548 549static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 550{ 551 int ret; 552 553 ret = regmap_write(ksz_regmap_8(dev), reg, value); 554 if (ret) 555 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 556 ERR_PTR(ret)); 557 558 return ret; 559} 560 561static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 562{ 563 int ret; 564 565 ret = regmap_write(ksz_regmap_16(dev), reg, value); 566 if (ret) 567 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 568 ERR_PTR(ret)); 569 570 return ret; 571} 572 573static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 574{ 575 int ret; 576 577 ret = regmap_write(ksz_regmap_32(dev), reg, value); 578 if (ret) 579 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 580 ERR_PTR(ret)); 581 582 return ret; 583} 584 585static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 586 u16 value) 587{ 588 int ret; 589 590 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 591 if (ret) 592 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 593 ERR_PTR(ret)); 594 595 return ret; 596} 597 598static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 599 u32 value) 600{ 601 int ret; 602 603 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 604 if (ret) 605 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 606 ERR_PTR(ret)); 607 608 return ret; 609} 610 611static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 612{ 613 u32 val[2]; 614 615 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 616 value = swab64(value); 617 val[0] = swab32(value & 0xffffffffULL); 618 val[1] = swab32(value >> 32ULL); 619 620 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 621} 622 623static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 624{ 625 int ret; 626 627 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 628 if (ret) 629 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 630 ERR_PTR(ret)); 631 632 return ret; 633} 634 635static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 636 u8 *data) 637{ 638 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 639} 640 641static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 642 u16 *data) 643{ 644 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 645} 646 647static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 648 u32 *data) 649{ 650 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 651} 652 653static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 654 u8 data) 655{ 656 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 657} 658 659static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 660 u16 data) 661{ 662 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 663 data); 664} 665 666static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 667 u32 data) 668{ 669 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 670 data); 671} 672 673static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 674 u8 mask, u8 val) 675{ 676 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 677 mask, val); 678} 679 680static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 681 u32 mask, u32 val) 682{ 683 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 684 mask, val); 685} 686 687static inline void ksz_regmap_lock(void *__mtx) 688{ 689 struct mutex *mtx = __mtx; 690 mutex_lock(mtx); 691} 692 693static inline void ksz_regmap_unlock(void *__mtx) 694{ 695 struct mutex *mtx = __mtx; 696 mutex_unlock(mtx); 697} 698 699static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 700{ 701 return dev->chip_id == KSZ8795_CHIP_ID || 702 dev->chip_id == KSZ8794_CHIP_ID || 703 dev->chip_id == KSZ8765_CHIP_ID; 704} 705 706static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 707{ 708 return dev->chip_id == KSZ88X3_CHIP_ID; 709} 710 711static inline bool ksz_is_8895_family(struct ksz_device *dev) 712{ 713 return dev->chip_id == KSZ8895_CHIP_ID || 714 dev->chip_id == KSZ8864_CHIP_ID; 715} 716 717static inline bool is_ksz8(struct ksz_device *dev) 718{ 719 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 720 ksz_is_8895_family(dev) || ksz_is_ksz8463(dev); 721} 722 723static inline bool is_ksz88xx(struct ksz_device *dev) 724{ 725 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) || 726 ksz_is_ksz8463(dev); 727} 728 729static inline bool is_ksz9477(struct ksz_device *dev) 730{ 731 return dev->chip_id == KSZ9477_CHIP_ID; 732} 733 734static inline int is_lan937x(struct ksz_device *dev) 735{ 736 return dev->chip_id == LAN9370_CHIP_ID || 737 dev->chip_id == LAN9371_CHIP_ID || 738 dev->chip_id == LAN9372_CHIP_ID || 739 dev->chip_id == LAN9373_CHIP_ID || 740 dev->chip_id == LAN9374_CHIP_ID; 741} 742 743static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 744{ 745 return (dev->chip_id == LAN9371_CHIP_ID || 746 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 747} 748 749static inline int ksz_get_sgmii_port(struct ksz_device *dev) 750{ 751 return dev->info->sgmii_port - 1; 752} 753 754static inline bool ksz_has_sgmii_port(struct ksz_device *dev) 755{ 756 return dev->info->sgmii_port > 0; 757} 758 759static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port) 760{ 761 return dev->info->sgmii_port == port + 1; 762} 763 764/* STP State Defines */ 765#define PORT_TX_ENABLE BIT(2) 766#define PORT_RX_ENABLE BIT(1) 767#define PORT_LEARN_DISABLE BIT(0) 768 769/* Switch ID Defines */ 770#define REG_CHIP_ID0 0x00 771 772#define SW_FAMILY_ID_M GENMASK(15, 8) 773#define KSZ84_FAMILY_ID 0x84 774#define KSZ87_FAMILY_ID 0x87 775#define KSZ88_FAMILY_ID 0x88 776#define KSZ8895_FAMILY_ID 0x95 777 778#define KSZ8_PORT_STATUS_0 0x08 779#define KSZ8_PORT_FIBER_MODE BIT(7) 780 781#define SW_CHIP_ID_M GENMASK(7, 4) 782#define KSZ87_CHIP_ID_94 0x6 783#define KSZ87_CHIP_ID_95 0x9 784#define KSZ88_CHIP_ID_63 0x3 785#define KSZ8895_CHIP_ID_95 0x4 786#define KSZ8895_CHIP_ID_95R 0x6 787 788/* KSZ8895 specific register */ 789#define REG_KSZ8864_CHIP_ID 0xFE 790#define SW_KSZ8864 BIT(7) 791 792#define SW_REV_ID_M GENMASK(7, 4) 793 794/* KSZ9893, KSZ9563, KSZ8563 specific register */ 795#define REG_CHIP_ID4 0x0f 796#define SKU_ID_KSZ8563 0x3c 797#define SKU_ID_KSZ9563 0x1c 798 799/* Driver set switch broadcast storm protection at 10% rate. */ 800#define BROADCAST_STORM_PROT_RATE 10 801 802/* 148,800 frames * 67 ms / 100 */ 803#define BROADCAST_STORM_VALUE 9969 804 805#define BROADCAST_STORM_RATE_HI 0x07 806#define BROADCAST_STORM_RATE_LO 0xFF 807#define BROADCAST_STORM_RATE 0x07FF 808 809#define MULTICAST_STORM_DISABLE BIT(6) 810 811#define SW_START 0x01 812 813/* xMII configuration */ 814#define P_MII_DUPLEX_M BIT(6) 815#define P_MII_100MBIT_M BIT(4) 816 817#define P_GMII_1GBIT_M BIT(6) 818#define P_RGMII_ID_IG_ENABLE BIT(4) 819#define P_RGMII_ID_EG_ENABLE BIT(3) 820#define P_MII_MAC_MODE BIT(2) 821#define P_MII_SEL_M 0x3 822 823/* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 824#define PME_WOL_MAGICPKT BIT(2) 825#define PME_WOL_LINKUP BIT(1) 826#define PME_WOL_ENERGY BIT(0) 827 828#define PME_ENABLE BIT(1) 829#define PME_POLARITY BIT(0) 830 831#define KSZ87XX_REG_INT_EN 0x7D 832#define KSZ87XX_INT_PME_MASK BIT(4) 833 834/* Interrupt */ 835#define REG_SW_PORT_INT_STATUS__1 0x001B 836#define REG_SW_PORT_INT_MASK__1 0x001F 837 838#define REG_PORT_INT_STATUS 0x001B 839#define REG_PORT_INT_MASK 0x001F 840 841#define PORT_SRC_PHY_INT 1 842#define PORT_SRC_PTP_INT 2 843 844#define KSZ8795_HUGE_PACKET_SIZE 2000 845#define KSZ8863_HUGE_PACKET_SIZE 1916 846#define KSZ8863_NORMAL_PACKET_SIZE 1536 847#define KSZ8_LEGAL_PACKET_SIZE 1518 848#define KSZ9477_MAX_FRAME_SIZE 9000 849 850#define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 851/* Drive Strength of I/O Pad 852 * 0: 8mA, 1: 16mA 853 */ 854#define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 855 856#define KSZ8795_REG_SW_CTRL_20 0xa3 857#define KSZ9477_REG_SW_IO_STRENGTH 0x010d 858#define SW_DRIVE_STRENGTH_M 0x7 859#define SW_DRIVE_STRENGTH_2MA 0 860#define SW_DRIVE_STRENGTH_4MA 1 861#define SW_DRIVE_STRENGTH_8MA 2 862#define SW_DRIVE_STRENGTH_12MA 3 863#define SW_DRIVE_STRENGTH_16MA 4 864#define SW_DRIVE_STRENGTH_20MA 5 865#define SW_DRIVE_STRENGTH_24MA 6 866#define SW_DRIVE_STRENGTH_28MA 7 867#define SW_HI_SPEED_DRIVE_STRENGTH_S 4 868#define SW_LO_SPEED_DRIVE_STRENGTH_S 0 869 870/* TXQ Split Control Register for per-port, per-queue configuration. 871 * Register 0xAF is TXQ Split for Q3 on Port 1. 872 * Register offset formula: 0xAF + (port * 4) + (3 - queue) 873 * where: port = 0..2, queue = 0..3 874 */ 875#define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \ 876 (0xAF + ((port) * 4) + (3 - (queue))) 877 878/* Bit 7 selects between: 879 * 0 = Strict priority mode (highest-priority queue first) 880 * 1 = Weighted Fair Queuing (WFQ) mode: 881 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1 882 * If any queues are empty, weight is redistributed. 883 * 884 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873 885 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs. 886 */ 887#define KSZ8873_TXQ_WFQ_ENABLE BIT(7) 888 889#define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 890#define KSZ9477_OUT_RATE_NO_LIMIT 0 891 892#define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 893 894#define KSZ9477_PORT_TC_MAP_S 4 895 896/* CBS related registers */ 897#define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 898 899#define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 900 901#define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 902#define MTI_SCHEDULE_STRICT_PRIO 0 903#define MTI_SCHEDULE_WRR 2 904#define MTI_SHAPING_M GENMASK(5, 4) 905#define MTI_SHAPING_OFF 0 906#define MTI_SHAPING_SRP 1 907#define MTI_SHAPING_TIME_AWARE 2 908 909#define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 910#define KSZ9477_DEFAULT_WRR_WEIGHT 1 911 912#define REG_PORT_MTI_HI_WATER_MARK 0x0916 913#define REG_PORT_MTI_LO_WATER_MARK 0x0918 914 915/* Regmap tables generation */ 916#define KSZ_SPI_OP_RD 3 917#define KSZ_SPI_OP_WR 2 918 919#define swabnot_used(x) 0 920 921#define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 922 swab##swp((opcode) << ((regbits) + (regpad))) 923 924#define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 925 { \ 926 .name = #width, \ 927 .val_bits = (width), \ 928 .reg_stride = 1, \ 929 .reg_bits = (regbits) + (regalign), \ 930 .pad_bits = (regpad), \ 931 .max_register = BIT(regbits) - 1, \ 932 .cache_type = REGCACHE_NONE, \ 933 .read_flag_mask = \ 934 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 935 regbits, regpad), \ 936 .write_flag_mask = \ 937 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 938 regbits, regpad), \ 939 .lock = ksz_regmap_lock, \ 940 .unlock = ksz_regmap_unlock, \ 941 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 942 .val_format_endian = REGMAP_ENDIAN_BIG \ 943 } 944 945#define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 946 static const struct regmap_config ksz##_regmap_config[] = { \ 947 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 948 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 949 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 950 } 951 952#define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \ 953 { \ 954 .name = #width, \ 955 .val_bits = (width), \ 956 .reg_stride = (width / 8), \ 957 .reg_bits = (regbits) + (regalign), \ 958 .pad_bits = (regpad), \ 959 .read = ksz8463_spi_read, \ 960 .write = ksz8463_spi_write, \ 961 .max_register = BIT(regbits) - 1, \ 962 .cache_type = REGCACHE_NONE, \ 963 .zero_flag_mask = 1, \ 964 .use_single_read = 1, \ 965 .use_single_write = 1, \ 966 .lock = ksz_regmap_lock, \ 967 .unlock = ksz_regmap_unlock, \ 968 } 969 970#define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \ 971 static const struct regmap_config ksz##_regmap_config[] = { \ 972 [KSZ_REGMAP_8] = KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalign)), \ 973 [KSZ_REGMAP_16] = KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regalign)), \ 974 [KSZ_REGMAP_32] = KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regalign)), \ 975 } 976 977#endif
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