mxl-gsw1xx.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Register definitions for MaxLinear GSW1xx series switches
  3 *
  4 * Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
  5 * Copyright (C) 2023 - 2024 MaxLinear Inc.
  6 */
  7#ifndef __MXL_GSW1XX_H
  8#define __MXL_GSW1XX_H
  9
 10#include <linux/bitfield.h>
 11
 12#define GSW1XX_PORTS				6
 13/* Port used for RGMII or optional RMII */
 14#define GSW1XX_MII_PORT				5
 15/* Port used for SGMII */
 16#define GSW1XX_SGMII_PORT			4
 17
 18#define GSW1XX_SYS_CLK_FREQ			340000000
 19
 20/* SMDIO switch register base address */
 21#define GSW1XX_SMDIO_BADR			0x1f
 22#define  GSW1XX_SMDIO_BADR_UNKNOWN		-1
 23
 24/* GSW1XX SGMII PCS */
 25#define GSW1XX_SGMII_BASE			0xd000
 26#define GSW1XX_SGMII_PHY_HWBU_CTRL		0x009
 27#define  GSW1XX_SGMII_PHY_HWBU_CTRL_EN_HWBU_FSM	BIT(0)
 28#define  GSW1XX_SGMII_PHY_HWBU_CTRL_HW_FSM_EN	BIT(3)
 29#define GSW1XX_SGMII_TBI_TXANEGH		0x300
 30#define GSW1XX_SGMII_TBI_TXANEGL		0x301
 31#define GSW1XX_SGMII_TBI_ANEGCTL		0x304
 32#define  GSW1XX_SGMII_TBI_ANEGCTL_LT		GENMASK(1, 0)
 33#define   GSW1XX_SGMII_TBI_ANEGCTL_LT_10US	0
 34#define   GSW1XX_SGMII_TBI_ANEGCTL_LT_1_6MS	1
 35#define   GSW1XX_SGMII_TBI_ANEGCTL_LT_5MS	2
 36#define   GSW1XX_SGMII_TBI_ANEGCTL_LT_10MS	3
 37#define  GSW1XX_SGMII_TBI_ANEGCTL_ANEGEN	BIT(2)
 38#define  GSW1XX_SGMII_TBI_ANEGCTL_RANEG		BIT(3)
 39#define  GSW1XX_SGMII_TBI_ANEGCTL_OVRABL	BIT(4)
 40#define  GSW1XX_SGMII_TBI_ANEGCTL_OVRANEG	BIT(5)
 41#define  GSW1XX_SGMII_TBI_ANEGCTL_ANMODE	GENMASK(7, 6)
 42#define   GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_1000BASEX	1
 43#define   GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_PHY	2
 44#define   GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_MAC	3
 45#define  GSW1XX_SGMII_TBI_ANEGCTL_BCOMP		BIT(15)
 46
 47#define GSW1XX_SGMII_TBI_TBICTL			0x305
 48#define  GSW1XX_SGMII_TBI_TBICTL_INITTBI	BIT(0)
 49#define  GSW1XX_SGMII_TBI_TBICTL_ENTBI		BIT(1)
 50#define  GSW1XX_SGMII_TBI_TBICTL_CRSTRR		BIT(4)
 51#define  GSW1XX_SGMII_TBI_TBICTL_CRSOFF		BIT(5)
 52#define GSW1XX_SGMII_TBI_TBISTAT		0x309
 53#define  GSW1XX_SGMII_TBI_TBISTAT_LINK		BIT(0)
 54#define  GSW1XX_SGMII_TBI_TBISTAT_AN_COMPLETE	BIT(1)
 55#define GSW1XX_SGMII_TBI_LPSTAT			0x30a
 56#define  GSW1XX_SGMII_TBI_LPSTAT_DUPLEX		BIT(0)
 57#define  GSW1XX_SGMII_TBI_LPSTAT_PAUSE_RX	BIT(1)
 58#define  GSW1XX_SGMII_TBI_LPSTAT_PAUSE_TX	BIT(2)
 59#define  GSW1XX_SGMII_TBI_LPSTAT_SPEED		GENMASK(6, 5)
 60#define   GSW1XX_SGMII_TBI_LPSTAT_SPEED_10	0
 61#define   GSW1XX_SGMII_TBI_LPSTAT_SPEED_100	1
 62#define   GSW1XX_SGMII_TBI_LPSTAT_SPEED_1000	2
 63#define   GSW1XX_SGMII_TBI_LPSTAT_SPEED_NOSGMII	3
 64#define GSW1XX_SGMII_PHY_D			0x100
 65#define GSW1XX_SGMII_PHY_A			0x101
 66#define GSW1XX_SGMII_PHY_C			0x102
 67#define  GSW1XX_SGMII_PHY_STATUS		BIT(0)
 68#define  GSW1XX_SGMII_PHY_READ			BIT(4)
 69#define  GSW1XX_SGMII_PHY_WRITE			BIT(8)
 70#define  GSW1XX_SGMII_PHY_RESET_N		BIT(12)
 71#define GSW1XX_SGMII_PCS_RXB_CTL		0x401
 72#define  GSW1XX_SGMII_PCS_RXB_CTL_INIT_RX_RXB	BIT(1)
 73#define GSW1XX_SGMII_PCS_TXB_CTL		0x404
 74#define  GSW1XX_SGMII_PCS_TXB_CTL_INIT_TX_TXB	BIT(1)
 75
 76#define GSW1XX_SGMII_PHY_RX0_CFG2		0x004
 77#define  GSW1XX_SGMII_PHY_RX0_CFG2_EQ		GENMASK(2, 0)
 78#define   GSW1XX_SGMII_PHY_RX0_CFG2_EQ_DEF	2
 79#define  GSW1XX_SGMII_PHY_RX0_CFG2_INVERT	BIT(3)
 80#define  GSW1XX_SGMII_PHY_RX0_CFG2_LOS_EN	BIT(4)
 81#define  GSW1XX_SGMII_PHY_RX0_CFG2_TERM_EN	BIT(5)
 82#define  GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT	GENMASK(12, 6)
 83#define   GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF	20
 84
 85#define GSW1XX_SGMII_PHY_TX0_CFG3		0x007
 86#define  GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_EN	BIT(12)
 87#define  GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL	GENMASK(11, 9)
 88#define   GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF	4
 89#define  GSW1XX_SGMII_PHY_TX0_CFG3_INVERT	BIT(8)
 90
 91/* GSW1XX PDI Registers */
 92#define GSW1XX_SWITCH_BASE			0xe000
 93
 94/* GSW1XX MII Registers */
 95#define GSW1XX_RGMII_BASE			0xf100
 96
 97/* GSW1XX GPIO Registers */
 98#define GSW1XX_GPIO_BASE			0xf300
 99#define GPIO_ALTSEL0				0x83
100#define GPIO_ALTSEL0_EXTPHY_MUX_VAL		0x03c3
101#define GPIO_ALTSEL1				0x84
102#define GPIO_ALTSEL1_EXTPHY_MUX_VAL		0x003f
103
104/* MDIO bus controller */
105#define GSW1XX_MMDIO_BASE			0xf400
106
107/* generic IC registers */
108#define GSW1XX_SHELL_BASE			0xfa00
109#define  GSW1XX_SHELL_RST_REQ			0x01
110#define   GSW1XX_RST_REQ_SGMII_SHELL		BIT(5)
111/* RGMII PAD Slew Control Register */
112#define  GSW1XX_SHELL_RGMII_SLEW_CFG		0x78
113#define   RGMII_SLEW_CFG_RX_2_5_V		BIT(4)
114#define   RGMII_SLEW_CFG_TX_2_5_V		BIT(5)
115
116/* SGMII clock related settings */
117#define GSW1XX_CLK_BASE				0xf900
118#define  GSW1XX_CLK_NCO_CTRL			0x68
119#define   GSW1XX_SGMII_HSP_MASK			GENMASK(3, 2)
120#define   GSW1XX_SGMII_SEL			BIT(1)
121#define   GSW1XX_SGMII_1G			0x0
122#define   GSW1XX_SGMII_2G5			0xc
123#define   GSW1XX_SGMII_1G_NCO1			0x0
124#define   GSW1XX_SGMII_2G5_NCO2			0x2
125
126#endif /* __MXL_GSW1XX_H */