lantiq_gswip.h

  1// SPDX-License-Identifier: GPL-2.0
  2#ifndef __LANTIQ_GSWIP_H
  3#define __LANTIQ_GSWIP_H
  4
  5#include <linux/bitfield.h>
  6#include <linux/clk.h>
  7#include <linux/mutex.h>
  8#include <linux/phylink.h>
  9#include <linux/platform_device.h>
 10#include <linux/regmap.h>
 11#include <linux/reset.h>
 12#include <linux/swab.h>
 13#include <net/dsa.h>
 14
 15/* GSWIP MDIO Registers */
 16#define GSWIP_MDIO_GLOB			0x00
 17#define  GSWIP_MDIO_GLOB_ENABLE		BIT(15)
 18#define GSWIP_MDIO_CTRL			0x08
 19#define  GSWIP_MDIO_CTRL_BUSY		BIT(12)
 20#define  GSWIP_MDIO_CTRL_RD		BIT(11)
 21#define  GSWIP_MDIO_CTRL_WR		BIT(10)
 22#define  GSWIP_MDIO_CTRL_PHYAD_MASK	0x1f
 23#define  GSWIP_MDIO_CTRL_PHYAD_SHIFT	5
 24#define  GSWIP_MDIO_CTRL_REGAD_MASK	0x1f
 25#define GSWIP_MDIO_READ			0x09
 26#define GSWIP_MDIO_WRITE		0x0A
 27#define GSWIP_MDIO_MDC_CFG0		0x0B
 28#define GSWIP_MDIO_MDC_CFG1		0x0C
 29#define GSWIP_MDIO_PHYp(p)		(0x15 - (p))
 30#define  GSWIP_MDIO_PHY_LINK_MASK	0x6000
 31#define  GSWIP_MDIO_PHY_LINK_AUTO	0x0000
 32#define  GSWIP_MDIO_PHY_LINK_DOWN	0x4000
 33#define  GSWIP_MDIO_PHY_LINK_UP		0x2000
 34#define  GSWIP_MDIO_PHY_SPEED_MASK	0x1800
 35#define  GSWIP_MDIO_PHY_SPEED_AUTO	0x1800
 36#define  GSWIP_MDIO_PHY_SPEED_M10	0x0000
 37#define  GSWIP_MDIO_PHY_SPEED_M100	0x0800
 38#define  GSWIP_MDIO_PHY_SPEED_G1	0x1000
 39#define  GSWIP_MDIO_PHY_FDUP_MASK	0x0600
 40#define  GSWIP_MDIO_PHY_FDUP_AUTO	0x0000
 41#define  GSWIP_MDIO_PHY_FDUP_EN		0x0200
 42#define  GSWIP_MDIO_PHY_FDUP_DIS	0x0600
 43#define  GSWIP_MDIO_PHY_FCONTX_MASK	0x0180
 44#define  GSWIP_MDIO_PHY_FCONTX_AUTO	0x0000
 45#define  GSWIP_MDIO_PHY_FCONTX_EN	0x0100
 46#define  GSWIP_MDIO_PHY_FCONTX_DIS	0x0180
 47#define  GSWIP_MDIO_PHY_FCONRX_MASK	0x0060
 48#define  GSWIP_MDIO_PHY_FCONRX_AUTO	0x0000
 49#define  GSWIP_MDIO_PHY_FCONRX_EN	0x0020
 50#define  GSWIP_MDIO_PHY_FCONRX_DIS	0x0060
 51#define  GSWIP_MDIO_PHY_ADDR_MASK	0x001f
 52#define  GSWIP_MDIO_PHY_MASK		(GSWIP_MDIO_PHY_ADDR_MASK | \
 53					 GSWIP_MDIO_PHY_FCONRX_MASK | \
 54					 GSWIP_MDIO_PHY_FCONTX_MASK | \
 55					 GSWIP_MDIO_PHY_LINK_MASK | \
 56					 GSWIP_MDIO_PHY_SPEED_MASK | \
 57					 GSWIP_MDIO_PHY_FDUP_MASK)
 58
 59/* GSWIP MII Registers */
 60#define GSWIP_MII_CFGp(p)		(0x2 * (p))
 61#define  GSWIP_MII_CFG_RESET		BIT(15)
 62#define  GSWIP_MII_CFG_EN		BIT(14)
 63#define  GSWIP_MII_CFG_ISOLATE		BIT(13)
 64#define  GSWIP_MII_CFG_LDCLKDIS		BIT(12)
 65#define  GSWIP_MII_CFG_RGMII_IBS	BIT(8)
 66#define  GSWIP_MII_CFG_RMII_CLK		BIT(7)
 67#define  GSWIP_MII_CFG_MODE_MIIP	0x0
 68#define  GSWIP_MII_CFG_MODE_MIIM	0x1
 69#define  GSWIP_MII_CFG_MODE_RMIIP	0x2
 70#define  GSWIP_MII_CFG_MODE_RMIIM	0x3
 71#define  GSWIP_MII_CFG_MODE_RGMII	0x4
 72#define  GSWIP_MII_CFG_MODE_GMII	0x9
 73#define  GSWIP_MII_CFG_MODE_MASK	0xf
 74#define  GSWIP_MII_CFG_RATE_M2P5	0x00
 75#define  GSWIP_MII_CFG_RATE_M25	0x10
 76#define  GSWIP_MII_CFG_RATE_M125	0x20
 77#define  GSWIP_MII_CFG_RATE_M50	0x30
 78#define  GSWIP_MII_CFG_RATE_AUTO	0x40
 79#define  GSWIP_MII_CFG_RATE_MASK	0x70
 80#define GSWIP_MII_PCDU0			0x01
 81#define GSWIP_MII_PCDU1			0x03
 82#define GSWIP_MII_PCDU5			0x05
 83#define  GSWIP_MII_PCDU_TXDLY_MASK	GENMASK(2, 0)
 84#define  GSWIP_MII_PCDU_RXDLY_MASK	GENMASK(9, 7)
 85#define  GSWIP_MII_PCDU_TXDLY(x)	u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_TXDLY_MASK)
 86#define  GSWIP_MII_PCDU_RXDLY(x)	u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_RXDLY_MASK)
 87#define GSWIP_MII_PCDU_RXDLY_DEFAULT	2000 /* picoseconds */
 88#define GSWIP_MII_PCDU_TXDLY_DEFAULT	2000 /* picoseconds */
 89
 90/* GSWIP Core Registers */
 91#define GSWIP_SWRES			0x000
 92#define  GSWIP_SWRES_R1			BIT(1)	/* GSWIP Software reset */
 93#define  GSWIP_SWRES_R0			BIT(0)	/* GSWIP Hardware reset */
 94#define GSWIP_VERSION			0x013
 95#define  GSWIP_VERSION_REV_MASK		GENMASK(7, 0)
 96#define  GSWIP_VERSION_MOD_MASK		GENMASK(15, 8)
 97#define  GSWIP_VERSION_REV(v)		FIELD_GET(GSWIP_VERSION_REV_MASK, v)
 98#define  GSWIP_VERSION_MOD(v)		FIELD_GET(GSWIP_VERSION_MOD_MASK, v)
 99#define   GSWIP_VERSION_2_0		0x100
100#define   GSWIP_VERSION_2_1		0x021
101#define   GSWIP_VERSION_2_2		0x122
102#define   GSWIP_VERSION_2_2_ETC		0x022
103/* The hardware has the 'major/minor' version bytes in the wrong order
104 * preventing numerical comparisons. Swap the bytes of the 16-bit value
105 * to end up with REV being the most significant byte and MOD being the
106 * least significant byte, which then allows comparing it with the
107 * value stored in struct gswip_priv.
108 */
109#define GSWIP_VERSION_GE(priv, ver)	((priv)->version >= swab16(ver))
110
111#define GSWIP_BM_RAM_VAL(x)		(0x043 - (x))
112#define GSWIP_BM_RAM_ADDR		0x044
113#define GSWIP_BM_RAM_CTRL		0x045
114#define  GSWIP_BM_RAM_CTRL_BAS		BIT(15)
115#define  GSWIP_BM_RAM_CTRL_OPMOD	BIT(5)
116#define  GSWIP_BM_RAM_CTRL_ADDR_MASK	GENMASK(4, 0)
117#define GSWIP_BM_QUEUE_GCTRL		0x04A
118#define  GSWIP_BM_QUEUE_GCTRL_GL_MOD	BIT(10)
119/* buffer management Port Configuration Register */
120#define GSWIP_BM_PCFGp(p)		(0x080 + ((p) * 2))
121#define  GSWIP_BM_PCFG_CNTEN		BIT(0)	/* RMON Counter Enable */
122#define  GSWIP_BM_PCFG_IGCNT		BIT(1)	/* Ingres Special Tag RMON count */
123/* buffer management Port Control Register */
124#define GSWIP_BM_RMON_CTRLp(p)		(0x81 + ((p) * 2))
125#define  GSWIP_BM_CTRL_RMON_RAM1_RES	BIT(0)	/* Software Reset for RMON RAM 1 */
126#define  GSWIP_BM_CTRL_RMON_RAM2_RES	BIT(1)	/* Software Reset for RMON RAM 2 */
127
128/* PCE */
129#define GSWIP_PCE_TBL_KEY(x)		(0x447 - (x))
130#define GSWIP_PCE_TBL_MASK		0x448
131#define GSWIP_PCE_TBL_VAL(x)		(0x44D - (x))
132#define GSWIP_PCE_TBL_ADDR		0x44E
133#define GSWIP_PCE_TBL_CTRL		0x44F
134#define  GSWIP_PCE_TBL_CTRL_BAS		BIT(15)
135#define  GSWIP_PCE_TBL_CTRL_TYPE	BIT(13)
136#define  GSWIP_PCE_TBL_CTRL_VLD		BIT(12)
137#define  GSWIP_PCE_TBL_CTRL_KEYFORM	BIT(11)
138#define  GSWIP_PCE_TBL_CTRL_GMAP_MASK	GENMASK(10, 7)
139#define  GSWIP_PCE_TBL_CTRL_OPMOD_MASK	GENMASK(6, 5)
140#define  GSWIP_PCE_TBL_CTRL_OPMOD_ADRD	0x00
141#define  GSWIP_PCE_TBL_CTRL_OPMOD_ADWR	0x20
142#define  GSWIP_PCE_TBL_CTRL_OPMOD_KSRD	0x40
143#define  GSWIP_PCE_TBL_CTRL_OPMOD_KSWR	0x60
144#define  GSWIP_PCE_TBL_CTRL_ADDR_MASK	GENMASK(4, 0)
145#define GSWIP_PCE_PMAP1			0x453	/* Monitoring port map */
146#define GSWIP_PCE_PMAP2			0x454	/* Default Multicast port map */
147#define GSWIP_PCE_PMAP3			0x455	/* Default Unknown Unicast port map */
148#define GSWIP_PCE_GCTRL_0		0x456
149#define  GSWIP_PCE_GCTRL_0_MTFL		BIT(0)  /* MAC Table Flushing */
150#define  GSWIP_PCE_GCTRL_0_MC_VALID	BIT(3)
151#define  GSWIP_PCE_GCTRL_0_VLAN		BIT(14) /* VLAN aware Switching */
152#define GSWIP_PCE_GCTRL_1		0x457
153#define  GSWIP_PCE_GCTRL_1_MAC_GLOCK	BIT(2)	/* MAC Address table lock */
154#define  GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD	BIT(3) /* Mac address table lock forwarding mode */
155#define GSWIP_PCE_PCTRL_0p(p)		(0x480 + ((p) * 0xA))
156#define  GSWIP_PCE_PCTRL_0_TVM		BIT(5)	/* Transparent VLAN mode */
157#define  GSWIP_PCE_PCTRL_0_VREP		BIT(6)	/* VLAN Replace Mode */
158#define  GSWIP_PCE_PCTRL_0_INGRESS	BIT(11)	/* Accept special tag in ingress */
159#define  GSWIP_PCE_PCTRL_0_PSTATE_LISTEN	0x0
160#define  GSWIP_PCE_PCTRL_0_PSTATE_RX		0x1
161#define  GSWIP_PCE_PCTRL_0_PSTATE_TX		0x2
162#define  GSWIP_PCE_PCTRL_0_PSTATE_LEARNING	0x3
163#define  GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING	0x7
164#define  GSWIP_PCE_PCTRL_0_PSTATE_MASK	GENMASK(2, 0)
165/* Ethernet Switch PCE Port Control Register 3 */
166#define GSWIP_PCE_PCTRL_3p(p)		(0x483 + ((p) * 0xA))
167#define  GSWIP_PCE_PCTRL_3_LNDIS	BIT(15)  /* Learning Disable */
168#define GSWIP_PCE_VCTRL(p)		(0x485 + ((p) * 0xA))
169#define  GSWIP_PCE_VCTRL_UVR		BIT(0)	/* Unknown VLAN Rule */
170#define  GSWIP_PCE_VCTRL_VINR		GENMASK(2, 1) /* VLAN Ingress Tag Rule */
171#define  GSWIP_PCE_VCTRL_VINR_ALL	0 /* Admit tagged and untagged packets */
172#define  GSWIP_PCE_VCTRL_VINR_TAGGED	1 /* Admit only tagged packets */
173#define  GSWIP_PCE_VCTRL_VINR_UNTAGGED	2 /* Admit only untagged packets */
174#define  GSWIP_PCE_VCTRL_VIMR		BIT(3)	/* VLAN Ingress Member violation rule */
175#define  GSWIP_PCE_VCTRL_VEMR		BIT(4)	/* VLAN Egress Member violation rule */
176#define  GSWIP_PCE_VCTRL_VSR		BIT(5)	/* VLAN Security */
177#define  GSWIP_PCE_VCTRL_VID0		BIT(6)	/* Priority Tagged Rule */
178#define GSWIP_PCE_DEFPVID(p)		(0x486 + ((p) * 0xA))
179
180#define GSWIP_MAC_FLEN			0x8C5
181#define GSWIP_MAC_CTRL_0p(p)		(0x903 + ((p) * 0xC))
182#define  GSWIP_MAC_CTRL_0_PADEN		BIT(8)
183#define  GSWIP_MAC_CTRL_0_FCS_EN	BIT(7)
184#define  GSWIP_MAC_CTRL_0_FCON_MASK	0x0070
185#define  GSWIP_MAC_CTRL_0_FCON_AUTO	0x0000
186#define  GSWIP_MAC_CTRL_0_FCON_RX	0x0010
187#define  GSWIP_MAC_CTRL_0_FCON_TX	0x0020
188#define  GSWIP_MAC_CTRL_0_FCON_RXTX	0x0030
189#define  GSWIP_MAC_CTRL_0_FCON_NONE	0x0040
190#define  GSWIP_MAC_CTRL_0_FDUP_MASK	0x000C
191#define  GSWIP_MAC_CTRL_0_FDUP_AUTO	0x0000
192#define  GSWIP_MAC_CTRL_0_FDUP_EN	0x0004
193#define  GSWIP_MAC_CTRL_0_FDUP_DIS	0x000C
194#define  GSWIP_MAC_CTRL_0_GMII_MASK	0x0003
195#define  GSWIP_MAC_CTRL_0_GMII_AUTO	0x0000
196#define  GSWIP_MAC_CTRL_0_GMII_MII	0x0001
197#define  GSWIP_MAC_CTRL_0_GMII_RGMII	0x0002
198#define GSWIP_MAC_CTRL_2p(p)		(0x905 + ((p) * 0xC))
199#define GSWIP_MAC_CTRL_2_LCHKL		BIT(2) /* Frame Length Check Long Enable */
200#define GSWIP_MAC_CTRL_2_MLEN		BIT(3) /* Maximum Untagged Frame Lnegth */
201#define GSWIP_MAC_CTRL_4p(p)		(0x907 + ((p) * 0xC))
202#define  GSWIP_MAC_CTRL_4_LPIEN		BIT(7) /* LPI Mode Enable */
203#define  GSWIP_MAC_CTRL_4_GWAIT_MASK	GENMASK(14, 8) /* LPI Wait Time 1G */
204#define  GSWIP_MAC_CTRL_4_GWAIT(t)	u16_encode_bits((t), GSWIP_MAC_CTRL_4_GWAIT_MASK)
205#define  GSWIP_MAC_CTRL_4_WAIT_MASK	GENMASK(6, 0) /* LPI Wait Time 100M */
206#define  GSWIP_MAC_CTRL_4_WAIT(t)	u16_encode_bits((t), GSWIP_MAC_CTRL_4_WAIT_MASK)
207
208/* Ethernet Switch Fetch DMA Port Control Register */
209#define GSWIP_FDMA_PCTRLp(p)		(0xA80 + ((p) * 0x6))
210#define  GSWIP_FDMA_PCTRL_EN		BIT(0)	/* FDMA Port Enable */
211#define  GSWIP_FDMA_PCTRL_STEN		BIT(1)	/* Special Tag Insertion Enable */
212#define  GSWIP_FDMA_PCTRL_VLANMOD_MASK	GENMASK(4, 3)	/* VLAN Modification Control */
213#define  GSWIP_FDMA_PCTRL_VLANMOD_SHIFT	3	/* VLAN Modification Control */
214#define  GSWIP_FDMA_PCTRL_VLANMOD_DIS	(0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
215#define  GSWIP_FDMA_PCTRL_VLANMOD_PRIO	(0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
216#define  GSWIP_FDMA_PCTRL_VLANMOD_ID	(0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
217#define  GSWIP_FDMA_PCTRL_VLANMOD_BOTH	(0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
218
219/* Ethernet Switch Store DMA Port Control Register */
220#define GSWIP_SDMA_PCTRLp(p)		(0xBC0 + ((p) * 0x6))
221#define  GSWIP_SDMA_PCTRL_EN		BIT(0)	/* SDMA Port Enable */
222#define  GSWIP_SDMA_PCTRL_FCEN		BIT(1)	/* Flow Control Enable */
223#define  GSWIP_SDMA_PCTRL_PAUFWD	BIT(3)	/* Pause Frame Forwarding */
224
225#define GSWIP_TABLE_ACTIVE_VLAN		0x01
226#define GSWIP_TABLE_VLAN_MAPPING	0x02
227#define GSWIP_TABLE_MAC_BRIDGE		0x0b
228#define  GSWIP_TABLE_MAC_BRIDGE_KEY3_FID	GENMASK(5, 0)	/* Filtering identifier */
229#define  GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT	GENMASK(7, 4)	/* Port on learned entries */
230#define  GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC	BIT(0)		/* Static, non-aging entry */
231#define  GSWIP_TABLE_MAC_BRIDGE_VAL1_VALID	BIT(1)		/* Valid bit */
232
233#define XRX200_GPHY_FW_ALIGN	(16 * 1024)
234
235/* Maximum packet size supported by the switch. In theory this should be 10240,
236 * but long packets currently cause lock-ups with an MTU of over 2526. Medium
237 * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP
238 * over 2526), hence an MTU value of 2400 seems safe. This issue only affects
239 * packet reception. This is probably caused by the PPA engine, which is on the
240 * RX part of the device. Packet transmission works properly up to 10240.
241 */
242#define GSWIP_MAX_PACKET_LENGTH	2400
243
244#define GSWIP_VLAN_UNAWARE_PVID	0
245
246struct gswip_pce_microcode {
247	u16 val_3;
248	u16 val_2;
249	u16 val_1;
250	u16 val_0;
251};
252
253struct gswip_hw_info {
254	int max_ports;
255	unsigned int allowed_cpu_ports;
256	unsigned int mii_ports;
257	int mii_port_reg_offset;
258	bool supports_2500m;
259	const struct gswip_pce_microcode (*pce_microcode)[];
260	size_t pce_microcode_size;
261	enum dsa_tag_protocol tag_protocol;
262	void (*phylink_get_caps)(struct dsa_switch *ds, int port,
263				 struct phylink_config *config);
264	struct phylink_pcs *(*mac_select_pcs)(struct phylink_config *config,
265					      phy_interface_t interface);
266};
267
268struct gswip_gphy_fw {
269	struct clk *clk_gate;
270	struct reset_control *reset;
271	u32 fw_addr_offset;
272	char *fw_name;
273};
274
275struct gswip_vlan {
276	struct net_device *bridge;
277	u16 vid;
278	u8 fid;
279};
280
281struct gswip_priv {
282	struct regmap *gswip;
283	struct regmap *mdio;
284	struct regmap *mii;
285	const struct gswip_hw_info *hw_info;
286	const struct xway_gphy_match_data *gphy_fw_name_cfg;
287	struct dsa_switch *ds;
288	struct device *dev;
289	struct regmap *rcu_regmap;
290	struct gswip_vlan vlans[64];
291	int num_gphy_fw;
292	struct gswip_gphy_fw *gphy_fw;
293	struct mutex pce_table_lock;
294	u16 version;
295};
296
297int gswip_probe_common(struct gswip_priv *priv, u32 version);
298
299#endif /* __LANTIQ_GSWIP_H */