ks8995.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * SPI driver for Micrel/Kendin KS8995M and KSZ8864RMN ethernet switches
  4 *
  5 * Copyright (C) 2008 Gabor Juhos <juhosg at openwrt.org>
  6 * Copyright (C) 2025 Linus Walleij <linus.walleij@linaro.org>
  7 *
  8 * This file was based on: drivers/spi/at25.c
  9 *     Copyright (C) 2006 David Brownell
 10 */
 11
 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 13
 14#include <linux/bits.h>
 15#include <linux/if_bridge.h>
 16#include <linux/if_vlan.h>
 17#include <linux/types.h>
 18#include <linux/kernel.h>
 19#include <linux/module.h>
 20#include <linux/delay.h>
 21#include <linux/device.h>
 22#include <linux/gpio/consumer.h>
 23#include <linux/of.h>
 24#include <linux/spi/spi.h>
 25#include <net/dsa.h>
 26
 27#define DRV_VERSION		"0.1.1"
 28#define DRV_DESC		"Micrel KS8995 Ethernet switch SPI driver"
 29
 30/* ------------------------------------------------------------------------ */
 31
 32#define KS8995_REG_ID0		0x00    /* Chip ID0 */
 33#define KS8995_REG_ID1		0x01    /* Chip ID1 */
 34
 35#define KS8995_REG_GC0		0x02    /* Global Control 0 */
 36
 37#define KS8995_GC0_P5_PHY	BIT(3)	/* Port 5 PHY enabled */
 38
 39#define KS8995_REG_GC1		0x03    /* Global Control 1 */
 40#define KS8995_REG_GC2		0x04    /* Global Control 2 */
 41
 42#define KS8995_GC2_HUGE		BIT(2)	/* Huge packet support */
 43#define KS8995_GC2_LEGAL	BIT(1)	/* Legal size override */
 44
 45#define KS8995_REG_GC3		0x05    /* Global Control 3 */
 46#define KS8995_REG_GC4		0x06    /* Global Control 4 */
 47
 48#define KS8995_GC4_10BT		BIT(4)	/* Force switch to 10Mbit */
 49#define KS8995_GC4_MII_FLOW	BIT(5)	/* MII full-duplex flow control enable */
 50#define KS8995_GC4_MII_HD	BIT(6)	/* MII half-duplex mode enable */
 51
 52#define KS8995_REG_GC5		0x07    /* Global Control 5 */
 53#define KS8995_REG_GC6		0x08    /* Global Control 6 */
 54#define KS8995_REG_GC7		0x09    /* Global Control 7 */
 55#define KS8995_REG_GC8		0x0a    /* Global Control 8 */
 56#define KS8995_REG_GC9		0x0b    /* Global Control 9 */
 57
 58#define KS8995_GC9_SPECIAL	BIT(0)	/* Special tagging mode (DSA) */
 59
 60/* In DSA the ports 1-4 are numbered 0-3 and the CPU port is port 4 */
 61#define KS8995_REG_PC(p, r)	(0x10 + (0x10 * (p)) + (r)) /* Port Control */
 62#define KS8995_REG_PS(p, r)	(0x1e + (0x10 * (p)) + (r)) /* Port Status */
 63
 64#define KS8995_REG_PC0		0x00    /* Port Control 0 */
 65#define KS8995_REG_PC1		0x01    /* Port Control 1 */
 66#define KS8995_REG_PC2		0x02    /* Port Control 2 */
 67#define KS8995_REG_PC3		0x03    /* Port Control 3 */
 68#define KS8995_REG_PC4		0x04    /* Port Control 4 */
 69#define KS8995_REG_PC5		0x05    /* Port Control 5 */
 70#define KS8995_REG_PC6		0x06    /* Port Control 6 */
 71#define KS8995_REG_PC7		0x07    /* Port Control 7 */
 72#define KS8995_REG_PC8		0x08    /* Port Control 8 */
 73#define KS8995_REG_PC9		0x09    /* Port Control 9 */
 74#define KS8995_REG_PC10		0x0a    /* Port Control 10 */
 75#define KS8995_REG_PC11		0x0b    /* Port Control 11 */
 76#define KS8995_REG_PC12		0x0c    /* Port Control 12 */
 77#define KS8995_REG_PC13		0x0d    /* Port Control 13 */
 78
 79#define KS8995_PC0_TAG_INS	BIT(2)	/* Enable tag insertion on port */
 80#define KS8995_PC0_TAG_REM	BIT(1)	/* Enable tag removal on port */
 81#define KS8995_PC0_PRIO_EN	BIT(0)	/* Enable priority handling */
 82
 83#define KS8995_PC2_TXEN		BIT(2)	/* Enable TX on port */
 84#define KS8995_PC2_RXEN		BIT(1)	/* Enable RX on port */
 85#define KS8995_PC2_LEARN_DIS	BIT(0)	/* Disable learning on port */
 86
 87#define KS8995_PC13_TXDIS	BIT(6)	/* Disable transmitter */
 88#define KS8995_PC13_PWDN	BIT(3)	/* Power down */
 89
 90#define KS8995_REG_TPC0		0x60    /* TOS Priority Control 0 */
 91#define KS8995_REG_TPC1		0x61    /* TOS Priority Control 1 */
 92#define KS8995_REG_TPC2		0x62    /* TOS Priority Control 2 */
 93#define KS8995_REG_TPC3		0x63    /* TOS Priority Control 3 */
 94#define KS8995_REG_TPC4		0x64    /* TOS Priority Control 4 */
 95#define KS8995_REG_TPC5		0x65    /* TOS Priority Control 5 */
 96#define KS8995_REG_TPC6		0x66    /* TOS Priority Control 6 */
 97#define KS8995_REG_TPC7		0x67    /* TOS Priority Control 7 */
 98
 99#define KS8995_REG_MAC0		0x68    /* MAC address 0 */
100#define KS8995_REG_MAC1		0x69    /* MAC address 1 */
101#define KS8995_REG_MAC2		0x6a    /* MAC address 2 */
102#define KS8995_REG_MAC3		0x6b    /* MAC address 3 */
103#define KS8995_REG_MAC4		0x6c    /* MAC address 4 */
104#define KS8995_REG_MAC5		0x6d    /* MAC address 5 */
105
106#define KS8995_REG_IAC0		0x6e    /* Indirect Access Control 0 */
107#define KS8995_REG_IAC1		0x6f    /* Indirect Access Control 0 */
108#define KS8995_REG_IAD7		0x70    /* Indirect Access Data 7 */
109#define KS8995_REG_IAD6		0x71    /* Indirect Access Data 6 */
110#define KS8995_REG_IAD5		0x72    /* Indirect Access Data 5 */
111#define KS8995_REG_IAD4		0x73    /* Indirect Access Data 4 */
112#define KS8995_REG_IAD3		0x74    /* Indirect Access Data 3 */
113#define KS8995_REG_IAD2		0x75    /* Indirect Access Data 2 */
114#define KS8995_REG_IAD1		0x76    /* Indirect Access Data 1 */
115#define KS8995_REG_IAD0		0x77    /* Indirect Access Data 0 */
116
117#define KSZ8864_REG_ID1		0xfe	/* Chip ID in bit 7 */
118
119#define KS8995_REGS_SIZE	0x80
120#define KSZ8864_REGS_SIZE	0x100
121#define KSZ8795_REGS_SIZE	0x100
122
123#define ID1_CHIPID_M		0xf
124#define ID1_CHIPID_S		4
125#define ID1_REVISION_M		0x7
126#define ID1_REVISION_S		1
127#define ID1_START_SW		1	/* start the switch */
128
129#define FAMILY_KS8995		0x95
130#define FAMILY_KSZ8795		0x87
131#define CHIPID_M		0
132#define KS8995_CHIP_ID		0x00
133#define KSZ8864_CHIP_ID		0x01
134#define KSZ8795_CHIP_ID		0x09
135
136#define KS8995_CMD_WRITE	0x02U
137#define KS8995_CMD_READ		0x03U
138
139#define KS8995_CPU_PORT		4
140#define KS8995_NUM_PORTS	5 /* 5 ports including the CPU port */
141#define KS8995_RESET_DELAY	10 /* usec */
142
143enum ks8995_chip_variant {
144	ks8995,
145	ksz8864,
146	ksz8795,
147	max_variant
148};
149
150struct ks8995_chip_params {
151	char *name;
152	int family_id;
153	int chip_id;
154	int regs_size;
155	int addr_width;
156	int addr_shift;
157};
158
159static const struct ks8995_chip_params ks8995_chip[] = {
160	[ks8995] = {
161		.name = "KS8995MA",
162		.family_id = FAMILY_KS8995,
163		.chip_id = KS8995_CHIP_ID,
164		.regs_size = KS8995_REGS_SIZE,
165		.addr_width = 8,
166		.addr_shift = 0,
167	},
168	[ksz8864] = {
169		.name = "KSZ8864RMN",
170		.family_id = FAMILY_KS8995,
171		.chip_id = KSZ8864_CHIP_ID,
172		.regs_size = KSZ8864_REGS_SIZE,
173		.addr_width = 8,
174		.addr_shift = 0,
175	},
176	[ksz8795] = {
177		.name = "KSZ8795CLX",
178		.family_id = FAMILY_KSZ8795,
179		.chip_id = KSZ8795_CHIP_ID,
180		.regs_size = KSZ8795_REGS_SIZE,
181		.addr_width = 12,
182		.addr_shift = 1,
183	},
184};
185
186struct ks8995_switch {
187	struct spi_device	*spi;
188	struct device		*dev;
189	struct dsa_switch	*ds;
190	struct mutex		lock;
191	struct gpio_desc	*reset_gpio;
192	struct bin_attribute	regs_attr;
193	const struct ks8995_chip_params	*chip;
194	int			revision_id;
195	unsigned int max_mtu[KS8995_NUM_PORTS];
196};
197
198static const struct spi_device_id ks8995_id[] = {
199	{"ks8995", ks8995},
200	{"ksz8864", ksz8864},
201	{"ksz8795", ksz8795},
202	{ }
203};
204MODULE_DEVICE_TABLE(spi, ks8995_id);
205
206static const struct of_device_id ks8995_spi_of_match[] = {
207	{ .compatible = "micrel,ks8995" },
208	{ .compatible = "micrel,ksz8864" },
209	{ .compatible = "micrel,ksz8795" },
210	{ },
211};
212MODULE_DEVICE_TABLE(of, ks8995_spi_of_match);
213
214static inline u8 get_chip_id(u8 val)
215{
216	return (val >> ID1_CHIPID_S) & ID1_CHIPID_M;
217}
218
219static inline u8 get_chip_rev(u8 val)
220{
221	return (val >> ID1_REVISION_S) & ID1_REVISION_M;
222}
223
224/* create_spi_cmd - create a chip specific SPI command header
225 * @ks: pointer to switch instance
226 * @cmd: SPI command for switch
227 * @address: register address for command
228 *
229 * Different chip families use different bit pattern to address the switches
230 * registers:
231 *
232 * KS8995: 8bit command + 8bit address
233 * KSZ8795: 3bit command + 12bit address + 1bit TR (?)
234 */
235static inline __be16 create_spi_cmd(struct ks8995_switch *ks, int cmd,
236				    unsigned address)
237{
238	u16 result = cmd;
239
240	/* make room for address (incl. address shift) */
241	result <<= ks->chip->addr_width + ks->chip->addr_shift;
242	/* add address */
243	result |= address << ks->chip->addr_shift;
244	/* SPI protocol needs big endian */
245	return cpu_to_be16(result);
246}
247/* ------------------------------------------------------------------------ */
248static int ks8995_read(struct ks8995_switch *ks, char *buf,
249		 unsigned offset, size_t count)
250{
251	__be16 cmd;
252	struct spi_transfer t[2];
253	struct spi_message m;
254	int err;
255
256	cmd = create_spi_cmd(ks, KS8995_CMD_READ, offset);
257	spi_message_init(&m);
258
259	memset(&t, 0, sizeof(t));
260
261	t[0].tx_buf = &cmd;
262	t[0].len = sizeof(cmd);
263	spi_message_add_tail(&t[0], &m);
264
265	t[1].rx_buf = buf;
266	t[1].len = count;
267	spi_message_add_tail(&t[1], &m);
268
269	mutex_lock(&ks->lock);
270	err = spi_sync(ks->spi, &m);
271	mutex_unlock(&ks->lock);
272
273	return err ? err : count;
274}
275
276static int ks8995_write(struct ks8995_switch *ks, char *buf,
277		 unsigned offset, size_t count)
278{
279	__be16 cmd;
280	struct spi_transfer t[2];
281	struct spi_message m;
282	int err;
283
284	cmd = create_spi_cmd(ks, KS8995_CMD_WRITE, offset);
285	spi_message_init(&m);
286
287	memset(&t, 0, sizeof(t));
288
289	t[0].tx_buf = &cmd;
290	t[0].len = sizeof(cmd);
291	spi_message_add_tail(&t[0], &m);
292
293	t[1].tx_buf = buf;
294	t[1].len = count;
295	spi_message_add_tail(&t[1], &m);
296
297	mutex_lock(&ks->lock);
298	err = spi_sync(ks->spi, &m);
299	mutex_unlock(&ks->lock);
300
301	return err ? err : count;
302}
303
304static inline int ks8995_read_reg(struct ks8995_switch *ks, u8 addr, u8 *buf)
305{
306	return ks8995_read(ks, buf, addr, 1) != 1;
307}
308
309static inline int ks8995_write_reg(struct ks8995_switch *ks, u8 addr, u8 val)
310{
311	char buf = val;
312
313	return ks8995_write(ks, &buf, addr, 1) != 1;
314}
315
316/* ------------------------------------------------------------------------ */
317
318static int ks8995_stop(struct ks8995_switch *ks)
319{
320	return ks8995_write_reg(ks, KS8995_REG_ID1, 0);
321}
322
323static int ks8995_start(struct ks8995_switch *ks)
324{
325	return ks8995_write_reg(ks, KS8995_REG_ID1, 1);
326}
327
328static int ks8995_reset(struct ks8995_switch *ks)
329{
330	int err;
331
332	err = ks8995_stop(ks);
333	if (err)
334		return err;
335
336	udelay(KS8995_RESET_DELAY);
337
338	return ks8995_start(ks);
339}
340
341/* ks8995_get_revision - get chip revision
342 * @ks: pointer to switch instance
343 *
344 * Verify chip family and id and get chip revision.
345 */
346static int ks8995_get_revision(struct ks8995_switch *ks)
347{
348	int err;
349	u8 id0, id1, ksz8864_id;
350
351	/* read family id */
352	err = ks8995_read_reg(ks, KS8995_REG_ID0, &id0);
353	if (err) {
354		err = -EIO;
355		goto err_out;
356	}
357
358	/* verify family id */
359	if (id0 != ks->chip->family_id) {
360		dev_err(&ks->spi->dev, "chip family id mismatch: expected 0x%02x but 0x%02x read\n",
361			ks->chip->family_id, id0);
362		err = -ENODEV;
363		goto err_out;
364	}
365
366	switch (ks->chip->family_id) {
367	case FAMILY_KS8995:
368		/* try reading chip id at CHIP ID1 */
369		err = ks8995_read_reg(ks, KS8995_REG_ID1, &id1);
370		if (err) {
371			err = -EIO;
372			goto err_out;
373		}
374
375		/* verify chip id */
376		if ((get_chip_id(id1) == CHIPID_M) &&
377		    (get_chip_id(id1) == ks->chip->chip_id)) {
378			/* KS8995MA */
379			ks->revision_id = get_chip_rev(id1);
380		} else if (get_chip_id(id1) != CHIPID_M) {
381			/* KSZ8864RMN */
382			err = ks8995_read_reg(ks, KS8995_REG_ID1, &ksz8864_id);
383			if (err) {
384				err = -EIO;
385				goto err_out;
386			}
387
388			if ((ksz8864_id & 0x80) &&
389			    (ks->chip->chip_id == KSZ8864_CHIP_ID)) {
390				ks->revision_id = get_chip_rev(id1);
391			}
392
393		} else {
394			dev_err(&ks->spi->dev, "unsupported chip id for KS8995 family: 0x%02x\n",
395				id1);
396			err = -ENODEV;
397		}
398		break;
399	case FAMILY_KSZ8795:
400		/* try reading chip id at CHIP ID1 */
401		err = ks8995_read_reg(ks, KS8995_REG_ID1, &id1);
402		if (err) {
403			err = -EIO;
404			goto err_out;
405		}
406
407		if (get_chip_id(id1) == ks->chip->chip_id) {
408			ks->revision_id = get_chip_rev(id1);
409		} else {
410			dev_err(&ks->spi->dev, "unsupported chip id for KSZ8795 family: 0x%02x\n",
411				id1);
412			err = -ENODEV;
413		}
414		break;
415	default:
416		dev_err(&ks->spi->dev, "unsupported family id: 0x%02x\n", id0);
417		err = -ENODEV;
418		break;
419	}
420err_out:
421	return err;
422}
423
424static int ks8995_check_config(struct ks8995_switch *ks)
425{
426	int ret;
427	u8 val;
428
429	ret = ks8995_read_reg(ks, KS8995_REG_GC0, &val);
430	if (ret) {
431		dev_err(ks->dev, "failed to read KS8995_REG_GC0\n");
432		return ret;
433	}
434
435	dev_dbg(ks->dev, "port 5 PHY %senabled\n",
436		(val & KS8995_GC0_P5_PHY) ? "" : "not ");
437
438	val |= KS8995_GC0_P5_PHY;
439	ret = ks8995_write_reg(ks, KS8995_REG_GC0, val);
440	if (ret)
441		dev_err(ks->dev, "failed to set KS8995_REG_GC0\n");
442
443	dev_dbg(ks->dev, "set KS8995_REG_GC0 to 0x%02x\n", val);
444
445	return 0;
446}
447
448static void
449ks8995_mac_config(struct phylink_config *config, unsigned int mode,
450		  const struct phylink_link_state *state)
451{
452}
453
454static void
455ks8995_mac_link_up(struct phylink_config *config, struct phy_device *phydev,
456		   unsigned int mode, phy_interface_t interface,
457		   int speed, int duplex, bool tx_pause, bool rx_pause)
458{
459	struct dsa_port *dp = dsa_phylink_to_port(config);
460	struct ks8995_switch *ks = dp->ds->priv;
461	int port = dp->index;
462	int ret;
463	u8 val;
464
465	/* Allow forcing the mode on the fixed CPU port, no autonegotiation.
466	 * We assume autonegotiation works on the PHY-facing ports.
467	 */
468	if (port != KS8995_CPU_PORT)
469		return;
470
471	dev_dbg(ks->dev, "MAC link up on CPU port (%d)\n", port);
472
473	ret = ks8995_read_reg(ks, KS8995_REG_GC4, &val);
474	if (ret) {
475		dev_err(ks->dev, "failed to read KS8995_REG_GC4\n");
476		return;
477	}
478
479	/* Conjure port config */
480	switch (speed) {
481	case SPEED_10:
482		dev_dbg(ks->dev, "set switch MII to 100Mbit mode\n");
483		val |= KS8995_GC4_10BT;
484		break;
485	case SPEED_100:
486	default:
487		dev_dbg(ks->dev, "set switch MII to 100Mbit mode\n");
488		val &= ~KS8995_GC4_10BT;
489		break;
490	}
491
492	if (duplex == DUPLEX_HALF) {
493		dev_dbg(ks->dev, "set switch MII to half duplex\n");
494		val |= KS8995_GC4_MII_HD;
495	} else {
496		dev_dbg(ks->dev, "set switch MII to full duplex\n");
497		val &= ~KS8995_GC4_MII_HD;
498	}
499
500	dev_dbg(ks->dev, "set KS8995_REG_GC4 to %02x\n", val);
501
502	/* Enable the CPU port */
503	ret = ks8995_write_reg(ks, KS8995_REG_GC4, val);
504	if (ret)
505		dev_err(ks->dev, "failed to set KS8995_REG_GC4\n");
506}
507
508static void
509ks8995_mac_link_down(struct phylink_config *config, unsigned int mode,
510		     phy_interface_t interface)
511{
512	struct dsa_port *dp = dsa_phylink_to_port(config);
513	struct ks8995_switch *ks = dp->ds->priv;
514	int port = dp->index;
515
516	if (port != KS8995_CPU_PORT)
517		return;
518
519	dev_dbg(ks->dev, "MAC link down on CPU port (%d)\n", port);
520
521	/* Disable the CPU port */
522}
523
524static const struct phylink_mac_ops ks8995_phylink_mac_ops = {
525	.mac_config = ks8995_mac_config,
526	.mac_link_up = ks8995_mac_link_up,
527	.mac_link_down = ks8995_mac_link_down,
528};
529
530static enum
531dsa_tag_protocol ks8995_get_tag_protocol(struct dsa_switch *ds,
532					 int port,
533					 enum dsa_tag_protocol mp)
534{
535	/* This switch actually uses the 6 byte KS8995 protocol */
536	return DSA_TAG_PROTO_NONE;
537}
538
539static int ks8995_setup(struct dsa_switch *ds)
540{
541	return 0;
542}
543
544static int ks8995_port_enable(struct dsa_switch *ds, int port,
545			      struct phy_device *phy)
546{
547	struct ks8995_switch *ks = ds->priv;
548
549	dev_dbg(ks->dev, "enable port %d\n", port);
550
551	return 0;
552}
553
554static void ks8995_port_disable(struct dsa_switch *ds, int port)
555{
556	struct ks8995_switch *ks = ds->priv;
557
558	dev_dbg(ks->dev, "disable port %d\n", port);
559}
560
561static int ks8995_port_pre_bridge_flags(struct dsa_switch *ds, int port,
562					struct switchdev_brport_flags flags,
563					struct netlink_ext_ack *extack)
564{
565	/* We support enabling/disabling learning */
566	if (flags.mask & ~(BR_LEARNING))
567		return -EINVAL;
568
569	return 0;
570}
571
572static int ks8995_port_bridge_flags(struct dsa_switch *ds, int port,
573				    struct switchdev_brport_flags flags,
574				    struct netlink_ext_ack *extack)
575{
576	struct ks8995_switch *ks = ds->priv;
577	int ret;
578	u8 val;
579
580	if (flags.mask & BR_LEARNING) {
581		ret = ks8995_read_reg(ks, KS8995_REG_PC(port, KS8995_REG_PC2), &val);
582		if (ret) {
583			dev_err(ks->dev, "failed to read KS8995_REG_PC2 on port %d\n", port);
584			return ret;
585		}
586
587		if (flags.val & BR_LEARNING)
588			val &= ~KS8995_PC2_LEARN_DIS;
589		else
590			val |= KS8995_PC2_LEARN_DIS;
591
592		ret = ks8995_write_reg(ks, KS8995_REG_PC(port, KS8995_REG_PC2), val);
593		if (ret) {
594			dev_err(ks->dev, "failed to write KS8995_REG_PC2 on port %d\n", port);
595			return ret;
596		}
597	}
598
599	return 0;
600}
601
602static void ks8995_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
603{
604	struct ks8995_switch *ks = ds->priv;
605	int ret;
606	u8 val;
607
608	ret = ks8995_read_reg(ks, KS8995_REG_PC(port, KS8995_REG_PC2), &val);
609	if (ret) {
610		dev_err(ks->dev, "failed to read KS8995_REG_PC2 on port %d\n", port);
611		return;
612	}
613
614	/* Set the bits for the different STP states in accordance with
615	 * the datasheet, pages 36-37 "Spanning tree support".
616	 */
617	switch (state) {
618	case BR_STATE_DISABLED:
619	case BR_STATE_BLOCKING:
620	case BR_STATE_LISTENING:
621		val &= ~KS8995_PC2_TXEN;
622		val &= ~KS8995_PC2_RXEN;
623		val |= KS8995_PC2_LEARN_DIS;
624		break;
625	case BR_STATE_LEARNING:
626		val &= ~KS8995_PC2_TXEN;
627		val &= ~KS8995_PC2_RXEN;
628		val &= ~KS8995_PC2_LEARN_DIS;
629		break;
630	case BR_STATE_FORWARDING:
631		val |= KS8995_PC2_TXEN;
632		val |= KS8995_PC2_RXEN;
633		val &= ~KS8995_PC2_LEARN_DIS;
634		break;
635	default:
636		dev_err(ks->dev, "unknown bridge state requested\n");
637		return;
638	}
639
640	ret = ks8995_write_reg(ks, KS8995_REG_PC(port, KS8995_REG_PC2), val);
641	if (ret) {
642		dev_err(ks->dev, "failed to write KS8995_REG_PC2 on port %d\n", port);
643		return;
644	}
645
646	dev_dbg(ks->dev, "set KS8995_REG_PC2 for port %d to %02x\n", port, val);
647}
648
649static void ks8995_phylink_get_caps(struct dsa_switch *dsa, int port,
650				    struct phylink_config *config)
651{
652	unsigned long *interfaces = config->supported_interfaces;
653
654	if (port == KS8995_CPU_PORT)
655		__set_bit(PHY_INTERFACE_MODE_MII, interfaces);
656
657	if (port <= 3) {
658		/* Internal PHYs */
659		__set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);
660		/* phylib default */
661		__set_bit(PHY_INTERFACE_MODE_MII, interfaces);
662	}
663
664	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
665}
666
667/* Huge packet support up to 1916 byte packages "inclusive"
668 * which means that tags are included. If the bit is not set
669 * it is 1536 bytes "inclusive". We present the length without
670 * tags or ethernet headers. The setting affects all ports.
671 */
672static int ks8995_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
673{
674	struct ks8995_switch *ks = ds->priv;
675	unsigned int max_mtu;
676	int ret;
677	u8 val;
678	int i;
679
680	ks->max_mtu[port] = new_mtu;
681
682	/* Roof out the MTU for the entire switch to the greatest
683	 * common denominator: the biggest set for any one port will
684	 * be the biggest MTU for the switch.
685	 */
686	max_mtu = ETH_DATA_LEN;
687	for (i = 0; i < KS8995_NUM_PORTS; i++) {
688		if (ks->max_mtu[i] > max_mtu)
689			max_mtu = ks->max_mtu[i];
690	}
691
692	/* Translate to layer 2 size.
693	 * Add ethernet and (possible) VLAN headers, and checksum to the size.
694	 * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
695	 */
696	max_mtu += VLAN_ETH_HLEN;
697	max_mtu += ETH_FCS_LEN;
698
699	ret = ks8995_read_reg(ks, KS8995_REG_GC2, &val);
700	if (ret) {
701		dev_err(ks->dev, "failed to read KS8995_REG_GC2\n");
702		return ret;
703	}
704
705	if (max_mtu <= 1522) {
706		val &= ~KS8995_GC2_HUGE;
707		val &= ~KS8995_GC2_LEGAL;
708	} else if (max_mtu > 1522 && max_mtu <= 1536) {
709		/* This accepts packets up to 1536 bytes */
710		val &= ~KS8995_GC2_HUGE;
711		val |= KS8995_GC2_LEGAL;
712	} else {
713		/* This accepts packets up to 1916 bytes */
714		val |= KS8995_GC2_HUGE;
715		val |= KS8995_GC2_LEGAL;
716	}
717
718	dev_dbg(ks->dev, "new max MTU %d bytes (inclusive)\n", max_mtu);
719
720	ret = ks8995_write_reg(ks, KS8995_REG_GC2, val);
721	if (ret)
722		dev_err(ks->dev, "failed to set KS8995_REG_GC2\n");
723
724	return ret;
725}
726
727static int ks8995_get_max_mtu(struct dsa_switch *ds, int port)
728{
729	return 1916 - ETH_HLEN - ETH_FCS_LEN;
730}
731
732static const struct dsa_switch_ops ks8995_ds_ops = {
733	.get_tag_protocol = ks8995_get_tag_protocol,
734	.setup = ks8995_setup,
735	.port_pre_bridge_flags = ks8995_port_pre_bridge_flags,
736	.port_bridge_flags = ks8995_port_bridge_flags,
737	.port_enable = ks8995_port_enable,
738	.port_disable = ks8995_port_disable,
739	.port_stp_state_set = ks8995_port_stp_state_set,
740	.port_change_mtu = ks8995_change_mtu,
741	.port_max_mtu = ks8995_get_max_mtu,
742	.phylink_get_caps = ks8995_phylink_get_caps,
743};
744
745/* ------------------------------------------------------------------------ */
746static int ks8995_probe(struct spi_device *spi)
747{
748	struct ks8995_switch *ks;
749	int err;
750	int variant = spi_get_device_id(spi)->driver_data;
751
752	if (variant >= max_variant) {
753		dev_err(&spi->dev, "bad chip variant %d\n", variant);
754		return -ENODEV;
755	}
756
757	ks = devm_kzalloc(&spi->dev, sizeof(*ks), GFP_KERNEL);
758	if (!ks)
759		return -ENOMEM;
760
761	mutex_init(&ks->lock);
762	ks->spi = spi;
763	ks->dev = &spi->dev;
764	ks->chip = &ks8995_chip[variant];
765
766	ks->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
767						 GPIOD_OUT_HIGH);
768	err = PTR_ERR_OR_ZERO(ks->reset_gpio);
769	if (err) {
770		dev_err(&spi->dev,
771			"failed to get reset gpio: %d\n", err);
772		return err;
773	}
774
775	err = gpiod_set_consumer_name(ks->reset_gpio, "switch-reset");
776	if (err)
777		return err;
778
779	if (ks->reset_gpio) {
780		/*
781		 * If a reset line was obtained, wait for 100us after
782		 * de-asserting RESET before accessing any registers, see
783		 * the KS8995MA datasheet, page 44.
784		 */
785		gpiod_set_value_cansleep(ks->reset_gpio, 0);
786		udelay(100);
787	}
788
789	spi_set_drvdata(spi, ks);
790
791	spi->mode = SPI_MODE_0;
792	spi->bits_per_word = 8;
793	err = spi_setup(spi);
794	if (err) {
795		dev_err(&spi->dev, "spi_setup failed, err=%d\n", err);
796		return err;
797	}
798
799	err = ks8995_get_revision(ks);
800	if (err)
801		return err;
802
803	err = ks8995_reset(ks);
804	if (err)
805		return err;
806
807	dev_info(&spi->dev, "%s device found, Chip ID:%x, Revision:%x\n",
808		 ks->chip->name, ks->chip->chip_id, ks->revision_id);
809
810	err = ks8995_check_config(ks);
811	if (err)
812		return err;
813
814	ks->ds = devm_kzalloc(&spi->dev, sizeof(*ks->ds), GFP_KERNEL);
815	if (!ks->ds)
816		return -ENOMEM;
817
818	ks->ds->dev = &spi->dev;
819	ks->ds->num_ports = KS8995_NUM_PORTS;
820	ks->ds->ops = &ks8995_ds_ops;
821	ks->ds->phylink_mac_ops = &ks8995_phylink_mac_ops;
822	ks->ds->priv = ks;
823
824	err = dsa_register_switch(ks->ds);
825	if (err)
826		return dev_err_probe(&spi->dev, err,
827				     "unable to register DSA switch\n");
828
829	return 0;
830}
831
832static void ks8995_remove(struct spi_device *spi)
833{
834	struct ks8995_switch *ks = spi_get_drvdata(spi);
835
836	dsa_unregister_switch(ks->ds);
837	/* assert reset */
838	gpiod_set_value_cansleep(ks->reset_gpio, 1);
839}
840
841/* ------------------------------------------------------------------------ */
842static struct spi_driver ks8995_driver = {
843	.driver = {
844		.name	    = "spi-ks8995",
845		.of_match_table = ks8995_spi_of_match,
846	},
847	.probe	  = ks8995_probe,
848	.remove	  = ks8995_remove,
849	.id_table = ks8995_id,
850};
851
852module_spi_driver(ks8995_driver);
853
854MODULE_DESCRIPTION(DRV_DESC);
855MODULE_VERSION(DRV_VERSION);
856MODULE_AUTHOR("Gabor Juhos <juhosg at openwrt.org>");
857MODULE_LICENSE("GPL v2");