b53_regs.h

  1/*
  2 * B53 register definitions
  3 *
  4 * Copyright (C) 2004 Broadcom Corporation
  5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
  6 *
  7 * Permission to use, copy, modify, and/or distribute this software for any
  8 * purpose with or without fee is hereby granted, provided that the above
  9 * copyright notice and this permission notice appear in all copies.
 10 *
 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 18 */
 19
 20#ifndef __B53_REGS_H
 21#define __B53_REGS_H
 22
 23/* Management Port (SMP) Page offsets */
 24#define B53_CTRL_PAGE			0x00 /* Control */
 25#define B53_STAT_PAGE			0x01 /* Status */
 26#define B53_MGMT_PAGE			0x02 /* Management Mode */
 27#define B53_MIB_AC_PAGE			0x03 /* MIB Autocast */
 28#define B53_ARLCTRL_PAGE		0x04 /* ARL Control */
 29#define B53_ARLIO_PAGE			0x05 /* ARL Access */
 30#define B53_FRAMEBUF_PAGE		0x06 /* Management frame access */
 31#define B53_MEM_ACCESS_PAGE		0x08 /* Memory access */
 32#define B53_IEEE_PAGE			0x0a /* IEEE 802.1X */
 33
 34/* PHY Registers */
 35#define B53_PORT_MII_PAGE(i)		(0x10 + (i)) /* Port i MII Registers */
 36#define B53_IM_PORT_PAGE		0x18 /* Inverse MII Port (to EMAC) */
 37#define B53_ALL_PORT_PAGE		0x19 /* All ports MII (broadcast) */
 38
 39/* MIB registers */
 40#define B53_MIB_PAGE(i)			(0x20 + (i))
 41
 42/* Quality of Service (QoS) Registers */
 43#define B53_QOS_PAGE			0x30
 44
 45/* Port VLAN Page */
 46#define B53_PVLAN_PAGE			0x31
 47
 48/* VLAN Registers */
 49#define B53_VLAN_PAGE			0x34
 50
 51/* Jumbo Frame Registers */
 52#define B53_JUMBO_PAGE			0x40
 53
 54/* EAP Registers */
 55#define B53_EAP_PAGE			0x42
 56
 57/* EEE Control Registers Page */
 58#define B53_EEE_PAGE			0x92
 59
 60/* CFP Configuration Registers Page */
 61#define B53_CFP_PAGE			0xa1
 62
 63/*************************************************************************
 64 * Control Page registers
 65 *************************************************************************/
 66
 67/* Port Control Register (8 bit) */
 68#define B53_PORT_CTRL(i)		(0x00 + (i))
 69#define   PORT_CTRL_RX_DISABLE		BIT(0)
 70#define   PORT_CTRL_TX_DISABLE		BIT(1)
 71#define   PORT_CTRL_RX_BCST_EN		BIT(2) /* Broadcast RX (P8 only) */
 72#define   PORT_CTRL_RX_MCST_EN		BIT(3) /* Multicast RX (P8 only) */
 73#define   PORT_CTRL_RX_UCST_EN		BIT(4) /* Unicast RX (P8 only) */
 74#define	  PORT_CTRL_STP_STATE_S		5
 75#define   PORT_CTRL_NO_STP		(0 << PORT_CTRL_STP_STATE_S)
 76#define   PORT_CTRL_DIS_STATE		(1 << PORT_CTRL_STP_STATE_S)
 77#define   PORT_CTRL_BLOCK_STATE		(2 << PORT_CTRL_STP_STATE_S)
 78#define   PORT_CTRL_LISTEN_STATE	(3 << PORT_CTRL_STP_STATE_S)
 79#define   PORT_CTRL_LEARN_STATE		(4 << PORT_CTRL_STP_STATE_S)
 80#define   PORT_CTRL_FWD_STATE		(5 << PORT_CTRL_STP_STATE_S)
 81#define   PORT_CTRL_STP_STATE_MASK	(0x7 << PORT_CTRL_STP_STATE_S)
 82
 83/* SMP Control Register (8 bit) */
 84#define B53_SMP_CTRL			0x0a
 85
 86/* Switch Mode Control Register (8 bit) */
 87#define B53_SWITCH_MODE			0x0b
 88#define   SM_SW_FWD_MODE		BIT(0)	/* 1 = Managed Mode */
 89#define   SM_SW_FWD_EN			BIT(1)	/* Forwarding Enable */
 90
 91/* IMP Port state override register (8 bit) */
 92#define B53_PORT_OVERRIDE_CTRL		0x0e
 93#define   PORT_OVERRIDE_LINK		BIT(0)
 94#define   PORT_OVERRIDE_FULL_DUPLEX	BIT(1) /* 0 = Half Duplex */
 95#define   PORT_OVERRIDE_SPEED_S		2
 96#define   PORT_OVERRIDE_SPEED_10M	(0 << PORT_OVERRIDE_SPEED_S)
 97#define   PORT_OVERRIDE_SPEED_100M	(1 << PORT_OVERRIDE_SPEED_S)
 98#define   PORT_OVERRIDE_SPEED_1000M	(2 << PORT_OVERRIDE_SPEED_S)
 99#define   PORT_OVERRIDE_LP_FLOW_25	BIT(3) /* BCM5325 only */
100#define   PORT_OVERRIDE_RV_MII_25	BIT(4) /* BCM5325 only */
101#define   PORT_OVERRIDE_RX_FLOW		BIT(4)
102#define   PORT_OVERRIDE_TX_FLOW		BIT(5)
103#define   PORT_OVERRIDE_SPEED_2000M	BIT(6) /* BCM5301X only, requires setting 1000M */
104#define   PORT_OVERRIDE_EN		BIT(7) /* Use the register contents */
105
106/* Power-down mode control (8 bit) */
107#define B53_PD_MODE_CTRL_25		0x0f
108#define  PD_MODE_PORT_MASK		0x1f
109/* Bit 0 also powers down the switch. */
110#define  PD_MODE_POWER_DOWN_PORT(i)	BIT(i)
111
112/* IP Multicast control (8 bit) */
113#define B53_IP_MULTICAST_CTRL		0x21
114#define  B53_IP_MC			BIT(0)
115#define  B53_UC_FWD_EN			BIT(6)
116#define  B53_MC_FWD_EN			BIT(7)
117
118/* Switch control (8 bit) */
119#define B53_SWITCH_CTRL			0x22
120#define  B53_MII_DUMB_FWDG_EN		BIT(6)
121
122/* Protected Port Selection (16 bit) */
123#define B53_PROTECTED_PORT_SEL		0x24
124#define B53_PROTECTED_PORT_SEL_25	0x26
125
126/* (16 bit) */
127#define B53_UC_FLOOD_MASK		0x32
128#define B53_MC_FLOOD_MASK		0x34
129#define B53_IPMC_FLOOD_MASK		0x36
130#define B53_DIS_LEARNING		0x3c
131
132/*
133 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
134 *
135 * For port 8 still use B53_PORT_OVERRIDE_CTRL
136 * Please note that not all ports are available on every hardware, e.g. BCM5301X
137 * don't include overriding port 6, BCM63xx also have some limitations.
138 */
139#define B53_GMII_PORT_OVERRIDE_CTRL(i)	(0x58 + (i))
140#define   GMII_PO_LINK			BIT(0)
141#define   GMII_PO_FULL_DUPLEX		BIT(1) /* 0 = Half Duplex */
142#define   GMII_PO_SPEED_S		2
143#define   GMII_PO_SPEED_10M		(0 << GMII_PO_SPEED_S)
144#define   GMII_PO_SPEED_100M		(1 << GMII_PO_SPEED_S)
145#define   GMII_PO_SPEED_1000M		(2 << GMII_PO_SPEED_S)
146#define   GMII_PO_RX_FLOW		BIT(4)
147#define   GMII_PO_TX_FLOW		BIT(5)
148#define   GMII_PO_EN			BIT(6) /* Use the register contents */
149#define   GMII_PO_SPEED_2000M		BIT(7) /* BCM5301X only, requires setting 1000M */
150
151#define B53_RGMII_CTRL_IMP		0x60
152#define   RGMII_CTRL_ENABLE_GMII	BIT(7)
153#define   RGMII_CTRL_MII_OVERRIDE	BIT(6)
154#define   RGMII_CTRL_TIMING_SEL		BIT(2)
155#define   RGMII_CTRL_DLL_RXC		BIT(1)
156#define   RGMII_CTRL_DLL_TXC		BIT(0)
157
158#define B53_RGMII_CTRL_P(i)		(B53_RGMII_CTRL_IMP + (i))
159
160/* Software reset register (8 bit) */
161#define B53_SOFTRESET			0x79
162#define   SW_RST			BIT(7)
163#define   EN_CH_RST			BIT(6)
164#define   EN_SW_RST			BIT(4)
165
166/* Fast Aging Control register (8 bit) */
167#define B53_FAST_AGE_CTRL		0x88
168#define   FAST_AGE_STATIC		BIT(0)
169#define   FAST_AGE_DYNAMIC		BIT(1)
170#define   FAST_AGE_PORT			BIT(2)
171#define   FAST_AGE_VLAN			BIT(3)
172#define   FAST_AGE_STP			BIT(4)
173#define   FAST_AGE_MC			BIT(5)
174#define   FAST_AGE_DONE			BIT(7)
175
176/* Fast Aging Port Control register (8 bit) */
177#define B53_FAST_AGE_PORT_CTRL		0x89
178
179/* Fast Aging VID Control register (16 bit) */
180#define B53_FAST_AGE_VID_CTRL		0x8a
181
182/*************************************************************************
183 * Status Page registers
184 *************************************************************************/
185
186/* Link Status Summary Register (16bit) */
187#define B53_LINK_STAT			0x00
188
189/* Link Status Change Register (16 bit) */
190#define B53_LINK_STAT_CHANGE		0x02
191
192/* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */
193#define B53_SPEED_STAT			0x04
194#define  SPEED_PORT_FE(reg, port)	(((reg) >> (port)) & 1)
195#define  SPEED_PORT_GE(reg, port)	(((reg) >> 2 * (port)) & 3)
196#define  SPEED_STAT_10M			0
197#define  SPEED_STAT_100M		1
198#define  SPEED_STAT_1000M		2
199
200/* Duplex Status Summary (16 bit) */
201#define B53_DUPLEX_STAT_FE		0x06
202#define B53_DUPLEX_STAT_GE		0x08
203#define B53_DUPLEX_STAT_63XX		0x0c
204
205/* Revision ID register for BCM5325 */
206#define B53_REV_ID_25			0x50
207
208/* Strap Value (48 bit) */
209#define B53_STRAP_VALUE			0x70
210#define   SV_GMII_CTRL_115		BIT(27)
211
212/*************************************************************************
213 * Management Mode Page Registers
214 *************************************************************************/
215
216/* Global Management Config Register (8 bit) */
217#define B53_GLOBAL_CONFIG		0x00
218#define   GC_RESET_MIB			0x01
219#define   GC_RX_BPDU_EN			0x02
220#define   GC_MIB_AC_HDR_EN		0x10
221#define   GC_MIB_AC_EN			0x20
222#define   GC_FRM_MGMT_PORT_M		0xC0
223#define   GC_FRM_MGMT_PORT_04		0x00
224#define   GC_FRM_MGMT_PORT_MII		0x80
225
226/* Broadcom Header control register (8 bit) */
227#define B53_BRCM_HDR			0x03
228#define   BRCM_HDR_P8_EN		BIT(0) /* Enable tagging on port 8 */
229#define   BRCM_HDR_P5_EN		BIT(1) /* Enable tagging on port 5 */
230#define   BRCM_HDR_P7_EN		BIT(2) /* Enable tagging on port 7 */
231
232/* Aging Time control register (32 bit) */
233#define B53_AGING_TIME_CONTROL		0x06
234#define B53_AGING_TIME_CONTROL_63XX	0x08
235#define  AGE_CHANGE			BIT(20)
236#define  AGE_TIME_MASK			0x7ffff
237#define  AGE_TIME_MAX			1048575
238
239/* Mirror capture control register (16 bit) */
240#define B53_MIR_CAP_CTL			0x10
241#define  CAP_PORT_MASK			0xf
242#define  BLK_NOT_MIR			BIT(14)
243#define  MIRROR_EN			BIT(15)
244
245/* Ingress mirror control register (16 bit) */
246#define B53_IG_MIR_CTL			0x12
247#define  MIRROR_MASK			0x1ff
248#define  DIV_EN				BIT(13)
249#define  MIRROR_FILTER_MASK		0x3
250#define  MIRROR_FILTER_SHIFT		14
251#define  MIRROR_ALL			0
252#define  MIRROR_DA			1
253#define  MIRROR_SA			2
254
255/* Ingress mirror divider register (16 bit) */
256#define B53_IG_MIR_DIV			0x14
257#define  IN_MIRROR_DIV_MASK		0x3ff
258
259/* Ingress mirror MAC address register (48 bit) */
260#define B53_IG_MIR_MAC			0x16
261
262/* Egress mirror control register (16 bit) */
263#define B53_EG_MIR_CTL			0x1C
264
265/* Egress mirror divider register (16 bit) */
266#define B53_EG_MIR_DIV			0x1E
267
268/* Egress mirror MAC address register (48 bit) */
269#define B53_EG_MIR_MAC			0x20
270
271/* Device ID register (8 or 32 bit) */
272#define B53_DEVICE_ID			0x30
273
274/* Revision ID register (8 bit) */
275#define B53_REV_ID			0x40
276
277/* Broadcom header RX control (16 bit) */
278#define B53_BRCM_HDR_RX_DIS		0x60
279
280/* Broadcom header TX control (16 bit)	*/
281#define B53_BRCM_HDR_TX_DIS		0x62
282
283/*************************************************************************
284 * ARL Access Page Registers
285 *************************************************************************/
286
287/* VLAN Table Access Register (8 bit) */
288#define B53_VT_ACCESS			0x80
289#define B53_VT_ACCESS_9798		0x60 /* for BCM5397/BCM5398 */
290#define B53_VT_ACCESS_63XX		0x60 /* for BCM6328/62/68 */
291#define   VTA_CMD_WRITE			0
292#define   VTA_CMD_READ			1
293#define   VTA_CMD_CLEAR			2
294#define   VTA_START_CMD			BIT(7)
295
296/* VLAN Table Index Register (16 bit) */
297#define B53_VT_INDEX			0x81
298#define B53_VT_INDEX_9798		0x61
299#define B53_VT_INDEX_63XX		0x62
300
301/* VLAN Table Entry Register (32 bit) */
302#define B53_VT_ENTRY			0x83
303#define B53_VT_ENTRY_9798		0x63
304#define B53_VT_ENTRY_63XX		0x64
305#define   VTE_MEMBERS			0x1ff
306#define   VTE_UNTAG_S			9
307#define   VTE_UNTAG			(0x1ff << 9)
308
309/*************************************************************************
310 * ARL I/O Registers
311 *************************************************************************/
312
313/* ARL Table Read/Write Register (8 bit) */
314#define B53_ARLTBL_RW_CTRL		0x00
315#define    ARLTBL_RW			BIT(0)
316#define    ARLTBL_IVL_SVL_SELECT	BIT(6)
317#define    ARLTBL_START_DONE		BIT(7)
318
319/* MAC Address Index Register (48 bit) */
320#define B53_MAC_ADDR_IDX		0x02
321
322/* VLAN ID Index Register (16 bit) */
323#define B53_VLAN_ID_IDX			0x08
324
325/* ARL Table MAC/VID Entry N Registers (64 bit)
326 *
327 * BCM5325 and BCM5365 share most definitions below
328 */
329#define B53_ARLTBL_MAC_VID_ENTRY(n)	((0x10 * (n)) + 0x10)
330#define   ARLTBL_MAC_MASK		0xffffffffffffULL
331#define   ARLTBL_VID_S			48
332#define   ARLTBL_VID_MASK		0xfff
333#define   ARLTBL_DATA_PORT_ID_S_25	48
334#define   ARLTBL_DATA_PORT_ID_MASK_25	GENMASK_ULL(53, 48)
335#define   ARLTBL_AGE_25			BIT_ULL(61)
336#define   ARLTBL_STATIC_25		BIT_ULL(62)
337#define   ARLTBL_VALID_25		BIT_ULL(63)
338
339/* ARL Table Data Entry N Registers (32 bit) */
340#define B53_ARLTBL_DATA_ENTRY(n)	((0x10 * (n)) + 0x18)
341#define   ARLTBL_DATA_PORT_ID_MASK	0x1ff
342#define   ARLTBL_TC(tc)			((3 & tc) << 11)
343#define   ARLTBL_AGE			BIT(14)
344#define   ARLTBL_STATIC			BIT(15)
345#define   ARLTBL_VALID			BIT(16)
346
347/* BCM5389 ARL Table Data Entry N Register format (16 bit) */
348#define   ARLTBL_DATA_PORT_ID_MASK_89	GENMASK(8, 0)
349#define   ARLTBL_TC_MASK_89		GENMASK(12, 10)
350#define   ARLTBL_AGE_89			BIT(13)
351#define   ARLTBL_STATIC_89		BIT(14)
352#define   ARLTBL_VALID_89		BIT(15)
353
354/* BCM5325/BCM565 ARL Table VID Entry N Registers (8 bit) */
355#define B53_ARLTBL_VID_ENTRY_25(n)	((0x2 * (n)) + 0x30)
356
357/* Maximum number of bin entries in the ARL for all switches */
358#define B53_ARLTBL_MAX_BIN_ENTRIES	4
359
360/* ARL Search Control Register (8 bit) */
361#define B53_ARL_SRCH_CTL		0x50
362#define B53_ARL_SRCH_CTL_25		0x20
363#define B53_ARL_SRCH_CTL_89		0x30
364#define   ARL_SRCH_VLID			BIT(0)
365#define   ARL_SRCH_STDN			BIT(7)
366
367/* ARL Search Address Register (16 bit) */
368#define B53_ARL_SRCH_ADDR		0x51
369#define B53_ARL_SRCH_ADDR_25		0x22
370#define B53_ARL_SRCH_ADDR_65		0x24
371#define B53_ARL_SRCH_ADDR_89		0x31
372#define B53_ARL_SRCH_ADDR_63XX		0x32
373#define  ARL_ADDR_MASK			GENMASK(14, 0)
374
375/* ARL Search MAC/VID Result (64 bit) */
376#define B53_ARL_SRCH_RSTL_0_MACVID	0x60
377#define B53_ARL_SRCH_RSLT_MACVID_89	0x33
378#define B53_ARL_SRCH_RSLT_MACVID_63XX	0x34
379
380/* Single register search result on 5325/5365 */
381#define B53_ARL_SRCH_RSTL_0_MACVID_25	0x24
382#define   ARL_SRCH_RSLT_PORT_ID_S_25	48
383#define   ARL_SRCH_RSLT_PORT_ID_MASK_25	GENMASK_ULL(52, 48)
384#define   ARL_SRCH_RSLT_VID_S_25	53
385#define   ARL_SRCH_RSLT_VID_MASK_25	GENMASK_ULL(60, 53)
386
387/* BCM5325/5365 Search result extend register (8 bit) */
388#define B53_ARL_SRCH_RSLT_EXT_25	0x2c
389#define   ARL_SRCH_RSLT_EXT_MC_MII	BIT(2)
390
391/* ARL Search Data Result (32 bit) */
392#define B53_ARL_SRCH_RSTL_0		0x68
393
394/* BCM5389 ARL Search Data Result (16 bit) */
395#define B53_ARL_SRCH_RSLT_89		0x3b
396
397#define B53_ARL_SRCH_RSTL_MACVID(x)	(B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10))
398#define B53_ARL_SRCH_RSTL(x)		(B53_ARL_SRCH_RSTL_0 + ((x) * 0x10))
399
400/* 63XX ARL Search Data Result (16 bit) */
401#define B53_ARL_SRCH_RSLT_63XX		0x3c
402#define   ARL_SRST_PORT_ID_MASK_63XX	GENMASK(9, 1)
403#define   ARL_SRST_TC_MASK_63XX		GENMASK(13, 11)
404#define   ARL_SRST_AGE_63XX		BIT(14)
405#define   ARL_SRST_STATIC_63XX		BIT(15)
406
407/*************************************************************************
408 * IEEE 802.1X Registers
409 *************************************************************************/
410
411/* Multicast DLF Drop Control register (16 bit) */
412#define B53_IEEE_MCAST_DLF		0x94
413#define B53_IEEE_MCAST_DROP_EN		BIT(11)
414
415/* Unicast DLF Drop Control register (16 bit) */
416#define B53_IEEE_UCAST_DLF		0x96
417#define B53_IEEE_UCAST_DROP_EN		BIT(11)
418
419/*************************************************************************
420 * Port VLAN Registers
421 *************************************************************************/
422
423/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
424#define B53_PVLAN_PORT_MASK(i)		((i) * 2)
425
426/* Join all VLANs register (16 bit) */
427#define B53_JOIN_ALL_VLAN_EN		0x50
428
429/*************************************************************************
430 * 802.1Q Page Registers
431 *************************************************************************/
432
433/* Global QoS Control (8 bit) */
434#define B53_QOS_GLOBAL_CTL		0x00
435
436/* Enable 802.1Q for individual Ports (16 bit) */
437#define B53_802_1P_EN			0x04
438
439/*************************************************************************
440 * VLAN Page Registers
441 *************************************************************************/
442
443/* VLAN Control 0 (8 bit) */
444#define B53_VLAN_CTRL0			0x00
445#define   VC0_8021PF_CTRL_MASK		0x3
446#define   VC0_8021PF_CTRL_NONE		0x0
447#define   VC0_8021PF_CTRL_CHANGE_PRI	0x1
448#define   VC0_8021PF_CTRL_CHANGE_VID	0x2
449#define   VC0_8021PF_CTRL_CHANGE_BOTH	0x3
450#define   VC0_8021QF_CTRL_MASK		0xc
451#define   VC0_8021QF_CTRL_CHANGE_PRI	0x1
452#define   VC0_8021QF_CTRL_CHANGE_VID	0x2
453#define   VC0_8021QF_CTRL_CHANGE_BOTH	0x3
454#define   VC0_RESERVED_1		BIT(1)
455#define   VC0_DROP_VID_MISS		BIT(4)
456#define   VC0_VID_HASH_VID		BIT(5)
457#define   VC0_VID_CHK_EN		BIT(6)	/* Use VID,DA or VID,SA */
458#define   VC0_VLAN_EN			BIT(7)	/* 802.1Q VLAN Enabled */
459
460/* VLAN Control 1 (8 bit) */
461#define B53_VLAN_CTRL1			0x01
462#define   VC1_RX_MCST_TAG_EN		BIT(1)
463#define   VC1_RX_MCST_FWD_EN		BIT(2)
464#define   VC1_RX_MCST_UNTAG_EN		BIT(3)
465
466/* VLAN Control 2 (8 bit) */
467#define B53_VLAN_CTRL2			0x02
468
469/* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */
470#define B53_VLAN_CTRL3			0x03
471#define B53_VLAN_CTRL3_63XX		0x04
472#define   VC3_MAXSIZE_1532		BIT(6) /* 5325 only */
473#define   VC3_HIGH_8BIT_EN		BIT(7) /* 5325 only */
474
475/* VLAN Control 4 (8 bit) */
476#define B53_VLAN_CTRL4			0x05
477#define B53_VLAN_CTRL4_25		0x04
478#define B53_VLAN_CTRL4_63XX		0x06
479#define   VC4_ING_VID_CHECK_S		6
480#define   VC4_ING_VID_CHECK_MASK	(0x3 << VC4_ING_VID_CHECK_S)
481#define   VC4_ING_VID_VIO_FWD		0 /* forward, but do not learn */
482#define   VC4_ING_VID_VIO_DROP		1 /* drop VID violations */
483#define   VC4_NO_ING_VID_CHK		2 /* do not check */
484#define   VC4_ING_VID_VIO_TO_IMP	3 /* redirect to MII port */
485
486/* VLAN Control 5 (8 bit) */
487#define B53_VLAN_CTRL5			0x06
488#define B53_VLAN_CTRL5_25		0x05
489#define B53_VLAN_CTRL5_63XX		0x07
490#define   VC5_VID_FFF_EN		BIT(2)
491#define   VC5_DROP_VTABLE_MISS		BIT(3)
492
493/* VLAN Control 6 (8 bit) */
494#define B53_VLAN_CTRL6			0x07
495#define B53_VLAN_CTRL6_63XX		0x08
496
497/* VLAN Table Access Register (16 bit) */
498#define B53_VLAN_TABLE_ACCESS_25	0x06	/* BCM5325E/5350 */
499#define B53_VLAN_TABLE_ACCESS_65	0x08	/* BCM5365 */
500#define   VTA_VID_LOW_MASK_25		0xf
501#define   VTA_VID_LOW_MASK_65		0xff
502#define   VTA_VID_HIGH_S_25		4
503#define   VTA_VID_HIGH_S_65		8
504#define   VTA_VID_HIGH_MASK_25		(0xff << VTA_VID_HIGH_S_25E)
505#define   VTA_VID_HIGH_MASK_65		(0xf << VTA_VID_HIGH_S_65)
506#define   VTA_RW_STATE			BIT(12)
507#define   VTA_RW_STATE_RD		0
508#define   VTA_RW_STATE_WR		BIT(12)
509#define   VTA_RW_OP_EN			BIT(13)
510
511/* VLAN Read/Write Registers for (16/32 bit) */
512#define B53_VLAN_WRITE_25		0x08
513#define B53_VLAN_WRITE_65		0x0a
514#define B53_VLAN_READ			0x0c
515#define   VA_MEMBER_MASK		0x3f
516#define   VA_UNTAG_S_25			6
517#define   VA_UNTAG_MASK_25		0x3f
518#define   VA_UNTAG_S_65			7
519#define   VA_UNTAG_MASK_65		0x1f
520#define   VA_VID_HIGH_S			12
521#define   VA_VID_HIGH_MASK		(0xffff << VA_VID_HIGH_S)
522#define   VA_VALID_25			BIT(20)
523#define   VA_VALID_25_R4		BIT(24)
524#define   VA_VALID_65			BIT(14)
525
526/* VLAN Port Default Tag (16 bit) */
527#define B53_VLAN_PORT_DEF_TAG(i)	(0x10 + 2 * (i))
528
529/*************************************************************************
530 * Jumbo Frame Page Registers
531 *************************************************************************/
532
533/* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */
534#define B53_JUMBO_PORT_MASK		0x01
535#define B53_JUMBO_PORT_MASK_63XX	0x04
536#define   JPM_10_100_JUMBO_EN		BIT(24) /* GigE always enabled */
537
538/* Good Frame Max Size without 802.1Q TAG (16 bit) */
539#define B53_JUMBO_MAX_SIZE		0x05
540#define B53_JUMBO_MAX_SIZE_63XX		0x08
541#define   JMS_MIN_SIZE			1518
542#define   JMS_MAX_SIZE			9724
543
544/*************************************************************************
545 * EAP Page Registers
546 *************************************************************************/
547#define B53_PORT_EAP_CONF(i)		(0x20 + 8 * (i))
548#define  EAP_MODE_SHIFT			51
549#define  EAP_MODE_SHIFT_63XX		50
550#define  EAP_MODE_MASK			(0x3ull << EAP_MODE_SHIFT)
551#define  EAP_MODE_MASK_63XX		(0x3ull << EAP_MODE_SHIFT_63XX)
552#define  EAP_MODE_BASIC			0
553#define  EAP_MODE_SIMPLIFIED		3
554
555/*************************************************************************
556 * EEE Configuration Page Registers
557 *************************************************************************/
558
559/* EEE Enable control register (16 bit) */
560#define B53_EEE_EN_CTRL			0x00
561
562/* EEE LPI assert status register (16 bit) */
563#define B53_EEE_LPI_ASSERT_STS		0x02
564
565/* EEE LPI indicate status register (16 bit) */
566#define B53_EEE_LPI_INDICATE		0x4
567
568/* EEE Receiving idle symbols status register (16 bit) */
569#define B53_EEE_RX_IDLE_SYM_STS		0x6
570
571/* EEE Pipeline timer register (32 bit) */
572#define B53_EEE_PIP_TIMER		0xC
573
574/* EEE Sleep timer Gig register (32 bit) */
575#define B53_EEE_SLEEP_TIMER_GIG(i)	(0x10 + 4 * (i))
576
577/* EEE Sleep timer FE register (32 bit) */
578#define B53_EEE_SLEEP_TIMER_FE(i)	(0x34 + 4 * (i))
579
580/* EEE Minimum LP timer Gig register (32 bit) */
581#define B53_EEE_MIN_LP_TIMER_GIG(i)	(0x58 + 4 * (i))
582
583/* EEE Minimum LP timer FE register (32 bit) */
584#define B53_EEE_MIN_LP_TIMER_FE(i)	(0x7c + 4 * (i))
585
586/* EEE Wake timer Gig register (16 bit) */
587#define B53_EEE_WAKE_TIMER_GIG(i)	(0xa0 + 2 * (i))
588
589/* EEE Wake timer FE register (16 bit) */
590#define B53_EEE_WAKE_TIMER_FE(i)	(0xb2 + 2 * (i))
591
592
593/*************************************************************************
594 * CFP Configuration Page Registers
595 *************************************************************************/
596
597/* CFP Control Register with ports map (8 bit) */
598#define B53_CFP_CTRL			0x00
599
600#endif /* !__B53_REGS_H */