mcp251xfd.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * mcp251xfd - Microchip MCP251xFD Family CAN controller driver
  4 *
  5 * Copyright (c) 2019, 2020, 2021, 2023 Pengutronix,
  6 *               Marc Kleine-Budde <kernel@pengutronix.de>
  7 * Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
  8 */
  9
 10#ifndef _MCP251XFD_H
 11#define _MCP251XFD_H
 12
 13#include <linux/bitfield.h>
 14#include <linux/can/core.h>
 15#include <linux/can/dev.h>
 16#include <linux/can/rx-offload.h>
 17#include <linux/gpio/consumer.h>
 18#include <linux/gpio/driver.h>
 19#include <linux/kernel.h>
 20#include <linux/netdevice.h>
 21#include <linux/regmap.h>
 22#include <linux/regulator/consumer.h>
 23#include <linux/spi/spi.h>
 24#include <linux/timecounter.h>
 25#include <linux/workqueue.h>
 26
 27/* MPC251x registers */
 28
 29/* CAN FD Controller Module SFR */
 30#define MCP251XFD_REG_CON 0x00
 31#define MCP251XFD_REG_CON_TXBWS_MASK GENMASK(31, 28)
 32#define MCP251XFD_REG_CON_ABAT BIT(27)
 33#define MCP251XFD_REG_CON_REQOP_MASK GENMASK(26, 24)
 34#define MCP251XFD_REG_CON_MODE_MIXED 0
 35#define MCP251XFD_REG_CON_MODE_SLEEP 1
 36#define MCP251XFD_REG_CON_MODE_INT_LOOPBACK 2
 37#define MCP251XFD_REG_CON_MODE_LISTENONLY 3
 38#define MCP251XFD_REG_CON_MODE_CONFIG 4
 39#define MCP251XFD_REG_CON_MODE_EXT_LOOPBACK 5
 40#define MCP251XFD_REG_CON_MODE_CAN2_0 6
 41#define MCP251XFD_REG_CON_MODE_RESTRICTED 7
 42#define MCP251XFD_REG_CON_OPMOD_MASK GENMASK(23, 21)
 43#define MCP251XFD_REG_CON_TXQEN BIT(20)
 44#define MCP251XFD_REG_CON_STEF BIT(19)
 45#define MCP251XFD_REG_CON_SERR2LOM BIT(18)
 46#define MCP251XFD_REG_CON_ESIGM BIT(17)
 47#define MCP251XFD_REG_CON_RTXAT BIT(16)
 48#define MCP251XFD_REG_CON_BRSDIS BIT(12)
 49#define MCP251XFD_REG_CON_BUSY BIT(11)
 50#define MCP251XFD_REG_CON_WFT_MASK GENMASK(10, 9)
 51#define MCP251XFD_REG_CON_WFT_T00FILTER 0x0
 52#define MCP251XFD_REG_CON_WFT_T01FILTER 0x1
 53#define MCP251XFD_REG_CON_WFT_T10FILTER 0x2
 54#define MCP251XFD_REG_CON_WFT_T11FILTER 0x3
 55#define MCP251XFD_REG_CON_WAKFIL BIT(8)
 56#define MCP251XFD_REG_CON_PXEDIS BIT(6)
 57#define MCP251XFD_REG_CON_ISOCRCEN BIT(5)
 58#define MCP251XFD_REG_CON_DNCNT_MASK GENMASK(4, 0)
 59
 60#define MCP251XFD_REG_NBTCFG 0x04
 61#define MCP251XFD_REG_NBTCFG_BRP_MASK GENMASK(31, 24)
 62#define MCP251XFD_REG_NBTCFG_TSEG1_MASK GENMASK(23, 16)
 63#define MCP251XFD_REG_NBTCFG_TSEG2_MASK GENMASK(14, 8)
 64#define MCP251XFD_REG_NBTCFG_SJW_MASK GENMASK(6, 0)
 65
 66#define MCP251XFD_REG_DBTCFG 0x08
 67#define MCP251XFD_REG_DBTCFG_BRP_MASK GENMASK(31, 24)
 68#define MCP251XFD_REG_DBTCFG_TSEG1_MASK GENMASK(20, 16)
 69#define MCP251XFD_REG_DBTCFG_TSEG2_MASK GENMASK(11, 8)
 70#define MCP251XFD_REG_DBTCFG_SJW_MASK GENMASK(3, 0)
 71
 72#define MCP251XFD_REG_TDC 0x0c
 73#define MCP251XFD_REG_TDC_EDGFLTEN BIT(25)
 74#define MCP251XFD_REG_TDC_SID11EN BIT(24)
 75#define MCP251XFD_REG_TDC_TDCMOD_MASK GENMASK(17, 16)
 76#define MCP251XFD_REG_TDC_TDCMOD_AUTO 2
 77#define MCP251XFD_REG_TDC_TDCMOD_MANUAL 1
 78#define MCP251XFD_REG_TDC_TDCMOD_DISABLED 0
 79#define MCP251XFD_REG_TDC_TDCO_MASK GENMASK(14, 8)
 80#define MCP251XFD_REG_TDC_TDCV_MASK GENMASK(5, 0)
 81
 82#define MCP251XFD_REG_TBC 0x10
 83
 84#define MCP251XFD_REG_TSCON 0x14
 85#define MCP251XFD_REG_TSCON_TSRES BIT(18)
 86#define MCP251XFD_REG_TSCON_TSEOF BIT(17)
 87#define MCP251XFD_REG_TSCON_TBCEN BIT(16)
 88#define MCP251XFD_REG_TSCON_TBCPRE_MASK GENMASK(9, 0)
 89
 90#define MCP251XFD_REG_VEC 0x18
 91#define MCP251XFD_REG_VEC_RXCODE_MASK GENMASK(30, 24)
 92#define MCP251XFD_REG_VEC_TXCODE_MASK GENMASK(22, 16)
 93#define MCP251XFD_REG_VEC_FILHIT_MASK GENMASK(12, 8)
 94#define MCP251XFD_REG_VEC_ICODE_MASK GENMASK(6, 0)
 95
 96#define MCP251XFD_REG_INT 0x1c
 97#define MCP251XFD_REG_INT_IF_MASK GENMASK(15, 0)
 98#define MCP251XFD_REG_INT_IE_MASK GENMASK(31, 16)
 99#define MCP251XFD_REG_INT_IVMIE BIT(31)
100#define MCP251XFD_REG_INT_WAKIE BIT(30)
101#define MCP251XFD_REG_INT_CERRIE BIT(29)
102#define MCP251XFD_REG_INT_SERRIE BIT(28)
103#define MCP251XFD_REG_INT_RXOVIE BIT(27)
104#define MCP251XFD_REG_INT_TXATIE BIT(26)
105#define MCP251XFD_REG_INT_SPICRCIE BIT(25)
106#define MCP251XFD_REG_INT_ECCIE BIT(24)
107#define MCP251XFD_REG_INT_TEFIE BIT(20)
108#define MCP251XFD_REG_INT_MODIE BIT(19)
109#define MCP251XFD_REG_INT_TBCIE BIT(18)
110#define MCP251XFD_REG_INT_RXIE BIT(17)
111#define MCP251XFD_REG_INT_TXIE BIT(16)
112#define MCP251XFD_REG_INT_IVMIF BIT(15)
113#define MCP251XFD_REG_INT_WAKIF BIT(14)
114#define MCP251XFD_REG_INT_CERRIF BIT(13)
115#define MCP251XFD_REG_INT_SERRIF BIT(12)
116#define MCP251XFD_REG_INT_RXOVIF BIT(11)
117#define MCP251XFD_REG_INT_TXATIF BIT(10)
118#define MCP251XFD_REG_INT_SPICRCIF BIT(9)
119#define MCP251XFD_REG_INT_ECCIF BIT(8)
120#define MCP251XFD_REG_INT_TEFIF BIT(4)
121#define MCP251XFD_REG_INT_MODIF BIT(3)
122#define MCP251XFD_REG_INT_TBCIF BIT(2)
123#define MCP251XFD_REG_INT_RXIF BIT(1)
124#define MCP251XFD_REG_INT_TXIF BIT(0)
125/* These IRQ flags must be cleared by SW in the CAN_INT register */
126#define MCP251XFD_REG_INT_IF_CLEARABLE_MASK \
127	(MCP251XFD_REG_INT_IVMIF | MCP251XFD_REG_INT_WAKIF | \
128	 MCP251XFD_REG_INT_CERRIF |  MCP251XFD_REG_INT_SERRIF | \
129	 MCP251XFD_REG_INT_MODIF)
130
131#define MCP251XFD_REG_RXIF 0x20
132#define MCP251XFD_REG_TXIF 0x24
133#define MCP251XFD_REG_RXOVIF 0x28
134#define MCP251XFD_REG_TXATIF 0x2c
135#define MCP251XFD_REG_TXREQ 0x30
136
137#define MCP251XFD_REG_TREC 0x34
138#define MCP251XFD_REG_TREC_TXBO BIT(21)
139#define MCP251XFD_REG_TREC_TXBP BIT(20)
140#define MCP251XFD_REG_TREC_RXBP BIT(19)
141#define MCP251XFD_REG_TREC_TXWARN BIT(18)
142#define MCP251XFD_REG_TREC_RXWARN BIT(17)
143#define MCP251XFD_REG_TREC_EWARN BIT(16)
144#define MCP251XFD_REG_TREC_TEC_MASK GENMASK(15, 8)
145#define MCP251XFD_REG_TREC_REC_MASK GENMASK(7, 0)
146
147#define MCP251XFD_REG_BDIAG0 0x38
148#define MCP251XFD_REG_BDIAG0_DTERRCNT_MASK GENMASK(31, 24)
149#define MCP251XFD_REG_BDIAG0_DRERRCNT_MASK GENMASK(23, 16)
150#define MCP251XFD_REG_BDIAG0_NTERRCNT_MASK GENMASK(15, 8)
151#define MCP251XFD_REG_BDIAG0_NRERRCNT_MASK GENMASK(7, 0)
152
153#define MCP251XFD_REG_BDIAG1 0x3c
154#define MCP251XFD_REG_BDIAG1_DLCMM BIT(31)
155#define MCP251XFD_REG_BDIAG1_ESI BIT(30)
156#define MCP251XFD_REG_BDIAG1_DCRCERR BIT(29)
157#define MCP251XFD_REG_BDIAG1_DSTUFERR BIT(28)
158#define MCP251XFD_REG_BDIAG1_DFORMERR BIT(27)
159#define MCP251XFD_REG_BDIAG1_DBIT1ERR BIT(25)
160#define MCP251XFD_REG_BDIAG1_DBIT0ERR BIT(24)
161#define MCP251XFD_REG_BDIAG1_TXBOERR BIT(23)
162#define MCP251XFD_REG_BDIAG1_NCRCERR BIT(21)
163#define MCP251XFD_REG_BDIAG1_NSTUFERR BIT(20)
164#define MCP251XFD_REG_BDIAG1_NFORMERR BIT(19)
165#define MCP251XFD_REG_BDIAG1_NACKERR BIT(18)
166#define MCP251XFD_REG_BDIAG1_NBIT1ERR BIT(17)
167#define MCP251XFD_REG_BDIAG1_NBIT0ERR BIT(16)
168#define MCP251XFD_REG_BDIAG1_BERR_MASK \
169	(MCP251XFD_REG_BDIAG1_DLCMM | MCP251XFD_REG_BDIAG1_ESI | \
170	 MCP251XFD_REG_BDIAG1_DCRCERR | MCP251XFD_REG_BDIAG1_DSTUFERR | \
171	 MCP251XFD_REG_BDIAG1_DFORMERR | MCP251XFD_REG_BDIAG1_DBIT1ERR | \
172	 MCP251XFD_REG_BDIAG1_DBIT0ERR | MCP251XFD_REG_BDIAG1_TXBOERR | \
173	 MCP251XFD_REG_BDIAG1_NCRCERR | MCP251XFD_REG_BDIAG1_NSTUFERR | \
174	 MCP251XFD_REG_BDIAG1_NFORMERR | MCP251XFD_REG_BDIAG1_NACKERR | \
175	 MCP251XFD_REG_BDIAG1_NBIT1ERR | MCP251XFD_REG_BDIAG1_NBIT0ERR)
176#define MCP251XFD_REG_BDIAG1_EFMSGCNT_MASK GENMASK(15, 0)
177
178#define MCP251XFD_REG_TEFCON 0x40
179#define MCP251XFD_REG_TEFCON_FSIZE_MASK GENMASK(28, 24)
180#define MCP251XFD_REG_TEFCON_FRESET BIT(10)
181#define MCP251XFD_REG_TEFCON_UINC BIT(8)
182#define MCP251XFD_REG_TEFCON_TEFTSEN BIT(5)
183#define MCP251XFD_REG_TEFCON_TEFOVIE BIT(3)
184#define MCP251XFD_REG_TEFCON_TEFFIE BIT(2)
185#define MCP251XFD_REG_TEFCON_TEFHIE BIT(1)
186#define MCP251XFD_REG_TEFCON_TEFNEIE BIT(0)
187
188#define MCP251XFD_REG_TEFSTA 0x44
189#define MCP251XFD_REG_TEFSTA_TEFOVIF BIT(3)
190#define MCP251XFD_REG_TEFSTA_TEFFIF BIT(2)
191#define MCP251XFD_REG_TEFSTA_TEFHIF BIT(1)
192#define MCP251XFD_REG_TEFSTA_TEFNEIF BIT(0)
193
194#define MCP251XFD_REG_TEFUA 0x48
195
196#define MCP251XFD_REG_TXQCON 0x50
197#define MCP251XFD_REG_TXQCON_PLSIZE_MASK GENMASK(31, 29)
198#define MCP251XFD_REG_TXQCON_PLSIZE_8 0
199#define MCP251XFD_REG_TXQCON_PLSIZE_12 1
200#define MCP251XFD_REG_TXQCON_PLSIZE_16 2
201#define MCP251XFD_REG_TXQCON_PLSIZE_20 3
202#define MCP251XFD_REG_TXQCON_PLSIZE_24 4
203#define MCP251XFD_REG_TXQCON_PLSIZE_32 5
204#define MCP251XFD_REG_TXQCON_PLSIZE_48 6
205#define MCP251XFD_REG_TXQCON_PLSIZE_64 7
206#define MCP251XFD_REG_TXQCON_FSIZE_MASK GENMASK(28, 24)
207#define MCP251XFD_REG_TXQCON_TXAT_UNLIMITED 3
208#define MCP251XFD_REG_TXQCON_TXAT_THREE_SHOT 1
209#define MCP251XFD_REG_TXQCON_TXAT_ONE_SHOT 0
210#define MCP251XFD_REG_TXQCON_TXAT_MASK GENMASK(22, 21)
211#define MCP251XFD_REG_TXQCON_TXPRI_MASK GENMASK(20, 16)
212#define MCP251XFD_REG_TXQCON_FRESET BIT(10)
213#define MCP251XFD_REG_TXQCON_TXREQ BIT(9)
214#define MCP251XFD_REG_TXQCON_UINC BIT(8)
215#define MCP251XFD_REG_TXQCON_TXEN BIT(7)
216#define MCP251XFD_REG_TXQCON_TXATIE BIT(4)
217#define MCP251XFD_REG_TXQCON_TXQEIE BIT(2)
218#define MCP251XFD_REG_TXQCON_TXQNIE BIT(0)
219
220#define MCP251XFD_REG_TXQSTA 0x54
221#define MCP251XFD_REG_TXQSTA_TXQCI_MASK GENMASK(12, 8)
222#define MCP251XFD_REG_TXQSTA_TXABT BIT(7)
223#define MCP251XFD_REG_TXQSTA_TXLARB BIT(6)
224#define MCP251XFD_REG_TXQSTA_TXERR BIT(5)
225#define MCP251XFD_REG_TXQSTA_TXATIF BIT(4)
226#define MCP251XFD_REG_TXQSTA_TXQEIF BIT(2)
227#define MCP251XFD_REG_TXQSTA_TXQNIF BIT(0)
228
229#define MCP251XFD_REG_TXQUA 0x58
230
231#define MCP251XFD_REG_FIFOCON(x) (0x50 + 0xc * (x))
232#define MCP251XFD_REG_FIFOCON_PLSIZE_MASK GENMASK(31, 29)
233#define MCP251XFD_REG_FIFOCON_PLSIZE_8 0
234#define MCP251XFD_REG_FIFOCON_PLSIZE_12 1
235#define MCP251XFD_REG_FIFOCON_PLSIZE_16 2
236#define MCP251XFD_REG_FIFOCON_PLSIZE_20 3
237#define MCP251XFD_REG_FIFOCON_PLSIZE_24 4
238#define MCP251XFD_REG_FIFOCON_PLSIZE_32 5
239#define MCP251XFD_REG_FIFOCON_PLSIZE_48 6
240#define MCP251XFD_REG_FIFOCON_PLSIZE_64 7
241#define MCP251XFD_REG_FIFOCON_FSIZE_MASK GENMASK(28, 24)
242#define MCP251XFD_REG_FIFOCON_TXAT_MASK GENMASK(22, 21)
243#define MCP251XFD_REG_FIFOCON_TXAT_ONE_SHOT 0
244#define MCP251XFD_REG_FIFOCON_TXAT_THREE_SHOT 1
245#define MCP251XFD_REG_FIFOCON_TXAT_UNLIMITED 3
246#define MCP251XFD_REG_FIFOCON_TXPRI_MASK GENMASK(20, 16)
247#define MCP251XFD_REG_FIFOCON_FRESET BIT(10)
248#define MCP251XFD_REG_FIFOCON_TXREQ BIT(9)
249#define MCP251XFD_REG_FIFOCON_UINC BIT(8)
250#define MCP251XFD_REG_FIFOCON_TXEN BIT(7)
251#define MCP251XFD_REG_FIFOCON_RTREN BIT(6)
252#define MCP251XFD_REG_FIFOCON_RXTSEN BIT(5)
253#define MCP251XFD_REG_FIFOCON_TXATIE BIT(4)
254#define MCP251XFD_REG_FIFOCON_RXOVIE BIT(3)
255#define MCP251XFD_REG_FIFOCON_TFERFFIE BIT(2)
256#define MCP251XFD_REG_FIFOCON_TFHRFHIE BIT(1)
257#define MCP251XFD_REG_FIFOCON_TFNRFNIE BIT(0)
258
259#define MCP251XFD_REG_FIFOSTA(x) (0x54 + 0xc * (x))
260#define MCP251XFD_REG_FIFOSTA_FIFOCI_MASK GENMASK(12, 8)
261#define MCP251XFD_REG_FIFOSTA_TXABT BIT(7)
262#define MCP251XFD_REG_FIFOSTA_TXLARB BIT(6)
263#define MCP251XFD_REG_FIFOSTA_TXERR BIT(5)
264#define MCP251XFD_REG_FIFOSTA_TXATIF BIT(4)
265#define MCP251XFD_REG_FIFOSTA_RXOVIF BIT(3)
266#define MCP251XFD_REG_FIFOSTA_TFERFFIF BIT(2)
267#define MCP251XFD_REG_FIFOSTA_TFHRFHIF BIT(1)
268#define MCP251XFD_REG_FIFOSTA_TFNRFNIF BIT(0)
269
270#define MCP251XFD_REG_FIFOUA(x) (0x58 + 0xc * (x))
271
272#define MCP251XFD_REG_FLTCON(x) (0x1d0 + 0x4 * (x))
273#define MCP251XFD_REG_FLTCON_FLTEN3 BIT(31)
274#define MCP251XFD_REG_FLTCON_F3BP_MASK GENMASK(28, 24)
275#define MCP251XFD_REG_FLTCON_FLTEN2 BIT(23)
276#define MCP251XFD_REG_FLTCON_F2BP_MASK GENMASK(20, 16)
277#define MCP251XFD_REG_FLTCON_FLTEN1 BIT(15)
278#define MCP251XFD_REG_FLTCON_F1BP_MASK GENMASK(12, 8)
279#define MCP251XFD_REG_FLTCON_FLTEN0 BIT(7)
280#define MCP251XFD_REG_FLTCON_F0BP_MASK GENMASK(4, 0)
281#define MCP251XFD_REG_FLTCON_FLTEN(x) (BIT(7) << 8 * ((x) & 0x3))
282#define MCP251XFD_REG_FLTCON_FLT_MASK(x) (GENMASK(7, 0) << (8 * ((x) & 0x3)))
283#define MCP251XFD_REG_FLTCON_FBP(x, fifo) ((fifo) << 8 * ((x) & 0x3))
284
285#define MCP251XFD_REG_FLTOBJ(x) (0x1f0 + 0x8 * (x))
286#define MCP251XFD_REG_FLTOBJ_EXIDE BIT(30)
287#define MCP251XFD_REG_FLTOBJ_SID11 BIT(29)
288#define MCP251XFD_REG_FLTOBJ_EID_MASK GENMASK(28, 11)
289#define MCP251XFD_REG_FLTOBJ_SID_MASK GENMASK(10, 0)
290
291#define MCP251XFD_REG_FLTMASK(x) (0x1f4 + 0x8 * (x))
292#define MCP251XFD_REG_MASK_MIDE BIT(30)
293#define MCP251XFD_REG_MASK_MSID11 BIT(29)
294#define MCP251XFD_REG_MASK_MEID_MASK GENMASK(28, 11)
295#define MCP251XFD_REG_MASK_MSID_MASK GENMASK(10, 0)
296
297/* RAM */
298#define MCP251XFD_RAM_START 0x400
299#define MCP251XFD_RAM_SIZE SZ_2K
300
301/* Message Object */
302#define MCP251XFD_OBJ_ID_SID11 BIT(29)
303#define MCP251XFD_OBJ_ID_EID_MASK GENMASK(28, 11)
304#define MCP251XFD_OBJ_ID_SID_MASK GENMASK(10, 0)
305#define MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK GENMASK(31, 9)
306#define MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK GENMASK(15, 9)
307#define MCP251XFD_OBJ_FLAGS_SEQ_MASK MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK
308#define MCP251XFD_OBJ_FLAGS_ESI BIT(8)
309#define MCP251XFD_OBJ_FLAGS_FDF BIT(7)
310#define MCP251XFD_OBJ_FLAGS_BRS BIT(6)
311#define MCP251XFD_OBJ_FLAGS_RTR BIT(5)
312#define MCP251XFD_OBJ_FLAGS_IDE BIT(4)
313#define MCP251XFD_OBJ_FLAGS_DLC_MASK GENMASK(3, 0)
314
315#define MCP251XFD_REG_FRAME_EFF_SID_MASK GENMASK(28, 18)
316#define MCP251XFD_REG_FRAME_EFF_EID_MASK GENMASK(17, 0)
317
318/* MCP2517/18FD SFR */
319#define MCP251XFD_REG_OSC 0xe00
320#define MCP251XFD_REG_OSC_SCLKRDY BIT(12)
321#define MCP251XFD_REG_OSC_OSCRDY BIT(10)
322#define MCP251XFD_REG_OSC_PLLRDY BIT(8)
323#define MCP251XFD_REG_OSC_CLKODIV_10 3
324#define MCP251XFD_REG_OSC_CLKODIV_4 2
325#define MCP251XFD_REG_OSC_CLKODIV_2 1
326#define MCP251XFD_REG_OSC_CLKODIV_1 0
327#define MCP251XFD_REG_OSC_CLKODIV_MASK GENMASK(6, 5)
328#define MCP251XFD_REG_OSC_SCLKDIV BIT(4)
329#define MCP251XFD_REG_OSC_LPMEN BIT(3)	/* MCP2518FD only */
330#define MCP251XFD_REG_OSC_OSCDIS BIT(2)
331#define MCP251XFD_REG_OSC_PLLEN BIT(0)
332
333#define MCP251XFD_REG_IOCON 0xe04
334#define MCP251XFD_REG_IOCON_INTOD BIT(30)
335#define MCP251XFD_REG_IOCON_SOF BIT(29)
336#define MCP251XFD_REG_IOCON_TXCANOD BIT(28)
337#define MCP251XFD_REG_IOCON_PM1 BIT(25)
338#define MCP251XFD_REG_IOCON_PM0 BIT(24)
339#define MCP251XFD_REG_IOCON_PM(n) (MCP251XFD_REG_IOCON_PM0 << (n))
340#define MCP251XFD_REG_IOCON_GPIO1 BIT(17)
341#define MCP251XFD_REG_IOCON_GPIO0 BIT(16)
342#define MCP251XFD_REG_IOCON_GPIO(n) (MCP251XFD_REG_IOCON_GPIO0 << (n))
343#define MCP251XFD_REG_IOCON_GPIO_MASK GENMASK(17, 16)
344#define MCP251XFD_REG_IOCON_LAT1 BIT(9)
345#define MCP251XFD_REG_IOCON_LAT0 BIT(8)
346#define MCP251XFD_REG_IOCON_LAT(n) (MCP251XFD_REG_IOCON_LAT0 << (n))
347#define MCP251XFD_REG_IOCON_LAT_MASK GENMASK(9, 8)
348#define MCP251XFD_REG_IOCON_XSTBYEN BIT(6)
349#define MCP251XFD_REG_IOCON_TRIS1 BIT(1)
350#define MCP251XFD_REG_IOCON_TRIS0 BIT(0)
351#define MCP251XFD_REG_IOCON_TRIS(n) (MCP251XFD_REG_IOCON_TRIS0 << (n))
352
353#define MCP251XFD_REG_CRC 0xe08
354#define MCP251XFD_REG_CRC_FERRIE BIT(25)
355#define MCP251XFD_REG_CRC_CRCERRIE BIT(24)
356#define MCP251XFD_REG_CRC_FERRIF BIT(17)
357#define MCP251XFD_REG_CRC_CRCERRIF BIT(16)
358#define MCP251XFD_REG_CRC_IF_MASK GENMASK(17, 16)
359#define MCP251XFD_REG_CRC_MASK GENMASK(15, 0)
360
361#define MCP251XFD_REG_ECCCON 0xe0c
362#define MCP251XFD_REG_ECCCON_PARITY_MASK GENMASK(14, 8)
363#define MCP251XFD_REG_ECCCON_DEDIE BIT(2)
364#define MCP251XFD_REG_ECCCON_SECIE BIT(1)
365#define MCP251XFD_REG_ECCCON_ECCEN BIT(0)
366
367#define MCP251XFD_REG_ECCSTAT 0xe10
368#define MCP251XFD_REG_ECCSTAT_ERRADDR_MASK GENMASK(27, 16)
369#define MCP251XFD_REG_ECCSTAT_IF_MASK GENMASK(2, 1)
370#define MCP251XFD_REG_ECCSTAT_DEDIF BIT(2)
371#define MCP251XFD_REG_ECCSTAT_SECIF BIT(1)
372
373#define MCP251XFD_REG_DEVID 0xe14	/* MCP2518FD only */
374#define MCP251XFD_REG_DEVID_ID_MASK GENMASK(7, 4)
375#define MCP251XFD_REG_DEVID_REV_MASK GENMASK(3, 0)
376
377/* SPI commands */
378#define MCP251XFD_SPI_INSTRUCTION_RESET 0x0000
379#define MCP251XFD_SPI_INSTRUCTION_WRITE 0x2000
380#define MCP251XFD_SPI_INSTRUCTION_READ 0x3000
381#define MCP251XFD_SPI_INSTRUCTION_WRITE_CRC 0xa000
382#define MCP251XFD_SPI_INSTRUCTION_READ_CRC 0xb000
383#define MCP251XFD_SPI_INSTRUCTION_WRITE_CRC_SAFE 0xc000
384#define MCP251XFD_SPI_ADDRESS_MASK GENMASK(11, 0)
385
386#define MCP251XFD_SYSCLOCK_HZ_MAX 40000000
387#define MCP251XFD_SYSCLOCK_HZ_MIN 1000000
388#define MCP251XFD_SPICLOCK_HZ_MAX 20000000
389#define MCP251XFD_TIMESTAMP_WORK_DELAY_SEC 45
390static_assert(MCP251XFD_TIMESTAMP_WORK_DELAY_SEC <
391	      CYCLECOUNTER_MASK(32) / MCP251XFD_SYSCLOCK_HZ_MAX / 2);
392#define MCP251XFD_OSC_PLL_MULTIPLIER 10
393#define MCP251XFD_OSC_STAB_SLEEP_US (3 * USEC_PER_MSEC)
394#define MCP251XFD_OSC_STAB_TIMEOUT_US (10 * MCP251XFD_OSC_STAB_SLEEP_US)
395#define MCP251XFD_POLL_SLEEP_US (10)
396#define MCP251XFD_POLL_TIMEOUT_US (USEC_PER_MSEC)
397#define MCP251XFD_FRAME_LEN_MAX_BITS (736)
398
399/* Misc */
400#define MCP251XFD_NAPI_WEIGHT 32
401#define MCP251XFD_SOFTRESET_RETRIES_MAX 3
402#define MCP251XFD_READ_CRC_RETRIES_MAX 3
403#define MCP251XFD_ECC_CNT_MAX 2
404#define MCP251XFD_SANITIZE_SPI 1
405#define MCP251XFD_SANITIZE_CAN 1
406
407/* FIFO and Ring */
408#define MCP251XFD_FIFO_TEF_NUM 1U
409#define MCP251XFD_FIFO_RX_NUM 3U
410#define MCP251XFD_FIFO_TX_NUM 1U
411
412#define MCP251XFD_FIFO_DEPTH 32U
413
414#define MCP251XFD_RX_OBJ_NUM_MIN 16U
415#define MCP251XFD_RX_OBJ_NUM_MAX (MCP251XFD_FIFO_RX_NUM * MCP251XFD_FIFO_DEPTH)
416#define MCP251XFD_RX_FIFO_DEPTH_MIN 4U
417#define MCP251XFD_RX_FIFO_DEPTH_COALESCE_MIN 8U
418
419#define MCP251XFD_TX_OBJ_NUM_MIN 2U
420#define MCP251XFD_TX_OBJ_NUM_MAX 16U
421#define MCP251XFD_TX_OBJ_NUM_CAN_DEFAULT 8U
422#define MCP251XFD_TX_OBJ_NUM_CANFD_DEFAULT 4U
423#define MCP251XFD_TX_FIFO_DEPTH_MIN 2U
424#define MCP251XFD_TX_FIFO_DEPTH_COALESCE_MIN 2U
425
426static_assert(MCP251XFD_FIFO_TEF_NUM == 1U);
427static_assert(MCP251XFD_FIFO_TEF_NUM == MCP251XFD_FIFO_TX_NUM);
428static_assert(MCP251XFD_FIFO_RX_NUM <= 4U);
429
430/* Silence TX MAB overflow warnings */
431#define MCP251XFD_QUIRK_MAB_NO_WARN BIT(0)
432/* Use CRC to access registers */
433#define MCP251XFD_QUIRK_CRC_REG BIT(1)
434/* Use CRC to access RX/TEF-RAM */
435#define MCP251XFD_QUIRK_CRC_RX BIT(2)
436/* Use CRC to access TX-RAM */
437#define MCP251XFD_QUIRK_CRC_TX BIT(3)
438/* Enable ECC for RAM */
439#define MCP251XFD_QUIRK_ECC BIT(4)
440/* Use Half Duplex SPI transfers */
441#define MCP251XFD_QUIRK_HALF_DUPLEX BIT(5)
442
443struct mcp251xfd_hw_tef_obj {
444	u32 id;
445	u32 flags;
446	u32 ts;
447};
448
449/* The tx_obj_raw version is used in spi async, i.e. without
450 * regmap. We have to take care of endianness ourselves.
451 */
452struct __packed mcp251xfd_hw_tx_obj_raw {
453	__le32 id;
454	__le32 flags;
455	u8 data[sizeof_field(struct canfd_frame, data)];
456};
457
458struct mcp251xfd_hw_tx_obj_can {
459	u32 id;
460	u32 flags;
461	u8 data[sizeof_field(struct can_frame, data)];
462};
463
464struct mcp251xfd_hw_tx_obj_canfd {
465	u32 id;
466	u32 flags;
467	u8 data[sizeof_field(struct canfd_frame, data)];
468};
469
470struct mcp251xfd_hw_rx_obj_can {
471	u32 id;
472	u32 flags;
473	u32 ts;
474	u8 data[sizeof_field(struct can_frame, data)];
475};
476
477struct mcp251xfd_hw_rx_obj_canfd {
478	u32 id;
479	u32 flags;
480	u32 ts;
481	u8 data[sizeof_field(struct canfd_frame, data)];
482};
483
484struct __packed mcp251xfd_buf_cmd {
485	__be16 cmd;
486};
487
488struct __packed mcp251xfd_buf_cmd_crc {
489	__be16 cmd;
490	u8 len;
491};
492
493union mcp251xfd_tx_obj_load_buf {
494	struct __packed {
495		struct mcp251xfd_buf_cmd cmd;
496		struct mcp251xfd_hw_tx_obj_raw hw_tx_obj;
497	} nocrc;
498	struct __packed {
499		struct mcp251xfd_buf_cmd_crc cmd;
500		struct mcp251xfd_hw_tx_obj_raw hw_tx_obj;
501		__be16 crc;
502	} crc;
503} ____cacheline_aligned;
504
505union mcp251xfd_write_reg_buf {
506	struct __packed {
507		struct mcp251xfd_buf_cmd cmd;
508		u8 data[4];
509	} nocrc;
510	struct __packed {
511		struct mcp251xfd_buf_cmd_crc cmd;
512		u8 data[4];
513		__be16 crc;
514	} crc;
515	struct __packed {
516		struct mcp251xfd_buf_cmd cmd;
517		u8 data[1];
518		__be16 crc;
519	} safe;
520} ____cacheline_aligned;
521
522struct mcp251xfd_tx_obj {
523	struct spi_message msg;
524	struct spi_transfer xfer[2];
525	union mcp251xfd_tx_obj_load_buf buf;
526};
527
528struct mcp251xfd_tef_ring {
529	unsigned int head;
530	unsigned int tail;
531
532	/* u8 obj_num equals tx_ring->obj_num */
533	/* u8 obj_size equals sizeof(struct mcp251xfd_hw_tef_obj) */
534	/* u8 obj_num_shift_to_u8 equals tx_ring->obj_num_shift_to_u8 */
535
536	union mcp251xfd_write_reg_buf irq_enable_buf;
537	struct spi_transfer irq_enable_xfer;
538	struct spi_message irq_enable_msg;
539
540	union mcp251xfd_write_reg_buf uinc_buf;
541	union mcp251xfd_write_reg_buf uinc_irq_disable_buf;
542	struct spi_transfer uinc_xfer[MCP251XFD_TX_OBJ_NUM_MAX];
543};
544
545struct mcp251xfd_tx_ring {
546	unsigned int head;
547	unsigned int tail;
548
549	u16 base;
550	u8 nr;
551	u8 fifo_nr;
552	u8 obj_num;
553	u8 obj_num_shift_to_u8;
554	u8 obj_size;
555
556	struct mcp251xfd_tx_obj obj[MCP251XFD_TX_OBJ_NUM_MAX];
557	union mcp251xfd_write_reg_buf rts_buf;
558};
559
560struct mcp251xfd_rx_ring {
561	unsigned int head;
562	unsigned int tail;
563
564	/* timestamp of the last valid received CAN frame */
565	u64 last_valid;
566
567	u16 base;
568	u8 nr;
569	u8 fifo_nr;
570	u8 obj_num;
571	u8 obj_num_shift_to_u8;
572	u8 obj_size;
573
574	union mcp251xfd_write_reg_buf irq_enable_buf;
575	struct spi_transfer irq_enable_xfer;
576	struct spi_message irq_enable_msg;
577
578	union mcp251xfd_write_reg_buf uinc_buf;
579	union mcp251xfd_write_reg_buf uinc_irq_disable_buf;
580	struct spi_transfer uinc_xfer[MCP251XFD_FIFO_DEPTH];
581	struct mcp251xfd_hw_rx_obj_canfd obj[];
582};
583
584struct __packed mcp251xfd_map_buf_nocrc {
585	struct mcp251xfd_buf_cmd cmd;
586	u8 data[256];
587} ____cacheline_aligned;
588
589struct __packed mcp251xfd_map_buf_crc {
590	struct mcp251xfd_buf_cmd_crc cmd;
591	u8 data[256 - 4];
592	__be16 crc;
593} ____cacheline_aligned;
594
595struct mcp251xfd_ecc {
596	u32 ecc_stat;
597	int cnt;
598};
599
600struct mcp251xfd_regs_status {
601	u32 intf;
602	u32 rxif;
603};
604
605enum mcp251xfd_model {
606	MCP251XFD_MODEL_MCP2517FD = 0x2517,
607	MCP251XFD_MODEL_MCP2518FD = 0x2518,
608	MCP251XFD_MODEL_MCP251863 = 0x251863,
609	MCP251XFD_MODEL_MCP251XFD = 0xffffffff,	/* autodetect model */
610};
611
612struct mcp251xfd_devtype_data {
613	enum mcp251xfd_model model;
614	u32 quirks;
615};
616
617enum mcp251xfd_flags {
618	MCP251XFD_FLAGS_DOWN,
619	MCP251XFD_FLAGS_FD_MODE,
620
621	__MCP251XFD_FLAGS_SIZE__
622};
623
624struct mcp251xfd_priv {
625	struct can_priv can;
626	struct can_rx_offload offload;
627	struct net_device *ndev;
628
629	struct regmap *map_reg;			/* register access */
630	struct regmap *map_rx;			/* RX/TEF RAM access */
631
632	struct regmap *map_nocrc;
633	struct mcp251xfd_map_buf_nocrc *map_buf_nocrc_rx;
634	struct mcp251xfd_map_buf_nocrc *map_buf_nocrc_tx;
635
636	struct regmap *map_crc;
637	struct mcp251xfd_map_buf_crc *map_buf_crc_rx;
638	struct mcp251xfd_map_buf_crc *map_buf_crc_tx;
639
640	struct spi_device *spi;
641	u32 spi_max_speed_hz_orig;
642	u32 spi_max_speed_hz_fast;
643	u32 spi_max_speed_hz_slow;
644
645	struct mcp251xfd_tef_ring tef[MCP251XFD_FIFO_TEF_NUM];
646	struct mcp251xfd_rx_ring *rx[MCP251XFD_FIFO_RX_NUM];
647	struct mcp251xfd_tx_ring tx[MCP251XFD_FIFO_TX_NUM];
648
649	struct workqueue_struct *wq;
650	struct work_struct tx_work;
651	struct mcp251xfd_tx_obj *tx_work_obj;
652
653	DECLARE_BITMAP(flags, __MCP251XFD_FLAGS_SIZE__);
654
655	u8 rx_ring_num;
656	u8 rx_obj_num;
657	u8 rx_obj_num_coalesce_irq;
658	u8 tx_obj_num_coalesce_irq;
659
660	u32 rx_coalesce_usecs_irq;
661	u32 tx_coalesce_usecs_irq;
662	struct hrtimer rx_irq_timer;
663	struct hrtimer tx_irq_timer;
664
665	struct mcp251xfd_ecc ecc;
666	struct mcp251xfd_regs_status regs_status;
667
668	struct cyclecounter cc;
669	struct timecounter tc;
670	struct delayed_work timestamp;
671
672	struct gpio_desc *rx_int;
673	struct clk *clk;
674	bool pll_enable;
675	struct regulator *reg_vdd;
676	struct regulator *reg_xceiver;
677
678	struct mcp251xfd_devtype_data devtype_data;
679	struct can_berr_counter bec;
680	struct gpio_chip gc;
681};
682
683#define MCP251XFD_IS(_model) \
684static inline bool \
685mcp251xfd_is_##_model(const struct mcp251xfd_priv *priv) \
686{ \
687	return priv->devtype_data.model == MCP251XFD_MODEL_MCP##_model; \
688}
689
690MCP251XFD_IS(2517FD);
691MCP251XFD_IS(2518FD);
692MCP251XFD_IS(251863);
693MCP251XFD_IS(251XFD);
694
695static inline bool mcp251xfd_is_fd_mode(const struct mcp251xfd_priv *priv)
696{
697	/* listen-only mode works like FD mode */
698	return priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_FD);
699}
700
701static inline u8 mcp251xfd_first_byte_set(u32 mask)
702{
703	return (mask & 0x0000ffff) ?
704		((mask & 0x000000ff) ? 0 : 1) :
705		((mask & 0x00ff0000) ? 2 : 3);
706}
707
708static inline u8 mcp251xfd_last_byte_set(u32 mask)
709{
710	return (mask & 0xffff0000) ?
711		((mask & 0xff000000) ? 3 : 2) :
712		((mask & 0x0000ff00) ? 1 : 0);
713}
714
715static inline __be16 mcp251xfd_cmd_reset(void)
716{
717	return cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_RESET);
718}
719
720static inline void
721mcp251xfd_spi_cmd_read_nocrc(struct mcp251xfd_buf_cmd *cmd, u16 addr)
722{
723	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ | addr);
724}
725
726static inline void
727mcp251xfd_spi_cmd_write_nocrc(struct mcp251xfd_buf_cmd *cmd, u16 addr)
728{
729	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE | addr);
730}
731
732static inline bool mcp251xfd_reg_in_ram(unsigned int reg)
733{
734	static const struct regmap_range range =
735		regmap_reg_range(MCP251XFD_RAM_START,
736				 MCP251XFD_RAM_START + MCP251XFD_RAM_SIZE - 4);
737
738	return regmap_reg_in_range(reg, &range);
739}
740
741static inline void
742__mcp251xfd_spi_cmd_crc_set_len(struct mcp251xfd_buf_cmd_crc *cmd,
743				u16 len, bool in_ram)
744{
745	/* Number of u32 for RAM access, number of u8 otherwise. */
746	if (in_ram)
747		cmd->len = len >> 2;
748	else
749		cmd->len = len;
750}
751
752static inline void
753mcp251xfd_spi_cmd_crc_set_len_in_ram(struct mcp251xfd_buf_cmd_crc *cmd, u16 len)
754{
755	__mcp251xfd_spi_cmd_crc_set_len(cmd, len, true);
756}
757
758static inline void
759mcp251xfd_spi_cmd_crc_set_len_in_reg(struct mcp251xfd_buf_cmd_crc *cmd, u16 len)
760{
761	__mcp251xfd_spi_cmd_crc_set_len(cmd, len, false);
762}
763
764static inline void
765mcp251xfd_spi_cmd_read_crc_set_addr(struct mcp251xfd_buf_cmd_crc *cmd, u16 addr)
766{
767	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ_CRC | addr);
768}
769
770static inline void
771mcp251xfd_spi_cmd_read_crc(struct mcp251xfd_buf_cmd_crc *cmd,
772			   u16 addr, u16 len)
773{
774	mcp251xfd_spi_cmd_read_crc_set_addr(cmd, addr);
775	__mcp251xfd_spi_cmd_crc_set_len(cmd, len, mcp251xfd_reg_in_ram(addr));
776}
777
778static inline void
779mcp251xfd_spi_cmd_write_crc_set_addr(struct mcp251xfd_buf_cmd_crc *cmd,
780				     u16 addr)
781{
782	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE_CRC | addr);
783}
784
785static inline void
786mcp251xfd_spi_cmd_write_safe_set_addr(struct mcp251xfd_buf_cmd *cmd,
787				     u16 addr)
788{
789	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE_CRC_SAFE | addr);
790}
791
792static inline void
793mcp251xfd_spi_cmd_write_crc(struct mcp251xfd_buf_cmd_crc *cmd,
794			    u16 addr, u16 len)
795{
796	mcp251xfd_spi_cmd_write_crc_set_addr(cmd, addr);
797	__mcp251xfd_spi_cmd_crc_set_len(cmd, len, mcp251xfd_reg_in_ram(addr));
798}
799
800static inline u8 *
801mcp251xfd_spi_cmd_write(const struct mcp251xfd_priv *priv,
802			union mcp251xfd_write_reg_buf *write_reg_buf,
803			u16 addr, u8 len)
804{
805	u8 *data;
806
807	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) {
808		if (len == 1) {
809			mcp251xfd_spi_cmd_write_safe_set_addr(&write_reg_buf->safe.cmd,
810							     addr);
811			data = write_reg_buf->safe.data;
812		} else {
813			mcp251xfd_spi_cmd_write_crc_set_addr(&write_reg_buf->crc.cmd,
814							     addr);
815			data = write_reg_buf->crc.data;
816		}
817	} else {
818		mcp251xfd_spi_cmd_write_nocrc(&write_reg_buf->nocrc.cmd,
819					      addr);
820		data = write_reg_buf->nocrc.data;
821	}
822
823	return data;
824}
825
826static inline int mcp251xfd_get_timestamp_raw(const struct mcp251xfd_priv *priv,
827					      u32 *ts_raw)
828{
829	return regmap_read(priv->map_reg, MCP251XFD_REG_TBC, ts_raw);
830}
831
832static inline void mcp251xfd_skb_set_timestamp(struct sk_buff *skb, u64 ns)
833{
834	struct skb_shared_hwtstamps *hwtstamps = skb_hwtstamps(skb);
835
836	hwtstamps->hwtstamp = ns_to_ktime(ns);
837}
838
839static inline
840void mcp251xfd_skb_set_timestamp_raw(const struct mcp251xfd_priv *priv,
841				     struct sk_buff *skb, u32 ts_raw)
842{
843	u64 ns;
844
845	ns = timecounter_cyc2time(&priv->tc, ts_raw);
846	mcp251xfd_skb_set_timestamp(skb, ns);
847}
848
849static inline u16 mcp251xfd_get_tef_obj_addr(u8 n)
850{
851	return MCP251XFD_RAM_START +
852		sizeof(struct mcp251xfd_hw_tef_obj) * n;
853}
854
855static inline u16
856mcp251xfd_get_tx_obj_addr(const struct mcp251xfd_tx_ring *ring, u8 n)
857{
858	return ring->base + ring->obj_size * n;
859}
860
861static inline u16
862mcp251xfd_get_rx_obj_addr(const struct mcp251xfd_rx_ring *ring, u8 n)
863{
864	return ring->base + ring->obj_size * n;
865}
866
867static inline int
868mcp251xfd_tx_tail_get_from_chip(const struct mcp251xfd_priv *priv,
869				u8 *tx_tail)
870{
871	u32 fifo_sta;
872	int err;
873
874	err = regmap_read(priv->map_reg,
875			  MCP251XFD_REG_FIFOSTA(priv->tx->fifo_nr),
876			  &fifo_sta);
877	if (err)
878		return err;
879
880	*tx_tail = FIELD_GET(MCP251XFD_REG_FIFOSTA_FIFOCI_MASK, fifo_sta);
881
882	return 0;
883}
884
885static inline u8 mcp251xfd_get_tef_head(const struct mcp251xfd_priv *priv)
886{
887	return priv->tef->head & (priv->tx->obj_num - 1);
888}
889
890static inline u8 mcp251xfd_get_tef_tail(const struct mcp251xfd_priv *priv)
891{
892	return priv->tef->tail & (priv->tx->obj_num - 1);
893}
894
895static inline u8 mcp251xfd_get_tef_linear_len(const struct mcp251xfd_priv *priv, u8 len)
896{
897	return min_t(u8, len, priv->tx->obj_num - mcp251xfd_get_tef_tail(priv));
898}
899
900static inline u8 mcp251xfd_get_tx_head(const struct mcp251xfd_tx_ring *ring)
901{
902	return ring->head & (ring->obj_num - 1);
903}
904
905static inline u8 mcp251xfd_get_tx_tail(const struct mcp251xfd_tx_ring *ring)
906{
907	return ring->tail & (ring->obj_num - 1);
908}
909
910static inline u8 mcp251xfd_get_tx_free(const struct mcp251xfd_tx_ring *ring)
911{
912	return ring->obj_num - (ring->head - ring->tail);
913}
914
915static inline int
916mcp251xfd_get_tx_nr_by_addr(const struct mcp251xfd_tx_ring *tx_ring, u8 *nr,
917			    u16 addr)
918{
919	if (addr < mcp251xfd_get_tx_obj_addr(tx_ring, 0) ||
920	    addr >= mcp251xfd_get_tx_obj_addr(tx_ring, tx_ring->obj_num))
921		return -ENOENT;
922
923	*nr = (addr - mcp251xfd_get_tx_obj_addr(tx_ring, 0)) /
924		tx_ring->obj_size;
925
926	return 0;
927}
928
929static inline u8 mcp251xfd_get_rx_head(const struct mcp251xfd_rx_ring *ring)
930{
931	return ring->head & (ring->obj_num - 1);
932}
933
934static inline u8 mcp251xfd_get_rx_tail(const struct mcp251xfd_rx_ring *ring)
935{
936	return ring->tail & (ring->obj_num - 1);
937}
938
939static inline u8
940mcp251xfd_get_rx_linear_len(const struct mcp251xfd_rx_ring *ring, u8 len)
941{
942	return min_t(u8, len, ring->obj_num - mcp251xfd_get_rx_tail(ring));
943}
944
945#define mcp251xfd_for_each_tx_obj(ring, _obj, n) \
946	for ((n) = 0, (_obj) = &(ring)->obj[(n)]; \
947	     (n) < (ring)->obj_num; \
948	     (n)++, (_obj) = &(ring)->obj[(n)])
949
950#define mcp251xfd_for_each_rx_ring(priv, ring, n) \
951	for ((n) = 0, (ring) = *((priv)->rx + (n)); \
952	     (n) < (priv)->rx_ring_num; \
953	     (n)++, (ring) = *((priv)->rx + (n)))
954
955int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv);
956u16 mcp251xfd_crc16_compute2(const void *cmd, size_t cmd_size,
957			     const void *data, size_t data_size);
958u16 mcp251xfd_crc16_compute(const void *data, size_t data_size);
959void mcp251xfd_ethtool_init(struct mcp251xfd_priv *priv);
960int mcp251xfd_regmap_init(struct mcp251xfd_priv *priv);
961extern const struct can_ram_config mcp251xfd_ram_config;
962int mcp251xfd_ring_init(struct mcp251xfd_priv *priv);
963void mcp251xfd_ring_free(struct mcp251xfd_priv *priv);
964int mcp251xfd_ring_alloc(struct mcp251xfd_priv *priv);
965int mcp251xfd_handle_rxif(struct mcp251xfd_priv *priv);
966int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv);
967void mcp251xfd_timestamp_init(struct mcp251xfd_priv *priv);
968void mcp251xfd_timestamp_start(struct mcp251xfd_priv *priv);
969void mcp251xfd_timestamp_stop(struct mcp251xfd_priv *priv);
970
971void mcp251xfd_tx_obj_write_sync(struct work_struct *work);
972netdev_tx_t mcp251xfd_start_xmit(struct sk_buff *skb,
973				 struct net_device *ndev);
974
975#if IS_ENABLED(CONFIG_DEV_COREDUMP)
976void mcp251xfd_dump(const struct mcp251xfd_priv *priv);
977#else
978static inline void mcp251xfd_dump(const struct mcp251xfd_priv *priv)
979{
980}
981#endif
982
983#endif