mcp251xfd-regmap.c

  1// SPDX-License-Identifier: GPL-2.0
  2//
  3// mcp251xfd - Microchip MCP251xFD Family CAN controller driver
  4//
  5// Copyright (c) 2019, 2020, 2021 Pengutronix,
  6//               Marc Kleine-Budde <kernel@pengutronix.de>
  7//
  8
  9#include "mcp251xfd.h"
 10
 11#include <linux/unaligned.h>
 12
 13static const struct regmap_config mcp251xfd_regmap_crc;
 14
 15static int
 16_mcp251xfd_regmap_nocrc_gather_write(void *context,
 17				     const void *reg, size_t reg_len,
 18				     const void *val, size_t val_len)
 19{
 20	struct spi_device *spi = context;
 21	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
 22	struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
 23	struct spi_transfer xfer[] = {
 24		{
 25			.tx_buf = buf_tx,
 26			.len = sizeof(buf_tx->cmd) + val_len,
 27		},
 28	};
 29
 30	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
 31
 32	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
 33	    reg_len != sizeof(buf_tx->cmd.cmd))
 34		return -EINVAL;
 35
 36	memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
 37	memcpy(buf_tx->data, val, val_len);
 38
 39	return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
 40}
 41
 42static int
 43mcp251xfd_regmap_nocrc_gather_write(void *context,
 44				    const void *reg_p, size_t reg_len,
 45				    const void *val, size_t val_len)
 46{
 47	const u16 byte_exclude = MCP251XFD_REG_IOCON +
 48				 mcp251xfd_first_byte_set(MCP251XFD_REG_IOCON_GPIO_MASK);
 49	u16 reg = be16_to_cpu(*(__be16 *)reg_p) & MCP251XFD_SPI_ADDRESS_MASK;
 50	int ret;
 51
 52	/* Never write to bits 16..23 of IOCON register to avoid clearing of LAT0/LAT1
 53	 *
 54	 * According to MCP2518FD Errata DS80000789E 5 writing IOCON register using one
 55	 * SPI write command clears LAT0/LAT1.
 56	 *
 57	 * Errata Fix/Work Around suggests to write registers with single byte
 58	 * write instructions. However, it seems that the byte at 0xe06(IOCON[23:16])
 59	 * is for read-only access and writing to it causes the clearing of LAT0/LAT1.
 60	 */
 61	if (reg <= byte_exclude && reg + val_len > byte_exclude) {
 62		size_t len = byte_exclude - reg;
 63
 64		/* Write up to 0xe05 */
 65		ret = _mcp251xfd_regmap_nocrc_gather_write(context, reg_p, reg_len, val, len);
 66		if (ret)
 67			return ret;
 68
 69		/* Write from 0xe07 on */
 70		reg += len + 1;
 71		reg = (__force unsigned short)cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE | reg);
 72		return _mcp251xfd_regmap_nocrc_gather_write(context, &reg, reg_len,
 73							    val + len + 1,
 74							    val_len - len - 1);
 75	}
 76
 77	return _mcp251xfd_regmap_nocrc_gather_write(context, reg_p, reg_len,
 78						  val, val_len);
 79}
 80
 81static int
 82mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count)
 83{
 84	const size_t data_offset = sizeof(__be16);
 85
 86	return mcp251xfd_regmap_nocrc_gather_write(context, data, data_offset,
 87						   data + data_offset, count - data_offset);
 88}
 89
 90static inline bool
 91mcp251xfd_update_bits_read_reg(const struct mcp251xfd_priv *priv,
 92			       unsigned int reg)
 93{
 94	struct mcp251xfd_rx_ring *ring;
 95	int n;
 96
 97	switch (reg) {
 98	case MCP251XFD_REG_INT:
 99	case MCP251XFD_REG_TEFCON:
100	case MCP251XFD_REG_FLTCON(0):
101	case MCP251XFD_REG_ECCSTAT:
102	case MCP251XFD_REG_CRC:
103		return false;
104	case MCP251XFD_REG_CON:
105	case MCP251XFD_REG_OSC:
106	case MCP251XFD_REG_ECCCON:
107	case MCP251XFD_REG_IOCON:
108		return true;
109	default:
110		mcp251xfd_for_each_rx_ring(priv, ring, n) {
111			if (reg == MCP251XFD_REG_FIFOCON(ring->fifo_nr))
112				return false;
113			if (reg == MCP251XFD_REG_FIFOSTA(ring->fifo_nr))
114				return true;
115		}
116
117		WARN(1, "Status of reg 0x%04x unknown.\n", reg);
118	}
119
120	return true;
121}
122
123static int
124mcp251xfd_regmap_nocrc_update_bits(void *context, unsigned int reg,
125				   unsigned int mask, unsigned int val)
126{
127	struct spi_device *spi = context;
128	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
129	struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx;
130	struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
131	__le32 orig_le32 = 0, mask_le32, val_le32, tmp_le32;
132	u8 first_byte, last_byte, len;
133	int err;
134
135	BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16));
136	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
137
138	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
139	    mask == 0)
140		return -EINVAL;
141
142	first_byte = mcp251xfd_first_byte_set(mask);
143	last_byte = mcp251xfd_last_byte_set(mask);
144	len = last_byte - first_byte + 1;
145
146	if (mcp251xfd_update_bits_read_reg(priv, reg)) {
147		struct spi_transfer xfer[2] = { };
148		struct spi_message msg;
149
150		spi_message_init(&msg);
151		spi_message_add_tail(&xfer[0], &msg);
152
153		if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
154			xfer[0].tx_buf = buf_tx;
155			xfer[0].len = sizeof(buf_tx->cmd);
156
157			xfer[1].rx_buf = buf_rx->data;
158			xfer[1].len = len;
159			spi_message_add_tail(&xfer[1], &msg);
160		} else {
161			xfer[0].tx_buf = buf_tx;
162			xfer[0].rx_buf = buf_rx;
163			xfer[0].len = sizeof(buf_tx->cmd) + len;
164
165			if (MCP251XFD_SANITIZE_SPI)
166				memset(buf_tx->data, 0x0, len);
167		}
168
169		mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, reg + first_byte);
170		err = spi_sync(spi, &msg);
171		if (err)
172			return err;
173
174		memcpy(&orig_le32, buf_rx->data, len);
175	}
176
177	mask_le32 = cpu_to_le32(mask >> BITS_PER_BYTE * first_byte);
178	val_le32 = cpu_to_le32(val >> BITS_PER_BYTE * first_byte);
179
180	tmp_le32 = orig_le32 & ~mask_le32;
181	tmp_le32 |= val_le32 & mask_le32;
182
183	reg += first_byte;
184	mcp251xfd_spi_cmd_write_nocrc(&buf_tx->cmd, reg);
185	return mcp251xfd_regmap_nocrc_gather_write(context, &buf_tx->cmd, 2, &tmp_le32, len);
186}
187
188static int
189mcp251xfd_regmap_nocrc_read(void *context,
190			    const void *reg, size_t reg_len,
191			    void *val_buf, size_t val_len)
192{
193	struct spi_device *spi = context;
194	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
195	struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx;
196	struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
197	struct spi_transfer xfer[2] = { };
198	struct spi_message msg;
199	int err;
200
201	BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16));
202	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
203
204	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
205	    reg_len != sizeof(buf_tx->cmd.cmd))
206		return -EINVAL;
207
208	spi_message_init(&msg);
209	spi_message_add_tail(&xfer[0], &msg);
210
211	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
212		xfer[0].tx_buf = reg;
213		xfer[0].len = sizeof(buf_tx->cmd);
214
215		xfer[1].rx_buf = val_buf;
216		xfer[1].len = val_len;
217		spi_message_add_tail(&xfer[1], &msg);
218	} else {
219		xfer[0].tx_buf = buf_tx;
220		xfer[0].rx_buf = buf_rx;
221		xfer[0].len = sizeof(buf_tx->cmd) + val_len;
222
223		memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
224		if (MCP251XFD_SANITIZE_SPI)
225			memset(buf_tx->data, 0x0, val_len);
226	}
227
228	err = spi_sync(spi, &msg);
229	if (err)
230		return err;
231
232	if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX))
233		memcpy(val_buf, buf_rx->data, val_len);
234
235	return 0;
236}
237
238static int
239_mcp251xfd_regmap_crc_gather_write(void *context,
240				   const void *reg_p, size_t reg_len,
241				   const void *val, size_t val_len)
242{
243	struct spi_device *spi = context;
244	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
245	struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
246	struct spi_transfer xfer[] = {
247		{
248			.tx_buf = buf_tx,
249			.len = sizeof(buf_tx->cmd) + val_len +
250				sizeof(buf_tx->crc),
251		},
252	};
253	u16 reg = *(u16 *)reg_p;
254	u16 crc;
255
256	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
257
258	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
259	    reg_len != sizeof(buf_tx->cmd.cmd) +
260	    mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE)
261		return -EINVAL;
262
263	mcp251xfd_spi_cmd_write_crc(&buf_tx->cmd, reg, val_len);
264	memcpy(buf_tx->data, val, val_len);
265
266	crc = mcp251xfd_crc16_compute(buf_tx, sizeof(buf_tx->cmd) + val_len);
267	put_unaligned_be16(crc, buf_tx->data + val_len);
268
269	return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
270}
271
272static int
273mcp251xfd_regmap_crc_gather_write(void *context,
274				  const void *reg_p, size_t reg_len,
275				  const void *val, size_t val_len)
276{
277	const u16 byte_exclude = MCP251XFD_REG_IOCON +
278				 mcp251xfd_first_byte_set(MCP251XFD_REG_IOCON_GPIO_MASK);
279	u16 reg = *(u16 *)reg_p;
280	int ret;
281
282	/* Never write to bits 16..23 of IOCON register to avoid clearing of LAT0/LAT1
283	 *
284	 * According to MCP2518FD Errata DS80000789E 5 writing IOCON register using one
285	 * SPI write command clears LAT0/LAT1.
286	 *
287	 * Errata Fix/Work Around suggests to write registers with single byte
288	 * write instructions. However, it seems that the byte at 0xe06(IOCON[23:16])
289	 * is for read-only access and writing to it causes the clearing of LAT0/LAT1.
290	 */
291	if (reg <= byte_exclude  && reg + val_len > byte_exclude) {
292		size_t len = byte_exclude - reg;
293
294		/* Write up to 0xe05 */
295		ret = _mcp251xfd_regmap_crc_gather_write(context, &reg, reg_len, val, len);
296		if (ret)
297			return ret;
298
299		/* Write from 0xe07 on */
300		reg += len + 1;
301		return _mcp251xfd_regmap_crc_gather_write(context, &reg, reg_len,
302							  val + len + 1,
303							  val_len - len - 1);
304	}
305
306	return _mcp251xfd_regmap_crc_gather_write(context, reg_p, reg_len,
307						  val, val_len);
308}
309
310static int
311mcp251xfd_regmap_crc_write(void *context,
312			   const void *data, size_t count)
313{
314	const size_t data_offset = sizeof(__be16) +
315		mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE;
316
317	return mcp251xfd_regmap_crc_gather_write(context,
318						 data, data_offset,
319						 data + data_offset,
320						 count - data_offset);
321}
322
323static int
324mcp251xfd_regmap_crc_read_check_crc(const struct mcp251xfd_map_buf_crc * const buf_rx,
325				    const struct mcp251xfd_map_buf_crc * const buf_tx,
326				    unsigned int data_len)
327{
328	u16 crc_received, crc_calculated;
329
330	crc_received = get_unaligned_be16(buf_rx->data + data_len);
331	crc_calculated = mcp251xfd_crc16_compute2(&buf_tx->cmd,
332						  sizeof(buf_tx->cmd),
333						  buf_rx->data,
334						  data_len);
335	if (crc_received != crc_calculated)
336		return -EBADMSG;
337
338	return 0;
339}
340
341static int
342mcp251xfd_regmap_crc_read_one(struct mcp251xfd_priv *priv,
343			      struct spi_message *msg, unsigned int data_len)
344{
345	const struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx;
346	const struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
347	int err;
348
349	BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8));
350	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
351
352	err = spi_sync(priv->spi, msg);
353	if (err)
354		return err;
355
356	return mcp251xfd_regmap_crc_read_check_crc(buf_rx, buf_tx, data_len);
357}
358
359static int
360mcp251xfd_regmap_crc_read(void *context,
361			  const void *reg_p, size_t reg_len,
362			  void *val_buf, size_t val_len)
363{
364	struct spi_device *spi = context;
365	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
366	struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx;
367	struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
368	struct spi_transfer xfer[2] = { };
369	struct spi_message msg;
370	u16 reg = *(u16 *)reg_p;
371	int i, err;
372
373	BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8));
374	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
375
376	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
377	    reg_len != sizeof(buf_tx->cmd.cmd) +
378	    mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE)
379		return -EINVAL;
380
381	spi_message_init(&msg);
382	spi_message_add_tail(&xfer[0], &msg);
383
384	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
385		xfer[0].tx_buf = buf_tx;
386		xfer[0].len = sizeof(buf_tx->cmd);
387
388		xfer[1].rx_buf = buf_rx->data;
389		xfer[1].len = val_len + sizeof(buf_tx->crc);
390		spi_message_add_tail(&xfer[1], &msg);
391	} else {
392		xfer[0].tx_buf = buf_tx;
393		xfer[0].rx_buf = buf_rx;
394		xfer[0].len = sizeof(buf_tx->cmd) + val_len +
395			sizeof(buf_tx->crc);
396
397		if (MCP251XFD_SANITIZE_SPI)
398			memset(buf_tx->data, 0x0, val_len +
399			       sizeof(buf_tx->crc));
400	}
401
402	mcp251xfd_spi_cmd_read_crc(&buf_tx->cmd, reg, val_len);
403
404	for (i = 0; i < MCP251XFD_READ_CRC_RETRIES_MAX; i++) {
405		err = mcp251xfd_regmap_crc_read_one(priv, &msg, val_len);
406		if (!err)
407			goto out;
408		if (err != -EBADMSG)
409			return err;
410
411		/* MCP251XFD_REG_TBC is the time base counter
412		 * register. It increments once per SYS clock tick,
413		 * which is 20 or 40 MHz.
414		 *
415		 * Observation on the mcp2518fd shows that if the
416		 * lowest byte (which is transferred first on the SPI
417		 * bus) of that register is 0x00 or 0x80 the
418		 * calculated CRC doesn't always match the transferred
419		 * one. On the mcp2517fd this problem is not limited
420		 * to the first byte being 0x00 or 0x80.
421		 *
422		 * If the highest bit in the lowest byte is flipped
423		 * the transferred CRC matches the calculated one. We
424		 * assume for now the CRC operates on the correct
425		 * data.
426		 */
427		if (reg == MCP251XFD_REG_TBC &&
428		    ((buf_rx->data[0] & 0xf8) == 0x0 ||
429		     (buf_rx->data[0] & 0xf8) == 0x80)) {
430			/* Flip highest bit in lowest byte of le32 */
431			buf_rx->data[0] ^= 0x80;
432
433			/* re-check CRC */
434			err = mcp251xfd_regmap_crc_read_check_crc(buf_rx,
435								  buf_tx,
436								  val_len);
437			if (!err) {
438				/* If CRC is now correct, assume
439				 * flipped data is OK.
440				 */
441				goto out;
442			}
443		}
444
445		/* MCP251XFD_REG_OSC is the first ever reg we read from.
446		 *
447		 * The chip may be in deep sleep and this SPI transfer
448		 * (i.e. the assertion of the CS) will wake the chip
449		 * up. This takes about 3ms. The CRC of this transfer
450		 * is wrong.
451		 *
452		 * Or there isn't a chip at all, in this case the CRC
453		 * will be wrong, too.
454		 *
455		 * In both cases ignore the CRC and copy the read data
456		 * to the caller. It will take care of both cases.
457		 *
458		 */
459		if (reg == MCP251XFD_REG_OSC && val_len == sizeof(__le32)) {
460			err = 0;
461			goto out;
462		}
463
464		netdev_info(priv->ndev,
465			    "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x) retrying.\n",
466			    reg, val_len, (int)val_len, buf_rx->data,
467			    get_unaligned_be16(buf_rx->data + val_len));
468	}
469
470	if (err) {
471		netdev_err(priv->ndev,
472			   "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x).\n",
473			   reg, val_len, (int)val_len, buf_rx->data,
474			   get_unaligned_be16(buf_rx->data + val_len));
475
476		return err;
477	}
478out:
479	memcpy(val_buf, buf_rx->data, val_len);
480
481	return 0;
482}
483
484static const struct regmap_range mcp251xfd_reg_table_yes_range[] = {
485	regmap_reg_range(0x000, 0x2ec),	/* CAN FD Controller Module SFR */
486	regmap_reg_range(0x400, 0xbfc),	/* RAM */
487	regmap_reg_range(0xe00, 0xe14),	/* MCP2517/18FD SFR */
488};
489
490static const struct regmap_access_table mcp251xfd_reg_table = {
491	.yes_ranges = mcp251xfd_reg_table_yes_range,
492	.n_yes_ranges = ARRAY_SIZE(mcp251xfd_reg_table_yes_range),
493};
494
495static const struct regmap_config mcp251xfd_regmap_nocrc = {
496	.name = "nocrc",
497	.reg_bits = 16,
498	.reg_stride = 4,
499	.pad_bits = 0,
500	.val_bits = 32,
501	.max_register = 0xffc,
502	.wr_table = &mcp251xfd_reg_table,
503	.rd_table = &mcp251xfd_reg_table,
504	.cache_type = REGCACHE_NONE,
505	.read_flag_mask = (__force unsigned long)
506		cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ),
507	.write_flag_mask = (__force unsigned long)
508		cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE),
509};
510
511static const struct regmap_bus mcp251xfd_bus_nocrc = {
512	.write = mcp251xfd_regmap_nocrc_write,
513	.gather_write = mcp251xfd_regmap_nocrc_gather_write,
514	.reg_update_bits = mcp251xfd_regmap_nocrc_update_bits,
515	.read = mcp251xfd_regmap_nocrc_read,
516	.reg_format_endian_default = REGMAP_ENDIAN_BIG,
517	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
518	.max_raw_read = sizeof_field(struct mcp251xfd_map_buf_nocrc, data),
519	.max_raw_write = sizeof_field(struct mcp251xfd_map_buf_nocrc, data),
520};
521
522static const struct regmap_config mcp251xfd_regmap_crc = {
523	.name = "crc",
524	.reg_bits = 16,
525	.reg_stride = 4,
526	.pad_bits = 16,		/* keep data bits aligned */
527	.val_bits = 32,
528	.max_register = 0xffc,
529	.wr_table = &mcp251xfd_reg_table,
530	.rd_table = &mcp251xfd_reg_table,
531	.cache_type = REGCACHE_NONE,
532};
533
534static const struct regmap_bus mcp251xfd_bus_crc = {
535	.write = mcp251xfd_regmap_crc_write,
536	.gather_write = mcp251xfd_regmap_crc_gather_write,
537	.read = mcp251xfd_regmap_crc_read,
538	.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
539	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
540	.max_raw_read = sizeof_field(struct mcp251xfd_map_buf_crc, data),
541	.max_raw_write = sizeof_field(struct mcp251xfd_map_buf_crc, data),
542};
543
544static inline bool
545mcp251xfd_regmap_use_nocrc(struct mcp251xfd_priv *priv)
546{
547	return (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)) ||
548		(!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX));
549}
550
551static inline bool
552mcp251xfd_regmap_use_crc(struct mcp251xfd_priv *priv)
553{
554	return (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) ||
555		(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX);
556}
557
558static int
559mcp251xfd_regmap_init_nocrc(struct mcp251xfd_priv *priv)
560{
561	if (!priv->map_nocrc) {
562		struct regmap *map;
563
564		map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_nocrc,
565				       priv->spi, &mcp251xfd_regmap_nocrc);
566		if (IS_ERR(map))
567			return PTR_ERR(map);
568
569		priv->map_nocrc = map;
570	}
571
572	if (!priv->map_buf_nocrc_rx) {
573		priv->map_buf_nocrc_rx =
574			devm_kzalloc(&priv->spi->dev,
575				     sizeof(*priv->map_buf_nocrc_rx),
576				     GFP_KERNEL);
577		if (!priv->map_buf_nocrc_rx)
578			return -ENOMEM;
579	}
580
581	if (!priv->map_buf_nocrc_tx) {
582		priv->map_buf_nocrc_tx =
583			devm_kzalloc(&priv->spi->dev,
584				     sizeof(*priv->map_buf_nocrc_tx),
585				     GFP_KERNEL);
586		if (!priv->map_buf_nocrc_tx)
587			return -ENOMEM;
588	}
589
590	if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG))
591		priv->map_reg = priv->map_nocrc;
592
593	if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX))
594		priv->map_rx = priv->map_nocrc;
595
596	return 0;
597}
598
599static void mcp251xfd_regmap_destroy_nocrc(struct mcp251xfd_priv *priv)
600{
601	if (priv->map_buf_nocrc_rx) {
602		devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_rx);
603		priv->map_buf_nocrc_rx = NULL;
604	}
605	if (priv->map_buf_nocrc_tx) {
606		devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_tx);
607		priv->map_buf_nocrc_tx = NULL;
608	}
609}
610
611static int
612mcp251xfd_regmap_init_crc(struct mcp251xfd_priv *priv)
613{
614	if (!priv->map_crc) {
615		struct regmap *map;
616
617		map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_crc,
618				       priv->spi, &mcp251xfd_regmap_crc);
619		if (IS_ERR(map))
620			return PTR_ERR(map);
621
622		priv->map_crc = map;
623	}
624
625	if (!priv->map_buf_crc_rx) {
626		priv->map_buf_crc_rx =
627			devm_kzalloc(&priv->spi->dev,
628				     sizeof(*priv->map_buf_crc_rx),
629				     GFP_KERNEL);
630		if (!priv->map_buf_crc_rx)
631			return -ENOMEM;
632	}
633
634	if (!priv->map_buf_crc_tx) {
635		priv->map_buf_crc_tx =
636			devm_kzalloc(&priv->spi->dev,
637				     sizeof(*priv->map_buf_crc_tx),
638				     GFP_KERNEL);
639		if (!priv->map_buf_crc_tx)
640			return -ENOMEM;
641	}
642
643	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)
644		priv->map_reg = priv->map_crc;
645
646	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX)
647		priv->map_rx = priv->map_crc;
648
649	return 0;
650}
651
652static void mcp251xfd_regmap_destroy_crc(struct mcp251xfd_priv *priv)
653{
654	if (priv->map_buf_crc_rx) {
655		devm_kfree(&priv->spi->dev, priv->map_buf_crc_rx);
656		priv->map_buf_crc_rx = NULL;
657	}
658	if (priv->map_buf_crc_tx) {
659		devm_kfree(&priv->spi->dev, priv->map_buf_crc_tx);
660		priv->map_buf_crc_tx = NULL;
661	}
662}
663
664int mcp251xfd_regmap_init(struct mcp251xfd_priv *priv)
665{
666	int err;
667
668	if (mcp251xfd_regmap_use_nocrc(priv)) {
669		err = mcp251xfd_regmap_init_nocrc(priv);
670
671		if (err)
672			return err;
673	} else {
674		mcp251xfd_regmap_destroy_nocrc(priv);
675	}
676
677	if (mcp251xfd_regmap_use_crc(priv)) {
678		err = mcp251xfd_regmap_init_crc(priv);
679
680		if (err)
681			return err;
682	} else {
683		mcp251xfd_regmap_destroy_crc(priv);
684	}
685
686	return 0;
687}