rcar_canfd.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/* Renesas R-Car CAN FD device driver
   3 *
   4 * Copyright (C) 2015 Renesas Electronics Corp.
   5 */
   6
   7/* The R-Car CAN FD controller can operate in either one of the below two modes
   8 *  - CAN FD only mode
   9 *  - Classical CAN (CAN 2.0) only mode
  10 *
  11 * This driver puts the controller in CAN FD only mode by default. In this
  12 * mode, the controller acts as a CAN FD node that can also interoperate with
  13 * CAN 2.0 nodes.
  14 *
  15 * To switch the controller to Classical CAN (CAN 2.0) only mode, add
  16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
  17 * also required to switch modes.
  18 *
  19 * Note: The h/w manual register naming convention is clumsy and not acceptable
  20 * to use as it is in the driver. However, those names are added as comments
  21 * wherever it is modified to a readable name.
  22 */
  23
  24#include <linux/bitfield.h>
  25#include <linux/bitmap.h>
  26#include <linux/bitops.h>
  27#include <linux/can/dev.h>
  28#include <linux/clk.h>
  29#include <linux/errno.h>
  30#include <linux/ethtool.h>
  31#include <linux/interrupt.h>
  32#include <linux/iopoll.h>
  33#include <linux/kernel.h>
  34#include <linux/module.h>
  35#include <linux/moduleparam.h>
  36#include <linux/netdevice.h>
  37#include <linux/of.h>
  38#include <linux/phy/phy.h>
  39#include <linux/platform_device.h>
  40#include <linux/reset.h>
  41#include <linux/types.h>
  42
  43#define RCANFD_DRV_NAME			"rcar_canfd"
  44
  45/* Global register bits */
  46
  47/* RSCFDnCFDGRMCFG */
  48#define RCANFD_GRMCFG_RCMC		BIT(0)
  49
  50/* RSCFDnCFDGCFG / RSCFDnGCFG */
  51#define RCANFD_GCFG_EEFE		BIT(6)
  52#define RCANFD_GCFG_CMPOC		BIT(5)	/* CAN FD only */
  53#define RCANFD_GCFG_DCS			BIT(4)
  54#define RCANFD_GCFG_DCE			BIT(1)
  55#define RCANFD_GCFG_TPRI		BIT(0)
  56
  57/* RSCFDnCFDGCTR / RSCFDnGCTR */
  58#define RCANFD_GCTR_TSRST		BIT(16)
  59#define RCANFD_GCTR_CFMPOFIE		BIT(11)	/* CAN FD only */
  60#define RCANFD_GCTR_THLEIE		BIT(10)
  61#define RCANFD_GCTR_MEIE		BIT(9)
  62#define RCANFD_GCTR_DEIE		BIT(8)
  63#define RCANFD_GCTR_GSLPR		BIT(2)
  64#define RCANFD_GCTR_GMDC_MASK		(0x3)
  65#define RCANFD_GCTR_GMDC_GOPM		(0x0)
  66#define RCANFD_GCTR_GMDC_GRESET		(0x1)
  67#define RCANFD_GCTR_GMDC_GTEST		(0x2)
  68
  69/* RSCFDnCFDGSTS / RSCFDnGSTS */
  70#define RCANFD_GSTS_GRAMINIT		BIT(3)
  71#define RCANFD_GSTS_GSLPSTS		BIT(2)
  72#define RCANFD_GSTS_GHLTSTS		BIT(1)
  73#define RCANFD_GSTS_GRSTSTS		BIT(0)
  74/* Non-operational status */
  75#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
  76
  77/* RSCFDnCFDGERFL / RSCFDnGERFL */
  78#define RCANFD_GERFL_EEF		GENMASK(23, 16)
  79#define RCANFD_GERFL_CMPOF		BIT(3)	/* CAN FD only */
  80#define RCANFD_GERFL_THLES		BIT(2)
  81#define RCANFD_GERFL_MES		BIT(1)
  82#define RCANFD_GERFL_DEF		BIT(0)
  83
  84#define RCANFD_GERFL_ERR(gpriv, x) \
  85({\
  86	typeof(gpriv) (_gpriv) = (gpriv); \
  87	((x) & ((FIELD_PREP(RCANFD_GERFL_EEF, (_gpriv)->channels_mask)) | \
  88		RCANFD_GERFL_MES | ((_gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0))); \
  89})
  90
  91/* AFL Rx rules registers */
  92
  93/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
  94#define RCANFD_GAFLECTR_AFLDAE		BIT(8)
  95#define RCANFD_GAFLECTR_AFLPN(gpriv, page_num)	((page_num) & (gpriv)->info->max_aflpn)
  96
  97/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
  98#define RCANFD_GAFLID_GAFLLB		BIT(29)
  99
 100/* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
 101#define RCANFD_GAFLP1_GAFLFDP(x)	(1 << (x))
 102
 103/* Channel register bits */
 104
 105/* RSCFDnCmCFG - Classical CAN only */
 106#define RCANFD_CFG_SJW		GENMASK(25, 24)
 107#define RCANFD_CFG_TSEG2	GENMASK(22, 20)
 108#define RCANFD_CFG_TSEG1	GENMASK(19, 16)
 109#define RCANFD_CFG_BRP		GENMASK(9, 0)
 110
 111/* RSCFDnCFDCmNCFG - CAN FD only */
 112#define RCANFD_NCFG_NBRP	GENMASK(9, 0)
 113
 114/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 115#define RCANFD_CCTR_CTME		BIT(24)
 116#define RCANFD_CCTR_ERRD		BIT(23)
 117#define RCANFD_CCTR_BOM_MASK		(0x3 << 21)
 118#define RCANFD_CCTR_BOM_ISO		(0x0 << 21)
 119#define RCANFD_CCTR_BOM_BENTRY		(0x1 << 21)
 120#define RCANFD_CCTR_BOM_BEND		(0x2 << 21)
 121#define RCANFD_CCTR_TDCVFIE		BIT(19)
 122#define RCANFD_CCTR_SOCOIE		BIT(18)
 123#define RCANFD_CCTR_EOCOIE		BIT(17)
 124#define RCANFD_CCTR_TAIE		BIT(16)
 125#define RCANFD_CCTR_ALIE		BIT(15)
 126#define RCANFD_CCTR_BLIE		BIT(14)
 127#define RCANFD_CCTR_OLIE		BIT(13)
 128#define RCANFD_CCTR_BORIE		BIT(12)
 129#define RCANFD_CCTR_BOEIE		BIT(11)
 130#define RCANFD_CCTR_EPIE		BIT(10)
 131#define RCANFD_CCTR_EWIE		BIT(9)
 132#define RCANFD_CCTR_BEIE		BIT(8)
 133#define RCANFD_CCTR_CSLPR		BIT(2)
 134#define RCANFD_CCTR_CHMDC_MASK		(0x3)
 135#define RCANFD_CCTR_CHDMC_COPM		(0x0)
 136#define RCANFD_CCTR_CHDMC_CRESET	(0x1)
 137#define RCANFD_CCTR_CHDMC_CHLT		(0x2)
 138
 139/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 140#define RCANFD_CSTS_COMSTS		BIT(7)
 141#define RCANFD_CSTS_RECSTS		BIT(6)
 142#define RCANFD_CSTS_TRMSTS		BIT(5)
 143#define RCANFD_CSTS_BOSTS		BIT(4)
 144#define RCANFD_CSTS_EPSTS		BIT(3)
 145#define RCANFD_CSTS_SLPSTS		BIT(2)
 146#define RCANFD_CSTS_HLTSTS		BIT(1)
 147#define RCANFD_CSTS_CRSTSTS		BIT(0)
 148
 149#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
 150#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
 151
 152/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 153#define RCANFD_CERFL_ADERR		BIT(14)
 154#define RCANFD_CERFL_B0ERR		BIT(13)
 155#define RCANFD_CERFL_B1ERR		BIT(12)
 156#define RCANFD_CERFL_CERR		BIT(11)
 157#define RCANFD_CERFL_AERR		BIT(10)
 158#define RCANFD_CERFL_FERR		BIT(9)
 159#define RCANFD_CERFL_SERR		BIT(8)
 160#define RCANFD_CERFL_ALF		BIT(7)
 161#define RCANFD_CERFL_BLF		BIT(6)
 162#define RCANFD_CERFL_OVLF		BIT(5)
 163#define RCANFD_CERFL_BORF		BIT(4)
 164#define RCANFD_CERFL_BOEF		BIT(3)
 165#define RCANFD_CERFL_EPF		BIT(2)
 166#define RCANFD_CERFL_EWF		BIT(1)
 167#define RCANFD_CERFL_BEF		BIT(0)
 168
 169#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
 170
 171/* RSCFDnCFDCmDCFG */
 172#define RCANFD_DCFG_DBRP		GENMASK(7, 0)
 173
 174/* RSCFDnCFDCmFDCFG */
 175#define RCANFD_GEN4_FDCFG_CLOE		BIT(30)
 176#define RCANFD_GEN4_FDCFG_FDOE		BIT(28)
 177#define RCANFD_FDCFG_TDCO		GENMASK(23, 16)
 178#define RCANFD_FDCFG_TDCE		BIT(9)
 179#define RCANFD_FDCFG_TDCOC		BIT(8)
 180
 181/* RSCFDnCFDCmFDSTS */
 182#define RCANFD_FDSTS_SOC		GENMASK(31, 24)
 183#define RCANFD_FDSTS_EOC		GENMASK(23, 16)
 184#define RCANFD_GEN4_FDSTS_TDCVF		BIT(15)
 185#define RCANFD_GEN4_FDSTS_PNSTS		GENMASK(13, 12)
 186#define RCANFD_FDSTS_SOCO		BIT(9)
 187#define RCANFD_FDSTS_EOCO		BIT(8)
 188#define RCANFD_FDSTS_TDCVF		BIT(7)
 189#define RCANFD_FDSTS_TDCR		GENMASK(7, 0)
 190
 191/* RSCFDnCFDRFCCx */
 192#define RCANFD_RFCC_RFIM		BIT(12)
 193#define RCANFD_RFCC_RFDC(x)		(((x) & 0x7) << 8)
 194#define RCANFD_RFCC_RFPLS(x)		(((x) & 0x7) << 4)
 195#define RCANFD_RFCC_RFIE		BIT(1)
 196#define RCANFD_RFCC_RFE			BIT(0)
 197
 198/* RSCFDnCFDRFSTSx */
 199#define RCANFD_RFSTS_RFIF		BIT(3)
 200#define RCANFD_RFSTS_RFMLT		BIT(2)
 201#define RCANFD_RFSTS_RFFLL		BIT(1)
 202#define RCANFD_RFSTS_RFEMP		BIT(0)
 203
 204/* RSCFDnCFDRFIDx */
 205#define RCANFD_RFID_RFIDE		BIT(31)
 206#define RCANFD_RFID_RFRTR		BIT(30)
 207
 208/* RSCFDnCFDRFPTRx */
 209#define RCANFD_RFPTR_RFDLC(x)		(((x) >> 28) & 0xf)
 210
 211/* RSCFDnCFDRFFDSTSx */
 212#define RCANFD_RFFDSTS_RFFDF		BIT(2)
 213#define RCANFD_RFFDSTS_RFBRS		BIT(1)
 214#define RCANFD_RFFDSTS_RFESI		BIT(0)
 215
 216/* Common FIFO bits */
 217
 218/* RSCFDnCFDCFCCk */
 219#define RCANFD_CFCC_CFTML(gpriv, cftml) \
 220({\
 221	typeof(gpriv) (_gpriv) = (gpriv); \
 222	(((cftml) & (_gpriv)->info->max_cftml) << (_gpriv)->info->sh->cftml); \
 223})
 224#define RCANFD_CFCC_CFM(gpriv, x)	(((x) & 0x3) << (gpriv)->info->sh->cfm)
 225#define RCANFD_CFCC_CFIM		BIT(12)
 226#define RCANFD_CFCC_CFDC(gpriv, x)	(((x) & 0x7) << (gpriv)->info->sh->cfdc)
 227#define RCANFD_CFCC_CFPLS(x)		(((x) & 0x7) << 4)
 228#define RCANFD_CFCC_CFTXIE		BIT(2)
 229#define RCANFD_CFCC_CFE			BIT(0)
 230
 231/* RSCFDnCFDCFSTSk */
 232#define RCANFD_CFSTS_CFMC(x)		(((x) >> 8) & 0xff)
 233#define RCANFD_CFSTS_CFTXIF		BIT(4)
 234#define RCANFD_CFSTS_CFMLT		BIT(2)
 235#define RCANFD_CFSTS_CFFLL		BIT(1)
 236#define RCANFD_CFSTS_CFEMP		BIT(0)
 237
 238/* RSCFDnCFDCFIDk */
 239#define RCANFD_CFID_CFIDE		BIT(31)
 240#define RCANFD_CFID_CFRTR		BIT(30)
 241
 242/* RSCFDnCFDCFPTRk */
 243#define RCANFD_CFPTR_CFDLC(x)		(((x) & 0xf) << 28)
 244
 245/* RSCFDnCFDCFFDCSTSk */
 246#define RCANFD_CFFDCSTS_CFFDF		BIT(2)
 247#define RCANFD_CFFDCSTS_CFBRS		BIT(1)
 248#define RCANFD_CFFDCSTS_CFESI		BIT(0)
 249
 250/* This controller supports either Classical CAN only mode or CAN FD only mode.
 251 * These modes are supported in two separate set of register maps & names.
 252 * However, some of the register offsets are common for both modes. Those
 253 * offsets are listed below as Common registers.
 254 *
 255 * The CAN FD only mode specific registers & Classical CAN only mode specific
 256 * registers are listed separately. Their register names starts with
 257 * RCANFD_F_xxx & RCANFD_C_xxx respectively.
 258 */
 259
 260/* Common registers */
 261
 262/* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
 263#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
 264/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 265#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
 266/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 267#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
 268/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 269#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
 270
 271/* RSCFDnCFDGCFG / RSCFDnGCFG */
 272#define RCANFD_GCFG			(0x0084)
 273/* RSCFDnCFDGCTR / RSCFDnGCTR */
 274#define RCANFD_GCTR			(0x0088)
 275/* RSCFDnCFDGCTS / RSCFDnGCTS */
 276#define RCANFD_GSTS			(0x008c)
 277/* RSCFDnCFDGERFL / RSCFDnGERFL */
 278#define RCANFD_GERFL			(0x0090)
 279/* RSCFDnCFDGTSC / RSCFDnGTSC */
 280#define RCANFD_GTSC			(0x0094)
 281/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 282#define RCANFD_GAFLECTR			(0x0098)
 283/* RSCFDnCFDGAFLCFG / RSCFDnGAFLCFG */
 284#define RCANFD_GAFLCFG(w)		(0x009c + (0x04 * (w)))
 285/* RSCFDnCFDRMNB / RSCFDnRMNB */
 286#define RCANFD_RMNB			(0x00a4)
 287/* RSCFDnCFDRMND / RSCFDnRMND */
 288#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
 289
 290/* RSCFDnCFDRFCCx / RSCFDnRFCCx */
 291#define RCANFD_RFCC(gpriv, x)		((gpriv)->info->regs->rfcc + (0x04 * (x)))
 292/* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
 293#define RCANFD_RFSTS(gpriv, x)		(RCANFD_RFCC(gpriv, x) + 0x20)
 294/* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
 295#define RCANFD_RFPCTR(gpriv, x)		(RCANFD_RFCC(gpriv, x) + 0x40)
 296
 297/* Common FIFO Control registers */
 298
 299/* RSCFDnCFDCFCCx / RSCFDnCFCCx */
 300#define RCANFD_CFCC(gpriv, ch, idx) \
 301	((gpriv)->info->regs->cfcc + (0x0c * (ch)) + (0x04 * (idx)))
 302/* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
 303#define RCANFD_CFSTS(gpriv, ch, idx) \
 304	((gpriv)->info->regs->cfsts + (0x0c * (ch)) + (0x04 * (idx)))
 305/* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
 306#define RCANFD_CFPCTR(gpriv, ch, idx) \
 307	((gpriv)->info->regs->cfpctr + (0x0c * (ch)) + (0x04 * (idx)))
 308
 309/* RSCFDnCFDGRMCFG */
 310#define RCANFD_GRMCFG			(0x04fc)
 311
 312/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 313#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
 314/* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
 315#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
 316/* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
 317#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
 318/* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
 319#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
 320
 321/* Classical CAN only mode register map */
 322
 323/* RSCFDnGAFLXXXj offset */
 324#define RCANFD_C_GAFL_OFFSET		(0x0500)
 325
 326/* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
 327#define RCANFD_C_RFOFFSET	(0x0e00)
 328#define RCANFD_C_RFID(x)	(RCANFD_C_RFOFFSET + (0x10 * (x)))
 329#define RCANFD_C_RFPTR(x)	(RCANFD_C_RFOFFSET + 0x04 + (0x10 * (x)))
 330#define RCANFD_C_RFDF(x, df) \
 331		(RCANFD_C_RFOFFSET + 0x08 + (0x10 * (x)) + (0x04 * (df)))
 332
 333/* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
 334#define RCANFD_C_CFOFFSET		(0x0e80)
 335
 336#define RCANFD_C_CFID(ch, idx) \
 337	(RCANFD_C_CFOFFSET + (0x30 * (ch)) + (0x10 * (idx)))
 338
 339#define RCANFD_C_CFPTR(ch, idx)	\
 340	(RCANFD_C_CFOFFSET + 0x04 + (0x30 * (ch)) + (0x10 * (idx)))
 341
 342#define RCANFD_C_CFDF(ch, idx, df) \
 343	(RCANFD_C_CFOFFSET + 0x08 + (0x30 * (ch)) + (0x10 * (idx)) + (0x04 * (df)))
 344
 345/* R-Car Gen4 Classical and CAN FD mode specific register map */
 346#define RCANFD_GEN4_GAFL_OFFSET		(0x1800)
 347
 348/* CAN FD mode specific register map */
 349
 350/* RSCFDnCFDCmXXX -> gpriv->fcbase[m].xxx */
 351struct rcar_canfd_f_c {
 352	u32 dcfg;
 353	u32 cfdcfg;
 354	u32 cfdctr;
 355	u32 cfdsts;
 356	u32 cfdcrc;
 357	u32 pad[3];
 358};
 359
 360/* RSCFDnCFDGAFLXXXj offset */
 361#define RCANFD_F_GAFL_OFFSET		(0x1000)
 362
 363/* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
 364#define RCANFD_F_RFOFFSET(gpriv)	((gpriv)->info->regs->rfoffset)
 365#define RCANFD_F_RFID(gpriv, x)		(RCANFD_F_RFOFFSET(gpriv) + (0x80 * (x)))
 366#define RCANFD_F_RFPTR(gpriv, x)	(RCANFD_F_RFOFFSET(gpriv) + 0x04 + (0x80 * (x)))
 367#define RCANFD_F_RFFDSTS(gpriv, x)	(RCANFD_F_RFOFFSET(gpriv) + 0x08 + (0x80 * (x)))
 368#define RCANFD_F_RFDF(gpriv, x, df) \
 369	(RCANFD_F_RFOFFSET(gpriv) + 0x0c + (0x80 * (x)) + (0x04 * (df)))
 370
 371/* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
 372#define RCANFD_F_CFOFFSET(gpriv)	((gpriv)->info->regs->cfoffset)
 373
 374#define RCANFD_F_CFID(gpriv, ch, idx) \
 375	(RCANFD_F_CFOFFSET(gpriv) + (0x180 * (ch)) + (0x80 * (idx)))
 376
 377#define RCANFD_F_CFPTR(gpriv, ch, idx) \
 378	(RCANFD_F_CFOFFSET(gpriv) + 0x04 + (0x180 * (ch)) + (0x80 * (idx)))
 379
 380#define RCANFD_F_CFFDCSTS(gpriv, ch, idx) \
 381	(RCANFD_F_CFOFFSET(gpriv) + 0x08 + (0x180 * (ch)) + (0x80 * (idx)))
 382
 383#define RCANFD_F_CFDF(gpriv, ch, idx, df) \
 384	(RCANFD_F_CFOFFSET(gpriv) + 0x0c + (0x180 * (ch)) + (0x80 * (idx)) + \
 385	 (0x04 * (df)))
 386
 387/* Constants */
 388#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
 389#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
 390
 391#define RCANFD_NUM_CHANNELS		8	/* Eight channels max */
 392
 393#define RCANFD_GAFL_PAGENUM(entry)	((entry) / 16)
 394#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
 395
 396/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
 397 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
 398 * number is added to RFFIFO index.
 399 */
 400#define RCANFD_RFFIFO_IDX		0
 401
 402/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
 403 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
 404 */
 405#define RCANFD_CFFIFO_IDX		0
 406
 407struct rcar_canfd_global;
 408
 409struct rcar_canfd_regs {
 410	u16 rfcc;	/* RX FIFO Configuration/Control Register */
 411	u16 cfcc;	/* Common FIFO Configuration/Control Register */
 412	u16 cfsts;	/* Common FIFO Status Register */
 413	u16 cfpctr;	/* Common FIFO Pointer Control Register */
 414	u16 coffset;	/* Channel Data Bitrate Configuration Register */
 415	u16 rfoffset;	/* Receive FIFO buffer access ID register */
 416	u16 cfoffset;	/* Transmit/receive FIFO buffer access ID register */
 417};
 418
 419struct rcar_canfd_shift_data {
 420	u8 ntseg2;	/* Nominal Bit Rate Time Segment 2 Control */
 421	u8 ntseg1;	/* Nominal Bit Rate Time Segment 1 Control */
 422	u8 nsjw;	/* Nominal Bit Rate Resynchronization Jump Width Control */
 423	u8 dtseg2;	/* Data Bit Rate Time Segment 2 Control */
 424	u8 dtseg1;	/* Data Bit Rate Time Segment 1 Control */
 425	u8 cftml;	/* Common FIFO TX Message Buffer Link */
 426	u8 cfm;		/* Common FIFO Mode */
 427	u8 cfdc;	/* Common FIFO Depth Configuration */
 428};
 429
 430struct rcar_canfd_hw_info {
 431	const struct can_bittiming_const *nom_bittiming;
 432	const struct can_bittiming_const *data_bittiming;
 433	const struct can_tdc_const *tdc_const;
 434	const struct rcar_canfd_regs *regs;
 435	const struct rcar_canfd_shift_data *sh;
 436	u8 rnc_field_width;
 437	u8 max_aflpn;
 438	u8 max_cftml;
 439	u8 max_channels;
 440	u8 postdiv;
 441	/* hardware features */
 442	unsigned shared_global_irqs:1;	/* Has shared global irqs */
 443	unsigned multi_channel_irqs:1;	/* Has multiple channel irqs */
 444	unsigned ch_interface_mode:1;	/* Has channel interface mode */
 445	unsigned shared_can_regs:1;	/* Has shared classical can registers */
 446	unsigned external_clk:1;	/* Has external clock */
 447};
 448
 449/* Channel priv data */
 450struct rcar_canfd_channel {
 451	struct can_priv can;			/* Must be the first member */
 452	struct net_device *ndev;
 453	struct rcar_canfd_global *gpriv;	/* Controller reference */
 454	void __iomem *base;			/* Register base address */
 455	struct phy *transceiver;		/* Optional transceiver */
 456	struct napi_struct napi;
 457	u32 tx_head;				/* Incremented on xmit */
 458	u32 tx_tail;				/* Incremented on xmit done */
 459	u32 channel;				/* Channel number */
 460	spinlock_t tx_lock;			/* To protect tx path */
 461};
 462
 463/* Global priv data */
 464struct rcar_canfd_global {
 465	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
 466	void __iomem *base;		/* Register base address */
 467	struct rcar_canfd_f_c __iomem *fcbase;
 468	struct platform_device *pdev;	/* Respective platform device */
 469	struct clk *clkp;		/* Peripheral clock */
 470	struct clk *can_clk;		/* fCAN clock */
 471	struct clk *clk_ram;		/* Clock RAM */
 472	unsigned long channels_mask;	/* Enabled channels mask */
 473	bool extclk;			/* CANFD or Ext clock */
 474	bool fdmode;			/* CAN FD or Classical CAN only mode */
 475	struct reset_control *rstc1;
 476	struct reset_control *rstc2;
 477	const struct rcar_canfd_hw_info *info;
 478};
 479
 480/* CAN FD mode nominal rate constants */
 481static const struct can_bittiming_const rcar_canfd_gen3_nom_bittiming_const = {
 482	.name = RCANFD_DRV_NAME,
 483	.tseg1_min = 2,
 484	.tseg1_max = 128,
 485	.tseg2_min = 2,
 486	.tseg2_max = 32,
 487	.sjw_max = 32,
 488	.brp_min = 1,
 489	.brp_max = 1024,
 490	.brp_inc = 1,
 491};
 492
 493static const struct can_bittiming_const rcar_canfd_gen4_nom_bittiming_const = {
 494	.name = RCANFD_DRV_NAME,
 495	.tseg1_min = 2,
 496	.tseg1_max = 256,
 497	.tseg2_min = 2,
 498	.tseg2_max = 128,
 499	.sjw_max = 128,
 500	.brp_min = 1,
 501	.brp_max = 1024,
 502	.brp_inc = 1,
 503};
 504
 505/* CAN FD mode data rate constants */
 506static const struct can_bittiming_const rcar_canfd_gen3_data_bittiming_const = {
 507	.name = RCANFD_DRV_NAME,
 508	.tseg1_min = 2,
 509	.tseg1_max = 16,
 510	.tseg2_min = 2,
 511	.tseg2_max = 8,
 512	.sjw_max = 8,
 513	.brp_min = 1,
 514	.brp_max = 256,
 515	.brp_inc = 1,
 516};
 517
 518static const struct can_bittiming_const rcar_canfd_gen4_data_bittiming_const = {
 519	.name = RCANFD_DRV_NAME,
 520	.tseg1_min = 2,
 521	.tseg1_max = 32,
 522	.tseg2_min = 2,
 523	.tseg2_max = 16,
 524	.sjw_max = 16,
 525	.brp_min = 1,
 526	.brp_max = 256,
 527	.brp_inc = 1,
 528};
 529
 530/* Classical CAN mode bitrate constants */
 531static const struct can_bittiming_const rcar_canfd_bittiming_const = {
 532	.name = RCANFD_DRV_NAME,
 533	.tseg1_min = 4,
 534	.tseg1_max = 16,
 535	.tseg2_min = 2,
 536	.tseg2_max = 8,
 537	.sjw_max = 4,
 538	.brp_min = 1,
 539	.brp_max = 1024,
 540	.brp_inc = 1,
 541};
 542
 543/* CAN FD Transmission Delay Compensation constants */
 544static const struct can_tdc_const rcar_canfd_gen3_tdc_const = {
 545	.tdcv_min = 1,
 546	.tdcv_max = 128,
 547	.tdco_min = 1,
 548	.tdco_max = 128,
 549	.tdcf_min = 0,	/* Filter window not supported */
 550	.tdcf_max = 0,
 551};
 552
 553static const struct can_tdc_const rcar_canfd_gen4_tdc_const = {
 554	.tdcv_min = 1,
 555	.tdcv_max = 256,
 556	.tdco_min = 1,
 557	.tdco_max = 256,
 558	.tdcf_min = 0,	/* Filter window not supported */
 559	.tdcf_max = 0,
 560};
 561
 562static const struct rcar_canfd_regs rcar_gen3_regs = {
 563	.rfcc = 0x00b8,
 564	.cfcc = 0x0118,
 565	.cfsts = 0x0178,
 566	.cfpctr = 0x01d8,
 567	.coffset = 0x0500,
 568	.rfoffset = 0x3000,
 569	.cfoffset = 0x3400,
 570};
 571
 572static const struct rcar_canfd_regs rcar_gen4_regs = {
 573	.rfcc = 0x00c0,
 574	.cfcc = 0x0120,
 575	.cfsts = 0x01e0,
 576	.cfpctr = 0x0240,
 577	.coffset = 0x1400,
 578	.rfoffset = 0x6000,
 579	.cfoffset = 0x6400,
 580};
 581
 582static const struct rcar_canfd_shift_data rcar_gen3_shift_data = {
 583	.ntseg2 = 24,
 584	.ntseg1 = 16,
 585	.nsjw = 11,
 586	.dtseg2 = 20,
 587	.dtseg1 = 16,
 588	.cftml = 20,
 589	.cfm = 16,
 590	.cfdc = 8,
 591};
 592
 593static const struct rcar_canfd_shift_data rcar_gen4_shift_data = {
 594	.ntseg2 = 25,
 595	.ntseg1 = 17,
 596	.nsjw = 10,
 597	.dtseg2 = 16,
 598	.dtseg1 = 8,
 599	.cftml = 16,
 600	.cfm = 8,
 601	.cfdc = 21,
 602};
 603
 604static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
 605	.nom_bittiming = &rcar_canfd_gen3_nom_bittiming_const,
 606	.data_bittiming = &rcar_canfd_gen3_data_bittiming_const,
 607	.tdc_const = &rcar_canfd_gen3_tdc_const,
 608	.regs = &rcar_gen3_regs,
 609	.sh = &rcar_gen3_shift_data,
 610	.rnc_field_width = 8,
 611	.max_aflpn = 31,
 612	.max_cftml = 15,
 613	.max_channels = 2,
 614	.postdiv = 2,
 615	.shared_global_irqs = 1,
 616	.ch_interface_mode = 0,
 617	.shared_can_regs = 0,
 618	.external_clk = 1,
 619};
 620
 621static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
 622	.nom_bittiming = &rcar_canfd_gen4_nom_bittiming_const,
 623	.data_bittiming = &rcar_canfd_gen4_data_bittiming_const,
 624	.tdc_const = &rcar_canfd_gen4_tdc_const,
 625	.regs = &rcar_gen4_regs,
 626	.sh = &rcar_gen4_shift_data,
 627	.rnc_field_width = 16,
 628	.max_aflpn = 127,
 629	.max_cftml = 31,
 630	.max_channels = 8,
 631	.postdiv = 2,
 632	.shared_global_irqs = 1,
 633	.ch_interface_mode = 1,
 634	.shared_can_regs = 1,
 635	.external_clk = 1,
 636};
 637
 638static const struct rcar_canfd_hw_info rzg2l_hw_info = {
 639	.nom_bittiming = &rcar_canfd_gen3_nom_bittiming_const,
 640	.data_bittiming = &rcar_canfd_gen3_data_bittiming_const,
 641	.tdc_const = &rcar_canfd_gen3_tdc_const,
 642	.regs = &rcar_gen3_regs,
 643	.sh = &rcar_gen3_shift_data,
 644	.rnc_field_width = 8,
 645	.max_aflpn = 31,
 646	.max_cftml = 15,
 647	.max_channels = 2,
 648	.postdiv = 1,
 649	.multi_channel_irqs = 1,
 650	.ch_interface_mode = 0,
 651	.shared_can_regs = 0,
 652	.external_clk = 1,
 653};
 654
 655static const struct rcar_canfd_hw_info r9a09g047_hw_info = {
 656	.nom_bittiming = &rcar_canfd_gen4_nom_bittiming_const,
 657	.data_bittiming = &rcar_canfd_gen4_data_bittiming_const,
 658	.tdc_const = &rcar_canfd_gen4_tdc_const,
 659	.regs = &rcar_gen4_regs,
 660	.sh = &rcar_gen4_shift_data,
 661	.rnc_field_width = 16,
 662	.max_aflpn = 63,
 663	.max_cftml = 31,
 664	.max_channels = 6,
 665	.postdiv = 1,
 666	.multi_channel_irqs = 1,
 667	.ch_interface_mode = 1,
 668	.shared_can_regs = 1,
 669	.external_clk = 0,
 670};
 671
 672/* Helper functions */
 673static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
 674{
 675	u32 data = readl(reg);
 676
 677	data &= ~mask;
 678	data |= (val & mask);
 679	writel(data, reg);
 680}
 681
 682static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
 683{
 684	return readl(base + offset);
 685}
 686
 687static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
 688{
 689	writel(val, base + offset);
 690}
 691
 692static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
 693{
 694	rcar_canfd_update(val, val, base + reg);
 695}
 696
 697static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
 698{
 699	rcar_canfd_update(val, 0, base + reg);
 700}
 701
 702static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
 703				  u32 mask, u32 val)
 704{
 705	rcar_canfd_update(mask, val, base + reg);
 706}
 707
 708static void rcar_canfd_set_bit_reg(void __iomem *addr, u32 val)
 709{
 710	rcar_canfd_update(val, val, addr);
 711}
 712
 713static void rcar_canfd_clear_bit_reg(void __iomem *addr, u32 val)
 714{
 715	rcar_canfd_update(val, 0, addr);
 716}
 717
 718static void rcar_canfd_update_bit_reg(void __iomem *addr, u32 mask, u32 val)
 719{
 720	rcar_canfd_update(mask, val, addr);
 721}
 722
 723static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
 724				struct canfd_frame *cf, u32 off)
 725{
 726	u32 *data = (u32 *)cf->data;
 727	u32 i, lwords;
 728
 729	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 730	for (i = 0; i < lwords; i++)
 731		data[i] = rcar_canfd_read(priv->base, off + i * sizeof(u32));
 732}
 733
 734static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
 735				struct canfd_frame *cf, u32 off)
 736{
 737	const u32 *data = (u32 *)cf->data;
 738	u32 i, lwords;
 739
 740	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 741	for (i = 0; i < lwords; i++)
 742		rcar_canfd_write(priv->base, off + i * sizeof(u32), data[i]);
 743}
 744
 745static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
 746{
 747	u32 i;
 748
 749	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
 750		can_free_echo_skb(ndev, i, NULL);
 751}
 752
 753static void rcar_canfd_set_rnc(struct rcar_canfd_global *gpriv, unsigned int ch,
 754			       unsigned int num_rules)
 755{
 756	unsigned int rnc_stride = 32 / gpriv->info->rnc_field_width;
 757	unsigned int shift = 32 - (ch % rnc_stride + 1) * gpriv->info->rnc_field_width;
 758	unsigned int w = ch / rnc_stride;
 759	u32 rnc = num_rules << shift;
 760
 761	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(w), rnc);
 762}
 763
 764static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 765{
 766	struct device *dev = &gpriv->pdev->dev;
 767	u32 sts, ch;
 768	int err;
 769
 770	/* Check RAMINIT flag as CAN RAM initialization takes place
 771	 * after the MCU reset
 772	 */
 773	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 774				 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
 775	if (err) {
 776		dev_dbg(dev, "global raminit failed\n");
 777		return err;
 778	}
 779
 780	/* Transition to Global Reset mode */
 781	rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
 782	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
 783			      RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
 784
 785	/* Ensure Global reset mode */
 786	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 787				 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
 788	if (err) {
 789		dev_dbg(dev, "global reset failed\n");
 790		return err;
 791	}
 792
 793	/* Reset Global error flags */
 794	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 795
 796	/* Set the controller into appropriate mode */
 797	if (!gpriv->info->ch_interface_mode) {
 798		if (gpriv->fdmode)
 799			rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 800					   RCANFD_GRMCFG_RCMC);
 801		else
 802			rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
 803					     RCANFD_GRMCFG_RCMC);
 804	}
 805
 806	/* Transition all Channels to reset mode */
 807	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
 808		rcar_canfd_clear_bit(gpriv->base,
 809				     RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 810
 811		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 812				      RCANFD_CCTR_CHMDC_MASK,
 813				      RCANFD_CCTR_CHDMC_CRESET);
 814
 815		/* Ensure Channel reset mode */
 816		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
 817					 (sts & RCANFD_CSTS_CRSTSTS),
 818					 2, 500000);
 819		if (err) {
 820			dev_dbg(dev, "channel %u reset failed\n", ch);
 821			return err;
 822		}
 823
 824		/* Set the controller into appropriate mode */
 825		if (gpriv->info->ch_interface_mode) {
 826			/* Do not set CLOE and FDOE simultaneously */
 827			if (!gpriv->fdmode) {
 828				rcar_canfd_clear_bit_reg(&gpriv->fcbase[ch].cfdcfg,
 829							 RCANFD_GEN4_FDCFG_FDOE);
 830				rcar_canfd_set_bit_reg(&gpriv->fcbase[ch].cfdcfg,
 831						       RCANFD_GEN4_FDCFG_CLOE);
 832			} else {
 833				rcar_canfd_clear_bit_reg(&gpriv->fcbase[ch].cfdcfg,
 834							 RCANFD_GEN4_FDCFG_FDOE);
 835				rcar_canfd_clear_bit_reg(&gpriv->fcbase[ch].cfdcfg,
 836							 RCANFD_GEN4_FDCFG_CLOE);
 837			}
 838		}
 839	}
 840
 841	return 0;
 842}
 843
 844static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 845{
 846	u32 cfg, ch;
 847
 848	/* Global configuration settings */
 849
 850	/* ECC Error flag Enable */
 851	cfg = RCANFD_GCFG_EEFE;
 852
 853	if (gpriv->fdmode)
 854		/* Truncate payload to configured message size RFPLS */
 855		cfg |= RCANFD_GCFG_CMPOC;
 856
 857	/* Set External Clock if selected */
 858	if (gpriv->extclk)
 859		cfg |= RCANFD_GCFG_DCS;
 860
 861	rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 862
 863	/* Channel configuration settings */
 864	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
 865		rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
 866				   RCANFD_CCTR_ERRD);
 867		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 868				      RCANFD_CCTR_BOM_MASK,
 869				      RCANFD_CCTR_BOM_BENTRY);
 870	}
 871}
 872
 873static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 874					   u32 ch, u32 rule_entry)
 875{
 876	unsigned int offset, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 877	u32 rule_entry_index = rule_entry % 16;
 878	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 879
 880	/* Enable write access to entry */
 881	page = RCANFD_GAFL_PAGENUM(rule_entry);
 882	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 883			   (RCANFD_GAFLECTR_AFLPN(gpriv, page) |
 884			    RCANFD_GAFLECTR_AFLDAE));
 885
 886	/* Write number of rules for channel */
 887	rcar_canfd_set_rnc(gpriv, ch, num_rules);
 888	if (gpriv->info->shared_can_regs)
 889		offset = RCANFD_GEN4_GAFL_OFFSET;
 890	else if (gpriv->fdmode)
 891		offset = RCANFD_F_GAFL_OFFSET;
 892	else
 893		offset = RCANFD_C_GAFL_OFFSET;
 894
 895	/* Accept all IDs */
 896	rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, rule_entry_index), 0);
 897	/* IDE or RTR is not considered for matching */
 898	rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, rule_entry_index), 0);
 899	/* Any data length accepted */
 900	rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, rule_entry_index), 0);
 901	/* Place the msg in corresponding Rx FIFO entry */
 902	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, rule_entry_index),
 903			   RCANFD_GAFLP1_GAFLFDP(ridx));
 904
 905	/* Disable write access to page */
 906	rcar_canfd_clear_bit(gpriv->base,
 907			     RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
 908}
 909
 910static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 911{
 912	/* Rx FIFO is used for reception */
 913	u32 cfg;
 914	u16 rfdc, rfpls;
 915
 916	/* Select Rx FIFO based on channel */
 917	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 918
 919	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
 920	if (gpriv->fdmode)
 921		rfpls = 7;	/* b111 - Max 64 bytes payload */
 922	else
 923		rfpls = 0;	/* b000 - Max 8 bytes payload */
 924
 925	cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 926		RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 927	rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
 928}
 929
 930static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 931{
 932	/* Tx/Rx(Common) FIFO configured in Tx mode is
 933	 * used for transmission
 934	 *
 935	 * Each channel has 3 Common FIFO dedicated to them.
 936	 * Use the 1st (index 0) out of 3
 937	 */
 938	u32 cfg;
 939	u16 cftml, cfm, cfdc, cfpls;
 940
 941	cftml = 0;		/* 0th buffer */
 942	cfm = 1;		/* b01 - Transmit mode */
 943	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
 944	if (gpriv->fdmode)
 945		cfpls = 7;	/* b111 - Max 64 bytes payload */
 946	else
 947		cfpls = 0;	/* b000 - Max 8 bytes payload */
 948
 949	cfg = (RCANFD_CFCC_CFTML(gpriv, cftml) | RCANFD_CFCC_CFM(gpriv, cfm) |
 950		RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(gpriv, cfdc) |
 951		RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
 952	rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
 953
 954	if (gpriv->fdmode)
 955		/* Clear FD mode specific control/status register */
 956		rcar_canfd_write(gpriv->base,
 957				 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 0);
 958}
 959
 960static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 961{
 962	u32 ctr;
 963
 964	/* Clear any stray error interrupt flags */
 965	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 966
 967	/* Global interrupts setup */
 968	ctr = RCANFD_GCTR_MEIE;
 969	if (gpriv->fdmode)
 970		ctr |= RCANFD_GCTR_CFMPOFIE;
 971
 972	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 973}
 974
 975static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
 976						 *gpriv)
 977{
 978	/* Disable all interrupts */
 979	rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
 980
 981	/* Clear any stray error interrupt flags */
 982	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 983}
 984
 985static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
 986						 *priv)
 987{
 988	u32 ctr, ch = priv->channel;
 989
 990	/* Clear any stray error flags */
 991	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 992
 993	/* Channel interrupts setup */
 994	ctr = (RCANFD_CCTR_TAIE |
 995	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 996	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 997	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 998	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 999	rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
1000}
1001
1002static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
1003						  *priv)
1004{
1005	u32 ctr, ch = priv->channel;
1006
1007	ctr = (RCANFD_CCTR_TAIE |
1008	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
1009	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
1010	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
1011	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
1012	rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
1013
1014	/* Clear any stray error flags */
1015	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
1016}
1017
1018static void rcar_canfd_global_error(struct net_device *ndev)
1019{
1020	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1021	struct rcar_canfd_global *gpriv = priv->gpriv;
1022	struct net_device_stats *stats = &ndev->stats;
1023	u32 ch = priv->channel;
1024	u32 gerfl, sts;
1025	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1026
1027	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1028	if (gerfl & FIELD_PREP(RCANFD_GERFL_EEF, BIT(ch))) {
1029		netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch);
1030		stats->tx_dropped++;
1031	}
1032	if (gerfl & RCANFD_GERFL_MES) {
1033		sts = rcar_canfd_read(priv->base,
1034				      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1035		if (sts & RCANFD_CFSTS_CFMLT) {
1036			netdev_dbg(ndev, "Tx Message Lost flag\n");
1037			stats->tx_dropped++;
1038			rcar_canfd_write(priv->base,
1039					 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1040					 sts & ~RCANFD_CFSTS_CFMLT);
1041		}
1042
1043		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1044		if (sts & RCANFD_RFSTS_RFMLT) {
1045			netdev_dbg(ndev, "Rx Message Lost flag\n");
1046			stats->rx_dropped++;
1047			rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1048					 sts & ~RCANFD_RFSTS_RFMLT);
1049		}
1050	}
1051	if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
1052		/* Message Lost flag will be set for respective channel
1053		 * when this condition happens with counters and flags
1054		 * already updated.
1055		 */
1056		netdev_dbg(ndev, "global payload overflow interrupt\n");
1057	}
1058
1059	/* Clear all global error interrupts. Only affected channels bits
1060	 * get cleared
1061	 */
1062	rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
1063}
1064
1065static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
1066			     u16 txerr, u16 rxerr)
1067{
1068	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1069	struct net_device_stats *stats = &ndev->stats;
1070	struct can_frame *cf;
1071	struct sk_buff *skb;
1072	u32 ch = priv->channel;
1073
1074	netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
1075
1076	/* Propagate the error condition to the CAN stack */
1077	skb = alloc_can_err_skb(ndev, &cf);
1078	if (!skb) {
1079		stats->rx_dropped++;
1080		return;
1081	}
1082
1083	/* Channel error interrupts */
1084	if (cerfl & RCANFD_CERFL_BEF) {
1085		netdev_dbg(ndev, "Bus error\n");
1086		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1087		cf->data[2] = CAN_ERR_PROT_UNSPEC;
1088		priv->can.can_stats.bus_error++;
1089	}
1090	if (cerfl & RCANFD_CERFL_ADERR) {
1091		netdev_dbg(ndev, "ACK Delimiter Error\n");
1092		stats->tx_errors++;
1093		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1094	}
1095	if (cerfl & RCANFD_CERFL_B0ERR) {
1096		netdev_dbg(ndev, "Bit Error (dominant)\n");
1097		stats->tx_errors++;
1098		cf->data[2] |= CAN_ERR_PROT_BIT0;
1099	}
1100	if (cerfl & RCANFD_CERFL_B1ERR) {
1101		netdev_dbg(ndev, "Bit Error (recessive)\n");
1102		stats->tx_errors++;
1103		cf->data[2] |= CAN_ERR_PROT_BIT1;
1104	}
1105	if (cerfl & RCANFD_CERFL_CERR) {
1106		netdev_dbg(ndev, "CRC Error\n");
1107		stats->rx_errors++;
1108		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1109	}
1110	if (cerfl & RCANFD_CERFL_AERR) {
1111		netdev_dbg(ndev, "ACK Error\n");
1112		stats->tx_errors++;
1113		cf->can_id |= CAN_ERR_ACK;
1114		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1115	}
1116	if (cerfl & RCANFD_CERFL_FERR) {
1117		netdev_dbg(ndev, "Form Error\n");
1118		stats->rx_errors++;
1119		cf->data[2] |= CAN_ERR_PROT_FORM;
1120	}
1121	if (cerfl & RCANFD_CERFL_SERR) {
1122		netdev_dbg(ndev, "Stuff Error\n");
1123		stats->rx_errors++;
1124		cf->data[2] |= CAN_ERR_PROT_STUFF;
1125	}
1126	if (cerfl & RCANFD_CERFL_ALF) {
1127		netdev_dbg(ndev, "Arbitration lost Error\n");
1128		priv->can.can_stats.arbitration_lost++;
1129		cf->can_id |= CAN_ERR_LOSTARB;
1130		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1131	}
1132	if (cerfl & RCANFD_CERFL_BLF) {
1133		netdev_dbg(ndev, "Bus Lock Error\n");
1134		stats->rx_errors++;
1135		cf->can_id |= CAN_ERR_BUSERROR;
1136	}
1137	if (cerfl & RCANFD_CERFL_EWF) {
1138		netdev_dbg(ndev, "Error warning interrupt\n");
1139		priv->can.state = CAN_STATE_ERROR_WARNING;
1140		priv->can.can_stats.error_warning++;
1141		cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1142		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1143			CAN_ERR_CRTL_RX_WARNING;
1144		cf->data[6] = txerr;
1145		cf->data[7] = rxerr;
1146	}
1147	if (cerfl & RCANFD_CERFL_EPF) {
1148		netdev_dbg(ndev, "Error passive interrupt\n");
1149		priv->can.state = CAN_STATE_ERROR_PASSIVE;
1150		priv->can.can_stats.error_passive++;
1151		cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1152		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1153			CAN_ERR_CRTL_RX_PASSIVE;
1154		cf->data[6] = txerr;
1155		cf->data[7] = rxerr;
1156	}
1157	if (cerfl & RCANFD_CERFL_BOEF) {
1158		netdev_dbg(ndev, "Bus-off entry interrupt\n");
1159		rcar_canfd_tx_failure_cleanup(ndev);
1160		priv->can.state = CAN_STATE_BUS_OFF;
1161		priv->can.can_stats.bus_off++;
1162		can_bus_off(ndev);
1163		cf->can_id |= CAN_ERR_BUSOFF;
1164	}
1165	if (cerfl & RCANFD_CERFL_OVLF) {
1166		netdev_dbg(ndev,
1167			   "Overload Frame Transmission error interrupt\n");
1168		stats->tx_errors++;
1169		cf->can_id |= CAN_ERR_PROT;
1170		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1171	}
1172
1173	/* Clear channel error interrupts that are handled */
1174	rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1175			 RCANFD_CERFL_ERR(~cerfl));
1176	netif_rx(skb);
1177}
1178
1179static void rcar_canfd_tx_done(struct net_device *ndev)
1180{
1181	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1182	struct rcar_canfd_global *gpriv = priv->gpriv;
1183	struct net_device_stats *stats = &ndev->stats;
1184	u32 sts;
1185	unsigned long flags;
1186	u32 ch = priv->channel;
1187
1188	do {
1189		u8 unsent, sent;
1190
1191		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1192		stats->tx_packets++;
1193		stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
1194
1195		spin_lock_irqsave(&priv->tx_lock, flags);
1196		priv->tx_tail++;
1197		sts = rcar_canfd_read(priv->base,
1198				      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1199		unsent = RCANFD_CFSTS_CFMC(sts);
1200
1201		/* Wake producer only when there is room */
1202		if (unsent != RCANFD_FIFO_DEPTH)
1203			netif_wake_queue(ndev);
1204
1205		if (priv->tx_head - priv->tx_tail <= unsent) {
1206			spin_unlock_irqrestore(&priv->tx_lock, flags);
1207			break;
1208		}
1209		spin_unlock_irqrestore(&priv->tx_lock, flags);
1210
1211	} while (1);
1212
1213	/* Clear interrupt */
1214	rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1215			 sts & ~RCANFD_CFSTS_CFTXIF);
1216}
1217
1218static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1219{
1220	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1221	struct net_device *ndev = priv->ndev;
1222	u32 gerfl;
1223
1224	/* Handle global error interrupts */
1225	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1226	if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1227		rcar_canfd_global_error(ndev);
1228}
1229
1230static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1231{
1232	struct rcar_canfd_global *gpriv = dev_id;
1233	u32 ch;
1234
1235	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1236		rcar_canfd_handle_global_err(gpriv, ch);
1237
1238	return IRQ_HANDLED;
1239}
1240
1241static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1242{
1243	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1244	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1245	u32 sts, cc;
1246
1247	/* Handle Rx interrupts */
1248	sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1249	cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx));
1250	if (likely(sts & RCANFD_RFSTS_RFIF &&
1251		   cc & RCANFD_RFCC_RFIE)) {
1252		if (napi_schedule_prep(&priv->napi)) {
1253			/* Disable Rx FIFO interrupts */
1254			rcar_canfd_clear_bit(priv->base,
1255					     RCANFD_RFCC(gpriv, ridx),
1256					     RCANFD_RFCC_RFIE);
1257			__napi_schedule(&priv->napi);
1258		}
1259	}
1260}
1261
1262static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1263{
1264	struct rcar_canfd_global *gpriv = dev_id;
1265	u32 ch;
1266
1267	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1268		rcar_canfd_handle_global_receive(gpriv, ch);
1269
1270	return IRQ_HANDLED;
1271}
1272
1273static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1274{
1275	struct rcar_canfd_global *gpriv = dev_id;
1276	u32 ch;
1277
1278	/* Global error interrupts still indicate a condition specific
1279	 * to a channel. RxFIFO interrupt is a global interrupt.
1280	 */
1281	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1282		rcar_canfd_handle_global_err(gpriv, ch);
1283		rcar_canfd_handle_global_receive(gpriv, ch);
1284	}
1285	return IRQ_HANDLED;
1286}
1287
1288static void rcar_canfd_state_change(struct net_device *ndev,
1289				    u16 txerr, u16 rxerr)
1290{
1291	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1292	struct net_device_stats *stats = &ndev->stats;
1293	enum can_state rx_state, tx_state, state = priv->can.state;
1294	struct can_frame *cf;
1295	struct sk_buff *skb;
1296
1297	/* Handle transition from error to normal states */
1298	if (txerr < 96 && rxerr < 96)
1299		state = CAN_STATE_ERROR_ACTIVE;
1300	else if (txerr < 128 && rxerr < 128)
1301		state = CAN_STATE_ERROR_WARNING;
1302
1303	if (state != priv->can.state) {
1304		netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1305			   state, priv->can.state, txerr, rxerr);
1306		skb = alloc_can_err_skb(ndev, &cf);
1307		if (!skb) {
1308			stats->rx_dropped++;
1309			return;
1310		}
1311		tx_state = txerr >= rxerr ? state : 0;
1312		rx_state = txerr <= rxerr ? state : 0;
1313
1314		can_change_state(ndev, cf, tx_state, rx_state);
1315		netif_rx(skb);
1316	}
1317}
1318
1319static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1320{
1321	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1322	struct net_device *ndev = priv->ndev;
1323	u32 sts;
1324
1325	/* Handle Tx interrupts */
1326	sts = rcar_canfd_read(priv->base,
1327			      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1328	if (likely(sts & RCANFD_CFSTS_CFTXIF))
1329		rcar_canfd_tx_done(ndev);
1330}
1331
1332static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1333{
1334	struct rcar_canfd_channel *priv = dev_id;
1335
1336	rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1337
1338	return IRQ_HANDLED;
1339}
1340
1341static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1342{
1343	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1344	struct net_device *ndev = priv->ndev;
1345	u16 txerr, rxerr;
1346	u32 sts, cerfl;
1347
1348	/* Handle channel error interrupts */
1349	cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1350	sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1351	txerr = RCANFD_CSTS_TECCNT(sts);
1352	rxerr = RCANFD_CSTS_RECCNT(sts);
1353	if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1354		rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1355
1356	/* Handle state change to lower states */
1357	if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1358		     priv->can.state != CAN_STATE_BUS_OFF))
1359		rcar_canfd_state_change(ndev, txerr, rxerr);
1360}
1361
1362static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1363{
1364	struct rcar_canfd_channel *priv = dev_id;
1365
1366	rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1367
1368	return IRQ_HANDLED;
1369}
1370
1371static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1372{
1373	struct rcar_canfd_global *gpriv = dev_id;
1374	u32 ch;
1375
1376	/* Common FIFO is a per channel resource */
1377	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1378		rcar_canfd_handle_channel_err(gpriv, ch);
1379		rcar_canfd_handle_channel_tx(gpriv, ch);
1380	}
1381
1382	return IRQ_HANDLED;
1383}
1384
1385static inline u32 rcar_canfd_compute_nominal_bit_rate_cfg(struct rcar_canfd_channel *priv,
1386							  u16 tseg1, u16 tseg2, u16 sjw, u16 brp)
1387{
1388	struct rcar_canfd_global *gpriv = priv->gpriv;
1389	const struct rcar_canfd_hw_info *info = gpriv->info;
1390	u32 ntseg1, ntseg2, nsjw, nbrp;
1391
1392	if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) {
1393		ntseg1 = (tseg1 & (info->nom_bittiming->tseg1_max - 1)) << info->sh->ntseg1;
1394		ntseg2 = (tseg2 & (info->nom_bittiming->tseg2_max - 1)) << info->sh->ntseg2;
1395		nsjw = (sjw & (info->nom_bittiming->sjw_max - 1)) << info->sh->nsjw;
1396		nbrp = FIELD_PREP(RCANFD_NCFG_NBRP, brp);
1397	} else {
1398		ntseg1 = FIELD_PREP(RCANFD_CFG_TSEG1, tseg1);
1399		ntseg2 = FIELD_PREP(RCANFD_CFG_TSEG2, tseg2);
1400		nsjw = FIELD_PREP(RCANFD_CFG_SJW, sjw);
1401		nbrp = FIELD_PREP(RCANFD_CFG_BRP, brp);
1402	}
1403
1404	return (ntseg1 | ntseg2 | nsjw | nbrp);
1405}
1406
1407static inline u32 rcar_canfd_compute_data_bit_rate_cfg(const struct rcar_canfd_hw_info *info,
1408						       u16 tseg1, u16 tseg2, u16 sjw, u16 brp)
1409{
1410	u32 dtseg1, dtseg2, dsjw, dbrp;
1411
1412	dtseg1 = (tseg1 & (info->data_bittiming->tseg1_max - 1)) << info->sh->dtseg1;
1413	dtseg2 = (tseg2 & (info->data_bittiming->tseg2_max - 1)) << info->sh->dtseg2;
1414	dsjw = (sjw & (info->data_bittiming->sjw_max - 1)) << 24;
1415	dbrp = FIELD_PREP(RCANFD_DCFG_DBRP, brp);
1416
1417	return (dtseg1 | dtseg2 | dsjw | dbrp);
1418}
1419
1420static void rcar_canfd_set_bittiming(struct net_device *ndev)
1421{
1422	u32 mask = RCANFD_FDCFG_TDCO | RCANFD_FDCFG_TDCE | RCANFD_FDCFG_TDCOC;
1423	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1424	struct rcar_canfd_global *gpriv = priv->gpriv;
1425	const struct can_bittiming *bt = &priv->can.bittiming;
1426	const struct can_bittiming *dbt = &priv->can.fd.data_bittiming;
1427	const struct can_tdc_const *tdc_const = priv->can.fd.tdc_const;
1428	const struct can_tdc *tdc = &priv->can.fd.tdc;
1429	u32 cfg, tdcmode = 0, tdco = 0;
1430	u16 brp, sjw, tseg1, tseg2;
1431	u32 ch = priv->channel;
1432
1433	/* Nominal bit timing settings */
1434	brp = bt->brp - 1;
1435	sjw = bt->sjw - 1;
1436	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1437	tseg2 = bt->phase_seg2 - 1;
1438	cfg = rcar_canfd_compute_nominal_bit_rate_cfg(priv, tseg1, tseg2, sjw, brp);
1439	rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1440
1441	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
1442		return;
1443
1444	/* Data bit timing settings */
1445	brp = dbt->brp - 1;
1446	sjw = dbt->sjw - 1;
1447	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1448	tseg2 = dbt->phase_seg2 - 1;
1449	cfg = rcar_canfd_compute_data_bit_rate_cfg(gpriv->info, tseg1, tseg2, sjw, brp);
1450	writel(cfg, &gpriv->fcbase[ch].dcfg);
1451
1452	/* Transceiver Delay Compensation */
1453	if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_AUTO) {
1454		/* TDC enabled, measured + offset */
1455		tdcmode = RCANFD_FDCFG_TDCE;
1456		tdco = tdc->tdco - 1;
1457	} else if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_MANUAL) {
1458		/* TDC enabled, offset only */
1459		tdcmode = RCANFD_FDCFG_TDCE | RCANFD_FDCFG_TDCOC;
1460		tdco = min(tdc->tdcv + tdc->tdco, tdc_const->tdco_max) - 1;
1461	}
1462
1463	rcar_canfd_update_bit_reg(&gpriv->fcbase[ch].cfdcfg, mask,
1464				  tdcmode | FIELD_PREP(RCANFD_FDCFG_TDCO, tdco));
1465}
1466
1467static int rcar_canfd_start(struct net_device *ndev)
1468{
1469	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1470	struct rcar_canfd_global *gpriv = priv->gpriv;
1471	int err = -EOPNOTSUPP;
1472	u32 sts, ch = priv->channel;
1473	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1474
1475	rcar_canfd_set_bittiming(ndev);
1476
1477	rcar_canfd_enable_channel_interrupts(priv);
1478
1479	/* Set channel to Operational mode */
1480	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1481			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1482
1483	/* Verify channel mode change */
1484	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1485				 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1486	if (err) {
1487		netdev_err(ndev, "channel %u communication state failed\n", ch);
1488		goto fail_mode_change;
1489	}
1490
1491	/* Enable Common & Rx FIFO */
1492	rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1493			   RCANFD_CFCC_CFE);
1494	rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1495
1496	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1497	return 0;
1498
1499fail_mode_change:
1500	rcar_canfd_disable_channel_interrupts(priv);
1501	return err;
1502}
1503
1504static int rcar_canfd_open(struct net_device *ndev)
1505{
1506	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1507	struct rcar_canfd_global *gpriv = priv->gpriv;
1508	int err;
1509
1510	err = phy_power_on(priv->transceiver);
1511	if (err) {
1512		netdev_err(ndev, "failed to power on PHY: %pe\n", ERR_PTR(err));
1513		return err;
1514	}
1515
1516	/* Peripheral clock is already enabled in probe */
1517	err = clk_prepare_enable(gpriv->can_clk);
1518	if (err) {
1519		netdev_err(ndev, "failed to enable CAN clock: %pe\n", ERR_PTR(err));
1520		goto out_phy;
1521	}
1522
1523	err = open_candev(ndev);
1524	if (err) {
1525		netdev_err(ndev, "open_candev() failed: %pe\n", ERR_PTR(err));
1526		goto out_can_clock;
1527	}
1528
1529	napi_enable(&priv->napi);
1530	err = rcar_canfd_start(ndev);
1531	if (err)
1532		goto out_close;
1533	netif_start_queue(ndev);
1534	return 0;
1535out_close:
1536	napi_disable(&priv->napi);
1537	close_candev(ndev);
1538out_can_clock:
1539	clk_disable_unprepare(gpriv->can_clk);
1540out_phy:
1541	phy_power_off(priv->transceiver);
1542	return err;
1543}
1544
1545static void rcar_canfd_stop(struct net_device *ndev)
1546{
1547	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1548	struct rcar_canfd_global *gpriv = priv->gpriv;
1549	int err;
1550	u32 sts, ch = priv->channel;
1551	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1552
1553	/* Transition to channel reset mode  */
1554	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1555			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1556
1557	/* Check Channel reset mode */
1558	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1559				 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1560	if (err)
1561		netdev_err(ndev, "channel %u reset failed\n", ch);
1562
1563	rcar_canfd_disable_channel_interrupts(priv);
1564
1565	/* Disable Common & Rx FIFO */
1566	rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1567			     RCANFD_CFCC_CFE);
1568	rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1569
1570	/* Set the state as STOPPED */
1571	priv->can.state = CAN_STATE_STOPPED;
1572}
1573
1574static int rcar_canfd_close(struct net_device *ndev)
1575{
1576	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1577	struct rcar_canfd_global *gpriv = priv->gpriv;
1578
1579	netif_stop_queue(ndev);
1580	rcar_canfd_stop(ndev);
1581	napi_disable(&priv->napi);
1582	close_candev(ndev);
1583	clk_disable_unprepare(gpriv->can_clk);
1584	phy_power_off(priv->transceiver);
1585	return 0;
1586}
1587
1588static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1589					 struct net_device *ndev)
1590{
1591	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1592	struct rcar_canfd_global *gpriv = priv->gpriv;
1593	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1594	u32 sts = 0, id, dlc;
1595	unsigned long flags;
1596	u32 ch = priv->channel;
1597
1598	if (can_dev_dropped_skb(ndev, skb))
1599		return NETDEV_TX_OK;
1600
1601	if (cf->can_id & CAN_EFF_FLAG) {
1602		id = cf->can_id & CAN_EFF_MASK;
1603		id |= RCANFD_CFID_CFIDE;
1604	} else {
1605		id = cf->can_id & CAN_SFF_MASK;
1606	}
1607
1608	if (cf->can_id & CAN_RTR_FLAG)
1609		id |= RCANFD_CFID_CFRTR;
1610
1611	dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1612
1613	if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) {
1614		rcar_canfd_write(priv->base,
1615				 RCANFD_F_CFID(gpriv, ch, RCANFD_CFFIFO_IDX), id);
1616		rcar_canfd_write(priv->base,
1617				 RCANFD_F_CFPTR(gpriv, ch, RCANFD_CFFIFO_IDX), dlc);
1618
1619		if (can_is_canfd_skb(skb)) {
1620			/* CAN FD frame format */
1621			sts |= RCANFD_CFFDCSTS_CFFDF;
1622			if (cf->flags & CANFD_BRS)
1623				sts |= RCANFD_CFFDCSTS_CFBRS;
1624
1625			if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1626				sts |= RCANFD_CFFDCSTS_CFESI;
1627		}
1628
1629		rcar_canfd_write(priv->base,
1630				 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), sts);
1631
1632		rcar_canfd_put_data(priv, cf,
1633				    RCANFD_F_CFDF(gpriv, ch, RCANFD_CFFIFO_IDX, 0));
1634	} else {
1635		rcar_canfd_write(priv->base,
1636				 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1637		rcar_canfd_write(priv->base,
1638				 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1639		rcar_canfd_put_data(priv, cf,
1640				    RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1641	}
1642
1643	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1644
1645	spin_lock_irqsave(&priv->tx_lock, flags);
1646	priv->tx_head++;
1647
1648	/* Stop the queue if we've filled all FIFO entries */
1649	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1650		netif_stop_queue(ndev);
1651
1652	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
1653	 * pointer for the Common FIFO
1654	 */
1655	rcar_canfd_write(priv->base,
1656			 RCANFD_CFPCTR(gpriv, ch, RCANFD_CFFIFO_IDX), 0xff);
1657
1658	spin_unlock_irqrestore(&priv->tx_lock, flags);
1659	return NETDEV_TX_OK;
1660}
1661
1662static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1663{
1664	struct net_device *ndev = priv->ndev;
1665	struct net_device_stats *stats = &ndev->stats;
1666	struct rcar_canfd_global *gpriv = priv->gpriv;
1667	struct canfd_frame *cf;
1668	struct sk_buff *skb;
1669	u32 sts = 0, id, dlc;
1670	u32 ch = priv->channel;
1671	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1672
1673	if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) {
1674		id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1675		dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1676
1677		sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1678
1679		if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1680		    sts & RCANFD_RFFDSTS_RFFDF)
1681			skb = alloc_canfd_skb(ndev, &cf);
1682		else
1683			skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
1684	} else {
1685		id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1686		dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1687		skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
1688	}
1689
1690	if (!skb) {
1691		stats->rx_dropped++;
1692		return;
1693	}
1694
1695	if (id & RCANFD_RFID_RFIDE)
1696		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1697	else
1698		cf->can_id = id & CAN_SFF_MASK;
1699
1700	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1701		if (sts & RCANFD_RFFDSTS_RFFDF)
1702			cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1703		else
1704			cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1705
1706		if (sts & RCANFD_RFFDSTS_RFESI) {
1707			cf->flags |= CANFD_ESI;
1708			netdev_dbg(ndev, "ESI Error\n");
1709		}
1710
1711		if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1712			cf->can_id |= CAN_RTR_FLAG;
1713		} else {
1714			if (sts & RCANFD_RFFDSTS_RFBRS)
1715				cf->flags |= CANFD_BRS;
1716
1717			rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1718		}
1719	} else {
1720		cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1721		if (id & RCANFD_RFID_RFRTR)
1722			cf->can_id |= CAN_RTR_FLAG;
1723		else if (gpriv->info->shared_can_regs)
1724			rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1725		else
1726			rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1727	}
1728
1729	/* Write 0xff to RFPC to increment the CPU-side
1730	 * pointer of the Rx FIFO
1731	 */
1732	rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
1733
1734	if (!(cf->can_id & CAN_RTR_FLAG))
1735		stats->rx_bytes += cf->len;
1736	stats->rx_packets++;
1737	netif_receive_skb(skb);
1738}
1739
1740static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1741{
1742	struct rcar_canfd_channel *priv =
1743		container_of(napi, struct rcar_canfd_channel, napi);
1744	struct rcar_canfd_global *gpriv = priv->gpriv;
1745	int num_pkts;
1746	u32 sts;
1747	u32 ch = priv->channel;
1748	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1749
1750	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1751		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1752		/* Check FIFO empty condition */
1753		if (sts & RCANFD_RFSTS_RFEMP)
1754			break;
1755
1756		rcar_canfd_rx_pkt(priv);
1757
1758		/* Clear interrupt bit */
1759		if (sts & RCANFD_RFSTS_RFIF)
1760			rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1761					 sts & ~RCANFD_RFSTS_RFIF);
1762	}
1763
1764	/* All packets processed */
1765	if (num_pkts < quota) {
1766		if (napi_complete_done(napi, num_pkts)) {
1767			/* Enable Rx FIFO interrupts */
1768			rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1769					   RCANFD_RFCC_RFIE);
1770		}
1771	}
1772	return num_pkts;
1773}
1774
1775static unsigned int rcar_canfd_get_tdcr(struct rcar_canfd_global *gpriv,
1776					unsigned int ch)
1777{
1778	u32 sts = readl(&gpriv->fcbase[ch].cfdsts);
1779	u32 tdcr = FIELD_GET(RCANFD_FDSTS_TDCR, sts);
1780
1781	return tdcr & (gpriv->info->tdc_const->tdcv_max - 1);
1782}
1783
1784static int rcar_canfd_get_auto_tdcv(const struct net_device *ndev, u32 *tdcv)
1785{
1786	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1787	u32 tdco = priv->can.fd.tdc.tdco;
1788	u32 tdcr;
1789
1790	/* Transceiver Delay Compensation Result */
1791	tdcr = rcar_canfd_get_tdcr(priv->gpriv, priv->channel) + 1;
1792
1793	*tdcv = tdcr < tdco ? 0 : tdcr - tdco;
1794
1795	return 0;
1796}
1797
1798static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1799{
1800	int err;
1801
1802	switch (mode) {
1803	case CAN_MODE_START:
1804		err = rcar_canfd_start(ndev);
1805		if (err)
1806			return err;
1807		netif_wake_queue(ndev);
1808		return 0;
1809	default:
1810		return -EOPNOTSUPP;
1811	}
1812}
1813
1814static int rcar_canfd_get_berr_counter(const struct net_device *ndev,
1815				       struct can_berr_counter *bec)
1816{
1817	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1818	u32 val, ch = priv->channel;
1819
1820	/* Peripheral clock is already enabled in probe */
1821	val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1822	bec->txerr = RCANFD_CSTS_TECCNT(val);
1823	bec->rxerr = RCANFD_CSTS_RECCNT(val);
1824	return 0;
1825}
1826
1827static const struct net_device_ops rcar_canfd_netdev_ops = {
1828	.ndo_open = rcar_canfd_open,
1829	.ndo_stop = rcar_canfd_close,
1830	.ndo_start_xmit = rcar_canfd_start_xmit,
1831};
1832
1833static const struct ethtool_ops rcar_canfd_ethtool_ops = {
1834	.get_ts_info = ethtool_op_get_ts_info,
1835};
1836
1837static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1838				    u32 fcan_freq, struct phy *transceiver)
1839{
1840	const struct rcar_canfd_hw_info *info = gpriv->info;
1841	struct platform_device *pdev = gpriv->pdev;
1842	struct device *dev = &pdev->dev;
1843	struct rcar_canfd_channel *priv;
1844	struct net_device *ndev;
1845	int err = -ENODEV;
1846
1847	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1848	if (!ndev)
1849		return -ENOMEM;
1850
1851	priv = netdev_priv(ndev);
1852
1853	ndev->netdev_ops = &rcar_canfd_netdev_ops;
1854	ndev->ethtool_ops = &rcar_canfd_ethtool_ops;
1855	ndev->flags |= IFF_ECHO;
1856	priv->ndev = ndev;
1857	priv->base = gpriv->base;
1858	priv->transceiver = transceiver;
1859	priv->channel = ch;
1860	priv->gpriv = gpriv;
1861	if (transceiver)
1862		priv->can.bitrate_max = transceiver->attrs.max_link_rate;
1863	priv->can.clock.freq = fcan_freq;
1864	dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
1865
1866	if (info->multi_channel_irqs) {
1867		char *irq_name;
1868		char name[10];
1869		int err_irq;
1870		int tx_irq;
1871
1872		scnprintf(name, sizeof(name), "ch%u_err", ch);
1873		err_irq = platform_get_irq_byname(pdev, name);
1874		if (err_irq < 0) {
1875			err = err_irq;
1876			goto fail;
1877		}
1878
1879		scnprintf(name, sizeof(name), "ch%u_trx", ch);
1880		tx_irq = platform_get_irq_byname(pdev, name);
1881		if (tx_irq < 0) {
1882			err = tx_irq;
1883			goto fail;
1884		}
1885
1886		irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_err",
1887					  ch);
1888		if (!irq_name) {
1889			err = -ENOMEM;
1890			goto fail;
1891		}
1892		err = devm_request_irq(dev, err_irq,
1893				       rcar_canfd_channel_err_interrupt, 0,
1894				       irq_name, priv);
1895		if (err) {
1896			dev_err(dev, "devm_request_irq CH Err %d failed: %pe\n",
1897				err_irq, ERR_PTR(err));
1898			goto fail;
1899		}
1900		irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_trx",
1901					  ch);
1902		if (!irq_name) {
1903			err = -ENOMEM;
1904			goto fail;
1905		}
1906		err = devm_request_irq(dev, tx_irq,
1907				       rcar_canfd_channel_tx_interrupt, 0,
1908				       irq_name, priv);
1909		if (err) {
1910			dev_err(dev, "devm_request_irq Tx %d failed: %pe\n",
1911				tx_irq, ERR_PTR(err));
1912			goto fail;
1913		}
1914	}
1915
1916	if (gpriv->fdmode) {
1917		priv->can.bittiming_const = gpriv->info->nom_bittiming;
1918		priv->can.fd.data_bittiming_const = gpriv->info->data_bittiming;
1919		priv->can.fd.tdc_const = gpriv->info->tdc_const;
1920
1921		/* Controller starts in CAN FD only mode */
1922		err = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1923		if (err)
1924			goto fail;
1925
1926		priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
1927					       CAN_CTRLMODE_TDC_AUTO |
1928					       CAN_CTRLMODE_TDC_MANUAL;
1929		priv->can.fd.do_get_auto_tdcv = rcar_canfd_get_auto_tdcv;
1930	} else {
1931		/* Controller starts in Classical CAN only mode */
1932		if (gpriv->info->shared_can_regs)
1933			priv->can.bittiming_const = gpriv->info->nom_bittiming;
1934		else
1935			priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1936		priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1937	}
1938
1939	priv->can.do_set_mode = rcar_canfd_do_set_mode;
1940	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1941	SET_NETDEV_DEV(ndev, dev);
1942
1943	netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1944			      RCANFD_NAPI_WEIGHT);
1945	spin_lock_init(&priv->tx_lock);
1946	gpriv->ch[priv->channel] = priv;
1947	err = register_candev(ndev);
1948	if (err) {
1949		dev_err(dev, "register_candev() failed: %pe\n", ERR_PTR(err));
1950		goto fail_candev;
1951	}
1952	dev_info(dev, "device registered (channel %u)\n", priv->channel);
1953	return 0;
1954
1955fail_candev:
1956	netif_napi_del(&priv->napi);
1957fail:
1958	free_candev(ndev);
1959	return err;
1960}
1961
1962static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1963{
1964	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1965
1966	if (priv) {
1967		unregister_candev(priv->ndev);
1968		netif_napi_del(&priv->napi);
1969		free_candev(priv->ndev);
1970	}
1971}
1972
1973static int rcar_canfd_global_init(struct rcar_canfd_global *gpriv)
1974{
1975	struct device *dev = &gpriv->pdev->dev;
1976	u32 rule_entry = 0;
1977	u32 ch, sts;
1978	int err;
1979
1980	err = reset_control_reset(gpriv->rstc1);
1981	if (err)
1982		return err;
1983
1984	err = reset_control_reset(gpriv->rstc2);
1985	if (err)
1986		goto fail_reset1;
1987
1988	/* Enable peripheral clock for register access */
1989	err = clk_prepare_enable(gpriv->clkp);
1990	if (err) {
1991		dev_err(dev, "failed to enable peripheral clock: %pe\n",
1992			ERR_PTR(err));
1993		goto fail_reset2;
1994	}
1995
1996	/* Enable RAM clock */
1997	err = clk_prepare_enable(gpriv->clk_ram);
1998	if (err) {
1999		dev_err(dev,
2000			"failed to enable RAM clock, error %d\n", err);
2001		goto fail_clk;
2002	}
2003
2004	err = rcar_canfd_reset_controller(gpriv);
2005	if (err) {
2006		dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err));
2007		goto fail_ram_clk;
2008	}
2009
2010	/* Controller in Global reset & Channel reset mode */
2011	rcar_canfd_configure_controller(gpriv);
2012
2013	/* Configure per channel attributes */
2014	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2015		/* Configure Channel's Rx fifo */
2016		rcar_canfd_configure_rx(gpriv, ch);
2017
2018		/* Configure Channel's Tx (Common) fifo */
2019		rcar_canfd_configure_tx(gpriv, ch);
2020
2021		/* Configure receive rules */
2022		rcar_canfd_configure_afl_rules(gpriv, ch, rule_entry);
2023		rule_entry += RCANFD_CHANNEL_NUMRULES;
2024	}
2025
2026	/* Configure common interrupts */
2027	rcar_canfd_enable_global_interrupts(gpriv);
2028
2029	/* Start Global operation mode */
2030	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2031			      RCANFD_GCTR_GMDC_GOPM);
2032
2033	/* Verify mode change */
2034	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2035				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
2036	if (err) {
2037		dev_err(dev, "global operational mode failed\n");
2038		goto fail_mode;
2039	}
2040
2041	return 0;
2042
2043fail_mode:
2044	rcar_canfd_disable_global_interrupts(gpriv);
2045fail_ram_clk:
2046	clk_disable_unprepare(gpriv->clk_ram);
2047fail_clk:
2048	clk_disable_unprepare(gpriv->clkp);
2049fail_reset2:
2050	reset_control_assert(gpriv->rstc2);
2051fail_reset1:
2052	reset_control_assert(gpriv->rstc1);
2053	return err;
2054}
2055
2056static void rcar_canfd_global_deinit(struct rcar_canfd_global *gpriv, bool full)
2057{
2058	rcar_canfd_disable_global_interrupts(gpriv);
2059
2060	if (full) {
2061		rcar_canfd_reset_controller(gpriv);
2062
2063		/* Enter global sleep mode */
2064		rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2065	}
2066
2067	clk_disable_unprepare(gpriv->clk_ram);
2068	clk_disable_unprepare(gpriv->clkp);
2069	reset_control_assert(gpriv->rstc2);
2070	reset_control_assert(gpriv->rstc1);
2071}
2072
2073static int rcar_canfd_probe(struct platform_device *pdev)
2074{
2075	struct phy *transceivers[RCANFD_NUM_CHANNELS] = { NULL, };
2076	const struct rcar_canfd_hw_info *info;
2077	struct device *dev = &pdev->dev;
2078	void __iomem *addr;
2079	struct rcar_canfd_global *gpriv;
2080	struct device_node *of_child;
2081	unsigned long channels_mask = 0;
2082	int err, ch_irq, g_irq;
2083	int g_err_irq, g_recc_irq;
2084	bool fdmode = true;			/* CAN FD only mode - default */
2085	char name[9] = "channelX";
2086	u32 ch, fcan_freq;
2087	int i;
2088
2089	info = of_device_get_match_data(dev);
2090
2091	if (of_property_read_bool(dev->of_node, "renesas,no-can-fd"))
2092		fdmode = false;			/* Classical CAN only mode */
2093
2094	for (i = 0; i < info->max_channels; ++i) {
2095		name[7] = '0' + i;
2096		of_child = of_get_available_child_by_name(dev->of_node, name);
2097		if (of_child) {
2098			channels_mask |= BIT(i);
2099			transceivers[i] = devm_of_phy_optional_get(dev,
2100							of_child, NULL);
2101			of_node_put(of_child);
2102		}
2103		if (IS_ERR(transceivers[i]))
2104			return PTR_ERR(transceivers[i]);
2105	}
2106
2107	if (info->shared_global_irqs) {
2108		ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
2109		if (ch_irq < 0) {
2110			/* For backward compatibility get irq by index */
2111			ch_irq = platform_get_irq(pdev, 0);
2112			if (ch_irq < 0)
2113				return ch_irq;
2114		}
2115
2116		g_irq = platform_get_irq_byname_optional(pdev, "g_int");
2117		if (g_irq < 0) {
2118			/* For backward compatibility get irq by index */
2119			g_irq = platform_get_irq(pdev, 1);
2120			if (g_irq < 0)
2121				return g_irq;
2122		}
2123	} else {
2124		g_err_irq = platform_get_irq_byname(pdev, "g_err");
2125		if (g_err_irq < 0)
2126			return g_err_irq;
2127
2128		g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
2129		if (g_recc_irq < 0)
2130			return g_recc_irq;
2131	}
2132
2133	/* Global controller context */
2134	gpriv = devm_kzalloc(dev, sizeof(*gpriv), GFP_KERNEL);
2135	if (!gpriv)
2136		return -ENOMEM;
2137
2138	gpriv->pdev = pdev;
2139	gpriv->channels_mask = channels_mask;
2140	gpriv->fdmode = fdmode;
2141	gpriv->info = info;
2142
2143	gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
2144	if (IS_ERR(gpriv->rstc1))
2145		return dev_err_probe(dev, PTR_ERR(gpriv->rstc1),
2146				     "failed to get rstp_n\n");
2147
2148	gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
2149	if (IS_ERR(gpriv->rstc2))
2150		return dev_err_probe(dev, PTR_ERR(gpriv->rstc2),
2151				     "failed to get rstc_n\n");
2152
2153	/* Peripheral clock */
2154	gpriv->clkp = devm_clk_get(dev, "fck");
2155	if (IS_ERR(gpriv->clkp))
2156		return dev_err_probe(dev, PTR_ERR(gpriv->clkp),
2157				     "cannot get peripheral clock\n");
2158
2159	/* fCAN clock: Pick External clock. If not available fallback to
2160	 * CANFD clock
2161	 */
2162	gpriv->can_clk = devm_clk_get(dev, "can_clk");
2163	if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
2164		gpriv->can_clk = devm_clk_get(dev, "canfd");
2165		if (IS_ERR(gpriv->can_clk))
2166			return dev_err_probe(dev, PTR_ERR(gpriv->can_clk),
2167					     "cannot get canfd clock\n");
2168
2169		/* CANFD clock may be further divided within the IP */
2170		fcan_freq = clk_get_rate(gpriv->can_clk) / info->postdiv;
2171	} else {
2172		fcan_freq = clk_get_rate(gpriv->can_clk);
2173		gpriv->extclk = gpriv->info->external_clk;
2174	}
2175
2176	gpriv->clk_ram = devm_clk_get_optional(dev, "ram_clk");
2177	if (IS_ERR(gpriv->clk_ram))
2178		return dev_err_probe(dev, PTR_ERR(gpriv->clk_ram),
2179				     "cannot get ram clock\n");
2180
2181	addr = devm_platform_ioremap_resource(pdev, 0);
2182	if (IS_ERR(addr)) {
2183		err = PTR_ERR(addr);
2184		goto fail_dev;
2185	}
2186	gpriv->base = addr;
2187	gpriv->fcbase = addr + gpriv->info->regs->coffset;
2188
2189	/* Request IRQ that's common for both channels */
2190	if (info->shared_global_irqs) {
2191		err = devm_request_irq(dev, ch_irq,
2192				       rcar_canfd_channel_interrupt, 0,
2193				       "canfd.ch_int", gpriv);
2194		if (err) {
2195			dev_err(dev, "devm_request_irq %d failed: %pe\n",
2196				ch_irq, ERR_PTR(err));
2197			goto fail_dev;
2198		}
2199
2200		err = devm_request_irq(dev, g_irq, rcar_canfd_global_interrupt,
2201				       0, "canfd.g_int", gpriv);
2202		if (err) {
2203			dev_err(dev, "devm_request_irq %d failed: %pe\n",
2204				g_irq, ERR_PTR(err));
2205			goto fail_dev;
2206		}
2207	} else {
2208		err = devm_request_irq(dev, g_recc_irq,
2209				       rcar_canfd_global_receive_fifo_interrupt, 0,
2210				       "canfd.g_recc", gpriv);
2211
2212		if (err) {
2213			dev_err(dev, "devm_request_irq %d failed: %pe\n",
2214				g_recc_irq, ERR_PTR(err));
2215			goto fail_dev;
2216		}
2217
2218		err = devm_request_irq(dev, g_err_irq,
2219				       rcar_canfd_global_err_interrupt, 0,
2220				       "canfd.g_err", gpriv);
2221		if (err) {
2222			dev_err(dev, "devm_request_irq %d failed: %pe\n",
2223				g_err_irq, ERR_PTR(err));
2224			goto fail_dev;
2225		}
2226	}
2227
2228	err = rcar_canfd_global_init(gpriv);
2229	if (err)
2230		goto fail_mode;
2231
2232	for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2233		err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq,
2234					       transceivers[ch]);
2235		if (err)
2236			goto fail_channel;
2237	}
2238
2239	platform_set_drvdata(pdev, gpriv);
2240	dev_info(dev, "global operational state (%s clk, %s mode)\n",
2241		 gpriv->extclk ? "ext" : "canfd",
2242		 gpriv->fdmode ? "fd" : "classical");
2243	return 0;
2244
2245fail_channel:
2246	for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
2247		rcar_canfd_channel_remove(gpriv, ch);
2248fail_mode:
2249	rcar_canfd_global_deinit(gpriv, false);
2250fail_dev:
2251	return err;
2252}
2253
2254static void rcar_canfd_remove(struct platform_device *pdev)
2255{
2256	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
2257	u32 ch;
2258
2259	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2260		rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2261		rcar_canfd_channel_remove(gpriv, ch);
2262	}
2263
2264	rcar_canfd_global_deinit(gpriv, true);
2265}
2266
2267static int rcar_canfd_suspend(struct device *dev)
2268{
2269	struct rcar_canfd_global *gpriv = dev_get_drvdata(dev);
2270	int err;
2271	u32 ch;
2272
2273	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2274		struct rcar_canfd_channel *priv = gpriv->ch[ch];
2275		struct net_device *ndev = priv->ndev;
2276
2277		if (!netif_running(ndev))
2278			continue;
2279
2280		netif_device_detach(ndev);
2281
2282		err = rcar_canfd_close(ndev);
2283		if (err) {
2284			netdev_err(ndev, "rcar_canfd_close() failed %pe\n",
2285				   ERR_PTR(err));
2286			return err;
2287		}
2288
2289		priv->can.state = CAN_STATE_SLEEPING;
2290	}
2291
2292	/* TODO Skip if wake-up (which is not yet supported) is enabled */
2293	rcar_canfd_global_deinit(gpriv, false);
2294
2295	return 0;
2296}
2297
2298static int rcar_canfd_resume(struct device *dev)
2299{
2300	struct rcar_canfd_global *gpriv = dev_get_drvdata(dev);
2301	int err;
2302	u32 ch;
2303
2304	err = rcar_canfd_global_init(gpriv);
2305	if (err) {
2306		dev_err(dev, "rcar_canfd_global_init() failed %pe\n", ERR_PTR(err));
2307		return err;
2308	}
2309
2310	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2311		struct rcar_canfd_channel *priv = gpriv->ch[ch];
2312		struct net_device *ndev = priv->ndev;
2313
2314		if (!netif_running(ndev))
2315			continue;
2316
2317		err = rcar_canfd_open(ndev);
2318		if (err) {
2319			netdev_err(ndev, "rcar_canfd_open() failed %pe\n",
2320				   ERR_PTR(err));
2321			return err;
2322		}
2323
2324		netif_device_attach(ndev);
2325	}
2326
2327	return 0;
2328}
2329
2330static DEFINE_SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2331				rcar_canfd_resume);
2332
2333static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2334	{ .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info },
2335	{ .compatible = "renesas,r9a09g047-canfd", .data = &r9a09g047_hw_info },
2336	{ .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info },
2337	{ .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info },
2338	{ .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },
2339	{ }
2340};
2341
2342MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2343
2344static struct platform_driver rcar_canfd_driver = {
2345	.driver = {
2346		.name = RCANFD_DRV_NAME,
2347		.of_match_table = of_match_ptr(rcar_canfd_of_table),
2348		.pm = pm_sleep_ptr(&rcar_canfd_pm_ops),
2349	},
2350	.probe = rcar_canfd_probe,
2351	.remove = rcar_canfd_remove,
2352};
2353
2354module_platform_driver(rcar_canfd_driver);
2355
2356MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
2357MODULE_LICENSE("GPL");
2358MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2359MODULE_ALIAS("platform:" RCANFD_DRV_NAME);