m_can.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* CAN bus driver for Bosch M_CAN controller
  3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4 */
  5
  6#ifndef _CAN_M_CAN_H_
  7#define _CAN_M_CAN_H_
  8
  9#include <linux/can/core.h>
 10#include <linux/can/dev.h>
 11#include <linux/can/rx-offload.h>
 12#include <linux/clk.h>
 13#include <linux/completion.h>
 14#include <linux/delay.h>
 15#include <linux/device.h>
 16#include <linux/dma-mapping.h>
 17#include <linux/freezer.h>
 18#include <linux/hrtimer.h>
 19#include <linux/interrupt.h>
 20#include <linux/io.h>
 21#include <linux/iopoll.h>
 22#include <linux/kernel.h>
 23#include <linux/module.h>
 24#include <linux/netdevice.h>
 25#include <linux/of.h>
 26#include <linux/phy/phy.h>
 27#include <linux/pinctrl/consumer.h>
 28#include <linux/pm_runtime.h>
 29#include <linux/slab.h>
 30#include <linux/uaccess.h>
 31
 32/* m_can lec values */
 33enum m_can_lec_type {
 34	LEC_NO_ERROR = 0,
 35	LEC_STUFF_ERROR,
 36	LEC_FORM_ERROR,
 37	LEC_ACK_ERROR,
 38	LEC_BIT1_ERROR,
 39	LEC_BIT0_ERROR,
 40	LEC_CRC_ERROR,
 41	LEC_NO_CHANGE,
 42};
 43
 44enum m_can_mram_cfg {
 45	MRAM_SIDF = 0,
 46	MRAM_XIDF,
 47	MRAM_RXF0,
 48	MRAM_RXF1,
 49	MRAM_RXB,
 50	MRAM_TXE,
 51	MRAM_TXB,
 52	MRAM_CFG_NUM,
 53};
 54
 55/* address offset and element number for each FIFO/Buffer in the Message RAM */
 56struct mram_cfg {
 57	u16 off;
 58	u8  num;
 59};
 60
 61struct m_can_classdev;
 62struct m_can_ops {
 63	/* Device specific call backs */
 64	int (*clear_interrupts)(struct m_can_classdev *cdev);
 65	u32 (*read_reg)(struct m_can_classdev *cdev, int reg);
 66	int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);
 67	int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);
 68	int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
 69			  const void *val, size_t val_count);
 70	int (*init)(struct m_can_classdev *cdev);
 71	int (*deinit)(struct m_can_classdev *cdev);
 72};
 73
 74struct m_can_tx_op {
 75	struct m_can_classdev *cdev;
 76	struct work_struct work;
 77	struct sk_buff *skb;
 78	bool submit;
 79};
 80
 81struct m_can_classdev {
 82	struct can_priv can;
 83	struct can_rx_offload offload;
 84	struct napi_struct napi;
 85	struct net_device *net;
 86	struct device *dev;
 87	struct clk *hclk;
 88	struct clk *cclk;
 89	struct reset_control *rst;
 90
 91	struct workqueue_struct *tx_wq;
 92	struct phy *transceiver;
 93
 94	ktime_t irq_timer_wait;
 95
 96	const struct m_can_ops *ops;
 97
 98	int version;
 99	u32 irqstatus;
100
101	int pm_clock_support;
102	int pm_wake_source;
103	int is_peripheral;
104	bool irq_edge_triggered;
105
106	// Cached M_CAN_IE register content
107	u32 active_interrupts;
108	u32 rx_max_coalesced_frames_irq;
109	u32 rx_coalesce_usecs_irq;
110	u32 tx_max_coalesced_frames;
111	u32 tx_max_coalesced_frames_irq;
112	u32 tx_coalesce_usecs_irq;
113
114	// Store this internally to avoid fetch delays on peripheral chips
115	u32 tx_fifo_putidx;
116
117	/* Protects shared state between start_xmit and m_can_isr */
118	spinlock_t tx_handling_spinlock;
119	int tx_fifo_in_flight;
120
121	struct m_can_tx_op *tx_ops;
122	int tx_fifo_size;
123	int next_tx_op;
124
125	int nr_txs_without_submit;
126	/* bitfield of fifo elements that will be submitted together */
127	u32 tx_peripheral_submit;
128
129	struct mram_cfg mcfg[MRAM_CFG_NUM];
130
131	struct hrtimer hrtimer;
132
133	struct pinctrl *pinctrl;
134	struct pinctrl_state *pinctrl_state_wakeup;
135};
136
137struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv);
138void m_can_class_free_dev(struct net_device *net);
139int m_can_class_register(struct m_can_classdev *cdev);
140void m_can_class_unregister(struct m_can_classdev *cdev);
141int m_can_class_get_clocks(struct m_can_classdev *cdev);
142int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size);
143
144int m_can_class_suspend(struct device *dev);
145int m_can_class_resume(struct device *dev);
146#endif	/* _CAN_M_H_ */