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flexcan-core.c
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linux-6.19.14/drivers/net/can/flexcan/flexcan-core.c
1// SPDX-License-Identifier: GPL-2.0 2// 3// flexcan.c - FLEXCAN CAN controller driver 4// 5// Copyright (c) 2005-2006 Varma Electronics Oy 6// Copyright (c) 2009 Sascha Hauer, Pengutronix 7// Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> 8// Copyright (c) 2014 David Jander, Protonic Holland 9// 10// Based on code originally by Andrey Volkov <avolkov@varma-el.com> 11 12#include <dt-bindings/firmware/imx/rsrc.h> 13#include <linux/bitfield.h> 14#include <linux/can.h> 15#include <linux/can/dev.h> 16#include <linux/can/error.h> 17#include <linux/clk.h> 18#include <linux/delay.h> 19#include <linux/firmware/imx/sci.h> 20#include <linux/interrupt.h> 21#include <linux/io.h> 22#include <linux/mfd/syscon.h> 23#include <linux/module.h> 24#include <linux/netdevice.h> 25#include <linux/of.h> 26#include <linux/pinctrl/consumer.h> 27#include <linux/platform_device.h> 28#include <linux/can/platform/flexcan.h> 29#include <linux/phy/phy.h> 30#include <linux/pm_runtime.h> 31#include <linux/property.h> 32#include <linux/regmap.h> 33#include <linux/regulator/consumer.h> 34 35#include "flexcan.h" 36 37#define DRV_NAME "flexcan" 38 39/* 8 for RX fifo and 2 error handling */ 40#define FLEXCAN_NAPI_WEIGHT (8 + 2) 41 42/* FLEXCAN module configuration register (CANMCR) bits */ 43#define FLEXCAN_MCR_MDIS BIT(31) 44#define FLEXCAN_MCR_FRZ BIT(30) 45#define FLEXCAN_MCR_FEN BIT(29) 46#define FLEXCAN_MCR_HALT BIT(28) 47#define FLEXCAN_MCR_NOT_RDY BIT(27) 48#define FLEXCAN_MCR_WAK_MSK BIT(26) 49#define FLEXCAN_MCR_SOFTRST BIT(25) 50#define FLEXCAN_MCR_FRZ_ACK BIT(24) 51#define FLEXCAN_MCR_SUPV BIT(23) 52#define FLEXCAN_MCR_SLF_WAK BIT(22) 53#define FLEXCAN_MCR_WRN_EN BIT(21) 54#define FLEXCAN_MCR_LPM_ACK BIT(20) 55#define FLEXCAN_MCR_WAK_SRC BIT(19) 56#define FLEXCAN_MCR_DOZE BIT(18) 57#define FLEXCAN_MCR_SRX_DIS BIT(17) 58#define FLEXCAN_MCR_IRMQ BIT(16) 59#define FLEXCAN_MCR_LPRIO_EN BIT(13) 60#define FLEXCAN_MCR_AEN BIT(12) 61#define FLEXCAN_MCR_FDEN BIT(11) 62/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */ 63#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) 64#define FLEXCAN_MCR_IDAM_A (0x0 << 8) 65#define FLEXCAN_MCR_IDAM_B (0x1 << 8) 66#define FLEXCAN_MCR_IDAM_C (0x2 << 8) 67#define FLEXCAN_MCR_IDAM_D (0x3 << 8) 68 69/* FLEXCAN control register (CANCTRL) bits */ 70#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 71#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 72#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 73#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 74#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 75#define FLEXCAN_CTRL_ERR_MSK BIT(14) 76#define FLEXCAN_CTRL_CLK_SRC BIT(13) 77#define FLEXCAN_CTRL_LPB BIT(12) 78#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 79#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 80#define FLEXCAN_CTRL_SMP BIT(7) 81#define FLEXCAN_CTRL_BOFF_REC BIT(6) 82#define FLEXCAN_CTRL_TSYN BIT(5) 83#define FLEXCAN_CTRL_LBUF BIT(4) 84#define FLEXCAN_CTRL_LOM BIT(3) 85#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 86#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 87#define FLEXCAN_CTRL_ERR_STATE \ 88 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 89 FLEXCAN_CTRL_BOFF_MSK) 90#define FLEXCAN_CTRL_ERR_ALL \ 91 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 92 93/* FLEXCAN control register 2 (CTRL2) bits */ 94#define FLEXCAN_CTRL2_ECRWRE BIT(29) 95#define FLEXCAN_CTRL2_WRMFRZ BIT(28) 96#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24) 97#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19) 98#define FLEXCAN_CTRL2_MRP BIT(18) 99#define FLEXCAN_CTRL2_RRS BIT(17) 100#define FLEXCAN_CTRL2_EACEN BIT(16) 101#define FLEXCAN_CTRL2_ISOCANFDEN BIT(12) 102 103/* FLEXCAN memory error control register (MECR) bits */ 104#define FLEXCAN_MECR_ECRWRDIS BIT(31) 105#define FLEXCAN_MECR_HANCEI_MSK BIT(19) 106#define FLEXCAN_MECR_FANCEI_MSK BIT(18) 107#define FLEXCAN_MECR_CEI_MSK BIT(16) 108#define FLEXCAN_MECR_HAERRIE BIT(15) 109#define FLEXCAN_MECR_FAERRIE BIT(14) 110#define FLEXCAN_MECR_EXTERRIE BIT(13) 111#define FLEXCAN_MECR_RERRDIS BIT(9) 112#define FLEXCAN_MECR_ECCDIS BIT(8) 113#define FLEXCAN_MECR_NCEFAFRZ BIT(7) 114 115/* FLEXCAN error and status register (ESR) bits */ 116#define FLEXCAN_ESR_TWRN_INT BIT(17) 117#define FLEXCAN_ESR_RWRN_INT BIT(16) 118#define FLEXCAN_ESR_BIT1_ERR BIT(15) 119#define FLEXCAN_ESR_BIT0_ERR BIT(14) 120#define FLEXCAN_ESR_ACK_ERR BIT(13) 121#define FLEXCAN_ESR_CRC_ERR BIT(12) 122#define FLEXCAN_ESR_FRM_ERR BIT(11) 123#define FLEXCAN_ESR_STF_ERR BIT(10) 124#define FLEXCAN_ESR_TX_WRN BIT(9) 125#define FLEXCAN_ESR_RX_WRN BIT(8) 126#define FLEXCAN_ESR_IDLE BIT(7) 127#define FLEXCAN_ESR_TXRX BIT(6) 128#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 129#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 130#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 131#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 132#define FLEXCAN_ESR_BOFF_INT BIT(2) 133#define FLEXCAN_ESR_ERR_INT BIT(1) 134#define FLEXCAN_ESR_WAK_INT BIT(0) 135#define FLEXCAN_ESR_ERR_BUS \ 136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 139#define FLEXCAN_ESR_ERR_STATE \ 140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 141#define FLEXCAN_ESR_ERR_ALL \ 142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 143#define FLEXCAN_ESR_ALL_INT \ 144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 146 147/* FLEXCAN Bit Timing register (CBT) bits */ 148#define FLEXCAN_CBT_BTF BIT(31) 149#define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21) 150#define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16) 151#define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10) 152#define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5) 153#define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0) 154 155/* FLEXCAN FD control register (FDCTRL) bits */ 156#define FLEXCAN_FDCTRL_FDRATE BIT(31) 157#define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19) 158#define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16) 159#define FLEXCAN_FDCTRL_MBDSR_8 0x0 160#define FLEXCAN_FDCTRL_MBDSR_12 0x1 161#define FLEXCAN_FDCTRL_MBDSR_32 0x2 162#define FLEXCAN_FDCTRL_MBDSR_64 0x3 163#define FLEXCAN_FDCTRL_TDCEN BIT(15) 164#define FLEXCAN_FDCTRL_TDCFAIL BIT(14) 165#define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8) 166#define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0) 167 168/* FLEXCAN FD Bit Timing register (FDCBT) bits */ 169#define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20) 170#define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16) 171#define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10) 172#define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5) 173#define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0) 174 175/* FLEXCAN interrupt flag register (IFLAG) bits */ 176/* Errata ERR005829 step7: Reserve first valid MB */ 177#define FLEXCAN_TX_MB_RESERVED_RX_FIFO 8 178#define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX 0 179#define FLEXCAN_RX_MB_RX_MAILBOX_FIRST (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1) 180#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x) 181#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 182#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 183#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 184 185/* FLEXCAN message buffers */ 186#define FLEXCAN_MB_CODE_MASK (0xf << 24) 187#define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24) 188#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) 189#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) 190#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) 191#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24) 192#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) 193 194#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) 195#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) 196#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) 197#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) 198 199#define FLEXCAN_MB_CNT_EDL BIT(31) 200#define FLEXCAN_MB_CNT_BRS BIT(30) 201#define FLEXCAN_MB_CNT_ESI BIT(29) 202#define FLEXCAN_MB_CNT_SRR BIT(22) 203#define FLEXCAN_MB_CNT_IDE BIT(21) 204#define FLEXCAN_MB_CNT_RTR BIT(20) 205#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 206#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 207 208#define FLEXCAN_TIMEOUT_US (250) 209 210/* Structure of the message buffer */ 211struct flexcan_mb { 212 u32 can_ctrl; 213 u32 can_id; 214 u32 data[]; 215}; 216 217/* Structure of the hardware registers */ 218struct flexcan_regs { 219 u32 mcr; /* 0x00 */ 220 u32 ctrl; /* 0x04 - Not affected by Soft Reset */ 221 u32 timer; /* 0x08 */ 222 u32 tcr; /* 0x0c */ 223 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */ 224 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */ 225 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */ 226 u32 ecr; /* 0x1c */ 227 u32 esr; /* 0x20 */ 228 u32 imask2; /* 0x24 */ 229 u32 imask1; /* 0x28 */ 230 u32 iflag2; /* 0x2c */ 231 u32 iflag1; /* 0x30 */ 232 union { /* 0x34 */ 233 u32 gfwr_mx28; /* MX28, MX53 */ 234 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */ 235 }; 236 u32 esr2; /* 0x38 */ 237 u32 imeur; /* 0x3c */ 238 u32 lrfr; /* 0x40 */ 239 u32 crcr; /* 0x44 */ 240 u32 rxfgmask; /* 0x48 */ 241 u32 rxfir; /* 0x4c - Not affected by Soft Reset */ 242 u32 cbt; /* 0x50 - Not affected by Soft Reset */ 243 u32 _reserved2; /* 0x54 */ 244 u32 dbg1; /* 0x58 */ 245 u32 dbg2; /* 0x5c */ 246 u32 _reserved3[8]; /* 0x60 */ 247 struct_group(init, 248 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */ 249 /* FIFO-mode: 250 * MB 251 * 0x080...0x08f 0 RX message buffer 252 * 0x090...0x0df 1-5 reserved 253 * 0x0e0...0x0ff 6-7 8 entry ID table 254 * (mx25, mx28, mx35, mx53) 255 * 0x0e0...0x2df 6-7..37 8..128 entry ID table 256 * size conf'ed via ctrl2::RFFN 257 * (mx6, vf610) 258 */ 259 u32 _reserved4[256]; /* 0x480 */ 260 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */ 261 u32 _reserved5[24]; /* 0x980 */ 262 u32 gfwr_mx6; /* 0x9e0 - MX6 */ 263 u32 _reserved6[39]; /* 0x9e4 */ 264 u32 _rxfir[6]; /* 0xa80 */ 265 u32 _reserved8[2]; /* 0xa98 */ 266 u32 _rxmgmask; /* 0xaa0 */ 267 u32 _rxfgmask; /* 0xaa4 */ 268 u32 _rx14mask; /* 0xaa8 */ 269 u32 _rx15mask; /* 0xaac */ 270 u32 tx_smb[4]; /* 0xab0 */ 271 u32 rx_smb0[4]; /* 0xac0 */ 272 u32 rx_smb1[4]; /* 0xad0 */ 273 ); 274 u32 mecr; /* 0xae0 */ 275 u32 erriar; /* 0xae4 */ 276 u32 erridpr; /* 0xae8 */ 277 u32 errippr; /* 0xaec */ 278 u32 rerrar; /* 0xaf0 */ 279 u32 rerrdr; /* 0xaf4 */ 280 u32 rerrsynr; /* 0xaf8 */ 281 u32 errsr; /* 0xafc */ 282 u32 _reserved7[64]; /* 0xb00 */ 283 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */ 284 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */ 285 u32 fdcrc; /* 0xc08 */ 286 u32 _reserved9[199]; /* 0xc0c */ 287 struct_group(init_fd, 288 u32 tx_smb_fd[18]; /* 0xf28 */ 289 u32 rx_smb0_fd[18]; /* 0xf70 */ 290 u32 rx_smb1_fd[18]; /* 0xfb8 */ 291 ); 292}; 293 294static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8); 295 296static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = { 297 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE | 298 FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 | 299 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 300 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 301}; 302 303static const struct flexcan_devtype_data fsl_p1010_devtype_data = { 304 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE | 305 FLEXCAN_QUIRK_BROKEN_PERR_STATE | 306 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN | 307 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 308 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 309}; 310 311static const struct flexcan_devtype_data fsl_imx25_devtype_data = { 312 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE | 313 FLEXCAN_QUIRK_BROKEN_PERR_STATE | 314 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 315 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 316}; 317 318static const struct flexcan_devtype_data fsl_imx28_devtype_data = { 319 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE | 320 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 321 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 322}; 323 324static const struct flexcan_devtype_data fsl_imx6q_devtype_data = { 325 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 326 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 327 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR | 328 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 329 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 330}; 331 332static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = { 333 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 334 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 335 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW | 336 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 337 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 338}; 339 340static struct flexcan_devtype_data fsl_imx8mp_devtype_data = { 341 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 342 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 343 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR | 344 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC | 345 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 346 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 347}; 348 349static struct flexcan_devtype_data fsl_imx93_devtype_data = { 350 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 351 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 352 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR | 353 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC | 354 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 355 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 356}; 357 358static const struct flexcan_devtype_data fsl_imx95_devtype_data = { 359 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 360 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 361 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_FD | 362 FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 363 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI, 364}; 365 366static const struct flexcan_devtype_data fsl_vf610_devtype_data = { 367 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 368 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 369 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC | 370 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 371 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 372}; 373 374static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = { 375 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 376 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX | 377 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 378 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 379}; 380 381static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = { 382 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 383 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 384 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD | 385 FLEXCAN_QUIRK_SUPPORT_ECC | 386 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 387 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 388}; 389 390static const struct flexcan_devtype_data nxp_s32g2_devtype_data = { 391 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 392 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 393 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD | 394 FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_NR_IRQ_3 | 395 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 396 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | 397 FLEXCAN_QUIRK_SECONDARY_MB_IRQ, 398}; 399 400static const struct can_bittiming_const flexcan_bittiming_const = { 401 .name = DRV_NAME, 402 .tseg1_min = 4, 403 .tseg1_max = 16, 404 .tseg2_min = 2, 405 .tseg2_max = 8, 406 .sjw_max = 4, 407 .brp_min = 1, 408 .brp_max = 256, 409 .brp_inc = 1, 410}; 411 412static const struct can_bittiming_const flexcan_fd_bittiming_const = { 413 .name = DRV_NAME, 414 .tseg1_min = 2, 415 .tseg1_max = 96, 416 .tseg2_min = 2, 417 .tseg2_max = 32, 418 .sjw_max = 16, 419 .brp_min = 1, 420 .brp_max = 1024, 421 .brp_inc = 1, 422}; 423 424static const struct can_bittiming_const flexcan_fd_data_bittiming_const = { 425 .name = DRV_NAME, 426 .tseg1_min = 2, 427 .tseg1_max = 39, 428 .tseg2_min = 2, 429 .tseg2_max = 8, 430 .sjw_max = 4, 431 .brp_min = 1, 432 .brp_max = 1024, 433 .brp_inc = 1, 434}; 435 436/* FlexCAN module is essentially modelled as a little-endian IP in most 437 * SoCs, i.e the registers as well as the message buffer areas are 438 * implemented in a little-endian fashion. 439 * 440 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN 441 * module in a big-endian fashion (i.e the registers as well as the 442 * message buffer areas are implemented in a big-endian way). 443 * 444 * In addition, the FlexCAN module can be found on SoCs having ARM or 445 * PPC cores. So, we need to abstract off the register read/write 446 * functions, ensuring that these cater to all the combinations of module 447 * endianness and underlying CPU endianness. 448 */ 449static inline u32 flexcan_read_be(void __iomem *addr) 450{ 451 return ioread32be(addr); 452} 453 454static inline void flexcan_write_be(u32 val, void __iomem *addr) 455{ 456 iowrite32be(val, addr); 457} 458 459static inline u32 flexcan_read_le(void __iomem *addr) 460{ 461 return ioread32(addr); 462} 463 464static inline void flexcan_write_le(u32 val, void __iomem *addr) 465{ 466 iowrite32(val, addr); 467} 468 469static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv, 470 u8 mb_index) 471{ 472 u8 bank_size; 473 bool bank; 474 475 if (WARN_ON(mb_index >= priv->mb_count)) 476 return NULL; 477 478 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size; 479 480 bank = mb_index >= bank_size; 481 if (bank) 482 mb_index -= bank_size; 483 484 return (struct flexcan_mb __iomem *) 485 (&priv->regs->mb[bank][priv->mb_size * mb_index]); 486} 487 488static int flexcan_low_power_enter_ack(struct flexcan_priv *priv) 489{ 490 struct flexcan_regs __iomem *regs = priv->regs; 491 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 492 493 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 494 udelay(10); 495 496 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 497 return -ETIMEDOUT; 498 499 return 0; 500} 501 502static int flexcan_low_power_exit_ack(struct flexcan_priv *priv) 503{ 504 struct flexcan_regs __iomem *regs = priv->regs; 505 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 506 507 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 508 udelay(10); 509 510 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) 511 return -ETIMEDOUT; 512 513 return 0; 514} 515 516static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable) 517{ 518 struct flexcan_regs __iomem *regs = priv->regs; 519 u32 reg_mcr; 520 521 reg_mcr = priv->read(®s->mcr); 522 523 if (enable) 524 reg_mcr |= FLEXCAN_MCR_WAK_MSK; 525 else 526 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK; 527 528 priv->write(reg_mcr, ®s->mcr); 529} 530 531static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled) 532{ 533 u8 idx = priv->scu_idx; 534 u32 rsrc_id, val; 535 536 rsrc_id = IMX_SC_R_CAN(idx); 537 538 if (enabled) 539 val = 1; 540 else 541 val = 0; 542 543 /* stop mode request via scu firmware */ 544 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id, 545 IMX_SC_C_IPG_STOP, val); 546} 547 548static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv) 549{ 550 struct flexcan_regs __iomem *regs = priv->regs; 551 u32 reg_mcr; 552 int ret; 553 554 reg_mcr = priv->read(®s->mcr); 555 reg_mcr |= FLEXCAN_MCR_SLF_WAK; 556 priv->write(reg_mcr, ®s->mcr); 557 558 /* enable stop request */ 559 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) { 560 ret = flexcan_stop_mode_enable_scfw(priv, true); 561 if (ret < 0) 562 return ret; 563 } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) { 564 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, 565 1 << priv->stm.req_bit, 1 << priv->stm.req_bit); 566 } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI) { 567 /* For the SCMI mode, driver do nothing, ATF will send request to 568 * SM(system manager, M33 core) through SCMI protocol after linux 569 * suspend. Once SM get this request, it will send IPG_STOP signal 570 * to Flex_CAN, let CAN in STOP mode. 571 */ 572 return 0; 573 } 574 575 return flexcan_low_power_enter_ack(priv); 576} 577 578static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv) 579{ 580 struct flexcan_regs __iomem *regs = priv->regs; 581 u32 reg_mcr; 582 int ret; 583 584 /* Remove stop request, for FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI, 585 * do nothing here, because ATF already send request to SM before 586 * linux resume. Once SM get this request, it will deassert the 587 * IPG_STOP signal to Flex_CAN. 588 */ 589 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) { 590 ret = flexcan_stop_mode_enable_scfw(priv, false); 591 if (ret < 0) 592 return ret; 593 } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) { 594 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, 595 1 << priv->stm.req_bit, 0); 596 } 597 598 reg_mcr = priv->read(®s->mcr); 599 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK; 600 priv->write(reg_mcr, ®s->mcr); 601 602 return flexcan_low_power_exit_ack(priv); 603} 604 605static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv) 606{ 607 struct flexcan_regs __iomem *regs = priv->regs; 608 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK); 609 610 priv->write(reg_ctrl, ®s->ctrl); 611} 612 613static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv) 614{ 615 struct flexcan_regs __iomem *regs = priv->regs; 616 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK); 617 618 priv->write(reg_ctrl, ®s->ctrl); 619} 620 621static int flexcan_clks_enable(const struct flexcan_priv *priv) 622{ 623 int err = 0; 624 625 if (priv->clk_ipg) { 626 err = clk_prepare_enable(priv->clk_ipg); 627 if (err) 628 return err; 629 } 630 631 if (priv->clk_per) { 632 err = clk_prepare_enable(priv->clk_per); 633 if (err) 634 clk_disable_unprepare(priv->clk_ipg); 635 } 636 637 return err; 638} 639 640static void flexcan_clks_disable(const struct flexcan_priv *priv) 641{ 642 clk_disable_unprepare(priv->clk_per); 643 clk_disable_unprepare(priv->clk_ipg); 644} 645 646static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) 647{ 648 if (priv->reg_xceiver) 649 return regulator_enable(priv->reg_xceiver); 650 else if (priv->transceiver) 651 return phy_power_on(priv->transceiver); 652 653 return 0; 654} 655 656static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) 657{ 658 if (priv->reg_xceiver) 659 return regulator_disable(priv->reg_xceiver); 660 else if (priv->transceiver) 661 return phy_power_off(priv->transceiver); 662 663 return 0; 664} 665 666static int flexcan_chip_enable(struct flexcan_priv *priv) 667{ 668 struct flexcan_regs __iomem *regs = priv->regs; 669 u32 reg; 670 671 reg = priv->read(®s->mcr); 672 reg &= ~FLEXCAN_MCR_MDIS; 673 priv->write(reg, ®s->mcr); 674 675 return flexcan_low_power_exit_ack(priv); 676} 677 678static int flexcan_chip_disable(struct flexcan_priv *priv) 679{ 680 struct flexcan_regs __iomem *regs = priv->regs; 681 u32 reg; 682 683 reg = priv->read(®s->mcr); 684 reg |= FLEXCAN_MCR_MDIS; 685 priv->write(reg, ®s->mcr); 686 687 return flexcan_low_power_enter_ack(priv); 688} 689 690static int flexcan_chip_freeze(struct flexcan_priv *priv) 691{ 692 struct flexcan_regs __iomem *regs = priv->regs; 693 unsigned int timeout; 694 u32 bitrate = priv->can.bittiming.bitrate; 695 u32 reg; 696 697 if (bitrate) 698 timeout = 1000 * 1000 * 10 / bitrate; 699 else 700 timeout = FLEXCAN_TIMEOUT_US / 10; 701 702 reg = priv->read(®s->mcr); 703 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT; 704 priv->write(reg, ®s->mcr); 705 706 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 707 udelay(100); 708 709 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 710 return -ETIMEDOUT; 711 712 return 0; 713} 714 715static int flexcan_chip_unfreeze(struct flexcan_priv *priv) 716{ 717 struct flexcan_regs __iomem *regs = priv->regs; 718 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 719 u32 reg; 720 721 reg = priv->read(®s->mcr); 722 reg &= ~FLEXCAN_MCR_HALT; 723 priv->write(reg, ®s->mcr); 724 725 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 726 udelay(10); 727 728 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) 729 return -ETIMEDOUT; 730 731 return 0; 732} 733 734static int flexcan_chip_softreset(struct flexcan_priv *priv) 735{ 736 struct flexcan_regs __iomem *regs = priv->regs; 737 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 738 739 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 740 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) 741 udelay(10); 742 743 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST) 744 return -ETIMEDOUT; 745 746 return 0; 747} 748 749static int __flexcan_get_berr_counter(const struct net_device *dev, 750 struct can_berr_counter *bec) 751{ 752 const struct flexcan_priv *priv = netdev_priv(dev); 753 struct flexcan_regs __iomem *regs = priv->regs; 754 u32 reg = priv->read(®s->ecr); 755 756 bec->txerr = (reg >> 0) & 0xff; 757 bec->rxerr = (reg >> 8) & 0xff; 758 759 return 0; 760} 761 762static int flexcan_get_berr_counter(const struct net_device *dev, 763 struct can_berr_counter *bec) 764{ 765 const struct flexcan_priv *priv = netdev_priv(dev); 766 int err; 767 768 err = pm_runtime_resume_and_get(priv->dev); 769 if (err < 0) 770 return err; 771 772 err = __flexcan_get_berr_counter(dev, bec); 773 774 pm_runtime_put(priv->dev); 775 776 return err; 777} 778 779static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 780{ 781 const struct flexcan_priv *priv = netdev_priv(dev); 782 struct canfd_frame *cfd = (struct canfd_frame *)skb->data; 783 u32 can_id; 784 u32 data; 785 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16); 786 int i; 787 788 if (can_dev_dropped_skb(dev, skb)) 789 return NETDEV_TX_OK; 790 791 netif_stop_queue(dev); 792 793 if (cfd->can_id & CAN_EFF_FLAG) { 794 can_id = cfd->can_id & CAN_EFF_MASK; 795 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 796 } else { 797 can_id = (cfd->can_id & CAN_SFF_MASK) << 18; 798 } 799 800 if (cfd->can_id & CAN_RTR_FLAG) 801 ctrl |= FLEXCAN_MB_CNT_RTR; 802 803 if (can_is_canfd_skb(skb)) { 804 ctrl |= FLEXCAN_MB_CNT_EDL; 805 806 if (cfd->flags & CANFD_BRS) 807 ctrl |= FLEXCAN_MB_CNT_BRS; 808 } 809 810 for (i = 0; i < cfd->len; i += sizeof(u32)) { 811 data = be32_to_cpup((__be32 *)&cfd->data[i]); 812 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]); 813 } 814 815 can_put_echo_skb(skb, dev, 0, 0); 816 817 priv->write(can_id, &priv->tx_mb->can_id); 818 priv->write(ctrl, &priv->tx_mb->can_ctrl); 819 820 /* Errata ERR005829 step8: 821 * Write twice INACTIVE(0x8) code to first MB. 822 */ 823 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 824 &priv->tx_mb_reserved->can_ctrl); 825 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 826 &priv->tx_mb_reserved->can_ctrl); 827 828 return NETDEV_TX_OK; 829} 830 831static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr) 832{ 833 struct flexcan_priv *priv = netdev_priv(dev); 834 struct flexcan_regs __iomem *regs = priv->regs; 835 struct sk_buff *skb; 836 struct can_frame *cf; 837 bool rx_errors = false, tx_errors = false; 838 u32 timestamp; 839 int err; 840 841 timestamp = priv->read(®s->timer) << 16; 842 843 skb = alloc_can_err_skb(dev, &cf); 844 if (unlikely(!skb)) 845 return; 846 847 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 848 849 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 850 netdev_dbg(dev, "BIT1_ERR irq\n"); 851 cf->data[2] |= CAN_ERR_PROT_BIT1; 852 tx_errors = true; 853 } 854 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 855 netdev_dbg(dev, "BIT0_ERR irq\n"); 856 cf->data[2] |= CAN_ERR_PROT_BIT0; 857 tx_errors = true; 858 } 859 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 860 netdev_dbg(dev, "ACK_ERR irq\n"); 861 cf->can_id |= CAN_ERR_ACK; 862 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 863 tx_errors = true; 864 } 865 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 866 netdev_dbg(dev, "CRC_ERR irq\n"); 867 cf->data[2] |= CAN_ERR_PROT_BIT; 868 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 869 rx_errors = true; 870 } 871 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 872 netdev_dbg(dev, "FRM_ERR irq\n"); 873 cf->data[2] |= CAN_ERR_PROT_FORM; 874 rx_errors = true; 875 } 876 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 877 netdev_dbg(dev, "STF_ERR irq\n"); 878 cf->data[2] |= CAN_ERR_PROT_STUFF; 879 rx_errors = true; 880 } 881 882 priv->can.can_stats.bus_error++; 883 if (rx_errors) 884 dev->stats.rx_errors++; 885 if (tx_errors) 886 dev->stats.tx_errors++; 887 888 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 889 if (err) 890 dev->stats.rx_fifo_errors++; 891} 892 893static void flexcan_irq_state(struct net_device *dev, u32 reg_esr) 894{ 895 struct flexcan_priv *priv = netdev_priv(dev); 896 struct flexcan_regs __iomem *regs = priv->regs; 897 struct sk_buff *skb; 898 struct can_frame *cf; 899 enum can_state new_state, rx_state, tx_state; 900 int flt; 901 struct can_berr_counter bec; 902 u32 timestamp; 903 int err; 904 905 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 906 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 907 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ? 908 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; 909 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ? 910 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; 911 new_state = max(tx_state, rx_state); 912 } else { 913 __flexcan_get_berr_counter(dev, &bec); 914 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ? 915 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF; 916 rx_state = bec.rxerr >= bec.txerr ? new_state : 0; 917 tx_state = bec.rxerr <= bec.txerr ? new_state : 0; 918 } 919 920 /* state hasn't changed */ 921 if (likely(new_state == priv->can.state)) 922 return; 923 924 timestamp = priv->read(®s->timer) << 16; 925 926 skb = alloc_can_err_skb(dev, &cf); 927 if (unlikely(!skb)) 928 return; 929 930 can_change_state(dev, cf, tx_state, rx_state); 931 932 if (unlikely(new_state == CAN_STATE_BUS_OFF)) 933 can_bus_off(dev); 934 935 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 936 if (err) 937 dev->stats.rx_fifo_errors++; 938} 939 940static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask) 941{ 942 u64 reg = 0; 943 944 if (upper_32_bits(mask)) 945 reg = (u64)priv->read(addr - 4) << 32; 946 if (lower_32_bits(mask)) 947 reg |= priv->read(addr); 948 949 return reg & mask; 950} 951 952static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr) 953{ 954 if (upper_32_bits(val)) 955 priv->write(upper_32_bits(val), addr - 4); 956 if (lower_32_bits(val)) 957 priv->write(lower_32_bits(val), addr); 958} 959 960static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv) 961{ 962 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask); 963} 964 965static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv) 966{ 967 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask); 968} 969 970static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload) 971{ 972 return container_of(offload, struct flexcan_priv, offload); 973} 974 975static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload, 976 unsigned int n, u32 *timestamp, 977 bool drop) 978{ 979 struct flexcan_priv *priv = rx_offload_to_priv(offload); 980 struct flexcan_regs __iomem *regs = priv->regs; 981 struct flexcan_mb __iomem *mb; 982 struct sk_buff *skb; 983 struct canfd_frame *cfd; 984 u32 reg_ctrl, reg_id, reg_iflag1; 985 int i; 986 987 mb = flexcan_get_mb(priv, n); 988 989 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 990 u32 code; 991 992 do { 993 reg_ctrl = priv->read(&mb->can_ctrl); 994 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT); 995 996 /* is this MB empty? */ 997 code = reg_ctrl & FLEXCAN_MB_CODE_MASK; 998 if ((code != FLEXCAN_MB_CODE_RX_FULL) && 999 (code != FLEXCAN_MB_CODE_RX_OVERRUN)) 1000 return NULL; 1001 1002 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) { 1003 /* This MB was overrun, we lost data */ 1004 offload->dev->stats.rx_over_errors++; 1005 offload->dev->stats.rx_errors++; 1006 } 1007 } else { 1008 reg_iflag1 = priv->read(®s->iflag1); 1009 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE)) 1010 return NULL; 1011 1012 reg_ctrl = priv->read(&mb->can_ctrl); 1013 } 1014 1015 if (unlikely(drop)) { 1016 skb = ERR_PTR(-ENOBUFS); 1017 goto mark_as_read; 1018 } 1019 1020 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) 1021 skb = alloc_canfd_skb(offload->dev, &cfd); 1022 else 1023 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd); 1024 if (unlikely(!skb)) { 1025 skb = ERR_PTR(-ENOMEM); 1026 goto mark_as_read; 1027 } 1028 1029 /* increase timstamp to full 32 bit */ 1030 *timestamp = reg_ctrl << 16; 1031 1032 reg_id = priv->read(&mb->can_id); 1033 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 1034 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 1035 else 1036 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK; 1037 1038 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) { 1039 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf); 1040 1041 if (reg_ctrl & FLEXCAN_MB_CNT_BRS) 1042 cfd->flags |= CANFD_BRS; 1043 } else { 1044 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf); 1045 1046 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 1047 cfd->can_id |= CAN_RTR_FLAG; 1048 } 1049 1050 if (reg_ctrl & FLEXCAN_MB_CNT_ESI) 1051 cfd->flags |= CANFD_ESI; 1052 1053 for (i = 0; i < cfd->len; i += sizeof(u32)) { 1054 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)])); 1055 *(__be32 *)(cfd->data + i) = data; 1056 } 1057 1058 mark_as_read: 1059 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1060 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1); 1061 else 1062 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 1063 1064 /* Read the Free Running Timer. It is optional but recommended 1065 * to unlock Mailbox as soon as possible and make it available 1066 * for reception. 1067 */ 1068 priv->read(®s->timer); 1069 1070 return skb; 1071} 1072 1073static irqreturn_t flexcan_irq(int irq, void *dev_id) 1074{ 1075 struct net_device *dev = dev_id; 1076 struct net_device_stats *stats = &dev->stats; 1077 struct flexcan_priv *priv = netdev_priv(dev); 1078 struct flexcan_regs __iomem *regs = priv->regs; 1079 irqreturn_t handled = IRQ_NONE; 1080 u64 reg_iflag_tx; 1081 u32 reg_esr; 1082 enum can_state last_state = priv->can.state; 1083 1084 /* reception interrupt */ 1085 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1086 u64 reg_iflag_rx; 1087 int ret; 1088 1089 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) { 1090 handled = IRQ_HANDLED; 1091 ret = can_rx_offload_irq_offload_timestamp(&priv->offload, 1092 reg_iflag_rx); 1093 if (!ret) 1094 break; 1095 } 1096 } else { 1097 u32 reg_iflag1; 1098 1099 reg_iflag1 = priv->read(®s->iflag1); 1100 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) { 1101 handled = IRQ_HANDLED; 1102 can_rx_offload_irq_offload_fifo(&priv->offload); 1103 } 1104 1105 /* FIFO overflow interrupt */ 1106 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 1107 handled = IRQ_HANDLED; 1108 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, 1109 ®s->iflag1); 1110 dev->stats.rx_over_errors++; 1111 dev->stats.rx_errors++; 1112 } 1113 } 1114 1115 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv); 1116 1117 /* transmission complete interrupt */ 1118 if (reg_iflag_tx & priv->tx_mask) { 1119 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl); 1120 1121 handled = IRQ_HANDLED; 1122 stats->tx_bytes += 1123 can_rx_offload_get_echo_skb_queue_timestamp(&priv->offload, 0, 1124 reg_ctrl << 16, NULL); 1125 stats->tx_packets++; 1126 1127 /* after sending a RTR frame MB is in RX mode */ 1128 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1129 &priv->tx_mb->can_ctrl); 1130 flexcan_write64(priv, priv->tx_mask, ®s->iflag1); 1131 netif_wake_queue(dev); 1132 } 1133 1134 reg_esr = priv->read(®s->esr); 1135 1136 /* ACK all bus error, state change and wake IRQ sources */ 1137 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) { 1138 handled = IRQ_HANDLED; 1139 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr); 1140 } 1141 1142 /* state change interrupt or broken error state quirk fix is enabled */ 1143 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) || 1144 (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE | 1145 FLEXCAN_QUIRK_BROKEN_PERR_STATE))) 1146 flexcan_irq_state(dev, reg_esr); 1147 1148 /* bus error IRQ - handle if bus error reporting is activated */ 1149 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) && 1150 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1151 flexcan_irq_bus_err(dev, reg_esr); 1152 1153 /* availability of error interrupt among state transitions in case 1154 * bus error reporting is de-activated and 1155 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled: 1156 * +--------------------------------------------------------------+ 1157 * | +----------------------------------------------+ [stopped / | 1158 * | | | sleeping] -+ 1159 * +-+-> active <-> warning <-> passive -> bus off -+ 1160 * ___________^^^^^^^^^^^^_______________________________ 1161 * disabled(1) enabled disabled 1162 * 1163 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled 1164 */ 1165 if ((last_state != priv->can.state) && 1166 (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) && 1167 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 1168 switch (priv->can.state) { 1169 case CAN_STATE_ERROR_ACTIVE: 1170 if (priv->devtype_data.quirks & 1171 FLEXCAN_QUIRK_BROKEN_WERR_STATE) 1172 flexcan_error_irq_enable(priv); 1173 else 1174 flexcan_error_irq_disable(priv); 1175 break; 1176 1177 case CAN_STATE_ERROR_WARNING: 1178 flexcan_error_irq_enable(priv); 1179 break; 1180 1181 case CAN_STATE_ERROR_PASSIVE: 1182 case CAN_STATE_BUS_OFF: 1183 flexcan_error_irq_disable(priv); 1184 break; 1185 1186 default: 1187 break; 1188 } 1189 } 1190 1191 if (handled) 1192 can_rx_offload_irq_finish(&priv->offload); 1193 1194 return handled; 1195} 1196 1197static void flexcan_set_bittiming_ctrl(const struct net_device *dev) 1198{ 1199 const struct flexcan_priv *priv = netdev_priv(dev); 1200 const struct can_bittiming *bt = &priv->can.bittiming; 1201 struct flexcan_regs __iomem *regs = priv->regs; 1202 u32 reg; 1203 1204 reg = priv->read(®s->ctrl); 1205 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 1206 FLEXCAN_CTRL_RJW(0x3) | 1207 FLEXCAN_CTRL_PSEG1(0x7) | 1208 FLEXCAN_CTRL_PSEG2(0x7) | 1209 FLEXCAN_CTRL_PROPSEG(0x7)); 1210 1211 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 1212 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 1213 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 1214 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 1215 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 1216 1217 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); 1218 priv->write(reg, ®s->ctrl); 1219 1220 /* print chip status */ 1221 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 1222 priv->read(®s->mcr), priv->read(®s->ctrl)); 1223} 1224 1225static void flexcan_set_bittiming_cbt(const struct net_device *dev) 1226{ 1227 struct flexcan_priv *priv = netdev_priv(dev); 1228 struct can_bittiming *bt = &priv->can.bittiming; 1229 struct can_bittiming *dbt = &priv->can.fd.data_bittiming; 1230 struct flexcan_regs __iomem *regs = priv->regs; 1231 u32 reg_cbt, reg_fdctrl; 1232 1233 /* CBT */ 1234 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit 1235 * long. The can_calc_bittiming() tries to divide the tseg1 1236 * equally between phase_seg1 and prop_seg, which may not fit 1237 * in CBT register. Therefore, if phase_seg1 is more than 1238 * possible value, increase prop_seg and decrease phase_seg1. 1239 */ 1240 if (bt->phase_seg1 > 0x20) { 1241 bt->prop_seg += (bt->phase_seg1 - 0x20); 1242 bt->phase_seg1 = 0x20; 1243 } 1244 1245 reg_cbt = FLEXCAN_CBT_BTF | 1246 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) | 1247 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) | 1248 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) | 1249 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) | 1250 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1); 1251 1252 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt); 1253 priv->write(reg_cbt, ®s->cbt); 1254 1255 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1256 u32 reg_fdcbt, reg_ctrl2; 1257 1258 if (bt->brp != dbt->brp) 1259 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n", 1260 dbt->brp, bt->brp); 1261 1262 /* FDCBT */ 1263 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is 1264 * 5 bit long. The can_calc_bittiming tries to divide 1265 * the tseg1 equally between phase_seg1 and prop_seg, 1266 * which may not fit in FDCBT register. Therefore, if 1267 * phase_seg1 is more than possible value, increase 1268 * prop_seg and decrease phase_seg1 1269 */ 1270 if (dbt->phase_seg1 > 0x8) { 1271 dbt->prop_seg += (dbt->phase_seg1 - 0x8); 1272 dbt->phase_seg1 = 0x8; 1273 } 1274 1275 reg_fdcbt = priv->read(®s->fdcbt); 1276 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) | 1277 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) | 1278 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) | 1279 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) | 1280 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7)); 1281 1282 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) | 1283 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) | 1284 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) | 1285 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) | 1286 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1); 1287 1288 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt); 1289 priv->write(reg_fdcbt, ®s->fdcbt); 1290 1291 /* CTRL2 */ 1292 reg_ctrl2 = priv->read(®s->ctrl2); 1293 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN; 1294 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) 1295 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN; 1296 1297 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2); 1298 priv->write(reg_ctrl2, ®s->ctrl2); 1299 } 1300 1301 /* FDCTRL */ 1302 reg_fdctrl = priv->read(®s->fdctrl); 1303 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE | 1304 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f)); 1305 1306 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1307 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE; 1308 1309 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1310 /* TDC must be disabled for Loop Back mode */ 1311 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN; 1312 } else { 1313 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN | 1314 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 1315 ((dbt->phase_seg1 - 1) + 1316 dbt->prop_seg + 2) * 1317 ((dbt->brp - 1 ) + 1)); 1318 } 1319 } 1320 1321 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl); 1322 priv->write(reg_fdctrl, ®s->fdctrl); 1323 1324 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n", 1325 __func__, 1326 priv->read(®s->mcr), priv->read(®s->ctrl), 1327 priv->read(®s->ctrl2), priv->read(®s->fdctrl), 1328 priv->read(®s->cbt), priv->read(®s->fdcbt)); 1329} 1330 1331static void flexcan_set_bittiming(struct net_device *dev) 1332{ 1333 const struct flexcan_priv *priv = netdev_priv(dev); 1334 struct flexcan_regs __iomem *regs = priv->regs; 1335 u32 reg; 1336 1337 reg = priv->read(®s->ctrl); 1338 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP | 1339 FLEXCAN_CTRL_LOM); 1340 1341 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 1342 reg |= FLEXCAN_CTRL_LPB; 1343 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1344 reg |= FLEXCAN_CTRL_LOM; 1345 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 1346 reg |= FLEXCAN_CTRL_SMP; 1347 1348 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); 1349 priv->write(reg, ®s->ctrl); 1350 1351 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) 1352 return flexcan_set_bittiming_cbt(dev); 1353 else 1354 return flexcan_set_bittiming_ctrl(dev); 1355} 1356 1357static void flexcan_ram_init(struct net_device *dev) 1358{ 1359 struct flexcan_priv *priv = netdev_priv(dev); 1360 struct flexcan_regs __iomem *regs = priv->regs; 1361 u32 reg_ctrl2; 1362 1363 /* 11.8.3.13 Detection and correction of memory errors: 1364 * CTRL2[WRMFRZ] grants write access to all memory positions 1365 * that require initialization, ranging from 0x080 to 0xADF 1366 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled. 1367 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers 1368 * need to be initialized as well. MCR[RFEN] must not be set 1369 * during memory initialization. 1370 */ 1371 reg_ctrl2 = priv->read(®s->ctrl2); 1372 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ; 1373 priv->write(reg_ctrl2, ®s->ctrl2); 1374 1375 memset_io(®s->init, 0, sizeof(regs->init)); 1376 1377 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1378 memset_io(®s->init_fd, 0, sizeof(regs->init_fd)); 1379 1380 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ; 1381 priv->write(reg_ctrl2, ®s->ctrl2); 1382} 1383 1384static int flexcan_rx_offload_setup(struct net_device *dev) 1385{ 1386 struct flexcan_priv *priv = netdev_priv(dev); 1387 int err; 1388 1389 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1390 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN; 1391 else 1392 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN; 1393 1394 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16) 1395 priv->mb_count = 16; 1396 else 1397 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) + 1398 (sizeof(priv->regs->mb[1]) / priv->mb_size); 1399 1400 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1401 priv->tx_mb_reserved = 1402 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX); 1403 else 1404 priv->tx_mb_reserved = 1405 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO); 1406 priv->tx_mb_idx = priv->mb_count - 1; 1407 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx); 1408 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx); 1409 1410 priv->offload.mailbox_read = flexcan_mailbox_read; 1411 1412 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1413 priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST; 1414 priv->offload.mb_last = priv->mb_count - 2; 1415 1416 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last, 1417 priv->offload.mb_first); 1418 err = can_rx_offload_add_timestamp(dev, &priv->offload); 1419 } else { 1420 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | 1421 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE; 1422 err = can_rx_offload_add_fifo(dev, &priv->offload, 1423 FLEXCAN_NAPI_WEIGHT); 1424 } 1425 1426 return err; 1427} 1428 1429static void flexcan_chip_interrupts_enable(const struct net_device *dev) 1430{ 1431 const struct flexcan_priv *priv = netdev_priv(dev); 1432 struct flexcan_regs __iomem *regs = priv->regs; 1433 u64 reg_imask; 1434 1435 disable_irq(dev->irq); 1436 priv->write(priv->reg_ctrl_default, ®s->ctrl); 1437 reg_imask = priv->rx_mask | priv->tx_mask; 1438 priv->write(upper_32_bits(reg_imask), ®s->imask2); 1439 priv->write(lower_32_bits(reg_imask), ®s->imask1); 1440 enable_irq(dev->irq); 1441} 1442 1443static void flexcan_chip_interrupts_disable(const struct net_device *dev) 1444{ 1445 const struct flexcan_priv *priv = netdev_priv(dev); 1446 struct flexcan_regs __iomem *regs = priv->regs; 1447 1448 priv->write(0, ®s->imask2); 1449 priv->write(0, ®s->imask1); 1450 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 1451 ®s->ctrl); 1452} 1453 1454/* flexcan_chip_start 1455 * 1456 * this functions is entered with clocks enabled 1457 * 1458 */ 1459static int flexcan_chip_start(struct net_device *dev) 1460{ 1461 struct flexcan_priv *priv = netdev_priv(dev); 1462 struct flexcan_regs __iomem *regs = priv->regs; 1463 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; 1464 int err, i; 1465 struct flexcan_mb __iomem *mb; 1466 1467 /* enable module */ 1468 err = flexcan_chip_enable(priv); 1469 if (err) 1470 return err; 1471 1472 /* soft reset */ 1473 err = flexcan_chip_softreset(priv); 1474 if (err) 1475 goto out_chip_disable; 1476 1477 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC) 1478 flexcan_ram_init(dev); 1479 1480 flexcan_set_bittiming(dev); 1481 1482 /* set freeze, halt */ 1483 err = flexcan_chip_freeze(priv); 1484 if (err) 1485 goto out_chip_disable; 1486 1487 /* MCR 1488 * 1489 * only supervisor access 1490 * enable warning int 1491 * enable individual RX masking 1492 * choose format C 1493 * set max mailbox number 1494 */ 1495 reg_mcr = priv->read(®s->mcr); 1496 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 1497 reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | 1498 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx); 1499 1500 /* MCR 1501 * 1502 * FIFO: 1503 * - disable for mailbox mode 1504 * - enable for FIFO mode 1505 */ 1506 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1507 reg_mcr &= ~FLEXCAN_MCR_FEN; 1508 else 1509 reg_mcr |= FLEXCAN_MCR_FEN; 1510 1511 /* MCR 1512 * 1513 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be 1514 * asserted because this will impede the self reception 1515 * of a transmitted message. This is not documented in 1516 * earlier versions of flexcan block guide. 1517 * 1518 * Self Reception: 1519 * - enable Self Reception for loopback mode 1520 * (by clearing "Self Reception Disable" bit) 1521 * - disable for normal operation 1522 */ 1523 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 1524 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS; 1525 else 1526 reg_mcr |= FLEXCAN_MCR_SRX_DIS; 1527 1528 /* MCR - CAN-FD */ 1529 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1530 reg_mcr |= FLEXCAN_MCR_FDEN; 1531 else 1532 reg_mcr &= ~FLEXCAN_MCR_FDEN; 1533 1534 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 1535 priv->write(reg_mcr, ®s->mcr); 1536 1537 /* CTRL 1538 * 1539 * disable timer sync feature 1540 * 1541 * disable auto busoff recovery 1542 * transmit lowest buffer first 1543 * 1544 * enable tx and rx warning interrupt 1545 * enable bus off interrupt 1546 * (== FLEXCAN_CTRL_ERR_STATE) 1547 */ 1548 reg_ctrl = priv->read(®s->ctrl); 1549 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 1550 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 1551 FLEXCAN_CTRL_ERR_STATE; 1552 1553 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 1554 * on most Flexcan cores, too. Otherwise we don't get 1555 * any error warning or passive interrupts. 1556 */ 1557 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE || 1558 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 1559 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 1560 else 1561 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK; 1562 1563 /* save for later use */ 1564 priv->reg_ctrl_default = reg_ctrl; 1565 /* leave interrupts disabled for now */ 1566 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL; 1567 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 1568 priv->write(reg_ctrl, ®s->ctrl); 1569 1570 if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) { 1571 reg_ctrl2 = priv->read(®s->ctrl2); 1572 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS; 1573 priv->write(reg_ctrl2, ®s->ctrl2); 1574 } 1575 1576 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) { 1577 u32 reg_fdctrl; 1578 1579 reg_fdctrl = priv->read(®s->fdctrl); 1580 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) | 1581 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3)); 1582 1583 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1584 reg_fdctrl |= 1585 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 1586 FLEXCAN_FDCTRL_MBDSR_64) | 1587 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 1588 FLEXCAN_FDCTRL_MBDSR_64); 1589 } else { 1590 reg_fdctrl |= 1591 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 1592 FLEXCAN_FDCTRL_MBDSR_8) | 1593 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 1594 FLEXCAN_FDCTRL_MBDSR_8); 1595 } 1596 1597 netdev_dbg(dev, "%s: writing fdctrl=0x%08x", 1598 __func__, reg_fdctrl); 1599 priv->write(reg_fdctrl, ®s->fdctrl); 1600 } 1601 1602 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1603 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) { 1604 mb = flexcan_get_mb(priv, i); 1605 priv->write(FLEXCAN_MB_CODE_RX_EMPTY, 1606 &mb->can_ctrl); 1607 } 1608 } else { 1609 /* clear and invalidate unused mailboxes first */ 1610 for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) { 1611 mb = flexcan_get_mb(priv, i); 1612 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE, 1613 &mb->can_ctrl); 1614 } 1615 } 1616 1617 /* Errata ERR005829: mark first TX mailbox as INACTIVE */ 1618 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1619 &priv->tx_mb_reserved->can_ctrl); 1620 1621 /* mark TX mailbox as INACTIVE */ 1622 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1623 &priv->tx_mb->can_ctrl); 1624 1625 /* acceptance mask/acceptance code (accept everything) */ 1626 priv->write(0x0, ®s->rxgmask); 1627 priv->write(0x0, ®s->rx14mask); 1628 priv->write(0x0, ®s->rx15mask); 1629 1630 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG) 1631 priv->write(0x0, ®s->rxfgmask); 1632 1633 /* clear acceptance filters */ 1634 for (i = 0; i < priv->mb_count; i++) 1635 priv->write(0, ®s->rximr[i]); 1636 1637 /* On Vybrid, disable non-correctable errors interrupt and 1638 * freeze mode. It still can correct the correctable errors 1639 * when HW supports ECC. 1640 * 1641 * This also works around errata e5295 which generates false 1642 * positive memory errors and put the device in freeze mode. 1643 */ 1644 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) { 1645 /* Follow the protocol as described in "Detection 1646 * and Correction of Memory Errors" to write to 1647 * MECR register (step 1 - 5) 1648 * 1649 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1 1650 * 2. set CTRL2[ECRWRE] 1651 */ 1652 reg_ctrl2 = priv->read(®s->ctrl2); 1653 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE; 1654 priv->write(reg_ctrl2, ®s->ctrl2); 1655 1656 /* 3. clear MECR[ECRWRDIS] */ 1657 reg_mecr = priv->read(®s->mecr); 1658 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS; 1659 priv->write(reg_mecr, ®s->mecr); 1660 1661 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */ 1662 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK | 1663 FLEXCAN_MECR_FANCEI_MSK); 1664 priv->write(reg_mecr, ®s->mecr); 1665 1666 /* 5. after configuration done, lock MECR by either 1667 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE] 1668 */ 1669 reg_mecr |= FLEXCAN_MECR_ECRWRDIS; 1670 priv->write(reg_mecr, ®s->mecr); 1671 1672 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE; 1673 priv->write(reg_ctrl2, ®s->ctrl2); 1674 } 1675 1676 /* synchronize with the can bus */ 1677 err = flexcan_chip_unfreeze(priv); 1678 if (err) 1679 goto out_chip_disable; 1680 1681 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1682 1683 /* print chip status */ 1684 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 1685 priv->read(®s->mcr), priv->read(®s->ctrl)); 1686 1687 return 0; 1688 1689 out_chip_disable: 1690 flexcan_chip_disable(priv); 1691 return err; 1692} 1693 1694/* __flexcan_chip_stop 1695 * 1696 * this function is entered with clocks enabled 1697 */ 1698static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error) 1699{ 1700 struct flexcan_priv *priv = netdev_priv(dev); 1701 int err; 1702 1703 /* freeze + disable module */ 1704 err = flexcan_chip_freeze(priv); 1705 if (err && !disable_on_error) 1706 return err; 1707 err = flexcan_chip_disable(priv); 1708 if (err && !disable_on_error) 1709 goto out_chip_unfreeze; 1710 1711 priv->can.state = CAN_STATE_STOPPED; 1712 1713 return 0; 1714 1715 out_chip_unfreeze: 1716 flexcan_chip_unfreeze(priv); 1717 1718 return err; 1719} 1720 1721static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev) 1722{ 1723 return __flexcan_chip_stop(dev, true); 1724} 1725 1726static inline int flexcan_chip_stop(struct net_device *dev) 1727{ 1728 return __flexcan_chip_stop(dev, false); 1729} 1730 1731static int flexcan_open(struct net_device *dev) 1732{ 1733 struct flexcan_priv *priv = netdev_priv(dev); 1734 int err; 1735 1736 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) && 1737 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) { 1738 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n"); 1739 return -EINVAL; 1740 } 1741 1742 err = pm_runtime_resume_and_get(priv->dev); 1743 if (err < 0) 1744 return err; 1745 1746 err = open_candev(dev); 1747 if (err) 1748 goto out_runtime_put; 1749 1750 err = flexcan_transceiver_enable(priv); 1751 if (err) 1752 goto out_close; 1753 1754 err = flexcan_rx_offload_setup(dev); 1755 if (err) 1756 goto out_transceiver_disable; 1757 1758 err = flexcan_chip_start(dev); 1759 if (err) 1760 goto out_can_rx_offload_del; 1761 1762 can_rx_offload_enable(&priv->offload); 1763 1764 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 1765 if (err) 1766 goto out_can_rx_offload_disable; 1767 1768 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 1769 err = request_irq(priv->irq_boff, 1770 flexcan_irq, IRQF_SHARED, dev->name, dev); 1771 if (err) 1772 goto out_free_irq; 1773 1774 err = request_irq(priv->irq_err, 1775 flexcan_irq, IRQF_SHARED, dev->name, dev); 1776 if (err) 1777 goto out_free_irq_boff; 1778 } 1779 1780 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) { 1781 err = request_irq(priv->irq_secondary_mb, 1782 flexcan_irq, IRQF_SHARED, dev->name, dev); 1783 if (err) 1784 goto out_free_irq_err; 1785 } 1786 1787 flexcan_chip_interrupts_enable(dev); 1788 1789 netif_start_queue(dev); 1790 1791 return 0; 1792 1793 out_free_irq_err: 1794 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) 1795 free_irq(priv->irq_err, dev); 1796 out_free_irq_boff: 1797 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) 1798 free_irq(priv->irq_boff, dev); 1799 out_free_irq: 1800 free_irq(dev->irq, dev); 1801 out_can_rx_offload_disable: 1802 can_rx_offload_disable(&priv->offload); 1803 flexcan_chip_stop(dev); 1804 out_can_rx_offload_del: 1805 can_rx_offload_del(&priv->offload); 1806 out_transceiver_disable: 1807 flexcan_transceiver_disable(priv); 1808 out_close: 1809 close_candev(dev); 1810 out_runtime_put: 1811 pm_runtime_put(priv->dev); 1812 1813 return err; 1814} 1815 1816static int flexcan_close(struct net_device *dev) 1817{ 1818 struct flexcan_priv *priv = netdev_priv(dev); 1819 1820 netif_stop_queue(dev); 1821 flexcan_chip_interrupts_disable(dev); 1822 1823 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) 1824 free_irq(priv->irq_secondary_mb, dev); 1825 1826 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 1827 free_irq(priv->irq_err, dev); 1828 free_irq(priv->irq_boff, dev); 1829 } 1830 1831 free_irq(dev->irq, dev); 1832 can_rx_offload_disable(&priv->offload); 1833 flexcan_chip_stop_disable_on_error(dev); 1834 1835 can_rx_offload_del(&priv->offload); 1836 flexcan_transceiver_disable(priv); 1837 close_candev(dev); 1838 1839 pm_runtime_put(priv->dev); 1840 1841 return 0; 1842} 1843 1844static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 1845{ 1846 int err; 1847 1848 switch (mode) { 1849 case CAN_MODE_START: 1850 err = flexcan_chip_start(dev); 1851 if (err) 1852 return err; 1853 1854 flexcan_chip_interrupts_enable(dev); 1855 1856 netif_wake_queue(dev); 1857 break; 1858 1859 default: 1860 return -EOPNOTSUPP; 1861 } 1862 1863 return 0; 1864} 1865 1866static const struct net_device_ops flexcan_netdev_ops = { 1867 .ndo_open = flexcan_open, 1868 .ndo_stop = flexcan_close, 1869 .ndo_start_xmit = flexcan_start_xmit, 1870}; 1871 1872static int register_flexcandev(struct net_device *dev) 1873{ 1874 struct flexcan_priv *priv = netdev_priv(dev); 1875 struct flexcan_regs __iomem *regs = priv->regs; 1876 u32 reg, err; 1877 1878 err = flexcan_clks_enable(priv); 1879 if (err) 1880 return err; 1881 1882 /* select "bus clock", chip must be disabled */ 1883 err = flexcan_chip_disable(priv); 1884 if (err) 1885 goto out_clks_disable; 1886 1887 reg = priv->read(®s->ctrl); 1888 if (priv->clk_src) 1889 reg |= FLEXCAN_CTRL_CLK_SRC; 1890 else 1891 reg &= ~FLEXCAN_CTRL_CLK_SRC; 1892 priv->write(reg, ®s->ctrl); 1893 1894 err = flexcan_chip_enable(priv); 1895 if (err) 1896 goto out_chip_disable; 1897 1898 /* set freeze, halt */ 1899 err = flexcan_chip_freeze(priv); 1900 if (err) 1901 goto out_chip_disable; 1902 1903 /* activate FIFO, restrict register access */ 1904 reg = priv->read(®s->mcr); 1905 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 1906 priv->write(reg, ®s->mcr); 1907 1908 /* Currently we only support newer versions of this core 1909 * featuring a RX hardware FIFO (although this driver doesn't 1910 * make use of it on some cores). Older cores, found on some 1911 * Coldfire derivates are not tested. 1912 */ 1913 reg = priv->read(®s->mcr); 1914 if (!(reg & FLEXCAN_MCR_FEN)) { 1915 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 1916 err = -ENODEV; 1917 goto out_chip_disable; 1918 } 1919 1920 err = register_candev(dev); 1921 if (err) 1922 goto out_chip_disable; 1923 1924 /* Disable core and let pm_runtime_put() disable the clocks. 1925 * If CONFIG_PM is not enabled, the clocks will stay powered. 1926 */ 1927 flexcan_chip_disable(priv); 1928 pm_runtime_put(priv->dev); 1929 1930 return 0; 1931 1932 out_chip_disable: 1933 flexcan_chip_disable(priv); 1934 out_clks_disable: 1935 flexcan_clks_disable(priv); 1936 return err; 1937} 1938 1939static void unregister_flexcandev(struct net_device *dev) 1940{ 1941 unregister_candev(dev); 1942} 1943 1944static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev) 1945{ 1946 struct net_device *dev = platform_get_drvdata(pdev); 1947 struct device_node *np = pdev->dev.of_node; 1948 struct device_node *gpr_np; 1949 struct flexcan_priv *priv; 1950 phandle phandle; 1951 u32 out_val[3]; 1952 int ret; 1953 1954 if (!np) 1955 return -EINVAL; 1956 1957 /* stop mode property format is: 1958 * <&gpr req_gpr req_bit>. 1959 */ 1960 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 1961 ARRAY_SIZE(out_val)); 1962 if (ret) { 1963 dev_dbg(&pdev->dev, "no stop-mode property\n"); 1964 return ret; 1965 } 1966 phandle = *out_val; 1967 1968 gpr_np = of_find_node_by_phandle(phandle); 1969 if (!gpr_np) { 1970 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n"); 1971 return -ENODEV; 1972 } 1973 1974 priv = netdev_priv(dev); 1975 priv->stm.gpr = syscon_node_to_regmap(gpr_np); 1976 if (IS_ERR(priv->stm.gpr)) { 1977 dev_dbg(&pdev->dev, "could not find gpr regmap\n"); 1978 ret = PTR_ERR(priv->stm.gpr); 1979 goto out_put_node; 1980 } 1981 1982 priv->stm.req_gpr = out_val[1]; 1983 priv->stm.req_bit = out_val[2]; 1984 1985 dev_dbg(&pdev->dev, 1986 "gpr %s req_gpr=0x02%x req_bit=%u\n", 1987 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit); 1988 1989 return 0; 1990 1991out_put_node: 1992 of_node_put(gpr_np); 1993 return ret; 1994} 1995 1996static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev) 1997{ 1998 struct net_device *dev = platform_get_drvdata(pdev); 1999 struct flexcan_priv *priv; 2000 u8 scu_idx; 2001 int ret; 2002 2003 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx); 2004 if (ret < 0) { 2005 dev_dbg(&pdev->dev, "failed to get scu index\n"); 2006 return ret; 2007 } 2008 2009 priv = netdev_priv(dev); 2010 priv->scu_idx = scu_idx; 2011 2012 /* this function could be deferred probe, return -EPROBE_DEFER */ 2013 return imx_scu_get_handle(&priv->sc_ipc_handle); 2014} 2015 2016/* flexcan_setup_stop_mode - Setup stop mode for wakeup 2017 * 2018 * Return: = 0 setup stop mode successfully or doesn't support this feature 2019 * < 0 fail to setup stop mode (could be deferred probe) 2020 */ 2021static int flexcan_setup_stop_mode(struct platform_device *pdev) 2022{ 2023 struct net_device *dev = platform_get_drvdata(pdev); 2024 struct flexcan_priv *priv; 2025 int ret; 2026 2027 priv = netdev_priv(dev); 2028 2029 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) 2030 ret = flexcan_setup_stop_mode_scfw(pdev); 2031 else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) 2032 ret = flexcan_setup_stop_mode_gpr(pdev); 2033 else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI) 2034 /* ATF will handle all STOP_IPG related work */ 2035 ret = 0; 2036 else 2037 /* return 0 directly if doesn't support stop mode feature */ 2038 return 0; 2039 2040 /* If ret is -EINVAL, this means SoC claim to support stop mode, but 2041 * dts file lack the stop mode property definition. For this case, 2042 * directly return 0, this will skip the wakeup capable setting and 2043 * will not block the driver probe. 2044 */ 2045 if (ret == -EINVAL) 2046 return 0; 2047 else if (ret) 2048 return ret; 2049 2050 device_set_wakeup_capable(&pdev->dev, true); 2051 2052 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source")) 2053 device_set_wakeup_enable(&pdev->dev, true); 2054 2055 return 0; 2056} 2057 2058static const struct of_device_id flexcan_of_match[] = { 2059 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, }, 2060 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, }, 2061 { .compatible = "fsl,imx93-flexcan", .data = &fsl_imx93_devtype_data, }, 2062 { .compatible = "fsl,imx95-flexcan", .data = &fsl_imx95_devtype_data, }, 2063 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 2064 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 2065 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, }, 2066 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, }, 2067 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, }, 2068 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 2069 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, }, 2070 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, }, 2071 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, }, 2072 { .compatible = "nxp,s32g2-flexcan", .data = &nxp_s32g2_devtype_data, }, 2073 { /* sentinel */ }, 2074}; 2075MODULE_DEVICE_TABLE(of, flexcan_of_match); 2076 2077static const struct platform_device_id flexcan_id_table[] = { 2078 { 2079 .name = "flexcan-mcf5441x", 2080 .driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data, 2081 }, { 2082 /* sentinel */ 2083 }, 2084}; 2085MODULE_DEVICE_TABLE(platform, flexcan_id_table); 2086 2087static int flexcan_probe(struct platform_device *pdev) 2088{ 2089 const struct flexcan_devtype_data *devtype_data; 2090 struct net_device *dev; 2091 struct flexcan_priv *priv; 2092 struct regulator *reg_xceiver; 2093 struct phy *transceiver; 2094 struct clk *clk_ipg = NULL, *clk_per = NULL; 2095 struct flexcan_regs __iomem *regs; 2096 struct flexcan_platform_data *pdata; 2097 int err, irq; 2098 u8 clk_src = 1; 2099 u32 clock_freq = 0; 2100 2101 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver"); 2102 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) 2103 return -EPROBE_DEFER; 2104 else if (PTR_ERR(reg_xceiver) == -ENODEV) 2105 reg_xceiver = NULL; 2106 else if (IS_ERR(reg_xceiver)) 2107 return PTR_ERR(reg_xceiver); 2108 2109 transceiver = devm_phy_optional_get(&pdev->dev, NULL); 2110 if (IS_ERR(transceiver)) 2111 return dev_err_probe(&pdev->dev, PTR_ERR(transceiver), 2112 "failed to get phy\n"); 2113 2114 if (pdev->dev.of_node) { 2115 of_property_read_u32(pdev->dev.of_node, 2116 "clock-frequency", &clock_freq); 2117 of_property_read_u8(pdev->dev.of_node, 2118 "fsl,clk-source", &clk_src); 2119 } else { 2120 pdata = dev_get_platdata(&pdev->dev); 2121 if (pdata) { 2122 clock_freq = pdata->clock_frequency; 2123 clk_src = pdata->clk_src; 2124 } 2125 } 2126 2127 if (!clock_freq) { 2128 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2129 if (IS_ERR(clk_ipg)) { 2130 dev_err(&pdev->dev, "no ipg clock defined\n"); 2131 return PTR_ERR(clk_ipg); 2132 } 2133 2134 clk_per = devm_clk_get(&pdev->dev, "per"); 2135 if (IS_ERR(clk_per)) { 2136 dev_err(&pdev->dev, "no per clock defined\n"); 2137 return PTR_ERR(clk_per); 2138 } 2139 clock_freq = clk_get_rate(clk_per); 2140 } 2141 2142 irq = platform_get_irq(pdev, 0); 2143 if (irq < 0) 2144 return irq; 2145 2146 regs = devm_platform_ioremap_resource(pdev, 0); 2147 if (IS_ERR(regs)) 2148 return PTR_ERR(regs); 2149 2150 devtype_data = device_get_match_data(&pdev->dev); 2151 2152 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) && 2153 !((devtype_data->quirks & 2154 (FLEXCAN_QUIRK_USE_RX_MAILBOX | 2155 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2156 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | 2157 FLEXCAN_QUIRK_SUPPORT_RX_FIFO)) == 2158 (FLEXCAN_QUIRK_USE_RX_MAILBOX | 2159 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2160 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR))) { 2161 dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n"); 2162 return -EINVAL; 2163 } 2164 2165 if ((devtype_data->quirks & 2166 (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2167 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)) == 2168 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR) { 2169 dev_err(&pdev->dev, 2170 "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n", 2171 devtype_data->quirks); 2172 return -EINVAL; 2173 } 2174 2175 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 2176 if (!dev) 2177 return -ENOMEM; 2178 2179 platform_set_drvdata(pdev, dev); 2180 SET_NETDEV_DEV(dev, &pdev->dev); 2181 2182 dev->netdev_ops = &flexcan_netdev_ops; 2183 dev->ethtool_ops = &flexcan_ethtool_ops; 2184 dev->irq = irq; 2185 dev->flags |= IFF_ECHO; 2186 2187 priv = netdev_priv(dev); 2188 priv->devtype_data = *devtype_data; 2189 2190 if (of_property_read_bool(pdev->dev.of_node, "big-endian") || 2191 priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) { 2192 priv->read = flexcan_read_be; 2193 priv->write = flexcan_write_be; 2194 } else { 2195 priv->read = flexcan_read_le; 2196 priv->write = flexcan_write_le; 2197 } 2198 2199 priv->dev = &pdev->dev; 2200 priv->can.clock.freq = clock_freq; 2201 priv->can.do_set_mode = flexcan_set_mode; 2202 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 2203 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 2204 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 2205 CAN_CTRLMODE_BERR_REPORTING; 2206 priv->regs = regs; 2207 priv->clk_ipg = clk_ipg; 2208 priv->clk_per = clk_per; 2209 priv->clk_src = clk_src; 2210 priv->reg_xceiver = reg_xceiver; 2211 priv->transceiver = transceiver; 2212 2213 if (transceiver) 2214 priv->can.bitrate_max = transceiver->attrs.max_link_rate; 2215 2216 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 2217 priv->irq_boff = platform_get_irq(pdev, 1); 2218 if (priv->irq_boff < 0) { 2219 err = priv->irq_boff; 2220 goto failed_platform_get_irq; 2221 } 2222 priv->irq_err = platform_get_irq(pdev, 2); 2223 if (priv->irq_err < 0) { 2224 err = priv->irq_err; 2225 goto failed_platform_get_irq; 2226 } 2227 } 2228 2229 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) { 2230 priv->irq_secondary_mb = platform_get_irq_byname(pdev, "mb-1"); 2231 if (priv->irq_secondary_mb < 0) { 2232 err = priv->irq_secondary_mb; 2233 goto failed_platform_get_irq; 2234 } 2235 } 2236 2237 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) { 2238 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | 2239 CAN_CTRLMODE_FD_NON_ISO; 2240 priv->can.bittiming_const = &flexcan_fd_bittiming_const; 2241 priv->can.fd.data_bittiming_const = 2242 &flexcan_fd_data_bittiming_const; 2243 } else { 2244 priv->can.bittiming_const = &flexcan_bittiming_const; 2245 } 2246 2247 pm_runtime_get_noresume(&pdev->dev); 2248 pm_runtime_set_active(&pdev->dev); 2249 pm_runtime_enable(&pdev->dev); 2250 2251 err = register_flexcandev(dev); 2252 if (err) { 2253 dev_err(&pdev->dev, "registering netdev failed\n"); 2254 goto failed_register; 2255 } 2256 2257 err = flexcan_setup_stop_mode(pdev); 2258 if (err < 0) { 2259 dev_err_probe(&pdev->dev, err, "setup stop mode failed\n"); 2260 goto failed_setup_stop_mode; 2261 } 2262 2263 of_can_transceiver(dev); 2264 2265 return 0; 2266 2267 failed_setup_stop_mode: 2268 unregister_flexcandev(dev); 2269 failed_register: 2270 pm_runtime_put_noidle(&pdev->dev); 2271 pm_runtime_disable(&pdev->dev); 2272 failed_platform_get_irq: 2273 free_candev(dev); 2274 return err; 2275} 2276 2277static void flexcan_remove(struct platform_device *pdev) 2278{ 2279 struct net_device *dev = platform_get_drvdata(pdev); 2280 2281 device_set_wakeup_enable(&pdev->dev, false); 2282 device_set_wakeup_capable(&pdev->dev, false); 2283 unregister_flexcandev(dev); 2284 pm_runtime_disable(&pdev->dev); 2285 free_candev(dev); 2286} 2287 2288static int __maybe_unused flexcan_suspend(struct device *device) 2289{ 2290 struct net_device *dev = dev_get_drvdata(device); 2291 struct flexcan_priv *priv = netdev_priv(dev); 2292 int err; 2293 2294 if (netif_running(dev)) { 2295 /* if wakeup is enabled, enter stop mode 2296 * else enter disabled mode. 2297 */ 2298 if (device_may_wakeup(device)) { 2299 enable_irq_wake(dev->irq); 2300 err = flexcan_enter_stop_mode(priv); 2301 if (err) 2302 return err; 2303 } else { 2304 err = flexcan_chip_stop(dev); 2305 if (err) 2306 return err; 2307 2308 flexcan_chip_interrupts_disable(dev); 2309 2310 err = flexcan_transceiver_disable(priv); 2311 if (err) 2312 return err; 2313 2314 err = pinctrl_pm_select_sleep_state(device); 2315 if (err) 2316 return err; 2317 } 2318 netif_stop_queue(dev); 2319 netif_device_detach(dev); 2320 2321 priv->can.state = CAN_STATE_SLEEPING; 2322 } 2323 2324 return 0; 2325} 2326 2327static int __maybe_unused flexcan_resume(struct device *device) 2328{ 2329 struct net_device *dev = dev_get_drvdata(device); 2330 struct flexcan_priv *priv = netdev_priv(dev); 2331 int err; 2332 2333 if (netif_running(dev)) { 2334 netif_device_attach(dev); 2335 netif_start_queue(dev); 2336 if (device_may_wakeup(device)) { 2337 disable_irq_wake(dev->irq); 2338 err = flexcan_exit_stop_mode(priv); 2339 if (err) 2340 return err; 2341 } else { 2342 err = pinctrl_pm_select_default_state(device); 2343 if (err) 2344 return err; 2345 2346 err = flexcan_transceiver_enable(priv); 2347 if (err) 2348 return err; 2349 2350 err = flexcan_chip_start(dev); 2351 if (err) { 2352 flexcan_transceiver_disable(priv); 2353 return err; 2354 } 2355 2356 flexcan_chip_interrupts_enable(dev); 2357 } 2358 2359 priv->can.state = CAN_STATE_ERROR_ACTIVE; 2360 } 2361 2362 return 0; 2363} 2364 2365static int __maybe_unused flexcan_runtime_suspend(struct device *device) 2366{ 2367 struct net_device *dev = dev_get_drvdata(device); 2368 struct flexcan_priv *priv = netdev_priv(dev); 2369 2370 flexcan_clks_disable(priv); 2371 2372 return 0; 2373} 2374 2375static int __maybe_unused flexcan_runtime_resume(struct device *device) 2376{ 2377 struct net_device *dev = dev_get_drvdata(device); 2378 struct flexcan_priv *priv = netdev_priv(dev); 2379 2380 return flexcan_clks_enable(priv); 2381} 2382 2383static int __maybe_unused flexcan_noirq_suspend(struct device *device) 2384{ 2385 struct net_device *dev = dev_get_drvdata(device); 2386 struct flexcan_priv *priv = netdev_priv(dev); 2387 2388 if (netif_running(dev)) { 2389 int err; 2390 2391 if (device_may_wakeup(device)) 2392 flexcan_enable_wakeup_irq(priv, true); 2393 2394 /* For FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI, it need ATF to send 2395 * to SM through SCMI protocol, SM will assert the IPG_STOP 2396 * signal. But all this works need the CAN clocks keep on. 2397 * After the CAN module get the IPG_STOP mode, and switch to 2398 * STOP mode, whether still keep the CAN clocks on or gate them 2399 * off depend on the Hardware design. 2400 */ 2401 if (!(device_may_wakeup(device) && 2402 priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)) { 2403 err = pm_runtime_force_suspend(device); 2404 if (err) 2405 return err; 2406 } 2407 } 2408 2409 return 0; 2410} 2411 2412static int __maybe_unused flexcan_noirq_resume(struct device *device) 2413{ 2414 struct net_device *dev = dev_get_drvdata(device); 2415 struct flexcan_priv *priv = netdev_priv(dev); 2416 2417 if (netif_running(dev)) { 2418 int err; 2419 2420 if (!(device_may_wakeup(device) && 2421 priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)) { 2422 err = pm_runtime_force_resume(device); 2423 if (err) 2424 return err; 2425 } 2426 2427 if (device_may_wakeup(device)) 2428 flexcan_enable_wakeup_irq(priv, false); 2429 } 2430 2431 return 0; 2432} 2433 2434static const struct dev_pm_ops flexcan_pm_ops = { 2435 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume) 2436 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL) 2437 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume) 2438}; 2439 2440static struct platform_driver flexcan_driver = { 2441 .driver = { 2442 .name = DRV_NAME, 2443 .pm = &flexcan_pm_ops, 2444 .of_match_table = flexcan_of_match, 2445 }, 2446 .probe = flexcan_probe, 2447 .remove = flexcan_remove, 2448 .id_table = flexcan_id_table, 2449}; 2450 2451module_platform_driver(flexcan_driver); 2452 2453MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 2454 "Marc Kleine-Budde <kernel@pengutronix.de>"); 2455MODULE_LICENSE("GPL v2"); 2456MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
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