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sunxi_nand.c
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linux-6.19.14/drivers/mtd/nand/raw/sunxi_nand.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com> 4 * 5 * Derived from: 6 * https://github.com/yuq/sunxi-nfc-mtd 7 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com> 8 * 9 * https://github.com/hno/Allwinner-Info 10 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström> 11 * 12 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com> 13 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org> 14 */ 15 16#include <linux/dma-mapping.h> 17#include <linux/slab.h> 18#include <linux/module.h> 19#include <linux/moduleparam.h> 20#include <linux/platform_device.h> 21#include <linux/of.h> 22#include <linux/mtd/mtd.h> 23#include <linux/mtd/rawnand.h> 24#include <linux/mtd/partitions.h> 25#include <linux/clk.h> 26#include <linux/delay.h> 27#include <linux/dmaengine.h> 28#include <linux/interrupt.h> 29#include <linux/iopoll.h> 30#include <linux/reset.h> 31 32/* non compile-time field get/prep */ 33#undef field_get 34#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 35#undef field_prep 36#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 37 38#define NFC_REG_CTL 0x0000 39#define NFC_REG_ST 0x0004 40#define NFC_REG_INT 0x0008 41#define NFC_REG_TIMING_CTL 0x000C 42#define NFC_REG_TIMING_CFG 0x0010 43#define NFC_REG_ADDR_LOW 0x0014 44#define NFC_REG_ADDR_HIGH 0x0018 45#define NFC_REG_SECTOR_NUM 0x001C 46#define NFC_REG_CNT 0x0020 47#define NFC_REG_CMD 0x0024 48#define NFC_REG_RCMD_SET 0x0028 49#define NFC_REG_WCMD_SET 0x002C 50#define NFC_REG_A10_IO_DATA 0x0030 51#define NFC_REG_A23_IO_DATA 0x0300 52#define NFC_REG_ECC_CTL 0x0034 53#define NFC_REG_ECC_ST 0x0038 54#define NFC_REG_H6_PAT_FOUND 0x003C 55#define NFC_REG_A10_ECC_ERR_CNT 0x0040 56#define NFC_REG_H6_ECC_ERR_CNT 0x0050 57#define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & ~0x3) 58#define NFC_REG_H6_RDATA_CTL 0x0044 59#define NFC_REG_H6_RDATA_0 0x0048 60#define NFC_REG_H6_RDATA_1 0x004C 61#define NFC_REG_A10_USER_DATA 0x0050 62#define NFC_REG_H6_USER_DATA 0x0080 63#define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) 64#define NFC_REG_H6_USER_DATA_LEN 0x0070 65/* A USER_DATA_LEN register can hold the length of 8 USER_DATA registers */ 66#define NFC_REG_USER_DATA_LEN_CAPACITY 8 67#define NFC_REG_USER_DATA_LEN(nfc, step) \ 68 (nfc->caps->reg_user_data_len + \ 69 ((step) / NFC_REG_USER_DATA_LEN_CAPACITY) * 4) 70#define NFC_REG_SPARE_AREA(nfc) (nfc->caps->reg_spare_area) 71#define NFC_REG_A10_SPARE_AREA 0x00A0 72#define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id) 73#define NFC_REG_A10_PAT_ID 0x00A4 74#define NFC_REG_MDMA_ADDR 0x00C0 75#define NFC_REG_MDMA_CNT 0x00C4 76#define NFC_REG_H6_EFNAND_STATUS 0x0110 77#define NFC_REG_H6_SPARE_AREA 0x0114 78#define NFC_REG_H6_PAT_ID 0x0118 79#define NFC_REG_H6_DDR2_SPEC_CTL 0x011C 80#define NFC_REG_H6_NDMA_MODE_CTL 0x0120 81#define NFC_REG_H6_MDMA_DLBA_REG 0x0200 82#define NFC_REG_H6_MDMA_STA 0x0204 83#define NFC_REG_H6_MDMA_INT_MAS 0x0208 84#define NFC_REG_H6_MDMA_DESC_ADDR 0x020C 85#define NFC_REG_H6_MDMA_BUF_ADDR 0x0210 86#define NFC_REG_H6_MDMA_CNT 0x0214 87 88#define NFC_RAM0_BASE 0x0400 89#define NFC_RAM1_BASE 0x0800 90 91/* define bit use in NFC_CTL */ 92#define NFC_EN BIT(0) 93#define NFC_RESET BIT(1) 94#define NFC_BUS_WIDTH_MSK BIT(2) 95#define NFC_BUS_WIDTH_8 (0 << 2) 96#define NFC_BUS_WIDTH_16 (1 << 2) 97#define NFC_RB_SEL_MSK BIT(3) 98#define NFC_RB_SEL(x) ((x) << 3) 99/* CE_SEL BIT 27 is meant to be used for GPIO chipselect */ 100#define NFC_CE_SEL_MSK GENMASK(26, 24) 101#define NFC_CE_SEL(x) ((x) << 24) 102#define NFC_CE_CTL BIT(6) 103#define NFC_PAGE_SHIFT_MSK GENMASK(11, 8) 104#define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8) 105#define NFC_SAM BIT(12) 106#define NFC_RAM_METHOD BIT(14) 107#define NFC_DMA_TYPE_NORMAL BIT(15) 108#define NFC_DEBUG_CTL BIT(31) 109 110/* define bit use in NFC_ST */ 111#define NFC_RB_B2R BIT(0) 112#define NFC_CMD_INT_FLAG BIT(1) 113#define NFC_DMA_INT_FLAG BIT(2) 114#define NFC_CMD_FIFO_STATUS BIT(3) 115#define NFC_STA BIT(4) 116#define NFC_NATCH_INT_FLAG BIT(5) 117#define NFC_RB_STATE(x) BIT(x + 8) 118#define NFC_RB_STATE_MSK GENMASK(11, 8) 119#define NDFC_RDATA_STA_1 BIT(12) 120#define NDFC_RDATA_STA_0 BIT(13) 121 122/* define bit use in NFC_INT */ 123#define NFC_B2R_INT_ENABLE BIT(0) 124#define NFC_CMD_INT_ENABLE BIT(1) 125#define NFC_DMA_INT_ENABLE BIT(2) 126#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \ 127 NFC_CMD_INT_ENABLE | \ 128 NFC_DMA_INT_ENABLE) 129 130/* define bit use in NFC_TIMING_CTL */ 131#define NFC_TIMING_CTL_EDO BIT(8) 132#define NFC_TIMING_CTL_E_EDO BIT(9) 133 134/* define NFC_TIMING_CFG register layout */ 135#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \ 136 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \ 137 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \ 138 (((tCAD) & 0x7) << 8)) 139 140#define NFC_TIMING_CFG2(tCDQSS, tSC, tCLHZ, tCSS, tWC) \ 141 ((((tCDQSS) & 0x1) << 11) | (((tSC) & 0x3) << 12) | \ 142 (((tCLHZ) & 0x3) << 14) | (((tCSS) & 0x3) << 16) | \ 143 (((tWC) & 0x3) << 18)) 144 145/* define bit use in NFC_CMD */ 146#define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0) 147#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) /* 15-10 reserved on H6 */ 148#define NFC_CMD_ADR_NUM_MSK GENMASK(9, 8) 149#define NFC_CMD(x) (x) 150#define NFC_ADR_NUM_MSK GENMASK(18, 16) 151#define NFC_ADR_NUM(x) (((x) - 1) << 16) 152#define NFC_SEND_ADR BIT(19) 153#define NFC_ACCESS_DIR BIT(20) 154#define NFC_DATA_TRANS BIT(21) 155#define NFC_SEND_CMD1 BIT(22) 156#define NFC_WAIT_FLAG BIT(23) 157#define NFC_SEND_CMD2 BIT(24) 158#define NFC_SEQ BIT(25) 159#define NFC_DATA_SWAP_METHOD BIT(26) 160#define NFC_ROW_AUTO_INC BIT(27) 161#define NFC_H6_SEND_RND_CMD2 BIT(27) 162#define NFC_SEND_CMD3 BIT(28) 163#define NFC_SEND_CMD4 BIT(29) 164#define NFC_CMD_TYPE_MSK GENMASK(31, 30) 165#define NFC_NORMAL_OP (0 << 30) 166#define NFC_ECC_OP (1 << 30) 167#define NFC_PAGE_OP (2U << 30) 168 169/* define bit use in NFC_RCMD_SET */ 170#define NFC_READ_CMD_MSK GENMASK(7, 0) 171#define NFC_RND_READ_CMD0_MSK GENMASK(15, 8) 172#define NFC_RND_READ_CMD1_MSK GENMASK(23, 16) 173#define NFC_RND_READ_CMD2_MSK GENMASK(31, 24) 174 175/* define bit use in NFC_WCMD_SET */ 176#define NFC_PROGRAM_CMD_MSK GENMASK(7, 0) 177#define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8) 178#define NFC_READ_CMD0_MSK GENMASK(23, 16) 179#define NFC_READ_CMD1_MSK GENMASK(31, 24) 180 181/* define bit use in NFC_ECC_CTL */ 182#define NFC_ECC_EN BIT(0) 183#define NFC_ECC_PIPELINE BIT(3) 184#define NFC_ECC_EXCEPTION BIT(4) 185#define NFC_ECC_BLOCK_SIZE_MSK BIT(5) 186#define NFC_ECC_BLOCK_512 BIT(5) 187#define NFC_RANDOM_EN(nfc) (nfc->caps->random_en_mask) 188#define NFC_RANDOM_DIRECTION(nfc) (nfc->caps->random_dir_mask) 189#define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask) 190#define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x)) 191/* RANDOM_PAGE_SIZE: 0: ECC block size 1: page size */ 192#define NFC_A23_RANDOM_PAGE_SIZE BIT(11) 193#define NFC_H6_RANDOM_PAGE_SIZE BIT(7) 194#define NFC_RANDOM_SEED_MSK GENMASK(30, 16) 195#define NFC_RANDOM_SEED(x) ((x) << 16) 196 197/* define bit use in NFC_ECC_ST */ 198#define NFC_ECC_ERR(x) BIT(x) 199#define NFC_ECC_ERR_MSK(nfc) (nfc->caps->ecc_err_mask) 200 201/* 202 * define bit use in NFC_REG_PAT_FOUND 203 * For A10/A23, NFC_REG_PAT_FOUND == NFC_ECC_ST register 204 */ 205#define NFC_ECC_PAT_FOUND_MSK(nfc) (nfc->caps->pat_found_mask) 206 207#define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff) 208 209#define NFC_USER_DATA_LEN_MSK(step) \ 210 (0xf << (((step) % NFC_REG_USER_DATA_LEN_CAPACITY) * 4)) 211 212#define NFC_DEFAULT_TIMEOUT_MS 1000 213 214#define NFC_MAX_CS 7 215 216/* 217 * On A10/A23, this is the size of the NDFC User Data Register, containing the 218 * mandatory user data bytes following the ECC for each ECC step. 219 * Thus, for each ECC step, we need the ECC bytes + USER_DATA_SZ. 220 * Those bits are currently unsused, and kept as default value 0xffffffff. 221 * 222 * On H6/H616, this size became configurable, from 0 bytes to 32, via the 223 * USER_DATA_LEN registers. 224 */ 225#define USER_DATA_SZ 4 226 227/** 228 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select 229 * 230 * @cs: the NAND CS id used to communicate with a NAND Chip 231 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC 232 */ 233struct sunxi_nand_chip_sel { 234 u8 cs; 235 s8 rb; 236}; 237 238/** 239 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support 240 * 241 * @ecc_ctl: ECC_CTL register value for this NAND chip 242 */ 243struct sunxi_nand_hw_ecc { 244 u32 ecc_ctl; 245}; 246 247/** 248 * struct sunxi_nand_chip - stores NAND chip device related information 249 * 250 * @node: used to store NAND chips into a list 251 * @nand: base NAND chip structure 252 * @ecc: ECC controller structure 253 * @clk_rate: clk_rate required for this NAND chip 254 * @timing_cfg: TIMING_CFG register value for this NAND chip 255 * @timing_ctl: TIMING_CTL register value for this NAND chip 256 * @nsels: number of CS lines required by the NAND chip 257 * @sels: array of CS lines descriptions 258 */ 259struct sunxi_nand_chip { 260 struct list_head node; 261 struct nand_chip nand; 262 struct sunxi_nand_hw_ecc ecc; 263 unsigned long clk_rate; 264 u32 timing_cfg; 265 u32 timing_ctl; 266 int nsels; 267 struct sunxi_nand_chip_sel sels[] __counted_by(nsels); 268}; 269 270static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand) 271{ 272 return container_of(nand, struct sunxi_nand_chip, nand); 273} 274 275/* 276 * NAND Controller capabilities structure: stores NAND controller capabilities 277 * for distinction between compatible strings. 278 * 279 * @has_mdma: Use mbus dma mode, otherwise general dma 280 * through MBUS on A23/A33 needs extra configuration. 281 * @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks 282 * @has_ecc_clk: If the controller needs an ECC clock. 283 * @has_mbus_clk: If the controller needs a mbus clock. 284 * @reg_io_data: I/O data register 285 * @reg_ecc_err_cnt: ECC error counter register 286 * @reg_user_data: User data register 287 * @reg_user_data_len: User data length register 288 * @reg_spare_area: Spare Area Register 289 * @reg_pat_id: Pattern ID Register 290 * @reg_pat_found: Data Pattern Status Register 291 * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register 292 * @random_dir_mask: RANDOM_DIRECTION mask in NFC_ECC_CTL register 293 * @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register 294 * @ecc_err_mask: NFC_ECC_ERR mask in NFC_ECC_ST register 295 * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register 296 * @dma_maxburst: DMA maxburst 297 * @ecc_strengths: Available ECC strengths array 298 * @nstrengths: Size of @ecc_strengths 299 * @max_ecc_steps: Maximum supported steps for ECC, this is also the 300 * number of user data registers 301 * @user_data_len_tab: Table of lenghts supported by USER_DATA_LEN register 302 * The table index is the value to set in NFC_USER_DATA_LEN 303 * registers, and the corresponding value is the number of 304 * bytes to write 305 * @nuser_data_tab: Size of @user_data_len_tab 306 * @sram_size: Size of the NAND controller SRAM 307 */ 308struct sunxi_nfc_caps { 309 bool has_mdma; 310 bool has_ecc_block_512; 311 bool has_ecc_clk; 312 bool has_mbus_clk; 313 unsigned int reg_io_data; 314 unsigned int reg_ecc_err_cnt; 315 unsigned int reg_user_data; 316 unsigned int reg_user_data_len; 317 unsigned int reg_spare_area; 318 unsigned int reg_pat_id; 319 unsigned int reg_pat_found; 320 unsigned int random_en_mask; 321 unsigned int random_dir_mask; 322 unsigned int ecc_mode_mask; 323 unsigned int ecc_err_mask; 324 unsigned int pat_found_mask; 325 unsigned int dma_maxburst; 326 const u8 *ecc_strengths; 327 unsigned int nstrengths; 328 const u8 *user_data_len_tab; 329 unsigned int nuser_data_tab; 330 unsigned int max_ecc_steps; 331 int sram_size; 332}; 333 334/** 335 * struct sunxi_nfc - stores sunxi NAND controller information 336 * 337 * @controller: base controller structure 338 * @dev: parent device (used to print error messages) 339 * @regs: NAND controller registers 340 * @ahb_clk: NAND controller AHB clock 341 * @mod_clk: NAND controller mod clock 342 * @ecc_clk: NAND controller ECC clock 343 * @mbus_clk: NAND controller MBUS clock 344 * @reset: NAND controller reset line 345 * @assigned_cs: bitmask describing already assigned CS lines 346 * @clk_rate: NAND controller current clock rate 347 * @chips: a list containing all the NAND chips attached to this NAND 348 * controller 349 * @complete: a completion object used to wait for NAND controller events 350 * @dmac: the DMA channel attached to the NAND controller 351 * @caps: NAND Controller capabilities 352 */ 353struct sunxi_nfc { 354 struct nand_controller controller; 355 struct device *dev; 356 void __iomem *regs; 357 struct clk *ahb_clk; 358 struct clk *mod_clk; 359 struct clk *ecc_clk; 360 struct clk *mbus_clk; 361 struct reset_control *reset; 362 unsigned long assigned_cs; 363 unsigned long clk_rate; 364 struct list_head chips; 365 struct completion complete; 366 struct dma_chan *dmac; 367 const struct sunxi_nfc_caps *caps; 368}; 369 370static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_controller *ctrl) 371{ 372 return container_of(ctrl, struct sunxi_nfc, controller); 373} 374 375static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id) 376{ 377 struct sunxi_nfc *nfc = dev_id; 378 u32 st = readl(nfc->regs + NFC_REG_ST); 379 u32 ien = readl(nfc->regs + NFC_REG_INT); 380 381 if (!(ien & st)) 382 return IRQ_NONE; 383 384 if ((ien & st) == ien) 385 complete(&nfc->complete); 386 387 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST); 388 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT); 389 390 return IRQ_HANDLED; 391} 392 393static int sunxi_nfc_wait_events(struct sunxi_nfc *nfc, u32 events, 394 bool use_polling, unsigned int timeout_ms) 395{ 396 int ret; 397 398 if (events & ~NFC_INT_MASK) 399 return -EINVAL; 400 401 if (!timeout_ms) 402 timeout_ms = NFC_DEFAULT_TIMEOUT_MS; 403 404 if (!use_polling) { 405 init_completion(&nfc->complete); 406 407 writel(events, nfc->regs + NFC_REG_INT); 408 409 ret = wait_for_completion_timeout(&nfc->complete, 410 msecs_to_jiffies(timeout_ms)); 411 if (!ret) 412 ret = -ETIMEDOUT; 413 else 414 ret = 0; 415 416 writel(0, nfc->regs + NFC_REG_INT); 417 } else { 418 u32 status; 419 420 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status, 421 (status & events) == events, 1, 422 timeout_ms * 1000); 423 } 424 425 writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST); 426 427 if (ret) 428 dev_err(nfc->dev, "wait interrupt timedout\n"); 429 430 return ret; 431} 432 433static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc) 434{ 435 u32 status; 436 int ret; 437 438 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status, 439 !(status & NFC_CMD_FIFO_STATUS), 1, 440 NFC_DEFAULT_TIMEOUT_MS * 1000); 441 if (ret) 442 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n"); 443 444 return ret; 445} 446 447static int sunxi_nfc_rst(struct sunxi_nfc *nfc) 448{ 449 u32 ctl; 450 int ret; 451 452 writel(0, nfc->regs + NFC_REG_ECC_CTL); 453 writel(NFC_RESET, nfc->regs + NFC_REG_CTL); 454 455 ret = readl_poll_timeout(nfc->regs + NFC_REG_CTL, ctl, 456 !(ctl & NFC_RESET), 1, 457 NFC_DEFAULT_TIMEOUT_MS * 1000); 458 if (ret) 459 dev_err(nfc->dev, "wait for NAND controller reset timedout\n"); 460 461 return ret; 462} 463 464static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf, 465 int chunksize, int nchunks, 466 enum dma_data_direction ddir, 467 struct scatterlist *sg) 468{ 469 struct dma_async_tx_descriptor *dmad; 470 enum dma_transfer_direction tdir; 471 dma_cookie_t dmat; 472 int ret; 473 474 if (ddir == DMA_FROM_DEVICE) 475 tdir = DMA_DEV_TO_MEM; 476 else 477 tdir = DMA_MEM_TO_DEV; 478 479 sg_init_one(sg, buf, nchunks * chunksize); 480 ret = dma_map_sg(nfc->dev, sg, 1, ddir); 481 if (!ret) 482 return -ENOMEM; 483 484 if (!nfc->caps->has_mdma) { 485 dmad = dmaengine_prep_slave_sg(nfc->dmac, sg, 1, tdir, DMA_CTRL_ACK); 486 if (!dmad) { 487 ret = -EINVAL; 488 goto err_unmap_buf; 489 } 490 } 491 492 writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD, 493 nfc->regs + NFC_REG_CTL); 494 writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM); 495 writel(chunksize, nfc->regs + NFC_REG_CNT); 496 497 if (nfc->caps->has_mdma) { 498 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_DMA_TYPE_NORMAL, 499 nfc->regs + NFC_REG_CTL); 500 writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT); 501 writel(sg_dma_address(sg), nfc->regs + NFC_REG_MDMA_ADDR); 502 } else { 503 dmat = dmaengine_submit(dmad); 504 505 ret = dma_submit_error(dmat); 506 if (ret) 507 goto err_clr_dma_flag; 508 } 509 510 return 0; 511 512err_clr_dma_flag: 513 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD, 514 nfc->regs + NFC_REG_CTL); 515 516err_unmap_buf: 517 dma_unmap_sg(nfc->dev, sg, 1, ddir); 518 return ret; 519} 520 521static void sunxi_nfc_dma_op_cleanup(struct sunxi_nfc *nfc, 522 enum dma_data_direction ddir, 523 struct scatterlist *sg) 524{ 525 dma_unmap_sg(nfc->dev, sg, 1, ddir); 526 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD, 527 nfc->regs + NFC_REG_CTL); 528} 529 530static void sunxi_nfc_select_chip(struct nand_chip *nand, unsigned int cs) 531{ 532 struct mtd_info *mtd = nand_to_mtd(nand); 533 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 534 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 535 struct sunxi_nand_chip_sel *sel; 536 u32 ctl; 537 538 if (cs >= sunxi_nand->nsels) 539 return; 540 541 ctl = readl(nfc->regs + NFC_REG_CTL) & 542 ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN); 543 544 sel = &sunxi_nand->sels[cs]; 545 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN | NFC_PAGE_SHIFT(nand->page_shift); 546 if (sel->rb >= 0) 547 ctl |= NFC_RB_SEL(sel->rb); 548 549 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA(nfc)); 550 551 if (nfc->clk_rate != sunxi_nand->clk_rate) { 552 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate); 553 nfc->clk_rate = sunxi_nand->clk_rate; 554 } 555 556 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL); 557 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG); 558 writel(ctl, nfc->regs + NFC_REG_CTL); 559} 560 561static void sunxi_nfc_read_buf(struct nand_chip *nand, uint8_t *buf, int len) 562{ 563 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 564 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 565 int ret; 566 int cnt; 567 int offs = 0; 568 u32 tmp; 569 570 while (len > offs) { 571 bool poll = false; 572 573 cnt = min(len - offs, nfc->caps->sram_size); 574 575 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 576 if (ret) 577 break; 578 579 writel(cnt, nfc->regs + NFC_REG_CNT); 580 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD; 581 writel(tmp, nfc->regs + NFC_REG_CMD); 582 583 /* Arbitrary limit for polling mode */ 584 if (cnt < 64) 585 poll = true; 586 587 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0); 588 if (ret) 589 break; 590 591 if (buf) 592 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE, 593 cnt); 594 offs += cnt; 595 } 596} 597 598static void sunxi_nfc_write_buf(struct nand_chip *nand, const uint8_t *buf, 599 int len) 600{ 601 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 602 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 603 int ret; 604 int cnt; 605 int offs = 0; 606 u32 tmp; 607 608 while (len > offs) { 609 bool poll = false; 610 611 cnt = min(len - offs, nfc->caps->sram_size); 612 613 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 614 if (ret) 615 break; 616 617 writel(cnt, nfc->regs + NFC_REG_CNT); 618 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt); 619 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | 620 NFC_ACCESS_DIR; 621 writel(tmp, nfc->regs + NFC_REG_CMD); 622 623 /* Arbitrary limit for polling mode */ 624 if (cnt < 64) 625 poll = true; 626 627 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0); 628 if (ret) 629 break; 630 631 offs += cnt; 632 } 633} 634 635/* These seed values have been extracted from Allwinner's BSP */ 636static const u16 sunxi_nfc_randomizer_page_seeds[] = { 637 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72, 638 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436, 639 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d, 640 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130, 641 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56, 642 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55, 643 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb, 644 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17, 645 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62, 646 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064, 647 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126, 648 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e, 649 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3, 650 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b, 651 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d, 652 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db, 653}; 654 655/* 656 * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds 657 * have been generated using 658 * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what 659 * the randomizer engine does internally before de/scrambling OOB data. 660 * 661 * Those tables are statically defined to avoid calculating randomizer state 662 * at runtime. 663 */ 664static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = { 665 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64, 666 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409, 667 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617, 668 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d, 669 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91, 670 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d, 671 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab, 672 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8, 673 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8, 674 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b, 675 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5, 676 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a, 677 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891, 678 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36, 679 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd, 680 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0, 681}; 682 683static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = { 684 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6, 685 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982, 686 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9, 687 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07, 688 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e, 689 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2, 690 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c, 691 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f, 692 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc, 693 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e, 694 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8, 695 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68, 696 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d, 697 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179, 698 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601, 699 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd, 700}; 701 702static u16 sunxi_nfc_randomizer_step(u16 state, int count) 703{ 704 state &= 0x7fff; 705 706 /* 707 * This loop is just a simple implementation of a Fibonacci LFSR using 708 * the x16 + x15 + 1 polynomial. 709 */ 710 while (count--) 711 state = ((state >> 1) | 712 (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff; 713 714 return state; 715} 716 717static u16 sunxi_nfc_randomizer_state(struct nand_chip *nand, int page, 718 bool ecc) 719{ 720 struct mtd_info *mtd = nand_to_mtd(nand); 721 const u16 *seeds = sunxi_nfc_randomizer_page_seeds; 722 int mod = mtd_div_by_ws(mtd->erasesize, mtd); 723 724 if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds)) 725 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds); 726 727 if (ecc) { 728 if (mtd->ecc_step_size == 512) 729 seeds = sunxi_nfc_randomizer_ecc512_seeds; 730 else 731 seeds = sunxi_nfc_randomizer_ecc1024_seeds; 732 } 733 734 return seeds[page % mod]; 735} 736 737static void sunxi_nfc_randomizer_config(struct nand_chip *nand, int page, 738 bool ecc) 739{ 740 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 741 u32 ecc_ctl; 742 u16 state; 743 744 if (!(nand->options & NAND_NEED_SCRAMBLING)) 745 return; 746 747 state = sunxi_nfc_randomizer_state(nand, page, ecc); 748 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK; 749 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL); 750} 751 752static void sunxi_nfc_randomizer_enable(struct nand_chip *nand) 753{ 754 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 755 756 if (!(nand->options & NAND_NEED_SCRAMBLING)) 757 return; 758 759 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN(nfc), 760 nfc->regs + NFC_REG_ECC_CTL); 761} 762 763static void sunxi_nfc_randomizer_disable(struct nand_chip *nand) 764{ 765 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 766 767 if (!(nand->options & NAND_NEED_SCRAMBLING)) 768 return; 769 770 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN(nfc), 771 nfc->regs + NFC_REG_ECC_CTL); 772} 773 774static void sunxi_nfc_randomize_bbm(struct nand_chip *nand, int page, u8 *bbm) 775{ 776 u16 state = sunxi_nfc_randomizer_state(nand, page, true); 777 778 bbm[0] ^= state; 779 bbm[1] ^= sunxi_nfc_randomizer_step(state, 8); 780} 781 782static void sunxi_nfc_randomizer_write_buf(struct nand_chip *nand, 783 const uint8_t *buf, int len, 784 bool ecc, int page) 785{ 786 sunxi_nfc_randomizer_config(nand, page, ecc); 787 sunxi_nfc_randomizer_enable(nand); 788 sunxi_nfc_write_buf(nand, buf, len); 789 sunxi_nfc_randomizer_disable(nand); 790} 791 792static void sunxi_nfc_randomizer_read_buf(struct nand_chip *nand, uint8_t *buf, 793 int len, bool ecc, int page) 794{ 795 sunxi_nfc_randomizer_config(nand, page, ecc); 796 sunxi_nfc_randomizer_enable(nand); 797 sunxi_nfc_read_buf(nand, buf, len); 798 sunxi_nfc_randomizer_disable(nand); 799} 800 801static void sunxi_nfc_hw_ecc_enable(struct nand_chip *nand) 802{ 803 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 804 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 805 806 writel(sunxi_nand->ecc.ecc_ctl, nfc->regs + NFC_REG_ECC_CTL); 807} 808 809static void sunxi_nfc_hw_ecc_disable(struct nand_chip *nand) 810{ 811 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 812 813 writel(0, nfc->regs + NFC_REG_ECC_CTL); 814} 815 816static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf) 817{ 818 buf[0] = user_data; 819 buf[1] = user_data >> 8; 820 buf[2] = user_data >> 16; 821 buf[3] = user_data >> 24; 822} 823 824static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf) 825{ 826 return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24); 827} 828 829static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip *nand, u8 *oob, 830 int step, bool bbm, int page) 831{ 832 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 833 834 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(nfc, step)), oob); 835 836 /* De-randomize the Bad Block Marker. */ 837 if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) 838 sunxi_nfc_randomize_bbm(nand, page, oob); 839} 840 841/* 842 * On H6/H6 the user_data length has to be set in specific registers 843 * before writing. 844 */ 845static void sunxi_nfc_reset_user_data_len(struct sunxi_nfc *nfc) 846{ 847 int loop_step = NFC_REG_USER_DATA_LEN_CAPACITY; 848 849 /* not all SoCs have this register */ 850 if (!nfc->caps->reg_user_data_len) 851 return; 852 853 for (int i = 0; i < nfc->caps->max_ecc_steps; i += loop_step) 854 writel(0, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, i)); 855} 856 857static void sunxi_nfc_set_user_data_len(struct sunxi_nfc *nfc, 858 int len, int step) 859{ 860 bool found = false; 861 u32 val; 862 int i; 863 864 /* not all SoCs have this register */ 865 if (!nfc->caps->reg_user_data_len) 866 return; 867 868 for (i = 0; i < nfc->caps->nuser_data_tab; i++) { 869 if (len == nfc->caps->user_data_len_tab[i]) { 870 found = true; 871 break; 872 } 873 } 874 875 if (!found) { 876 dev_warn(nfc->dev, 877 "Unsupported length for user data reg: %d\n", len); 878 return; 879 } 880 881 val = readl(nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step)); 882 883 val &= ~NFC_USER_DATA_LEN_MSK(step); 884 val |= field_prep(NFC_USER_DATA_LEN_MSK(step), i); 885 writel(val, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step)); 886} 887 888static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand, 889 const u8 *oob, int step, 890 bool bbm, int page) 891{ 892 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 893 u8 user_data[USER_DATA_SZ]; 894 895 /* Randomize the Bad Block Marker. */ 896 if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) { 897 memcpy(user_data, oob, sizeof(user_data)); 898 sunxi_nfc_randomize_bbm(nand, page, user_data); 899 oob = user_data; 900 } 901 902 writel(sunxi_nfc_buf_to_user_data(oob), 903 nfc->regs + NFC_REG_USER_DATA(nfc, step)); 904} 905 906static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand, 907 unsigned int *max_bitflips, int ret) 908{ 909 struct mtd_info *mtd = nand_to_mtd(nand); 910 911 if (ret < 0) { 912 mtd->ecc_stats.failed++; 913 } else { 914 mtd->ecc_stats.corrected += ret; 915 *max_bitflips = max_t(unsigned int, *max_bitflips, ret); 916 } 917} 918 919static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *oob, 920 int step, u32 status, u32 pattern_found, 921 bool *erased) 922{ 923 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 924 struct nand_ecc_ctrl *ecc = &nand->ecc; 925 u32 tmp; 926 927 *erased = false; 928 929 if (status & NFC_ECC_ERR(step)) 930 return -EBADMSG; 931 932 if (pattern_found & BIT(step)) { 933 u8 pattern; 934 935 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID(nfc)) & 0x1))) { 936 pattern = 0x0; 937 } else { 938 pattern = 0xff; 939 *erased = true; 940 } 941 942 if (data) 943 memset(data, pattern, ecc->size); 944 945 if (oob) 946 memset(oob, pattern, ecc->bytes + USER_DATA_SZ); 947 948 return 0; 949 } 950 951 tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(nfc, step)); 952 953 return NFC_ECC_ERR_CNT(step, tmp); 954} 955 956static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip *nand, 957 u8 *data, int data_off, 958 u8 *oob, int oob_off, 959 int *cur_off, 960 unsigned int *max_bitflips, 961 bool bbm, bool oob_required, int page) 962{ 963 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 964 struct nand_ecc_ctrl *ecc = &nand->ecc; 965 int raw_mode = 0; 966 u32 pattern_found; 967 bool erased; 968 int ret; 969 970 if (*cur_off != data_off) 971 nand_change_read_column_op(nand, data_off, NULL, 0, false); 972 973 sunxi_nfc_randomizer_read_buf(nand, NULL, ecc->size, false, page); 974 975 if (data_off + ecc->size != oob_off) 976 nand_change_read_column_op(nand, oob_off, NULL, 0, false); 977 978 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 979 if (ret) 980 return ret; 981 982 sunxi_nfc_reset_user_data_len(nfc); 983 sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); 984 sunxi_nfc_randomizer_config(nand, page, false); 985 sunxi_nfc_randomizer_enable(nand); 986 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP, 987 nfc->regs + NFC_REG_CMD); 988 989 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0); 990 sunxi_nfc_randomizer_disable(nand); 991 if (ret) 992 return ret; 993 994 *cur_off = oob_off + ecc->bytes + USER_DATA_SZ; 995 996 pattern_found = readl(nfc->regs + nfc->caps->reg_pat_found); 997 pattern_found = field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); 998 999 ret = sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0, 1000 readl(nfc->regs + NFC_REG_ECC_ST), 1001 pattern_found, 1002 &erased); 1003 if (erased) 1004 return 1; 1005 1006 if (ret < 0) { 1007 /* 1008 * Re-read the data with the randomizer disabled to identify 1009 * bitflips in erased pages. 1010 */ 1011 if (nand->options & NAND_NEED_SCRAMBLING) 1012 nand_change_read_column_op(nand, data_off, data, 1013 ecc->size, false); 1014 else 1015 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, 1016 ecc->size); 1017 1018 nand_change_read_column_op(nand, oob_off, oob, 1019 ecc->bytes + USER_DATA_SZ, false); 1020 1021 ret = nand_check_erased_ecc_chunk(data, ecc->size, oob, 1022 ecc->bytes + USER_DATA_SZ, 1023 NULL, 0, ecc->strength); 1024 if (ret >= 0) 1025 raw_mode = 1; 1026 } else { 1027 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size); 1028 1029 if (oob_required) { 1030 nand_change_read_column_op(nand, oob_off, NULL, 0, 1031 false); 1032 sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + USER_DATA_SZ, 1033 true, page); 1034 1035 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0, 1036 bbm, page); 1037 } 1038 } 1039 1040 sunxi_nfc_hw_ecc_update_stats(nand, max_bitflips, ret); 1041 1042 return raw_mode; 1043} 1044 1045static void sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip *nand, 1046 u8 *oob, int *cur_off, 1047 bool randomize, int page) 1048{ 1049 struct mtd_info *mtd = nand_to_mtd(nand); 1050 struct nand_ecc_ctrl *ecc = &nand->ecc; 1051 int offset = ((ecc->bytes + 4) * ecc->steps); 1052 int len = mtd->oobsize - offset; 1053 1054 if (len <= 0) 1055 return; 1056 1057 if (!cur_off || *cur_off != offset) 1058 nand_change_read_column_op(nand, mtd->writesize, NULL, 0, 1059 false); 1060 1061 if (!randomize) 1062 sunxi_nfc_read_buf(nand, oob + offset, len); 1063 else 1064 sunxi_nfc_randomizer_read_buf(nand, oob + offset, len, 1065 false, page); 1066 1067 if (cur_off) 1068 *cur_off = mtd->oobsize + mtd->writesize; 1069} 1070 1071static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip *nand, uint8_t *buf, 1072 int oob_required, int page, 1073 int nchunks) 1074{ 1075 bool randomized = nand->options & NAND_NEED_SCRAMBLING; 1076 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 1077 struct mtd_info *mtd = nand_to_mtd(nand); 1078 struct nand_ecc_ctrl *ecc = &nand->ecc; 1079 unsigned int max_bitflips = 0; 1080 int ret, i, raw_mode = 0; 1081 struct scatterlist sg; 1082 u32 status, pattern_found, wait; 1083 1084 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 1085 if (ret) 1086 return ret; 1087 1088 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, nchunks, 1089 DMA_FROM_DEVICE, &sg); 1090 if (ret) 1091 return ret; 1092 1093 sunxi_nfc_hw_ecc_enable(nand); 1094 sunxi_nfc_reset_user_data_len(nfc); 1095 sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); 1096 sunxi_nfc_randomizer_config(nand, page, false); 1097 sunxi_nfc_randomizer_enable(nand); 1098 1099 writel((NAND_CMD_RNDOUTSTART << 16) | (NAND_CMD_RNDOUT << 8) | 1100 NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET); 1101 1102 wait = NFC_CMD_INT_FLAG; 1103 1104 if (nfc->caps->has_mdma) 1105 wait |= NFC_DMA_INT_FLAG; 1106 else 1107 dma_async_issue_pending(nfc->dmac); 1108 1109 writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD | NFC_DATA_TRANS, 1110 nfc->regs + NFC_REG_CMD); 1111 1112 ret = sunxi_nfc_wait_events(nfc, wait, false, 0); 1113 if (ret && !nfc->caps->has_mdma) 1114 dmaengine_terminate_all(nfc->dmac); 1115 1116 sunxi_nfc_randomizer_disable(nand); 1117 sunxi_nfc_hw_ecc_disable(nand); 1118 1119 sunxi_nfc_dma_op_cleanup(nfc, DMA_FROM_DEVICE, &sg); 1120 1121 if (ret) 1122 return ret; 1123 1124 status = readl(nfc->regs + NFC_REG_ECC_ST); 1125 pattern_found = readl(nfc->regs + nfc->caps->reg_pat_found); 1126 pattern_found = field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); 1127 1128 for (i = 0; i < nchunks; i++) { 1129 int data_off = i * ecc->size; 1130 int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1131 u8 *data = buf + data_off; 1132 u8 *oob = nand->oob_poi + oob_off; 1133 bool erased; 1134 1135 ret = sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL, 1136 oob_required ? oob : NULL, 1137 i, status, pattern_found, 1138 &erased); 1139 1140 /* ECC errors are handled in the second loop. */ 1141 if (ret < 0) 1142 continue; 1143 1144 if (oob_required && !erased) { 1145 /* TODO: use DMA to retrieve OOB */ 1146 nand_change_read_column_op(nand, 1147 mtd->writesize + oob_off, 1148 oob, ecc->bytes + USER_DATA_SZ, false); 1149 1150 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i, 1151 !i, page); 1152 } 1153 1154 if (erased) 1155 raw_mode = 1; 1156 1157 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret); 1158 } 1159 1160 if (status & NFC_ECC_ERR_MSK(nfc)) { 1161 for (i = 0; i < nchunks; i++) { 1162 int data_off = i * ecc->size; 1163 int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1164 u8 *data = buf + data_off; 1165 u8 *oob = nand->oob_poi + oob_off; 1166 1167 if (!(status & NFC_ECC_ERR(i))) 1168 continue; 1169 1170 /* 1171 * Re-read the data with the randomizer disabled to 1172 * identify bitflips in erased pages. 1173 * TODO: use DMA to read page in raw mode 1174 */ 1175 if (randomized) 1176 nand_change_read_column_op(nand, data_off, 1177 data, ecc->size, 1178 false); 1179 1180 /* TODO: use DMA to retrieve OOB */ 1181 nand_change_read_column_op(nand, 1182 mtd->writesize + oob_off, 1183 oob, ecc->bytes + USER_DATA_SZ, false); 1184 1185 ret = nand_check_erased_ecc_chunk(data, ecc->size, oob, 1186 ecc->bytes + USER_DATA_SZ, 1187 NULL, 0, 1188 ecc->strength); 1189 if (ret >= 0) 1190 raw_mode = 1; 1191 1192 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret); 1193 } 1194 } 1195 1196 if (oob_required) 1197 sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi, 1198 NULL, !raw_mode, 1199 page); 1200 1201 return max_bitflips; 1202} 1203 1204static int sunxi_nfc_hw_ecc_write_chunk(struct nand_chip *nand, 1205 const u8 *data, int data_off, 1206 const u8 *oob, int oob_off, 1207 int *cur_off, bool bbm, 1208 int page) 1209{ 1210 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 1211 struct nand_ecc_ctrl *ecc = &nand->ecc; 1212 int ret; 1213 1214 if (data_off != *cur_off) 1215 nand_change_write_column_op(nand, data_off, NULL, 0, false); 1216 1217 sunxi_nfc_randomizer_write_buf(nand, data, ecc->size, false, page); 1218 1219 if (data_off + ecc->size != oob_off) 1220 nand_change_write_column_op(nand, oob_off, NULL, 0, false); 1221 1222 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 1223 if (ret) 1224 return ret; 1225 1226 sunxi_nfc_randomizer_config(nand, page, false); 1227 sunxi_nfc_randomizer_enable(nand); 1228 sunxi_nfc_reset_user_data_len(nfc); 1229 sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); 1230 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page); 1231 1232 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | 1233 NFC_ACCESS_DIR | NFC_ECC_OP, 1234 nfc->regs + NFC_REG_CMD); 1235 1236 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0); 1237 sunxi_nfc_randomizer_disable(nand); 1238 if (ret) 1239 return ret; 1240 1241 *cur_off = oob_off + ecc->bytes + USER_DATA_SZ; 1242 1243 return 0; 1244} 1245 1246static void sunxi_nfc_hw_ecc_write_extra_oob(struct nand_chip *nand, 1247 u8 *oob, int *cur_off, 1248 int page) 1249{ 1250 struct mtd_info *mtd = nand_to_mtd(nand); 1251 struct nand_ecc_ctrl *ecc = &nand->ecc; 1252 int offset = ((ecc->bytes + USER_DATA_SZ) * ecc->steps); 1253 int len = mtd->oobsize - offset; 1254 1255 if (len <= 0) 1256 return; 1257 1258 if (!cur_off || *cur_off != offset) 1259 nand_change_write_column_op(nand, offset + mtd->writesize, 1260 NULL, 0, false); 1261 1262 sunxi_nfc_randomizer_write_buf(nand, oob + offset, len, false, page); 1263 1264 if (cur_off) 1265 *cur_off = mtd->oobsize + mtd->writesize; 1266} 1267 1268static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *nand, uint8_t *buf, 1269 int oob_required, int page) 1270{ 1271 struct mtd_info *mtd = nand_to_mtd(nand); 1272 struct nand_ecc_ctrl *ecc = &nand->ecc; 1273 unsigned int max_bitflips = 0; 1274 int ret, i, cur_off = 0; 1275 bool raw_mode = false; 1276 1277 sunxi_nfc_select_chip(nand, nand->cur_cs); 1278 1279 nand_read_page_op(nand, page, 0, NULL, 0); 1280 1281 sunxi_nfc_hw_ecc_enable(nand); 1282 1283 for (i = 0; i < ecc->steps; i++) { 1284 int data_off = i * ecc->size; 1285 int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1286 u8 *data = buf + data_off; 1287 u8 *oob = nand->oob_poi + oob_off; 1288 1289 ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off, oob, 1290 oob_off + mtd->writesize, 1291 &cur_off, &max_bitflips, 1292 !i, oob_required, page); 1293 if (ret < 0) 1294 return ret; 1295 else if (ret) 1296 raw_mode = true; 1297 } 1298 1299 if (oob_required) 1300 sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi, &cur_off, 1301 !raw_mode, page); 1302 1303 sunxi_nfc_hw_ecc_disable(nand); 1304 1305 return max_bitflips; 1306} 1307 1308static int sunxi_nfc_hw_ecc_read_page_dma(struct nand_chip *nand, u8 *buf, 1309 int oob_required, int page) 1310{ 1311 int ret; 1312 1313 sunxi_nfc_select_chip(nand, nand->cur_cs); 1314 1315 nand_read_page_op(nand, page, 0, NULL, 0); 1316 1317 ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, oob_required, page, 1318 nand->ecc.steps); 1319 if (ret >= 0) 1320 return ret; 1321 1322 /* Fallback to PIO mode */ 1323 return sunxi_nfc_hw_ecc_read_page(nand, buf, oob_required, page); 1324} 1325 1326static int sunxi_nfc_hw_ecc_read_subpage(struct nand_chip *nand, 1327 u32 data_offs, u32 readlen, 1328 u8 *bufpoi, int page) 1329{ 1330 struct mtd_info *mtd = nand_to_mtd(nand); 1331 struct nand_ecc_ctrl *ecc = &nand->ecc; 1332 int ret, i, cur_off = 0; 1333 unsigned int max_bitflips = 0; 1334 1335 sunxi_nfc_select_chip(nand, nand->cur_cs); 1336 1337 nand_read_page_op(nand, page, 0, NULL, 0); 1338 1339 sunxi_nfc_hw_ecc_enable(nand); 1340 1341 for (i = data_offs / ecc->size; 1342 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) { 1343 int data_off = i * ecc->size; 1344 int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1345 u8 *data = bufpoi + data_off; 1346 u8 *oob = nand->oob_poi + oob_off; 1347 1348 ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off, 1349 oob, 1350 oob_off + mtd->writesize, 1351 &cur_off, &max_bitflips, !i, 1352 false, page); 1353 if (ret < 0) 1354 return ret; 1355 } 1356 1357 sunxi_nfc_hw_ecc_disable(nand); 1358 1359 return max_bitflips; 1360} 1361 1362static int sunxi_nfc_hw_ecc_read_subpage_dma(struct nand_chip *nand, 1363 u32 data_offs, u32 readlen, 1364 u8 *buf, int page) 1365{ 1366 int nchunks = DIV_ROUND_UP(data_offs + readlen, nand->ecc.size); 1367 int ret; 1368 1369 sunxi_nfc_select_chip(nand, nand->cur_cs); 1370 1371 nand_read_page_op(nand, page, 0, NULL, 0); 1372 1373 ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, false, page, nchunks); 1374 if (ret >= 0) 1375 return ret; 1376 1377 /* Fallback to PIO mode */ 1378 return sunxi_nfc_hw_ecc_read_subpage(nand, data_offs, readlen, 1379 buf, page); 1380} 1381 1382static int sunxi_nfc_hw_ecc_write_page(struct nand_chip *nand, 1383 const uint8_t *buf, int oob_required, 1384 int page) 1385{ 1386 struct mtd_info *mtd = nand_to_mtd(nand); 1387 struct nand_ecc_ctrl *ecc = &nand->ecc; 1388 int ret, i, cur_off = 0; 1389 1390 sunxi_nfc_select_chip(nand, nand->cur_cs); 1391 1392 nand_prog_page_begin_op(nand, page, 0, NULL, 0); 1393 1394 sunxi_nfc_hw_ecc_enable(nand); 1395 1396 for (i = 0; i < ecc->steps; i++) { 1397 int data_off = i * ecc->size; 1398 int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1399 const u8 *data = buf + data_off; 1400 const u8 *oob = nand->oob_poi + oob_off; 1401 1402 ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob, 1403 oob_off + mtd->writesize, 1404 &cur_off, !i, page); 1405 if (ret) 1406 return ret; 1407 } 1408 1409 if (oob_required || (nand->options & NAND_NEED_SCRAMBLING)) 1410 sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi, 1411 &cur_off, page); 1412 1413 sunxi_nfc_hw_ecc_disable(nand); 1414 1415 return nand_prog_page_end_op(nand); 1416} 1417 1418static int sunxi_nfc_hw_ecc_write_subpage(struct nand_chip *nand, 1419 u32 data_offs, u32 data_len, 1420 const u8 *buf, int oob_required, 1421 int page) 1422{ 1423 struct mtd_info *mtd = nand_to_mtd(nand); 1424 struct nand_ecc_ctrl *ecc = &nand->ecc; 1425 int ret, i, cur_off = 0; 1426 1427 sunxi_nfc_select_chip(nand, nand->cur_cs); 1428 1429 nand_prog_page_begin_op(nand, page, 0, NULL, 0); 1430 1431 sunxi_nfc_hw_ecc_enable(nand); 1432 1433 for (i = data_offs / ecc->size; 1434 i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) { 1435 int data_off = i * ecc->size; 1436 int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1437 const u8 *data = buf + data_off; 1438 const u8 *oob = nand->oob_poi + oob_off; 1439 1440 ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob, 1441 oob_off + mtd->writesize, 1442 &cur_off, !i, page); 1443 if (ret) 1444 return ret; 1445 } 1446 1447 sunxi_nfc_hw_ecc_disable(nand); 1448 1449 return nand_prog_page_end_op(nand); 1450} 1451 1452static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *nand, 1453 const u8 *buf, 1454 int oob_required, 1455 int page) 1456{ 1457 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 1458 struct nand_ecc_ctrl *ecc = &nand->ecc; 1459 struct scatterlist sg; 1460 u32 wait; 1461 int ret, i; 1462 1463 sunxi_nfc_select_chip(nand, nand->cur_cs); 1464 1465 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 1466 if (ret) 1467 return ret; 1468 1469 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, ecc->steps, 1470 DMA_TO_DEVICE, &sg); 1471 if (ret) 1472 goto pio_fallback; 1473 1474 sunxi_nfc_reset_user_data_len(nfc); 1475 for (i = 0; i < ecc->steps; i++) { 1476 const u8 *oob = nand->oob_poi + (i * (ecc->bytes + USER_DATA_SZ)); 1477 1478 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page); 1479 sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, i); 1480 } 1481 1482 nand_prog_page_begin_op(nand, page, 0, NULL, 0); 1483 1484 sunxi_nfc_hw_ecc_enable(nand); 1485 sunxi_nfc_randomizer_config(nand, page, false); 1486 sunxi_nfc_randomizer_enable(nand); 1487 1488 writel((NAND_CMD_RNDIN << 8) | NAND_CMD_PAGEPROG, 1489 nfc->regs + NFC_REG_WCMD_SET); 1490 1491 wait = NFC_CMD_INT_FLAG; 1492 1493 if (nfc->caps->has_mdma) 1494 wait |= NFC_DMA_INT_FLAG; 1495 else 1496 dma_async_issue_pending(nfc->dmac); 1497 1498 writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD | 1499 NFC_DATA_TRANS | NFC_ACCESS_DIR, 1500 nfc->regs + NFC_REG_CMD); 1501 1502 ret = sunxi_nfc_wait_events(nfc, wait, false, 0); 1503 if (ret && !nfc->caps->has_mdma) 1504 dmaengine_terminate_all(nfc->dmac); 1505 1506 sunxi_nfc_randomizer_disable(nand); 1507 sunxi_nfc_hw_ecc_disable(nand); 1508 1509 sunxi_nfc_dma_op_cleanup(nfc, DMA_TO_DEVICE, &sg); 1510 1511 if (ret) 1512 return ret; 1513 1514 if (oob_required || (nand->options & NAND_NEED_SCRAMBLING)) 1515 /* TODO: use DMA to transfer extra OOB bytes ? */ 1516 sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi, 1517 NULL, page); 1518 1519 return nand_prog_page_end_op(nand); 1520 1521pio_fallback: 1522 return sunxi_nfc_hw_ecc_write_page(nand, buf, oob_required, page); 1523} 1524 1525static int sunxi_nfc_hw_ecc_read_oob(struct nand_chip *nand, int page) 1526{ 1527 u8 *buf = nand_get_data_buf(nand); 1528 1529 return nand->ecc.read_page(nand, buf, 1, page); 1530} 1531 1532static int sunxi_nfc_hw_ecc_write_oob(struct nand_chip *nand, int page) 1533{ 1534 struct mtd_info *mtd = nand_to_mtd(nand); 1535 u8 *buf = nand_get_data_buf(nand); 1536 int ret; 1537 1538 memset(buf, 0xff, mtd->writesize); 1539 ret = nand->ecc.write_page(nand, buf, 1, page); 1540 if (ret) 1541 return ret; 1542 1543 /* Send command to program the OOB data */ 1544 return nand_prog_page_end_op(nand); 1545} 1546 1547static const s32 tWB_lut[] = {6, 12, 16, 20}; 1548static const s32 tRHW_lut[] = {4, 8, 12, 20}; 1549 1550static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration, 1551 u32 clk_period) 1552{ 1553 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period); 1554 int i; 1555 1556 for (i = 0; i < lut_size; i++) { 1557 if (clk_cycles <= lut[i]) 1558 return i; 1559 } 1560 1561 /* Doesn't fit */ 1562 return -EINVAL; 1563} 1564 1565#define sunxi_nand_lookup_timing(l, p, c) \ 1566 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c) 1567 1568static int sunxi_nfc_setup_interface(struct nand_chip *nand, int csline, 1569 const struct nand_interface_config *conf) 1570{ 1571 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 1572 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 1573 const struct nand_sdr_timings *timings; 1574 u32 min_clk_period = 0; 1575 s32 tWB, tADL, tWHR, tRHW, tCAD; 1576 long real_clk_rate; 1577 1578 timings = nand_get_sdr_timings(conf); 1579 if (IS_ERR(timings)) 1580 return -ENOTSUPP; 1581 1582 /* T1 <=> tCLS */ 1583 if (timings->tCLS_min > min_clk_period) 1584 min_clk_period = timings->tCLS_min; 1585 1586 /* T2 <=> tCLH */ 1587 if (timings->tCLH_min > min_clk_period) 1588 min_clk_period = timings->tCLH_min; 1589 1590 /* T3 <=> tCS */ 1591 if (timings->tCS_min > min_clk_period) 1592 min_clk_period = timings->tCS_min; 1593 1594 /* T4 <=> tCH */ 1595 if (timings->tCH_min > min_clk_period) 1596 min_clk_period = timings->tCH_min; 1597 1598 /* T5 <=> tWP */ 1599 if (timings->tWP_min > min_clk_period) 1600 min_clk_period = timings->tWP_min; 1601 1602 /* T6 <=> tWH */ 1603 if (timings->tWH_min > min_clk_period) 1604 min_clk_period = timings->tWH_min; 1605 1606 /* T7 <=> tALS */ 1607 if (timings->tALS_min > min_clk_period) 1608 min_clk_period = timings->tALS_min; 1609 1610 /* T8 <=> tDS */ 1611 if (timings->tDS_min > min_clk_period) 1612 min_clk_period = timings->tDS_min; 1613 1614 /* T9 <=> tDH */ 1615 if (timings->tDH_min > min_clk_period) 1616 min_clk_period = timings->tDH_min; 1617 1618 /* T10 <=> tRR */ 1619 if (timings->tRR_min > (min_clk_period * 3)) 1620 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3); 1621 1622 /* T11 <=> tALH */ 1623 if (timings->tALH_min > min_clk_period) 1624 min_clk_period = timings->tALH_min; 1625 1626 /* T12 <=> tRP */ 1627 if (timings->tRP_min > min_clk_period) 1628 min_clk_period = timings->tRP_min; 1629 1630 /* T13 <=> tREH */ 1631 if (timings->tREH_min > min_clk_period) 1632 min_clk_period = timings->tREH_min; 1633 1634 /* T14 <=> tRC */ 1635 if (timings->tRC_min > (min_clk_period * 2)) 1636 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2); 1637 1638 /* T15 <=> tWC */ 1639 if (timings->tWC_min > (min_clk_period * 2)) 1640 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2); 1641 1642 /* T16 - T19 + tCAD */ 1643 if (timings->tWB_max > (min_clk_period * 20)) 1644 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20); 1645 1646 if (timings->tADL_min > (min_clk_period * 32)) 1647 min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32); 1648 1649 if (timings->tWHR_min > (min_clk_period * 32)) 1650 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32); 1651 1652 if (timings->tRHW_min > (min_clk_period * 20)) 1653 min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20); 1654 1655 /* 1656 * In non-EDO, tREA should be less than tRP to guarantee that the 1657 * controller does not sample the IO lines too early. Unfortunately, 1658 * the sunxi NAND controller does not allow us to have different 1659 * values for tRP and tREH (tRP = tREH = tRW / 2). 1660 * 1661 * We have 2 options to overcome this limitation: 1662 * 1663 * 1/ Extend tRC to fulfil the tREA <= tRC / 2 constraint 1664 * 2/ Use EDO mode (only works if timings->tRLOH > 0) 1665 */ 1666 if (timings->tREA_max > min_clk_period && !timings->tRLOH_min) 1667 min_clk_period = timings->tREA_max; 1668 1669 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, 1670 min_clk_period); 1671 if (tWB < 0) { 1672 dev_err(nfc->dev, "unsupported tWB\n"); 1673 return tWB; 1674 } 1675 1676 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3; 1677 if (tADL > 3) { 1678 dev_err(nfc->dev, "unsupported tADL\n"); 1679 return -EINVAL; 1680 } 1681 1682 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; 1683 if (tWHR > 3) { 1684 dev_err(nfc->dev, "unsupported tWHR\n"); 1685 return -EINVAL; 1686 } 1687 1688 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min, 1689 min_clk_period); 1690 if (tRHW < 0) { 1691 dev_err(nfc->dev, "unsupported tRHW\n"); 1692 return tRHW; 1693 } 1694 1695 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 1696 return 0; 1697 1698 /* 1699 * TODO: according to ONFI specs this value only applies for DDR NAND, 1700 * but Allwinner seems to set this to 0x7. Mimic them for now. 1701 */ 1702 tCAD = 0x7; 1703 1704 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */ 1705 sunxi_nand->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD); 1706 1707 /* Convert min_clk_period from picoseconds to nanoseconds */ 1708 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); 1709 1710 /* 1711 * Unlike what is stated in Allwinner datasheet, the clk_rate should 1712 * be set to (1 / min_clk_period), and not (2 / min_clk_period). 1713 * This new formula was verified with a scope and validated by 1714 * Allwinner engineers. 1715 */ 1716 sunxi_nand->clk_rate = NSEC_PER_SEC / min_clk_period; 1717 real_clk_rate = clk_round_rate(nfc->mod_clk, sunxi_nand->clk_rate); 1718 if (real_clk_rate <= 0) { 1719 dev_err(nfc->dev, "Unable to round clk %lu\n", 1720 sunxi_nand->clk_rate); 1721 return -EINVAL; 1722 } 1723 1724 sunxi_nand->timing_ctl = 0; 1725 1726 /* 1727 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data 1728 * output cycle timings shall be used if the host drives tRC less than 1729 * 30 ns. We should also use EDO mode if tREA is bigger than tRP. 1730 */ 1731 min_clk_period = NSEC_PER_SEC / real_clk_rate; 1732 if (min_clk_period * 2 < 30 || min_clk_period * 1000 < timings->tREA_max) 1733 sunxi_nand->timing_ctl = NFC_TIMING_CTL_EDO; 1734 1735 return 0; 1736} 1737 1738static int sunxi_nand_ooblayout_ecc(struct mtd_info *mtd, int section, 1739 struct mtd_oob_region *oobregion) 1740{ 1741 struct nand_chip *nand = mtd_to_nand(mtd); 1742 struct nand_ecc_ctrl *ecc = &nand->ecc; 1743 1744 if (section >= ecc->steps) 1745 return -ERANGE; 1746 1747 oobregion->offset = section * (ecc->bytes + USER_DATA_SZ) + 4; 1748 oobregion->length = ecc->bytes; 1749 1750 return 0; 1751} 1752 1753static int sunxi_nand_ooblayout_free(struct mtd_info *mtd, int section, 1754 struct mtd_oob_region *oobregion) 1755{ 1756 struct nand_chip *nand = mtd_to_nand(mtd); 1757 struct nand_ecc_ctrl *ecc = &nand->ecc; 1758 1759 if (section > ecc->steps) 1760 return -ERANGE; 1761 1762 /* 1763 * The first 2 bytes are used for BB markers, hence we 1764 * only have 2 bytes available in the first user data 1765 * section. 1766 */ 1767 if (!section && ecc->engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 1768 oobregion->offset = 2; 1769 oobregion->length = 2; 1770 1771 return 0; 1772 } 1773 1774 /* 1775 * The controller does not provide access to OOB bytes 1776 * past the end of the ECC data. 1777 */ 1778 if (section == ecc->steps && ecc->engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1779 return -ERANGE; 1780 1781 oobregion->offset = section * (ecc->bytes + USER_DATA_SZ); 1782 1783 if (section < ecc->steps) 1784 oobregion->length = USER_DATA_SZ; 1785 else 1786 oobregion->length = mtd->oobsize - oobregion->offset; 1787 1788 return 0; 1789} 1790 1791static const struct mtd_ooblayout_ops sunxi_nand_ooblayout_ops = { 1792 .ecc = sunxi_nand_ooblayout_ecc, 1793 .free = sunxi_nand_ooblayout_free, 1794}; 1795 1796static int sunxi_nand_hw_ecc_ctrl_init(struct nand_chip *nand, 1797 struct nand_ecc_ctrl *ecc, 1798 struct device_node *np) 1799{ 1800 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 1801 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 1802 const u8 *strengths = nfc->caps->ecc_strengths; 1803 struct mtd_info *mtd = nand_to_mtd(nand); 1804 struct nand_device *nanddev = mtd_to_nanddev(mtd); 1805 int nsectors; 1806 int i; 1807 1808 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) { 1809 int bytes; 1810 1811 ecc->size = 1024; 1812 nsectors = mtd->writesize / ecc->size; 1813 1814 /* Reserve 2 bytes for the BBM */ 1815 bytes = (mtd->oobsize - 2) / nsectors; 1816 1817 /* 4 non-ECC bytes are added before each ECC bytes section */ 1818 bytes -= USER_DATA_SZ; 1819 1820 /* and bytes has to be even. */ 1821 if (bytes % 2) 1822 bytes--; 1823 1824 ecc->strength = bytes * 8 / fls(8 * ecc->size); 1825 1826 for (i = 0; i < nfc->caps->nstrengths; i++) { 1827 if (strengths[i] > ecc->strength) 1828 break; 1829 } 1830 1831 if (!i) 1832 ecc->strength = 0; 1833 else 1834 ecc->strength = strengths[i - 1]; 1835 } 1836 1837 if (ecc->size != 512 && ecc->size != 1024) 1838 return -EINVAL; 1839 1840 /* Prefer 1k ECC chunk over 512 ones */ 1841 if (ecc->size == 512 && mtd->writesize > 512) { 1842 ecc->size = 1024; 1843 ecc->strength *= 2; 1844 } 1845 1846 /* Add ECC info retrieval from DT */ 1847 for (i = 0; i < nfc->caps->nstrengths; i++) { 1848 if (ecc->strength <= strengths[i]) { 1849 /* 1850 * Update ecc->strength value with the actual strength 1851 * that will be used by the ECC engine. 1852 */ 1853 ecc->strength = strengths[i]; 1854 break; 1855 } 1856 } 1857 1858 if (i >= nfc->caps->nstrengths) { 1859 dev_err(nfc->dev, "unsupported strength\n"); 1860 return -ENOTSUPP; 1861 } 1862 1863 /* HW ECC always request ECC bytes for 1024 bytes blocks */ 1864 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8); 1865 1866 /* HW ECC always work with even numbers of ECC bytes */ 1867 ecc->bytes = ALIGN(ecc->bytes, 2); 1868 1869 nsectors = mtd->writesize / ecc->size; 1870 1871 if (mtd->oobsize < ((ecc->bytes + USER_DATA_SZ) * nsectors)) 1872 return -EINVAL; 1873 1874 ecc->read_oob = sunxi_nfc_hw_ecc_read_oob; 1875 ecc->write_oob = sunxi_nfc_hw_ecc_write_oob; 1876 mtd_set_ooblayout(mtd, &sunxi_nand_ooblayout_ops); 1877 1878 if (nfc->dmac || nfc->caps->has_mdma) { 1879 ecc->read_page = sunxi_nfc_hw_ecc_read_page_dma; 1880 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage_dma; 1881 ecc->write_page = sunxi_nfc_hw_ecc_write_page_dma; 1882 nand->options |= NAND_USES_DMA; 1883 } else { 1884 ecc->read_page = sunxi_nfc_hw_ecc_read_page; 1885 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage; 1886 ecc->write_page = sunxi_nfc_hw_ecc_write_page; 1887 } 1888 1889 /* TODO: support DMA for raw accesses and subpage write */ 1890 ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage; 1891 ecc->read_oob_raw = nand_read_oob_std; 1892 ecc->write_oob_raw = nand_write_oob_std; 1893 1894 sunxi_nand->ecc.ecc_ctl = NFC_ECC_MODE(nfc, i) | NFC_ECC_EXCEPTION | 1895 NFC_ECC_PIPELINE | NFC_ECC_EN; 1896 1897 if (ecc->size == 512) { 1898 if (nfc->caps->has_ecc_block_512) { 1899 sunxi_nand->ecc.ecc_ctl |= NFC_ECC_BLOCK_512; 1900 } else { 1901 dev_err(nfc->dev, "512B ECC block not supported\n"); 1902 return -EOPNOTSUPP; 1903 } 1904 } 1905 1906 return 0; 1907} 1908 1909static int sunxi_nand_attach_chip(struct nand_chip *nand) 1910{ 1911 const struct nand_ecc_props *requirements = 1912 nanddev_get_ecc_requirements(&nand->base); 1913 struct nand_ecc_ctrl *ecc = &nand->ecc; 1914 struct device_node *np = nand_get_flash_node(nand); 1915 int ret; 1916 1917 if (nand->bbt_options & NAND_BBT_USE_FLASH) 1918 nand->bbt_options |= NAND_BBT_NO_OOB; 1919 1920 if (nand->options & NAND_NEED_SCRAMBLING) 1921 nand->options |= NAND_NO_SUBPAGE_WRITE; 1922 1923 nand->options |= NAND_SUBPAGE_READ; 1924 1925 if (!ecc->size) { 1926 ecc->size = requirements->step_size; 1927 ecc->strength = requirements->strength; 1928 } 1929 1930 if (!ecc->size || !ecc->strength) 1931 return -EINVAL; 1932 1933 switch (ecc->engine_type) { 1934 case NAND_ECC_ENGINE_TYPE_ON_HOST: 1935 ret = sunxi_nand_hw_ecc_ctrl_init(nand, ecc, np); 1936 if (ret) 1937 return ret; 1938 break; 1939 case NAND_ECC_ENGINE_TYPE_NONE: 1940 case NAND_ECC_ENGINE_TYPE_SOFT: 1941 break; 1942 default: 1943 return -EINVAL; 1944 } 1945 1946 return 0; 1947} 1948 1949static int sunxi_nfc_exec_subop(struct nand_chip *nand, 1950 const struct nand_subop *subop) 1951{ 1952 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 1953 u32 cmd = 0, extcmd = 0, cnt = 0, addrs[2] = { }; 1954 unsigned int i, j, remaining, start; 1955 void *inbuf = NULL; 1956 int ret; 1957 1958 for (i = 0; i < subop->ninstrs; i++) { 1959 const struct nand_op_instr *instr = &subop->instrs[i]; 1960 1961 switch (instr->type) { 1962 case NAND_OP_CMD_INSTR: 1963 if (cmd & NFC_SEND_CMD1) { 1964 if (WARN_ON(cmd & NFC_SEND_CMD2)) 1965 return -EINVAL; 1966 1967 cmd |= NFC_SEND_CMD2; 1968 extcmd |= instr->ctx.cmd.opcode; 1969 } else { 1970 cmd |= NFC_SEND_CMD1 | 1971 NFC_CMD(instr->ctx.cmd.opcode); 1972 } 1973 break; 1974 1975 case NAND_OP_ADDR_INSTR: 1976 remaining = nand_subop_get_num_addr_cyc(subop, i); 1977 start = nand_subop_get_addr_start_off(subop, i); 1978 for (j = 0; j < 8 && j + start < remaining; j++) { 1979 u32 addr = instr->ctx.addr.addrs[j + start]; 1980 1981 addrs[j / 4] |= addr << (j % 4) * 8; 1982 } 1983 1984 if (j) 1985 cmd |= NFC_SEND_ADR | NFC_ADR_NUM(j); 1986 1987 break; 1988 1989 case NAND_OP_DATA_IN_INSTR: 1990 case NAND_OP_DATA_OUT_INSTR: 1991 start = nand_subop_get_data_start_off(subop, i); 1992 remaining = nand_subop_get_data_len(subop, i); 1993 cnt = min_t(u32, remaining, nfc->caps->sram_size); 1994 cmd |= NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD; 1995 1996 if (instr->type == NAND_OP_DATA_OUT_INSTR) { 1997 cmd |= NFC_ACCESS_DIR; 1998 memcpy_toio(nfc->regs + NFC_RAM0_BASE, 1999 instr->ctx.data.buf.out + start, 2000 cnt); 2001 } else { 2002 inbuf = instr->ctx.data.buf.in + start; 2003 } 2004 2005 break; 2006 2007 case NAND_OP_WAITRDY_INSTR: 2008 cmd |= NFC_WAIT_FLAG; 2009 break; 2010 } 2011 } 2012 2013 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 2014 if (ret) 2015 return ret; 2016 2017 if (cmd & NFC_SEND_ADR) { 2018 writel(addrs[0], nfc->regs + NFC_REG_ADDR_LOW); 2019 writel(addrs[1], nfc->regs + NFC_REG_ADDR_HIGH); 2020 } 2021 2022 if (cmd & NFC_SEND_CMD2) 2023 writel(extcmd, 2024 nfc->regs + 2025 (cmd & NFC_ACCESS_DIR ? 2026 NFC_REG_WCMD_SET : NFC_REG_RCMD_SET)); 2027 2028 if (cmd & NFC_DATA_TRANS) 2029 writel(cnt, nfc->regs + NFC_REG_CNT); 2030 2031 writel(cmd, nfc->regs + NFC_REG_CMD); 2032 2033 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, 2034 !(cmd & NFC_WAIT_FLAG) && cnt < 64, 2035 0); 2036 if (ret) 2037 return ret; 2038 2039 if (inbuf) 2040 memcpy_fromio(inbuf, nfc->regs + NFC_RAM0_BASE, cnt); 2041 2042 return 0; 2043} 2044 2045static int sunxi_nfc_soft_waitrdy(struct nand_chip *nand, 2046 const struct nand_subop *subop) 2047{ 2048 return nand_soft_waitrdy(nand, 2049 subop->instrs[0].ctx.waitrdy.timeout_ms); 2050} 2051 2052static const struct nand_op_parser sunxi_nfc_op_parser = NAND_OP_PARSER( 2053 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop, 2054 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2055 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8), 2056 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2057 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 2058 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 1024)), 2059 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop, 2060 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2061 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8), 2062 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 1024), 2063 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2064 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 2065); 2066 2067static const struct nand_op_parser sunxi_nfc_norb_op_parser = NAND_OP_PARSER( 2068 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop, 2069 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2070 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8), 2071 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2072 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 1024)), 2073 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop, 2074 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2075 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8), 2076 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 1024), 2077 NAND_OP_PARSER_PAT_CMD_ELEM(true)), 2078 NAND_OP_PARSER_PATTERN(sunxi_nfc_soft_waitrdy, 2079 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 2080); 2081 2082static int sunxi_nfc_exec_op(struct nand_chip *nand, 2083 const struct nand_operation *op, bool check_only) 2084{ 2085 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 2086 const struct nand_op_parser *parser; 2087 2088 if (!check_only) 2089 sunxi_nfc_select_chip(nand, op->cs); 2090 2091 if (sunxi_nand->sels[op->cs].rb >= 0) 2092 parser = &sunxi_nfc_op_parser; 2093 else 2094 parser = &sunxi_nfc_norb_op_parser; 2095 2096 return nand_op_parser_exec_op(nand, parser, op, check_only); 2097} 2098 2099static const struct nand_controller_ops sunxi_nand_controller_ops = { 2100 .attach_chip = sunxi_nand_attach_chip, 2101 .setup_interface = sunxi_nfc_setup_interface, 2102 .exec_op = sunxi_nfc_exec_op, 2103}; 2104 2105static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc) 2106{ 2107 struct sunxi_nand_chip *sunxi_nand; 2108 struct nand_chip *chip; 2109 int ret; 2110 2111 while (!list_empty(&nfc->chips)) { 2112 sunxi_nand = list_first_entry(&nfc->chips, 2113 struct sunxi_nand_chip, 2114 node); 2115 chip = &sunxi_nand->nand; 2116 ret = mtd_device_unregister(nand_to_mtd(chip)); 2117 WARN_ON(ret); 2118 nand_cleanup(chip); 2119 list_del(&sunxi_nand->node); 2120 } 2121} 2122 2123static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc, 2124 struct device_node *np) 2125{ 2126 struct sunxi_nand_chip *sunxi_nand; 2127 struct mtd_info *mtd; 2128 struct nand_chip *nand; 2129 int nsels; 2130 int ret; 2131 int i; 2132 u32 tmp; 2133 2134 if (!of_get_property(np, "reg", &nsels)) 2135 return -EINVAL; 2136 2137 nsels /= sizeof(u32); 2138 if (!nsels) { 2139 dev_err(dev, "invalid reg property size\n"); 2140 return -EINVAL; 2141 } 2142 2143 sunxi_nand = devm_kzalloc(dev, struct_size(sunxi_nand, sels, nsels), 2144 GFP_KERNEL); 2145 if (!sunxi_nand) 2146 return -ENOMEM; 2147 2148 sunxi_nand->nsels = nsels; 2149 2150 for (i = 0; i < nsels; i++) { 2151 ret = of_property_read_u32_index(np, "reg", i, &tmp); 2152 if (ret) { 2153 dev_err(dev, "could not retrieve reg property: %d\n", 2154 ret); 2155 return ret; 2156 } 2157 2158 if (tmp > NFC_MAX_CS) { 2159 dev_err(dev, 2160 "invalid reg value: %u (max CS = 7)\n", 2161 tmp); 2162 return -EINVAL; 2163 } 2164 2165 if (test_and_set_bit(tmp, &nfc->assigned_cs)) { 2166 dev_err(dev, "CS %d already assigned\n", tmp); 2167 return -EINVAL; 2168 } 2169 2170 sunxi_nand->sels[i].cs = tmp; 2171 2172 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) && 2173 tmp < 2) 2174 sunxi_nand->sels[i].rb = tmp; 2175 else 2176 sunxi_nand->sels[i].rb = -1; 2177 } 2178 2179 nand = &sunxi_nand->nand; 2180 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */ 2181 nand->controller = &nfc->controller; 2182 nand->controller->ops = &sunxi_nand_controller_ops; 2183 2184 /* 2185 * Set the ECC mode to the default value in case nothing is specified 2186 * in the DT. 2187 */ 2188 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2189 nand_set_flash_node(nand, np); 2190 2191 mtd = nand_to_mtd(nand); 2192 mtd->dev.parent = dev; 2193 2194 ret = nand_scan(nand, nsels); 2195 if (ret) 2196 return ret; 2197 2198 ret = mtd_device_register(mtd, NULL, 0); 2199 if (ret) { 2200 dev_err(dev, "failed to register mtd device: %d\n", ret); 2201 nand_cleanup(nand); 2202 return ret; 2203 } 2204 2205 list_add_tail(&sunxi_nand->node, &nfc->chips); 2206 2207 return 0; 2208} 2209 2210static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc) 2211{ 2212 struct device_node *np = dev->of_node; 2213 int ret; 2214 2215 for_each_child_of_node_scoped(np, nand_np) { 2216 ret = sunxi_nand_chip_init(dev, nfc, nand_np); 2217 if (ret) { 2218 sunxi_nand_chips_cleanup(nfc); 2219 return ret; 2220 } 2221 } 2222 2223 return 0; 2224} 2225 2226static int sunxi_nfc_dma_init(struct sunxi_nfc *nfc, struct resource *r) 2227{ 2228 int ret; 2229 2230 if (nfc->caps->has_mdma) 2231 return 0; 2232 2233 nfc->dmac = dma_request_chan(nfc->dev, "rxtx"); 2234 if (IS_ERR(nfc->dmac)) { 2235 ret = PTR_ERR(nfc->dmac); 2236 if (ret == -EPROBE_DEFER) 2237 return ret; 2238 2239 /* Ignore errors to fall back to PIO mode */ 2240 dev_warn(nfc->dev, "failed to request rxtx DMA channel: %d\n", ret); 2241 nfc->dmac = NULL; 2242 } else { 2243 struct dma_slave_config dmac_cfg = { }; 2244 2245 dmac_cfg.src_addr = r->start + nfc->caps->reg_io_data; 2246 dmac_cfg.dst_addr = dmac_cfg.src_addr; 2247 dmac_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2248 dmac_cfg.dst_addr_width = dmac_cfg.src_addr_width; 2249 dmac_cfg.src_maxburst = nfc->caps->dma_maxburst; 2250 dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst; 2251 dmaengine_slave_config(nfc->dmac, &dmac_cfg); 2252 } 2253 return 0; 2254} 2255 2256static int sunxi_nfc_probe(struct platform_device *pdev) 2257{ 2258 struct device *dev = &pdev->dev; 2259 struct resource *r; 2260 struct sunxi_nfc *nfc; 2261 int irq; 2262 int ret; 2263 2264 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 2265 if (!nfc) 2266 return -ENOMEM; 2267 2268 nfc->dev = dev; 2269 nand_controller_init(&nfc->controller); 2270 INIT_LIST_HEAD(&nfc->chips); 2271 2272 nfc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 2273 if (IS_ERR(nfc->regs)) 2274 return PTR_ERR(nfc->regs); 2275 2276 irq = platform_get_irq(pdev, 0); 2277 if (irq < 0) 2278 return irq; 2279 2280 nfc->caps = of_device_get_match_data(dev); 2281 if (!nfc->caps) 2282 return -EINVAL; 2283 2284 nfc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); 2285 if (IS_ERR(nfc->ahb_clk)) { 2286 dev_err(dev, "failed to retrieve ahb clk\n"); 2287 return PTR_ERR(nfc->ahb_clk); 2288 } 2289 2290 nfc->mod_clk = devm_clk_get_enabled(dev, "mod"); 2291 if (IS_ERR(nfc->mod_clk)) { 2292 dev_err(dev, "failed to retrieve mod clk\n"); 2293 return PTR_ERR(nfc->mod_clk); 2294 } 2295 2296 if (nfc->caps->has_ecc_clk) { 2297 nfc->ecc_clk = devm_clk_get_enabled(dev, "ecc"); 2298 if (IS_ERR(nfc->ecc_clk)) { 2299 dev_err(dev, "failed to retrieve ecc clk\n"); 2300 return PTR_ERR(nfc->ecc_clk); 2301 } 2302 } 2303 2304 if (nfc->caps->has_mbus_clk) { 2305 nfc->mbus_clk = devm_clk_get_enabled(dev, "mbus"); 2306 if (IS_ERR(nfc->mbus_clk)) { 2307 dev_err(dev, "failed to retrieve mbus clk\n"); 2308 return PTR_ERR(nfc->mbus_clk); 2309 } 2310 } 2311 2312 nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb"); 2313 if (IS_ERR(nfc->reset)) 2314 return PTR_ERR(nfc->reset); 2315 2316 ret = reset_control_deassert(nfc->reset); 2317 if (ret) { 2318 dev_err(dev, "reset err %d\n", ret); 2319 return ret; 2320 } 2321 2322 ret = sunxi_nfc_rst(nfc); 2323 if (ret) 2324 goto out_ahb_reset_reassert; 2325 2326 writel(0, nfc->regs + NFC_REG_INT); 2327 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt, 2328 0, "sunxi-nand", nfc); 2329 if (ret) 2330 goto out_ahb_reset_reassert; 2331 2332 ret = sunxi_nfc_dma_init(nfc, r); 2333 2334 if (ret) 2335 goto out_ahb_reset_reassert; 2336 2337 platform_set_drvdata(pdev, nfc); 2338 2339 ret = sunxi_nand_chips_init(dev, nfc); 2340 if (ret) { 2341 dev_err(dev, "failed to init nand chips\n"); 2342 goto out_release_dmac; 2343 } 2344 2345 return 0; 2346 2347out_release_dmac: 2348 if (nfc->dmac) 2349 dma_release_channel(nfc->dmac); 2350out_ahb_reset_reassert: 2351 reset_control_assert(nfc->reset); 2352 2353 return ret; 2354} 2355 2356static void sunxi_nfc_remove(struct platform_device *pdev) 2357{ 2358 struct sunxi_nfc *nfc = platform_get_drvdata(pdev); 2359 2360 sunxi_nand_chips_cleanup(nfc); 2361 2362 reset_control_assert(nfc->reset); 2363 2364 if (nfc->dmac) 2365 dma_release_channel(nfc->dmac); 2366} 2367 2368static const u8 sunxi_ecc_strengths_a10[] = { 2369 16, 24, 28, 32, 40, 48, 56, 60, 64 2370}; 2371 2372static const u8 sunxi_ecc_strengths_h6[] = { 2373 16, 24, 28, 32, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80 2374}; 2375 2376static const u8 sunxi_user_data_len_h6[] = { 2377 0, 4, 8, 12, 16, 20, 24, 28, 32 2378}; 2379 2380static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = { 2381 .has_ecc_block_512 = true, 2382 .reg_io_data = NFC_REG_A10_IO_DATA, 2383 .reg_ecc_err_cnt = NFC_REG_A10_ECC_ERR_CNT, 2384 .reg_user_data = NFC_REG_A10_USER_DATA, 2385 .reg_spare_area = NFC_REG_A10_SPARE_AREA, 2386 .reg_pat_id = NFC_REG_A10_PAT_ID, 2387 .reg_pat_found = NFC_REG_ECC_ST, 2388 .random_en_mask = BIT(9), 2389 .random_dir_mask = BIT(10), 2390 .ecc_mode_mask = GENMASK(15, 12), 2391 .ecc_err_mask = GENMASK(15, 0), 2392 .pat_found_mask = GENMASK(31, 16), 2393 .dma_maxburst = 4, 2394 .ecc_strengths = sunxi_ecc_strengths_a10, 2395 .nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_a10), 2396 .max_ecc_steps = 16, 2397 .sram_size = 1024, 2398}; 2399 2400static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = { 2401 .has_mdma = true, 2402 .has_ecc_block_512 = true, 2403 .reg_io_data = NFC_REG_A23_IO_DATA, 2404 .reg_ecc_err_cnt = NFC_REG_A10_ECC_ERR_CNT, 2405 .reg_user_data = NFC_REG_A10_USER_DATA, 2406 .reg_spare_area = NFC_REG_A10_SPARE_AREA, 2407 .reg_pat_id = NFC_REG_A10_PAT_ID, 2408 .reg_pat_found = NFC_REG_ECC_ST, 2409 .random_en_mask = BIT(9), 2410 .random_dir_mask = BIT(10), 2411 .ecc_mode_mask = GENMASK(15, 12), 2412 .ecc_err_mask = GENMASK(15, 0), 2413 .pat_found_mask = GENMASK(31, 16), 2414 .dma_maxburst = 8, 2415 .ecc_strengths = sunxi_ecc_strengths_a10, 2416 .nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_a10), 2417 .max_ecc_steps = 16, 2418 .sram_size = 1024, 2419}; 2420 2421static const struct sunxi_nfc_caps sunxi_nfc_h616_caps = { 2422 .has_ecc_clk = true, 2423 .has_mbus_clk = true, 2424 .reg_io_data = NFC_REG_A23_IO_DATA, 2425 .reg_ecc_err_cnt = NFC_REG_H6_ECC_ERR_CNT, 2426 .reg_user_data = NFC_REG_H6_USER_DATA, 2427 .reg_user_data_len = NFC_REG_H6_USER_DATA_LEN, 2428 .reg_spare_area = NFC_REG_H6_SPARE_AREA, 2429 .reg_pat_id = NFC_REG_H6_PAT_ID, 2430 .reg_pat_found = NFC_REG_H6_PAT_FOUND, 2431 .random_en_mask = BIT(5), 2432 .random_dir_mask = BIT(6), 2433 .ecc_mode_mask = GENMASK(15, 8), 2434 .ecc_err_mask = GENMASK(31, 0), 2435 .pat_found_mask = GENMASK(31, 0), 2436 .dma_maxburst = 8, 2437 .ecc_strengths = sunxi_ecc_strengths_h6, 2438 .nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_h6), 2439 .user_data_len_tab = sunxi_user_data_len_h6, 2440 .nuser_data_tab = ARRAY_SIZE(sunxi_user_data_len_h6), 2441 .max_ecc_steps = 32, 2442 .sram_size = 8192, 2443}; 2444 2445static const struct of_device_id sunxi_nfc_ids[] = { 2446 { 2447 .compatible = "allwinner,sun4i-a10-nand", 2448 .data = &sunxi_nfc_a10_caps, 2449 }, 2450 { 2451 .compatible = "allwinner,sun8i-a23-nand-controller", 2452 .data = &sunxi_nfc_a23_caps, 2453 }, 2454 { 2455 .compatible = "allwinner,sun50i-h616-nand-controller", 2456 .data = &sunxi_nfc_h616_caps, 2457 }, 2458 { /* sentinel */ } 2459}; 2460MODULE_DEVICE_TABLE(of, sunxi_nfc_ids); 2461 2462static struct platform_driver sunxi_nfc_driver = { 2463 .driver = { 2464 .name = "sunxi_nand", 2465 .of_match_table = sunxi_nfc_ids, 2466 }, 2467 .probe = sunxi_nfc_probe, 2468 .remove = sunxi_nfc_remove, 2469}; 2470module_platform_driver(sunxi_nfc_driver); 2471 2472MODULE_LICENSE("GPL"); 2473MODULE_AUTHOR("Boris BREZILLON"); 2474MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
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