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stm32_fmc2_nand.c
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linux-6.19.14/drivers/mtd/nand/raw/stm32_fmc2_nand.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) STMicroelectronics 2018 4 * Author: Christophe Kerello <christophe.kerello@st.com> 5 */ 6 7#include <linux/bitfield.h> 8#include <linux/clk.h> 9#include <linux/dmaengine.h> 10#include <linux/dma-mapping.h> 11#include <linux/errno.h> 12#include <linux/gpio/consumer.h> 13#include <linux/interrupt.h> 14#include <linux/iopoll.h> 15#include <linux/mfd/syscon.h> 16#include <linux/module.h> 17#include <linux/mtd/rawnand.h> 18#include <linux/of_address.h> 19#include <linux/of_device.h> 20#include <linux/pinctrl/consumer.h> 21#include <linux/platform_device.h> 22#include <linux/regmap.h> 23#include <linux/reset.h> 24 25/* Bad block marker length */ 26#define FMC2_BBM_LEN 2 27 28/* ECC step size */ 29#define FMC2_ECC_STEP_SIZE 512 30 31/* BCHDSRx registers length */ 32#define FMC2_BCHDSRS_LEN 20 33 34/* HECCR length */ 35#define FMC2_HECCR_LEN 4 36 37/* Max requests done for a 8k nand page size */ 38#define FMC2_MAX_SG 16 39 40/* Max chip enable */ 41#define FMC2_MAX_CE 4 42 43/* Max ECC buffer length */ 44#define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG) 45 46#define FMC2_TIMEOUT_MS 5000 47 48/* Timings */ 49#define FMC2_THIZ 1 50#define FMC2_TIO 8000 51#define FMC2_TSYNC 3000 52#define FMC2_PCR_TIMING_MASK 0xf 53#define FMC2_PMEM_PATT_TIMING_MASK 0xff 54 55/* FMC2 Controller Registers */ 56#define FMC2_BCR1 0x0 57#define FMC2_PCR 0x80 58#define FMC2_SR 0x84 59#define FMC2_PMEM 0x88 60#define FMC2_PATT 0x8c 61#define FMC2_HECCR 0x94 62#define FMC2_ISR 0x184 63#define FMC2_ICR 0x188 64#define FMC2_CSQCR 0x200 65#define FMC2_CSQCFGR1 0x204 66#define FMC2_CSQCFGR2 0x208 67#define FMC2_CSQCFGR3 0x20c 68#define FMC2_CSQAR1 0x210 69#define FMC2_CSQAR2 0x214 70#define FMC2_CSQIER 0x220 71#define FMC2_CSQISR 0x224 72#define FMC2_CSQICR 0x228 73#define FMC2_CSQEMSR 0x230 74#define FMC2_BCHIER 0x250 75#define FMC2_BCHISR 0x254 76#define FMC2_BCHICR 0x258 77#define FMC2_BCHPBR1 0x260 78#define FMC2_BCHPBR2 0x264 79#define FMC2_BCHPBR3 0x268 80#define FMC2_BCHPBR4 0x26c 81#define FMC2_BCHDSR0 0x27c 82#define FMC2_BCHDSR1 0x280 83#define FMC2_BCHDSR2 0x284 84#define FMC2_BCHDSR3 0x288 85#define FMC2_BCHDSR4 0x28c 86 87/* Register: FMC2_BCR1 */ 88#define FMC2_BCR1_FMC2EN BIT(31) 89 90/* Register: FMC2_PCR */ 91#define FMC2_PCR_PWAITEN BIT(1) 92#define FMC2_PCR_PBKEN BIT(2) 93#define FMC2_PCR_PWID GENMASK(5, 4) 94#define FMC2_PCR_PWID_BUSWIDTH_8 0 95#define FMC2_PCR_PWID_BUSWIDTH_16 1 96#define FMC2_PCR_ECCEN BIT(6) 97#define FMC2_PCR_ECCALG BIT(8) 98#define FMC2_PCR_TCLR GENMASK(12, 9) 99#define FMC2_PCR_TCLR_DEFAULT 0xf 100#define FMC2_PCR_TAR GENMASK(16, 13) 101#define FMC2_PCR_TAR_DEFAULT 0xf 102#define FMC2_PCR_ECCSS GENMASK(19, 17) 103#define FMC2_PCR_ECCSS_512 1 104#define FMC2_PCR_ECCSS_2048 3 105#define FMC2_PCR_BCHECC BIT(24) 106#define FMC2_PCR_WEN BIT(25) 107 108/* Register: FMC2_SR */ 109#define FMC2_SR_NWRF BIT(6) 110 111/* Register: FMC2_PMEM */ 112#define FMC2_PMEM_MEMSET GENMASK(7, 0) 113#define FMC2_PMEM_MEMWAIT GENMASK(15, 8) 114#define FMC2_PMEM_MEMHOLD GENMASK(23, 16) 115#define FMC2_PMEM_MEMHIZ GENMASK(31, 24) 116#define FMC2_PMEM_DEFAULT 0x0a0a0a0a 117 118/* Register: FMC2_PATT */ 119#define FMC2_PATT_ATTSET GENMASK(7, 0) 120#define FMC2_PATT_ATTWAIT GENMASK(15, 8) 121#define FMC2_PATT_ATTHOLD GENMASK(23, 16) 122#define FMC2_PATT_ATTHIZ GENMASK(31, 24) 123#define FMC2_PATT_DEFAULT 0x0a0a0a0a 124 125/* Register: FMC2_ISR */ 126#define FMC2_ISR_IHLF BIT(1) 127 128/* Register: FMC2_ICR */ 129#define FMC2_ICR_CIHLF BIT(1) 130 131/* Register: FMC2_CSQCR */ 132#define FMC2_CSQCR_CSQSTART BIT(0) 133 134/* Register: FMC2_CSQCFGR1 */ 135#define FMC2_CSQCFGR1_CMD2EN BIT(1) 136#define FMC2_CSQCFGR1_DMADEN BIT(2) 137#define FMC2_CSQCFGR1_ACYNBR GENMASK(6, 4) 138#define FMC2_CSQCFGR1_CMD1 GENMASK(15, 8) 139#define FMC2_CSQCFGR1_CMD2 GENMASK(23, 16) 140#define FMC2_CSQCFGR1_CMD1T BIT(24) 141#define FMC2_CSQCFGR1_CMD2T BIT(25) 142 143/* Register: FMC2_CSQCFGR2 */ 144#define FMC2_CSQCFGR2_SQSDTEN BIT(0) 145#define FMC2_CSQCFGR2_RCMD2EN BIT(1) 146#define FMC2_CSQCFGR2_DMASEN BIT(2) 147#define FMC2_CSQCFGR2_RCMD1 GENMASK(15, 8) 148#define FMC2_CSQCFGR2_RCMD2 GENMASK(23, 16) 149#define FMC2_CSQCFGR2_RCMD1T BIT(24) 150#define FMC2_CSQCFGR2_RCMD2T BIT(25) 151 152/* Register: FMC2_CSQCFGR3 */ 153#define FMC2_CSQCFGR3_SNBR GENMASK(13, 8) 154#define FMC2_CSQCFGR3_AC1T BIT(16) 155#define FMC2_CSQCFGR3_AC2T BIT(17) 156#define FMC2_CSQCFGR3_AC3T BIT(18) 157#define FMC2_CSQCFGR3_AC4T BIT(19) 158#define FMC2_CSQCFGR3_AC5T BIT(20) 159#define FMC2_CSQCFGR3_SDT BIT(21) 160#define FMC2_CSQCFGR3_RAC1T BIT(22) 161#define FMC2_CSQCFGR3_RAC2T BIT(23) 162 163/* Register: FMC2_CSQCAR1 */ 164#define FMC2_CSQCAR1_ADDC1 GENMASK(7, 0) 165#define FMC2_CSQCAR1_ADDC2 GENMASK(15, 8) 166#define FMC2_CSQCAR1_ADDC3 GENMASK(23, 16) 167#define FMC2_CSQCAR1_ADDC4 GENMASK(31, 24) 168 169/* Register: FMC2_CSQCAR2 */ 170#define FMC2_CSQCAR2_ADDC5 GENMASK(7, 0) 171#define FMC2_CSQCAR2_NANDCEN GENMASK(11, 10) 172#define FMC2_CSQCAR2_SAO GENMASK(31, 16) 173 174/* Register: FMC2_CSQIER */ 175#define FMC2_CSQIER_TCIE BIT(0) 176 177/* Register: FMC2_CSQICR */ 178#define FMC2_CSQICR_CLEAR_IRQ GENMASK(4, 0) 179 180/* Register: FMC2_CSQEMSR */ 181#define FMC2_CSQEMSR_SEM GENMASK(15, 0) 182 183/* Register: FMC2_BCHIER */ 184#define FMC2_BCHIER_DERIE BIT(1) 185#define FMC2_BCHIER_EPBRIE BIT(4) 186 187/* Register: FMC2_BCHICR */ 188#define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0) 189 190/* Register: FMC2_BCHDSR0 */ 191#define FMC2_BCHDSR0_DUE BIT(0) 192#define FMC2_BCHDSR0_DEF BIT(1) 193#define FMC2_BCHDSR0_DEN GENMASK(7, 4) 194 195/* Register: FMC2_BCHDSR1 */ 196#define FMC2_BCHDSR1_EBP1 GENMASK(12, 0) 197#define FMC2_BCHDSR1_EBP2 GENMASK(28, 16) 198 199/* Register: FMC2_BCHDSR2 */ 200#define FMC2_BCHDSR2_EBP3 GENMASK(12, 0) 201#define FMC2_BCHDSR2_EBP4 GENMASK(28, 16) 202 203/* Register: FMC2_BCHDSR3 */ 204#define FMC2_BCHDSR3_EBP5 GENMASK(12, 0) 205#define FMC2_BCHDSR3_EBP6 GENMASK(28, 16) 206 207/* Register: FMC2_BCHDSR4 */ 208#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) 209#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) 210 211enum stm32_fmc2_ecc { 212 FMC2_ECC_HAM = 1, 213 FMC2_ECC_BCH4 = 4, 214 FMC2_ECC_BCH8 = 8 215}; 216 217enum stm32_fmc2_irq_state { 218 FMC2_IRQ_UNKNOWN = 0, 219 FMC2_IRQ_BCH, 220 FMC2_IRQ_SEQ 221}; 222 223struct stm32_fmc2_timings { 224 u8 tclr; 225 u8 tar; 226 u8 thiz; 227 u8 twait; 228 u8 thold_mem; 229 u8 tset_mem; 230 u8 thold_att; 231 u8 tset_att; 232}; 233 234struct stm32_fmc2_nand { 235 struct nand_chip chip; 236 struct gpio_desc *wp_gpio; 237 struct stm32_fmc2_timings timings; 238 int ncs; 239 int cs_used[FMC2_MAX_CE]; 240}; 241 242static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip) 243{ 244 return container_of(chip, struct stm32_fmc2_nand, chip); 245} 246 247struct stm32_fmc2_nfc; 248 249struct stm32_fmc2_nfc_data { 250 int max_ncs; 251 int (*set_cdev)(struct stm32_fmc2_nfc *nfc); 252}; 253 254struct stm32_fmc2_nfc { 255 struct nand_controller base; 256 struct stm32_fmc2_nand nand; 257 struct device *dev; 258 struct device *cdev; 259 struct regmap *regmap; 260 void __iomem *data_base[FMC2_MAX_CE]; 261 void __iomem *cmd_base[FMC2_MAX_CE]; 262 void __iomem *addr_base[FMC2_MAX_CE]; 263 phys_addr_t io_phys_addr; 264 phys_addr_t data_phys_addr[FMC2_MAX_CE]; 265 struct clk *clk; 266 u8 irq_state; 267 const struct stm32_fmc2_nfc_data *data; 268 269 struct dma_chan *dma_tx_ch; 270 struct dma_chan *dma_rx_ch; 271 struct dma_chan *dma_ecc_ch; 272 struct sg_table dma_data_sg; 273 struct sg_table dma_ecc_sg; 274 u8 *ecc_buf; 275 dma_addr_t dma_ecc_addr; 276 int dma_ecc_len; 277 u32 tx_dma_max_burst; 278 u32 rx_dma_max_burst; 279 280 struct completion complete; 281 struct completion dma_data_complete; 282 struct completion dma_ecc_complete; 283 284 u8 cs_assigned; 285 int cs_sel; 286}; 287 288static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base) 289{ 290 return container_of(base, struct stm32_fmc2_nfc, base); 291} 292 293static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip) 294{ 295 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 296 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 297 struct stm32_fmc2_timings *timings = &nand->timings; 298 u32 pmem, patt; 299 300 /* Set tclr/tar timings */ 301 regmap_update_bits(nfc->regmap, FMC2_PCR, 302 FMC2_PCR_TCLR | FMC2_PCR_TAR, 303 FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) | 304 FIELD_PREP(FMC2_PCR_TAR, timings->tar)); 305 306 /* Set tset/twait/thold/thiz timings in common bank */ 307 pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem); 308 pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait); 309 pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem); 310 pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz); 311 regmap_write(nfc->regmap, FMC2_PMEM, pmem); 312 313 /* Set tset/twait/thold/thiz timings in attribut bank */ 314 patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att); 315 patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait); 316 patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att); 317 patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz); 318 regmap_write(nfc->regmap, FMC2_PATT, patt); 319} 320 321static void stm32_fmc2_nfc_setup(struct nand_chip *chip) 322{ 323 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 324 u32 pcr = 0, pcr_mask; 325 326 /* Configure ECC algorithm (default configuration is Hamming) */ 327 pcr_mask = FMC2_PCR_ECCALG; 328 pcr_mask |= FMC2_PCR_BCHECC; 329 if (chip->ecc.strength == FMC2_ECC_BCH8) { 330 pcr |= FMC2_PCR_ECCALG; 331 pcr |= FMC2_PCR_BCHECC; 332 } else if (chip->ecc.strength == FMC2_ECC_BCH4) { 333 pcr |= FMC2_PCR_ECCALG; 334 } 335 336 /* Set buswidth */ 337 pcr_mask |= FMC2_PCR_PWID; 338 if (chip->options & NAND_BUSWIDTH_16) 339 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16); 340 341 /* Set ECC sector size */ 342 pcr_mask |= FMC2_PCR_ECCSS; 343 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512); 344 345 regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr); 346} 347 348static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr) 349{ 350 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 351 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 352 struct dma_slave_config dma_cfg; 353 int ret; 354 355 if (nand->cs_used[chipnr] == nfc->cs_sel) 356 return 0; 357 358 nfc->cs_sel = nand->cs_used[chipnr]; 359 stm32_fmc2_nfc_setup(chip); 360 stm32_fmc2_nfc_timings_init(chip); 361 362 if (nfc->dma_tx_ch) { 363 memset(&dma_cfg, 0, sizeof(dma_cfg)); 364 dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel]; 365 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 366 dma_cfg.dst_maxburst = nfc->tx_dma_max_burst / 367 dma_cfg.dst_addr_width; 368 369 ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg); 370 if (ret) { 371 dev_err(nfc->dev, "tx DMA engine slave config failed\n"); 372 return ret; 373 } 374 } 375 376 if (nfc->dma_rx_ch) { 377 memset(&dma_cfg, 0, sizeof(dma_cfg)); 378 dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel]; 379 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 380 dma_cfg.src_maxburst = nfc->rx_dma_max_burst / 381 dma_cfg.src_addr_width; 382 383 ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg); 384 if (ret) { 385 dev_err(nfc->dev, "rx DMA engine slave config failed\n"); 386 return ret; 387 } 388 } 389 390 if (nfc->dma_ecc_ch) { 391 /* 392 * Hamming: we read HECCR register 393 * BCH4/BCH8: we read BCHDSRSx registers 394 */ 395 memset(&dma_cfg, 0, sizeof(dma_cfg)); 396 dma_cfg.src_addr = nfc->io_phys_addr; 397 dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ? 398 FMC2_HECCR : FMC2_BCHDSR0; 399 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 400 401 ret = dmaengine_slave_config(nfc->dma_ecc_ch, &dma_cfg); 402 if (ret) { 403 dev_err(nfc->dev, "ECC DMA engine slave config failed\n"); 404 return ret; 405 } 406 407 /* Calculate ECC length needed for one sector */ 408 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ? 409 FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN; 410 } 411 412 return 0; 413} 414 415static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set) 416{ 417 u32 pcr; 418 419 pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) : 420 FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8); 421 422 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr); 423} 424 425static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable) 426{ 427 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN, 428 enable ? FMC2_PCR_ECCEN : 0); 429} 430 431static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc) 432{ 433 nfc->irq_state = FMC2_IRQ_SEQ; 434 435 regmap_update_bits(nfc->regmap, FMC2_CSQIER, 436 FMC2_CSQIER_TCIE, FMC2_CSQIER_TCIE); 437} 438 439static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc) 440{ 441 regmap_update_bits(nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, 0); 442 443 nfc->irq_state = FMC2_IRQ_UNKNOWN; 444} 445 446static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc) 447{ 448 regmap_write(nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ); 449} 450 451static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode) 452{ 453 nfc->irq_state = FMC2_IRQ_BCH; 454 455 if (mode == NAND_ECC_WRITE) 456 regmap_update_bits(nfc->regmap, FMC2_BCHIER, 457 FMC2_BCHIER_EPBRIE, FMC2_BCHIER_EPBRIE); 458 else 459 regmap_update_bits(nfc->regmap, FMC2_BCHIER, 460 FMC2_BCHIER_DERIE, FMC2_BCHIER_DERIE); 461} 462 463static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc) 464{ 465 regmap_update_bits(nfc->regmap, FMC2_BCHIER, 466 FMC2_BCHIER_DERIE | FMC2_BCHIER_EPBRIE, 0); 467 468 nfc->irq_state = FMC2_IRQ_UNKNOWN; 469} 470 471static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc) 472{ 473 regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ); 474} 475 476/* 477 * Enable ECC logic and reset syndrome/parity bits previously calculated 478 * Syndrome/parity bits is cleared by setting the ECCEN bit to 0 479 */ 480static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode) 481{ 482 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 483 484 stm32_fmc2_nfc_set_ecc(nfc, false); 485 486 if (chip->ecc.strength != FMC2_ECC_HAM) { 487 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN, 488 mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0); 489 490 reinit_completion(&nfc->complete); 491 stm32_fmc2_nfc_clear_bch_irq(nfc); 492 stm32_fmc2_nfc_enable_bch_irq(nfc, mode); 493 } 494 495 stm32_fmc2_nfc_set_ecc(nfc, true); 496} 497 498/* 499 * ECC Hamming calculation 500 * ECC is 3 bytes for 512 bytes of data (supports error correction up to 501 * max of 1-bit) 502 */ 503static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc) 504{ 505 ecc[0] = ecc_sta; 506 ecc[1] = ecc_sta >> 8; 507 ecc[2] = ecc_sta >> 16; 508} 509 510static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data, 511 u8 *ecc) 512{ 513 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 514 u32 sr, heccr; 515 int ret; 516 517 ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr, 518 sr & FMC2_SR_NWRF, 1, 519 1000 * FMC2_TIMEOUT_MS); 520 if (ret) { 521 dev_err(nfc->dev, "ham timeout\n"); 522 return ret; 523 } 524 525 regmap_read(nfc->regmap, FMC2_HECCR, &heccr); 526 stm32_fmc2_nfc_ham_set_ecc(heccr, ecc); 527 stm32_fmc2_nfc_set_ecc(nfc, false); 528 529 return 0; 530} 531 532static int stm32_fmc2_nfc_ham_correct(struct nand_chip *chip, u8 *dat, 533 u8 *read_ecc, u8 *calc_ecc) 534{ 535 u8 bit_position = 0, b0, b1, b2; 536 u32 byte_addr = 0, b; 537 u32 i, shifting = 1; 538 539 /* Indicate which bit and byte is faulty (if any) */ 540 b0 = read_ecc[0] ^ calc_ecc[0]; 541 b1 = read_ecc[1] ^ calc_ecc[1]; 542 b2 = read_ecc[2] ^ calc_ecc[2]; 543 b = b0 | (b1 << 8) | (b2 << 16); 544 545 /* No errors */ 546 if (likely(!b)) 547 return 0; 548 549 /* Calculate bit position */ 550 for (i = 0; i < 3; i++) { 551 switch (b % 4) { 552 case 2: 553 bit_position += shifting; 554 break; 555 case 1: 556 break; 557 default: 558 return -EBADMSG; 559 } 560 shifting <<= 1; 561 b >>= 2; 562 } 563 564 /* Calculate byte position */ 565 shifting = 1; 566 for (i = 0; i < 9; i++) { 567 switch (b % 4) { 568 case 2: 569 byte_addr += shifting; 570 break; 571 case 1: 572 break; 573 default: 574 return -EBADMSG; 575 } 576 shifting <<= 1; 577 b >>= 2; 578 } 579 580 /* Flip the bit */ 581 dat[byte_addr] ^= (1 << bit_position); 582 583 return 1; 584} 585 586/* 587 * ECC BCH calculation and correction 588 * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to 589 * max of 4-bit/8-bit) 590 */ 591static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data, 592 u8 *ecc) 593{ 594 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 595 u32 bchpbr; 596 597 /* Wait until the BCH code is ready */ 598 if (!wait_for_completion_timeout(&nfc->complete, 599 msecs_to_jiffies(FMC2_TIMEOUT_MS))) { 600 dev_err(nfc->dev, "bch timeout\n"); 601 stm32_fmc2_nfc_disable_bch_irq(nfc); 602 return -ETIMEDOUT; 603 } 604 605 /* Read parity bits */ 606 regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr); 607 ecc[0] = bchpbr; 608 ecc[1] = bchpbr >> 8; 609 ecc[2] = bchpbr >> 16; 610 ecc[3] = bchpbr >> 24; 611 612 regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr); 613 ecc[4] = bchpbr; 614 ecc[5] = bchpbr >> 8; 615 ecc[6] = bchpbr >> 16; 616 617 if (chip->ecc.strength == FMC2_ECC_BCH8) { 618 ecc[7] = bchpbr >> 24; 619 620 regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr); 621 ecc[8] = bchpbr; 622 ecc[9] = bchpbr >> 8; 623 ecc[10] = bchpbr >> 16; 624 ecc[11] = bchpbr >> 24; 625 626 regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr); 627 ecc[12] = bchpbr; 628 } 629 630 stm32_fmc2_nfc_set_ecc(nfc, false); 631 632 return 0; 633} 634 635static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta) 636{ 637 u32 bchdsr0 = ecc_sta[0]; 638 u32 bchdsr1 = ecc_sta[1]; 639 u32 bchdsr2 = ecc_sta[2]; 640 u32 bchdsr3 = ecc_sta[3]; 641 u32 bchdsr4 = ecc_sta[4]; 642 u16 pos[8]; 643 int i, den; 644 unsigned int nb_errs = 0; 645 646 /* No errors found */ 647 if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF))) 648 return 0; 649 650 /* Too many errors detected */ 651 if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE)) 652 return -EBADMSG; 653 654 pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1); 655 pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1); 656 pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2); 657 pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2); 658 pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3); 659 pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3); 660 pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4); 661 pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4); 662 663 den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0); 664 for (i = 0; i < den; i++) { 665 if (pos[i] < eccsize * 8) { 666 change_bit(pos[i], (unsigned long *)dat); 667 nb_errs++; 668 } 669 } 670 671 return nb_errs; 672} 673 674static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat, 675 u8 *read_ecc, u8 *calc_ecc) 676{ 677 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 678 u32 ecc_sta[5]; 679 680 /* Wait until the decoding error is ready */ 681 if (!wait_for_completion_timeout(&nfc->complete, 682 msecs_to_jiffies(FMC2_TIMEOUT_MS))) { 683 dev_err(nfc->dev, "bch timeout\n"); 684 stm32_fmc2_nfc_disable_bch_irq(nfc); 685 return -ETIMEDOUT; 686 } 687 688 regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5); 689 690 stm32_fmc2_nfc_set_ecc(nfc, false); 691 692 return stm32_fmc2_nfc_bch_decode(chip->ecc.size, dat, ecc_sta); 693} 694 695static int stm32_fmc2_nfc_read_page(struct nand_chip *chip, u8 *buf, 696 int oob_required, int page) 697{ 698 struct mtd_info *mtd = nand_to_mtd(chip); 699 int ret, i, s, stat, eccsize = chip->ecc.size; 700 int eccbytes = chip->ecc.bytes; 701 int eccsteps = chip->ecc.steps; 702 int eccstrength = chip->ecc.strength; 703 u8 *p = buf; 704 u8 *ecc_calc = chip->ecc.calc_buf; 705 u8 *ecc_code = chip->ecc.code_buf; 706 unsigned int max_bitflips = 0; 707 708 ret = nand_read_page_op(chip, page, 0, NULL, 0); 709 if (ret) 710 return ret; 711 712 for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps; 713 s++, i += eccbytes, p += eccsize) { 714 chip->ecc.hwctl(chip, NAND_ECC_READ); 715 716 /* Read the nand page sector (512 bytes) */ 717 ret = nand_change_read_column_op(chip, s * eccsize, p, 718 eccsize, false); 719 if (ret) 720 return ret; 721 722 /* Read the corresponding ECC bytes */ 723 ret = nand_change_read_column_op(chip, i, ecc_code, 724 eccbytes, false); 725 if (ret) 726 return ret; 727 728 /* Correct the data */ 729 stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc); 730 if (stat == -EBADMSG) 731 /* Check for empty pages with bitflips */ 732 stat = nand_check_erased_ecc_chunk(p, eccsize, 733 ecc_code, eccbytes, 734 NULL, 0, 735 eccstrength); 736 737 if (stat < 0) { 738 mtd->ecc_stats.failed++; 739 } else { 740 mtd->ecc_stats.corrected += stat; 741 max_bitflips = max_t(unsigned int, max_bitflips, stat); 742 } 743 } 744 745 /* Read oob */ 746 if (oob_required) { 747 ret = nand_change_read_column_op(chip, mtd->writesize, 748 chip->oob_poi, mtd->oobsize, 749 false); 750 if (ret) 751 return ret; 752 } 753 754 return max_bitflips; 755} 756 757/* Sequencer read/write configuration */ 758static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page, 759 int raw, bool write_data) 760{ 761 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 762 struct mtd_info *mtd = nand_to_mtd(chip); 763 u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN; 764 /* 765 * cfg[0] => csqcfgr1, cfg[1] => csqcfgr2, cfg[2] => csqcfgr3 766 * cfg[3] => csqar1, cfg[4] => csqar2 767 */ 768 u32 cfg[5]; 769 770 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN, 771 write_data ? FMC2_PCR_WEN : 0); 772 773 /* 774 * - Set Program Page/Page Read command 775 * - Enable DMA request data 776 * - Set timings 777 */ 778 cfg[0] = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T; 779 if (write_data) 780 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN); 781 else 782 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) | 783 FMC2_CSQCFGR1_CMD2EN | 784 FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) | 785 FMC2_CSQCFGR1_CMD2T; 786 787 /* 788 * - Set Random Data Input/Random Data Read command 789 * - Enable the sequencer to access the Spare data area 790 * - Enable DMA request status decoding for read 791 * - Set timings 792 */ 793 if (write_data) 794 cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN); 795 else 796 cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) | 797 FMC2_CSQCFGR2_RCMD2EN | 798 FIELD_PREP(FMC2_CSQCFGR2_RCMD2, NAND_CMD_RNDOUTSTART) | 799 FMC2_CSQCFGR2_RCMD1T | 800 FMC2_CSQCFGR2_RCMD2T; 801 if (!raw) { 802 cfg[1] |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN; 803 cfg[1] |= FMC2_CSQCFGR2_SQSDTEN; 804 } 805 806 /* 807 * - Set the number of sectors to be written 808 * - Set timings 809 */ 810 cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1); 811 if (write_data) { 812 cfg[2] |= FMC2_CSQCFGR3_RAC2T; 813 if (chip->options & NAND_ROW_ADDR_3) 814 cfg[2] |= FMC2_CSQCFGR3_AC5T; 815 else 816 cfg[2] |= FMC2_CSQCFGR3_AC4T; 817 } 818 819 /* 820 * Set the fourth first address cycles 821 * Byte 1 and byte 2 => column, we start at 0x0 822 * Byte 3 and byte 4 => page 823 */ 824 cfg[3] = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page); 825 cfg[3] |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8); 826 827 /* 828 * - Set chip enable number 829 * - Set ECC byte offset in the spare area 830 * - Calculate the number of address cycles to be issued 831 * - Set byte 5 of address cycle if needed 832 */ 833 cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel); 834 if (chip->options & NAND_BUSWIDTH_16) 835 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1); 836 else 837 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset); 838 if (chip->options & NAND_ROW_ADDR_3) { 839 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5); 840 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16); 841 } else { 842 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4); 843 } 844 845 regmap_bulk_write(nfc->regmap, FMC2_CSQCFGR1, cfg, 5); 846} 847 848static void stm32_fmc2_nfc_dma_callback(void *arg) 849{ 850 complete((struct completion *)arg); 851} 852 853/* Read/write data from/to a page */ 854static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf, 855 int raw, bool write_data) 856{ 857 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 858 struct dma_async_tx_descriptor *desc_data, *desc_ecc; 859 struct scatterlist *sg; 860 struct dma_chan *dma_ch = nfc->dma_rx_ch; 861 enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE; 862 enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM; 863 int eccsteps = chip->ecc.steps; 864 int eccsize = chip->ecc.size; 865 unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS); 866 const u8 *p = buf; 867 int s, ret; 868 869 /* Configure DMA data */ 870 if (write_data) { 871 dma_data_dir = DMA_TO_DEVICE; 872 dma_transfer_dir = DMA_MEM_TO_DEV; 873 dma_ch = nfc->dma_tx_ch; 874 } 875 876 for_each_sg(nfc->dma_data_sg.sgl, sg, eccsteps, s) { 877 sg_set_buf(sg, p, eccsize); 878 p += eccsize; 879 } 880 881 ret = dma_map_sg(nfc->dev, nfc->dma_data_sg.sgl, 882 eccsteps, dma_data_dir); 883 if (!ret) 884 return -EIO; 885 886 desc_data = dmaengine_prep_slave_sg(dma_ch, nfc->dma_data_sg.sgl, 887 eccsteps, dma_transfer_dir, 888 DMA_PREP_INTERRUPT); 889 if (!desc_data) { 890 ret = -ENOMEM; 891 goto err_unmap_data; 892 } 893 894 reinit_completion(&nfc->dma_data_complete); 895 reinit_completion(&nfc->complete); 896 desc_data->callback = stm32_fmc2_nfc_dma_callback; 897 desc_data->callback_param = &nfc->dma_data_complete; 898 ret = dma_submit_error(dmaengine_submit(desc_data)); 899 if (ret) 900 goto err_unmap_data; 901 902 dma_async_issue_pending(dma_ch); 903 904 if (!write_data && !raw) { 905 /* Configure DMA ECC status */ 906 for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) { 907 sg_dma_address(sg) = nfc->dma_ecc_addr + 908 s * nfc->dma_ecc_len; 909 sg_dma_len(sg) = nfc->dma_ecc_len; 910 } 911 912 desc_ecc = dmaengine_prep_slave_sg(nfc->dma_ecc_ch, 913 nfc->dma_ecc_sg.sgl, 914 eccsteps, dma_transfer_dir, 915 DMA_PREP_INTERRUPT); 916 if (!desc_ecc) { 917 ret = -ENOMEM; 918 goto err_unmap_data; 919 } 920 921 reinit_completion(&nfc->dma_ecc_complete); 922 desc_ecc->callback = stm32_fmc2_nfc_dma_callback; 923 desc_ecc->callback_param = &nfc->dma_ecc_complete; 924 ret = dma_submit_error(dmaengine_submit(desc_ecc)); 925 if (ret) 926 goto err_unmap_data; 927 928 dma_async_issue_pending(nfc->dma_ecc_ch); 929 } 930 931 stm32_fmc2_nfc_clear_seq_irq(nfc); 932 stm32_fmc2_nfc_enable_seq_irq(nfc); 933 934 /* Start the transfer */ 935 regmap_update_bits(nfc->regmap, FMC2_CSQCR, 936 FMC2_CSQCR_CSQSTART, FMC2_CSQCR_CSQSTART); 937 938 /* Wait end of sequencer transfer */ 939 if (!wait_for_completion_timeout(&nfc->complete, timeout)) { 940 dev_err(nfc->dev, "seq timeout\n"); 941 stm32_fmc2_nfc_disable_seq_irq(nfc); 942 dmaengine_terminate_all(dma_ch); 943 if (!write_data && !raw) 944 dmaengine_terminate_all(nfc->dma_ecc_ch); 945 ret = -ETIMEDOUT; 946 goto err_unmap_data; 947 } 948 949 /* Wait DMA data transfer completion */ 950 if (!wait_for_completion_timeout(&nfc->dma_data_complete, timeout)) { 951 dev_err(nfc->dev, "data DMA timeout\n"); 952 dmaengine_terminate_all(dma_ch); 953 ret = -ETIMEDOUT; 954 } 955 956 /* Wait DMA ECC transfer completion */ 957 if (!write_data && !raw) { 958 if (!wait_for_completion_timeout(&nfc->dma_ecc_complete, 959 timeout)) { 960 dev_err(nfc->dev, "ECC DMA timeout\n"); 961 dmaengine_terminate_all(nfc->dma_ecc_ch); 962 ret = -ETIMEDOUT; 963 } 964 } 965 966err_unmap_data: 967 dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir); 968 969 return ret; 970} 971 972static int stm32_fmc2_nfc_seq_write(struct nand_chip *chip, const u8 *buf, 973 int oob_required, int page, int raw) 974{ 975 struct mtd_info *mtd = nand_to_mtd(chip); 976 int ret; 977 978 /* Configure the sequencer */ 979 stm32_fmc2_nfc_rw_page_init(chip, page, raw, true); 980 981 /* Write the page */ 982 ret = stm32_fmc2_nfc_xfer(chip, buf, raw, true); 983 if (ret) 984 return ret; 985 986 /* Write oob */ 987 if (oob_required) { 988 unsigned int offset_in_page = mtd->writesize; 989 const void *buf = chip->oob_poi; 990 unsigned int len = mtd->oobsize; 991 992 if (!raw) { 993 struct mtd_oob_region oob_free; 994 995 mtd_ooblayout_free(mtd, 0, &oob_free); 996 offset_in_page += oob_free.offset; 997 buf += oob_free.offset; 998 len = oob_free.length; 999 } 1000 1001 ret = nand_change_write_column_op(chip, offset_in_page, 1002 buf, len, false); 1003 if (ret) 1004 return ret; 1005 } 1006 1007 return nand_prog_page_end_op(chip); 1008} 1009 1010static int stm32_fmc2_nfc_seq_write_page(struct nand_chip *chip, const u8 *buf, 1011 int oob_required, int page) 1012{ 1013 int ret; 1014 1015 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs); 1016 if (ret) 1017 return ret; 1018 1019 return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, false); 1020} 1021 1022static int stm32_fmc2_nfc_seq_write_page_raw(struct nand_chip *chip, 1023 const u8 *buf, int oob_required, 1024 int page) 1025{ 1026 int ret; 1027 1028 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs); 1029 if (ret) 1030 return ret; 1031 1032 return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, true); 1033} 1034 1035/* Get a status indicating which sectors have errors */ 1036static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc) 1037{ 1038 u32 csqemsr; 1039 1040 regmap_read(nfc->regmap, FMC2_CSQEMSR, &csqemsr); 1041 1042 return FIELD_GET(FMC2_CSQEMSR_SEM, csqemsr); 1043} 1044 1045static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat, 1046 u8 *read_ecc, u8 *calc_ecc) 1047{ 1048 struct mtd_info *mtd = nand_to_mtd(chip); 1049 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1050 int eccbytes = chip->ecc.bytes; 1051 int eccsteps = chip->ecc.steps; 1052 int eccstrength = chip->ecc.strength; 1053 int i, s, eccsize = chip->ecc.size; 1054 u32 *ecc_sta = (u32 *)nfc->ecc_buf; 1055 u16 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc); 1056 unsigned int max_bitflips = 0; 1057 1058 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) { 1059 int stat = 0; 1060 1061 if (eccstrength == FMC2_ECC_HAM) { 1062 /* Ecc_sta = FMC2_HECCR */ 1063 if (sta_map & BIT(s)) { 1064 stm32_fmc2_nfc_ham_set_ecc(*ecc_sta, 1065 &calc_ecc[i]); 1066 stat = stm32_fmc2_nfc_ham_correct(chip, dat, 1067 &read_ecc[i], 1068 &calc_ecc[i]); 1069 } 1070 ecc_sta++; 1071 } else { 1072 /* 1073 * Ecc_sta[0] = FMC2_BCHDSR0 1074 * Ecc_sta[1] = FMC2_BCHDSR1 1075 * Ecc_sta[2] = FMC2_BCHDSR2 1076 * Ecc_sta[3] = FMC2_BCHDSR3 1077 * Ecc_sta[4] = FMC2_BCHDSR4 1078 */ 1079 if (sta_map & BIT(s)) 1080 stat = stm32_fmc2_nfc_bch_decode(eccsize, dat, 1081 ecc_sta); 1082 ecc_sta += 5; 1083 } 1084 1085 if (stat == -EBADMSG) 1086 /* Check for empty pages with bitflips */ 1087 stat = nand_check_erased_ecc_chunk(dat, eccsize, 1088 &read_ecc[i], 1089 eccbytes, 1090 NULL, 0, 1091 eccstrength); 1092 1093 if (stat < 0) { 1094 mtd->ecc_stats.failed++; 1095 } else { 1096 mtd->ecc_stats.corrected += stat; 1097 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1098 } 1099 } 1100 1101 return max_bitflips; 1102} 1103 1104static int stm32_fmc2_nfc_seq_read_page(struct nand_chip *chip, u8 *buf, 1105 int oob_required, int page) 1106{ 1107 struct mtd_info *mtd = nand_to_mtd(chip); 1108 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1109 u8 *ecc_calc = chip->ecc.calc_buf; 1110 u8 *ecc_code = chip->ecc.code_buf; 1111 u16 sta_map; 1112 int ret; 1113 1114 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs); 1115 if (ret) 1116 return ret; 1117 1118 /* Configure the sequencer */ 1119 stm32_fmc2_nfc_rw_page_init(chip, page, 0, false); 1120 1121 /* Read the page */ 1122 ret = stm32_fmc2_nfc_xfer(chip, buf, 0, false); 1123 if (ret) 1124 return ret; 1125 1126 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc); 1127 1128 /* Check if errors happen */ 1129 if (likely(!sta_map)) { 1130 if (oob_required) 1131 return nand_change_read_column_op(chip, mtd->writesize, 1132 chip->oob_poi, 1133 mtd->oobsize, false); 1134 1135 return 0; 1136 } 1137 1138 /* Read oob */ 1139 ret = nand_change_read_column_op(chip, mtd->writesize, 1140 chip->oob_poi, mtd->oobsize, false); 1141 if (ret) 1142 return ret; 1143 1144 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 1145 chip->ecc.total); 1146 if (ret) 1147 return ret; 1148 1149 /* Correct data */ 1150 return chip->ecc.correct(chip, buf, ecc_code, ecc_calc); 1151} 1152 1153static int stm32_fmc2_nfc_seq_read_page_raw(struct nand_chip *chip, u8 *buf, 1154 int oob_required, int page) 1155{ 1156 struct mtd_info *mtd = nand_to_mtd(chip); 1157 int ret; 1158 1159 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs); 1160 if (ret) 1161 return ret; 1162 1163 /* Configure the sequencer */ 1164 stm32_fmc2_nfc_rw_page_init(chip, page, 1, false); 1165 1166 /* Read the page */ 1167 ret = stm32_fmc2_nfc_xfer(chip, buf, 1, false); 1168 if (ret) 1169 return ret; 1170 1171 /* Read oob */ 1172 if (oob_required) 1173 return nand_change_read_column_op(chip, mtd->writesize, 1174 chip->oob_poi, mtd->oobsize, 1175 false); 1176 1177 return 0; 1178} 1179 1180static irqreturn_t stm32_fmc2_nfc_irq(int irq, void *dev_id) 1181{ 1182 struct stm32_fmc2_nfc *nfc = (struct stm32_fmc2_nfc *)dev_id; 1183 1184 if (nfc->irq_state == FMC2_IRQ_SEQ) 1185 /* Sequencer is used */ 1186 stm32_fmc2_nfc_disable_seq_irq(nfc); 1187 else if (nfc->irq_state == FMC2_IRQ_BCH) 1188 /* BCH is used */ 1189 stm32_fmc2_nfc_disable_bch_irq(nfc); 1190 1191 complete(&nfc->complete); 1192 1193 return IRQ_HANDLED; 1194} 1195 1196static void stm32_fmc2_nfc_read_data(struct nand_chip *chip, void *buf, 1197 unsigned int len, bool force_8bit) 1198{ 1199 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1200 void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel]; 1201 1202 if (force_8bit && chip->options & NAND_BUSWIDTH_16) 1203 /* Reconfigure bus width to 8-bit */ 1204 stm32_fmc2_nfc_set_buswidth_16(nfc, false); 1205 1206 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) { 1207 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) { 1208 *(u8 *)buf = readb_relaxed(io_addr_r); 1209 buf += sizeof(u8); 1210 len -= sizeof(u8); 1211 } 1212 1213 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && 1214 len >= sizeof(u16)) { 1215 *(u16 *)buf = readw_relaxed(io_addr_r); 1216 buf += sizeof(u16); 1217 len -= sizeof(u16); 1218 } 1219 } 1220 1221 /* Buf is aligned */ 1222 while (len >= sizeof(u32)) { 1223 *(u32 *)buf = readl_relaxed(io_addr_r); 1224 buf += sizeof(u32); 1225 len -= sizeof(u32); 1226 } 1227 1228 /* Read remaining bytes */ 1229 if (len >= sizeof(u16)) { 1230 *(u16 *)buf = readw_relaxed(io_addr_r); 1231 buf += sizeof(u16); 1232 len -= sizeof(u16); 1233 } 1234 1235 if (len) 1236 *(u8 *)buf = readb_relaxed(io_addr_r); 1237 1238 if (force_8bit && chip->options & NAND_BUSWIDTH_16) 1239 /* Reconfigure bus width to 16-bit */ 1240 stm32_fmc2_nfc_set_buswidth_16(nfc, true); 1241} 1242 1243static void stm32_fmc2_nfc_write_data(struct nand_chip *chip, const void *buf, 1244 unsigned int len, bool force_8bit) 1245{ 1246 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1247 void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel]; 1248 1249 if (force_8bit && chip->options & NAND_BUSWIDTH_16) 1250 /* Reconfigure bus width to 8-bit */ 1251 stm32_fmc2_nfc_set_buswidth_16(nfc, false); 1252 1253 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) { 1254 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) { 1255 writeb_relaxed(*(u8 *)buf, io_addr_w); 1256 buf += sizeof(u8); 1257 len -= sizeof(u8); 1258 } 1259 1260 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && 1261 len >= sizeof(u16)) { 1262 writew_relaxed(*(u16 *)buf, io_addr_w); 1263 buf += sizeof(u16); 1264 len -= sizeof(u16); 1265 } 1266 } 1267 1268 /* Buf is aligned */ 1269 while (len >= sizeof(u32)) { 1270 writel_relaxed(*(u32 *)buf, io_addr_w); 1271 buf += sizeof(u32); 1272 len -= sizeof(u32); 1273 } 1274 1275 /* Write remaining bytes */ 1276 if (len >= sizeof(u16)) { 1277 writew_relaxed(*(u16 *)buf, io_addr_w); 1278 buf += sizeof(u16); 1279 len -= sizeof(u16); 1280 } 1281 1282 if (len) 1283 writeb_relaxed(*(u8 *)buf, io_addr_w); 1284 1285 if (force_8bit && chip->options & NAND_BUSWIDTH_16) 1286 /* Reconfigure bus width to 16-bit */ 1287 stm32_fmc2_nfc_set_buswidth_16(nfc, true); 1288} 1289 1290static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip, 1291 unsigned long timeout_ms) 1292{ 1293 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1294 const struct nand_sdr_timings *timings; 1295 u32 isr, sr; 1296 1297 /* Check if there is no pending requests to the NAND flash */ 1298 if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr, 1299 sr & FMC2_SR_NWRF, 1, 1300 1000 * FMC2_TIMEOUT_MS)) 1301 dev_warn(nfc->dev, "Waitrdy timeout\n"); 1302 1303 /* Wait tWB before R/B# signal is low */ 1304 timings = nand_get_sdr_timings(nand_get_interface_config(chip)); 1305 ndelay(PSEC_TO_NSEC(timings->tWB_max)); 1306 1307 /* R/B# signal is low, clear high level flag */ 1308 regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF); 1309 1310 /* Wait R/B# signal is high */ 1311 return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr, 1312 isr & FMC2_ISR_IHLF, 5, 1313 1000 * FMC2_TIMEOUT_MS); 1314} 1315 1316static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip, 1317 const struct nand_operation *op, 1318 bool check_only) 1319{ 1320 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1321 const struct nand_op_instr *instr = NULL; 1322 unsigned int op_id, i, timeout; 1323 int ret; 1324 1325 if (check_only) 1326 return 0; 1327 1328 ret = stm32_fmc2_nfc_select_chip(chip, op->cs); 1329 if (ret) 1330 return ret; 1331 1332 for (op_id = 0; op_id < op->ninstrs; op_id++) { 1333 instr = &op->instrs[op_id]; 1334 1335 switch (instr->type) { 1336 case NAND_OP_CMD_INSTR: 1337 writeb_relaxed(instr->ctx.cmd.opcode, 1338 nfc->cmd_base[nfc->cs_sel]); 1339 break; 1340 1341 case NAND_OP_ADDR_INSTR: 1342 for (i = 0; i < instr->ctx.addr.naddrs; i++) 1343 writeb_relaxed(instr->ctx.addr.addrs[i], 1344 nfc->addr_base[nfc->cs_sel]); 1345 break; 1346 1347 case NAND_OP_DATA_IN_INSTR: 1348 stm32_fmc2_nfc_read_data(chip, instr->ctx.data.buf.in, 1349 instr->ctx.data.len, 1350 instr->ctx.data.force_8bit); 1351 break; 1352 1353 case NAND_OP_DATA_OUT_INSTR: 1354 stm32_fmc2_nfc_write_data(chip, instr->ctx.data.buf.out, 1355 instr->ctx.data.len, 1356 instr->ctx.data.force_8bit); 1357 break; 1358 1359 case NAND_OP_WAITRDY_INSTR: 1360 timeout = instr->ctx.waitrdy.timeout_ms; 1361 ret = stm32_fmc2_nfc_waitrdy(chip, timeout); 1362 break; 1363 } 1364 } 1365 1366 return ret; 1367} 1368 1369static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc) 1370{ 1371 u32 pcr; 1372 1373 regmap_read(nfc->regmap, FMC2_PCR, &pcr); 1374 1375 /* Set CS used to undefined */ 1376 nfc->cs_sel = -1; 1377 1378 /* Enable wait feature and nand flash memory bank */ 1379 pcr |= FMC2_PCR_PWAITEN; 1380 pcr |= FMC2_PCR_PBKEN; 1381 1382 /* Set buswidth to 8 bits mode for identification */ 1383 pcr &= ~FMC2_PCR_PWID; 1384 1385 /* ECC logic is disabled */ 1386 pcr &= ~FMC2_PCR_ECCEN; 1387 1388 /* Default mode */ 1389 pcr &= ~FMC2_PCR_ECCALG; 1390 pcr &= ~FMC2_PCR_BCHECC; 1391 pcr &= ~FMC2_PCR_WEN; 1392 1393 /* Set default ECC sector size */ 1394 pcr &= ~FMC2_PCR_ECCSS; 1395 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048); 1396 1397 /* Set default tclr/tar timings */ 1398 pcr &= ~FMC2_PCR_TCLR; 1399 pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT); 1400 pcr &= ~FMC2_PCR_TAR; 1401 pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); 1402 1403 /* Enable FMC2 controller */ 1404 if (nfc->dev == nfc->cdev) 1405 regmap_update_bits(nfc->regmap, FMC2_BCR1, 1406 FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); 1407 1408 regmap_write(nfc->regmap, FMC2_PCR, pcr); 1409 regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT); 1410 regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT); 1411} 1412 1413static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip, 1414 const struct nand_sdr_timings *sdrt) 1415{ 1416 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1417 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 1418 struct stm32_fmc2_timings *tims = &nand->timings; 1419 unsigned long hclk = clk_get_rate(nfc->clk); 1420 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); 1421 unsigned long timing, tar, tclr, thiz, twait; 1422 unsigned long tset_mem, tset_att, thold_mem, thold_att; 1423 1424 tar = max_t(unsigned long, hclkp, sdrt->tAR_min); 1425 timing = DIV_ROUND_UP(tar, hclkp) - 1; 1426 tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); 1427 1428 tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min); 1429 timing = DIV_ROUND_UP(tclr, hclkp) - 1; 1430 tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); 1431 1432 tims->thiz = FMC2_THIZ; 1433 thiz = (tims->thiz + 1) * hclkp; 1434 1435 /* 1436 * tWAIT > tRP 1437 * tWAIT > tWP 1438 * tWAIT > tREA + tIO 1439 */ 1440 twait = max_t(unsigned long, hclkp, sdrt->tRP_min); 1441 twait = max_t(unsigned long, twait, sdrt->tWP_min); 1442 twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO); 1443 timing = DIV_ROUND_UP(twait, hclkp); 1444 tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1445 1446 /* 1447 * tSETUP_MEM > tCS - tWAIT 1448 * tSETUP_MEM > tALS - tWAIT 1449 * tSETUP_MEM > tDS - (tWAIT - tHIZ) 1450 */ 1451 tset_mem = hclkp; 1452 if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait)) 1453 tset_mem = sdrt->tCS_min - twait; 1454 if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait)) 1455 tset_mem = sdrt->tALS_min - twait; 1456 if (twait > thiz && (sdrt->tDS_min > twait - thiz) && 1457 (tset_mem < sdrt->tDS_min - (twait - thiz))) 1458 tset_mem = sdrt->tDS_min - (twait - thiz); 1459 timing = DIV_ROUND_UP(tset_mem, hclkp); 1460 tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1461 1462 /* 1463 * tHOLD_MEM > tCH 1464 * tHOLD_MEM > tREH - tSETUP_MEM 1465 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) 1466 */ 1467 thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min); 1468 if (sdrt->tREH_min > tset_mem && 1469 (thold_mem < sdrt->tREH_min - tset_mem)) 1470 thold_mem = sdrt->tREH_min - tset_mem; 1471 if ((sdrt->tRC_min > tset_mem + twait) && 1472 (thold_mem < sdrt->tRC_min - (tset_mem + twait))) 1473 thold_mem = sdrt->tRC_min - (tset_mem + twait); 1474 if ((sdrt->tWC_min > tset_mem + twait) && 1475 (thold_mem < sdrt->tWC_min - (tset_mem + twait))) 1476 thold_mem = sdrt->tWC_min - (tset_mem + twait); 1477 timing = DIV_ROUND_UP(thold_mem, hclkp); 1478 tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1479 1480 /* 1481 * tSETUP_ATT > tCS - tWAIT 1482 * tSETUP_ATT > tCLS - tWAIT 1483 * tSETUP_ATT > tALS - tWAIT 1484 * tSETUP_ATT > tRHW - tHOLD_MEM 1485 * tSETUP_ATT > tDS - (tWAIT - tHIZ) 1486 */ 1487 tset_att = hclkp; 1488 if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait)) 1489 tset_att = sdrt->tCS_min - twait; 1490 if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait)) 1491 tset_att = sdrt->tCLS_min - twait; 1492 if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait)) 1493 tset_att = sdrt->tALS_min - twait; 1494 if (sdrt->tRHW_min > thold_mem && 1495 (tset_att < sdrt->tRHW_min - thold_mem)) 1496 tset_att = sdrt->tRHW_min - thold_mem; 1497 if (twait > thiz && (sdrt->tDS_min > twait - thiz) && 1498 (tset_att < sdrt->tDS_min - (twait - thiz))) 1499 tset_att = sdrt->tDS_min - (twait - thiz); 1500 timing = DIV_ROUND_UP(tset_att, hclkp); 1501 tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1502 1503 /* 1504 * tHOLD_ATT > tALH 1505 * tHOLD_ATT > tCH 1506 * tHOLD_ATT > tCLH 1507 * tHOLD_ATT > tCOH 1508 * tHOLD_ATT > tDH 1509 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM 1510 * tHOLD_ATT > tADL - tSETUP_MEM 1511 * tHOLD_ATT > tWH - tSETUP_MEM 1512 * tHOLD_ATT > tWHR - tSETUP_MEM 1513 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) 1514 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) 1515 */ 1516 thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min); 1517 thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min); 1518 thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min); 1519 thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min); 1520 thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min); 1521 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && 1522 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) 1523 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; 1524 if (sdrt->tADL_min > tset_mem && 1525 (thold_att < sdrt->tADL_min - tset_mem)) 1526 thold_att = sdrt->tADL_min - tset_mem; 1527 if (sdrt->tWH_min > tset_mem && 1528 (thold_att < sdrt->tWH_min - tset_mem)) 1529 thold_att = sdrt->tWH_min - tset_mem; 1530 if (sdrt->tWHR_min > tset_mem && 1531 (thold_att < sdrt->tWHR_min - tset_mem)) 1532 thold_att = sdrt->tWHR_min - tset_mem; 1533 if ((sdrt->tRC_min > tset_att + twait) && 1534 (thold_att < sdrt->tRC_min - (tset_att + twait))) 1535 thold_att = sdrt->tRC_min - (tset_att + twait); 1536 if ((sdrt->tWC_min > tset_att + twait) && 1537 (thold_att < sdrt->tWC_min - (tset_att + twait))) 1538 thold_att = sdrt->tWC_min - (tset_att + twait); 1539 timing = DIV_ROUND_UP(thold_att, hclkp); 1540 tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1541} 1542 1543static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, 1544 const struct nand_interface_config *conf) 1545{ 1546 const struct nand_sdr_timings *sdrt; 1547 1548 sdrt = nand_get_sdr_timings(conf); 1549 if (IS_ERR(sdrt)) 1550 return PTR_ERR(sdrt); 1551 1552 if (conf->timings.mode > 3) 1553 return -EOPNOTSUPP; 1554 1555 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 1556 return 0; 1557 1558 stm32_fmc2_nfc_calc_timings(chip, sdrt); 1559 stm32_fmc2_nfc_timings_init(chip); 1560 1561 return 0; 1562} 1563 1564static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) 1565{ 1566 struct dma_slave_caps caps; 1567 int ret = 0; 1568 1569 nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx"); 1570 if (IS_ERR(nfc->dma_tx_ch)) { 1571 ret = PTR_ERR(nfc->dma_tx_ch); 1572 if (ret != -ENODEV && ret != -EPROBE_DEFER) 1573 dev_err(nfc->dev, 1574 "failed to request tx DMA channel: %d\n", ret); 1575 nfc->dma_tx_ch = NULL; 1576 goto err_dma; 1577 } 1578 1579 ret = dma_get_slave_caps(nfc->dma_tx_ch, &caps); 1580 if (ret) 1581 return ret; 1582 nfc->tx_dma_max_burst = caps.max_burst; 1583 1584 nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx"); 1585 if (IS_ERR(nfc->dma_rx_ch)) { 1586 ret = PTR_ERR(nfc->dma_rx_ch); 1587 if (ret != -ENODEV && ret != -EPROBE_DEFER) 1588 dev_err(nfc->dev, 1589 "failed to request rx DMA channel: %d\n", ret); 1590 nfc->dma_rx_ch = NULL; 1591 goto err_dma; 1592 } 1593 1594 ret = dma_get_slave_caps(nfc->dma_rx_ch, &caps); 1595 if (ret) 1596 return ret; 1597 nfc->rx_dma_max_burst = caps.max_burst; 1598 1599 nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc"); 1600 if (IS_ERR(nfc->dma_ecc_ch)) { 1601 ret = PTR_ERR(nfc->dma_ecc_ch); 1602 if (ret != -ENODEV && ret != -EPROBE_DEFER) 1603 dev_err(nfc->dev, 1604 "failed to request ecc DMA channel: %d\n", ret); 1605 nfc->dma_ecc_ch = NULL; 1606 goto err_dma; 1607 } 1608 1609 ret = sg_alloc_table(&nfc->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL); 1610 if (ret) 1611 return ret; 1612 1613 /* Allocate a buffer to store ECC status registers */ 1614 nfc->ecc_buf = dmam_alloc_coherent(nfc->dev, FMC2_MAX_ECC_BUF_LEN, 1615 &nfc->dma_ecc_addr, GFP_KERNEL); 1616 if (!nfc->ecc_buf) 1617 return -ENOMEM; 1618 1619 ret = sg_alloc_table(&nfc->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL); 1620 if (ret) 1621 return ret; 1622 1623 init_completion(&nfc->dma_data_complete); 1624 init_completion(&nfc->dma_ecc_complete); 1625 1626 return 0; 1627 1628err_dma: 1629 if (ret == -ENODEV) { 1630 dev_warn(nfc->dev, 1631 "DMAs not defined in the DT, polling mode is used\n"); 1632 ret = 0; 1633 } 1634 1635 return ret; 1636} 1637 1638static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip) 1639{ 1640 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1641 1642 /* 1643 * Specific callbacks to read/write a page depending on 1644 * the mode (polling/sequencer) and the algo used (Hamming, BCH). 1645 */ 1646 if (nfc->dma_tx_ch && nfc->dma_rx_ch && nfc->dma_ecc_ch) { 1647 /* DMA => use sequencer mode callbacks */ 1648 chip->ecc.correct = stm32_fmc2_nfc_seq_correct; 1649 chip->ecc.write_page = stm32_fmc2_nfc_seq_write_page; 1650 chip->ecc.read_page = stm32_fmc2_nfc_seq_read_page; 1651 chip->ecc.write_page_raw = stm32_fmc2_nfc_seq_write_page_raw; 1652 chip->ecc.read_page_raw = stm32_fmc2_nfc_seq_read_page_raw; 1653 } else { 1654 /* No DMA => use polling mode callbacks */ 1655 chip->ecc.hwctl = stm32_fmc2_nfc_hwctl; 1656 if (chip->ecc.strength == FMC2_ECC_HAM) { 1657 /* Hamming is used */ 1658 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate; 1659 chip->ecc.correct = stm32_fmc2_nfc_ham_correct; 1660 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK; 1661 } else { 1662 /* BCH is used */ 1663 chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate; 1664 chip->ecc.correct = stm32_fmc2_nfc_bch_correct; 1665 chip->ecc.read_page = stm32_fmc2_nfc_read_page; 1666 } 1667 } 1668 1669 /* Specific configurations depending on the algo used */ 1670 if (chip->ecc.strength == FMC2_ECC_HAM) 1671 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3; 1672 else if (chip->ecc.strength == FMC2_ECC_BCH8) 1673 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13; 1674 else 1675 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7; 1676} 1677 1678static int stm32_fmc2_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, 1679 struct mtd_oob_region *oobregion) 1680{ 1681 struct nand_chip *chip = mtd_to_nand(mtd); 1682 struct nand_ecc_ctrl *ecc = &chip->ecc; 1683 1684 if (section) 1685 return -ERANGE; 1686 1687 oobregion->length = ecc->total; 1688 oobregion->offset = FMC2_BBM_LEN; 1689 1690 return 0; 1691} 1692 1693static int stm32_fmc2_nfc_ooblayout_free(struct mtd_info *mtd, int section, 1694 struct mtd_oob_region *oobregion) 1695{ 1696 struct nand_chip *chip = mtd_to_nand(mtd); 1697 struct nand_ecc_ctrl *ecc = &chip->ecc; 1698 1699 if (section) 1700 return -ERANGE; 1701 1702 oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN; 1703 oobregion->offset = ecc->total + FMC2_BBM_LEN; 1704 1705 return 0; 1706} 1707 1708static const struct mtd_ooblayout_ops stm32_fmc2_nfc_ooblayout_ops = { 1709 .ecc = stm32_fmc2_nfc_ooblayout_ecc, 1710 .free = stm32_fmc2_nfc_ooblayout_free, 1711}; 1712 1713static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength) 1714{ 1715 /* Hamming */ 1716 if (strength == FMC2_ECC_HAM) 1717 return 4; 1718 1719 /* BCH8 */ 1720 if (strength == FMC2_ECC_BCH8) 1721 return 14; 1722 1723 /* BCH4 */ 1724 return 8; 1725} 1726 1727NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes, 1728 FMC2_ECC_STEP_SIZE, 1729 FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8); 1730 1731static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip) 1732{ 1733 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1734 struct mtd_info *mtd = nand_to_mtd(chip); 1735 int ret; 1736 1737 /* 1738 * Only NAND_ECC_ENGINE_TYPE_ON_HOST mode is actually supported 1739 * Hamming => ecc.strength = 1 1740 * BCH4 => ecc.strength = 4 1741 * BCH8 => ecc.strength = 8 1742 * ECC sector size = 512 1743 */ 1744 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { 1745 dev_err(nfc->dev, 1746 "nand_ecc_engine_type is not well defined in the DT\n"); 1747 return -EINVAL; 1748 } 1749 1750 /* Default ECC settings in case they are not set in the device tree */ 1751 if (!chip->ecc.size) 1752 chip->ecc.size = FMC2_ECC_STEP_SIZE; 1753 1754 if (!chip->ecc.strength) 1755 chip->ecc.strength = FMC2_ECC_BCH8; 1756 1757 ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps, 1758 mtd->oobsize - FMC2_BBM_LEN); 1759 if (ret) { 1760 dev_err(nfc->dev, "no valid ECC settings set\n"); 1761 return ret; 1762 } 1763 1764 if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) { 1765 dev_err(nfc->dev, "nand page size is not supported\n"); 1766 return -EINVAL; 1767 } 1768 1769 if (chip->bbt_options & NAND_BBT_USE_FLASH) 1770 chip->bbt_options |= NAND_BBT_NO_OOB; 1771 1772 stm32_fmc2_nfc_nand_callbacks_setup(chip); 1773 1774 mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops); 1775 1776 stm32_fmc2_nfc_setup(chip); 1777 1778 return 0; 1779} 1780 1781static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = { 1782 .attach_chip = stm32_fmc2_nfc_attach_chip, 1783 .exec_op = stm32_fmc2_nfc_exec_op, 1784 .setup_interface = stm32_fmc2_nfc_setup_interface, 1785}; 1786 1787static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand) 1788{ 1789 if (nand->wp_gpio) 1790 gpiod_set_value(nand->wp_gpio, 1); 1791} 1792 1793static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand) 1794{ 1795 if (nand->wp_gpio) 1796 gpiod_set_value(nand->wp_gpio, 0); 1797} 1798 1799static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, 1800 struct device_node *dn) 1801{ 1802 struct stm32_fmc2_nand *nand = &nfc->nand; 1803 u32 cs; 1804 int ret, i; 1805 1806 if (!of_get_property(dn, "reg", &nand->ncs)) 1807 return -EINVAL; 1808 1809 nand->ncs /= sizeof(u32); 1810 if (!nand->ncs) { 1811 dev_err(nfc->dev, "invalid reg property size\n"); 1812 return -EINVAL; 1813 } 1814 1815 for (i = 0; i < nand->ncs; i++) { 1816 ret = of_property_read_u32_index(dn, "reg", i, &cs); 1817 if (ret) { 1818 dev_err(nfc->dev, "could not retrieve reg property: %d\n", 1819 ret); 1820 return ret; 1821 } 1822 1823 if (cs >= nfc->data->max_ncs) { 1824 dev_err(nfc->dev, "invalid reg value: %d\n", cs); 1825 return -EINVAL; 1826 } 1827 1828 if (nfc->cs_assigned & BIT(cs)) { 1829 dev_err(nfc->dev, "cs already assigned: %d\n", cs); 1830 return -EINVAL; 1831 } 1832 1833 nfc->cs_assigned |= BIT(cs); 1834 nand->cs_used[i] = cs; 1835 } 1836 1837 nand->wp_gpio = devm_fwnode_gpiod_get(nfc->dev, of_fwnode_handle(dn), 1838 "wp", GPIOD_OUT_HIGH, "wp"); 1839 if (IS_ERR(nand->wp_gpio)) { 1840 ret = PTR_ERR(nand->wp_gpio); 1841 if (ret != -ENOENT) 1842 return dev_err_probe(nfc->dev, ret, 1843 "failed to request WP GPIO\n"); 1844 1845 nand->wp_gpio = NULL; 1846 } 1847 1848 nand_set_flash_node(&nand->chip, dn); 1849 1850 return 0; 1851} 1852 1853static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc) 1854{ 1855 struct device_node *dn = nfc->dev->of_node; 1856 int nchips = of_get_child_count(dn); 1857 int ret = 0; 1858 1859 if (!nchips) { 1860 dev_err(nfc->dev, "NAND chip not defined\n"); 1861 return -EINVAL; 1862 } 1863 1864 if (nchips > 1) { 1865 dev_err(nfc->dev, "too many NAND chips defined\n"); 1866 return -EINVAL; 1867 } 1868 1869 for_each_child_of_node_scoped(dn, child) { 1870 ret = stm32_fmc2_nfc_parse_child(nfc, child); 1871 if (ret < 0) 1872 return ret; 1873 } 1874 1875 return ret; 1876} 1877 1878static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc) 1879{ 1880 struct device *dev = nfc->dev; 1881 bool ebi_found = false; 1882 1883 if (dev->parent && of_device_is_compatible(dev->parent->of_node, 1884 "st,stm32mp1-fmc2-ebi")) 1885 ebi_found = true; 1886 1887 if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) { 1888 if (ebi_found) { 1889 nfc->cdev = dev->parent; 1890 1891 return 0; 1892 } 1893 1894 return -EINVAL; 1895 } 1896 1897 if (ebi_found) 1898 return -EINVAL; 1899 1900 nfc->cdev = dev; 1901 1902 return 0; 1903} 1904 1905static int stm32_fmc2_nfc_probe(struct platform_device *pdev) 1906{ 1907 struct device *dev = &pdev->dev; 1908 struct reset_control *rstc; 1909 struct stm32_fmc2_nfc *nfc; 1910 struct stm32_fmc2_nand *nand; 1911 struct resource *res; 1912 struct mtd_info *mtd; 1913 struct nand_chip *chip; 1914 struct resource cres; 1915 int chip_cs, mem_region, ret, irq; 1916 int start_region = 0; 1917 1918 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1919 if (!nfc) 1920 return -ENOMEM; 1921 1922 nfc->dev = dev; 1923 nand_controller_init(&nfc->base); 1924 nfc->base.ops = &stm32_fmc2_nfc_controller_ops; 1925 1926 nfc->data = of_device_get_match_data(dev); 1927 if (!nfc->data) 1928 return -EINVAL; 1929 1930 if (nfc->data->set_cdev) { 1931 ret = nfc->data->set_cdev(nfc); 1932 if (ret) 1933 return ret; 1934 } else { 1935 nfc->cdev = dev->parent; 1936 } 1937 1938 ret = stm32_fmc2_nfc_parse_dt(nfc); 1939 if (ret) 1940 return ret; 1941 1942 ret = of_address_to_resource(nfc->cdev->of_node, 0, &cres); 1943 if (ret) 1944 return ret; 1945 1946 nfc->io_phys_addr = cres.start; 1947 1948 nfc->regmap = device_node_to_regmap(nfc->cdev->of_node); 1949 if (IS_ERR(nfc->regmap)) 1950 return PTR_ERR(nfc->regmap); 1951 1952 if (nfc->dev == nfc->cdev) 1953 start_region = 1; 1954 1955 for (chip_cs = 0, mem_region = start_region; chip_cs < nfc->data->max_ncs; 1956 chip_cs++, mem_region += 3) { 1957 if (!(nfc->cs_assigned & BIT(chip_cs))) 1958 continue; 1959 1960 nfc->data_base[chip_cs] = devm_platform_get_and_ioremap_resource(pdev, 1961 mem_region, &res); 1962 if (IS_ERR(nfc->data_base[chip_cs])) 1963 return PTR_ERR(nfc->data_base[chip_cs]); 1964 1965 nfc->data_phys_addr[chip_cs] = res->start; 1966 1967 nfc->cmd_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 1); 1968 if (IS_ERR(nfc->cmd_base[chip_cs])) 1969 return PTR_ERR(nfc->cmd_base[chip_cs]); 1970 1971 nfc->addr_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 2); 1972 if (IS_ERR(nfc->addr_base[chip_cs])) 1973 return PTR_ERR(nfc->addr_base[chip_cs]); 1974 } 1975 1976 irq = platform_get_irq(pdev, 0); 1977 if (irq < 0) 1978 return irq; 1979 1980 ret = devm_request_irq(dev, irq, stm32_fmc2_nfc_irq, 0, 1981 dev_name(dev), nfc); 1982 if (ret) { 1983 dev_err(dev, "failed to request irq\n"); 1984 return ret; 1985 } 1986 1987 init_completion(&nfc->complete); 1988 1989 nfc->clk = devm_clk_get_enabled(nfc->cdev, NULL); 1990 if (IS_ERR(nfc->clk)) { 1991 dev_err(dev, "can not get and enable the clock\n"); 1992 return PTR_ERR(nfc->clk); 1993 } 1994 1995 rstc = devm_reset_control_get(dev, NULL); 1996 if (IS_ERR(rstc)) { 1997 ret = PTR_ERR(rstc); 1998 if (ret == -EPROBE_DEFER) 1999 return ret; 2000 } else { 2001 reset_control_assert(rstc); 2002 reset_control_deassert(rstc); 2003 } 2004 2005 ret = stm32_fmc2_nfc_dma_setup(nfc); 2006 if (ret) 2007 goto err_release_dma; 2008 2009 stm32_fmc2_nfc_init(nfc); 2010 2011 nand = &nfc->nand; 2012 chip = &nand->chip; 2013 mtd = nand_to_mtd(chip); 2014 mtd->dev.parent = dev; 2015 2016 chip->controller = &nfc->base; 2017 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | 2018 NAND_USES_DMA; 2019 2020 stm32_fmc2_nfc_wp_disable(nand); 2021 2022 /* Scan to find existence of the device */ 2023 ret = nand_scan(chip, nand->ncs); 2024 if (ret) 2025 goto err_wp_enable; 2026 2027 ret = mtd_device_register(mtd, NULL, 0); 2028 if (ret) 2029 goto err_nand_cleanup; 2030 2031 platform_set_drvdata(pdev, nfc); 2032 2033 return 0; 2034 2035err_nand_cleanup: 2036 nand_cleanup(chip); 2037 2038err_wp_enable: 2039 stm32_fmc2_nfc_wp_enable(nand); 2040 2041err_release_dma: 2042 if (nfc->dma_ecc_ch) 2043 dma_release_channel(nfc->dma_ecc_ch); 2044 if (nfc->dma_tx_ch) 2045 dma_release_channel(nfc->dma_tx_ch); 2046 if (nfc->dma_rx_ch) 2047 dma_release_channel(nfc->dma_rx_ch); 2048 2049 sg_free_table(&nfc->dma_data_sg); 2050 sg_free_table(&nfc->dma_ecc_sg); 2051 2052 return ret; 2053} 2054 2055static void stm32_fmc2_nfc_remove(struct platform_device *pdev) 2056{ 2057 struct stm32_fmc2_nfc *nfc = platform_get_drvdata(pdev); 2058 struct stm32_fmc2_nand *nand = &nfc->nand; 2059 struct nand_chip *chip = &nand->chip; 2060 int ret; 2061 2062 ret = mtd_device_unregister(nand_to_mtd(chip)); 2063 WARN_ON(ret); 2064 nand_cleanup(chip); 2065 2066 if (nfc->dma_ecc_ch) 2067 dma_release_channel(nfc->dma_ecc_ch); 2068 if (nfc->dma_tx_ch) 2069 dma_release_channel(nfc->dma_tx_ch); 2070 if (nfc->dma_rx_ch) 2071 dma_release_channel(nfc->dma_rx_ch); 2072 2073 sg_free_table(&nfc->dma_data_sg); 2074 sg_free_table(&nfc->dma_ecc_sg); 2075 2076 stm32_fmc2_nfc_wp_enable(nand); 2077} 2078 2079static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev) 2080{ 2081 struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev); 2082 struct stm32_fmc2_nand *nand = &nfc->nand; 2083 2084 clk_disable_unprepare(nfc->clk); 2085 2086 stm32_fmc2_nfc_wp_enable(nand); 2087 2088 pinctrl_pm_select_sleep_state(dev); 2089 2090 return 0; 2091} 2092 2093static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev) 2094{ 2095 struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev); 2096 struct stm32_fmc2_nand *nand = &nfc->nand; 2097 int chip_cs, ret; 2098 2099 pinctrl_pm_select_default_state(dev); 2100 2101 ret = clk_prepare_enable(nfc->clk); 2102 if (ret) { 2103 dev_err(dev, "can not enable the clock\n"); 2104 return ret; 2105 } 2106 2107 stm32_fmc2_nfc_init(nfc); 2108 2109 stm32_fmc2_nfc_wp_disable(nand); 2110 2111 for (chip_cs = 0; chip_cs < nfc->data->max_ncs; chip_cs++) { 2112 if (!(nfc->cs_assigned & BIT(chip_cs))) 2113 continue; 2114 2115 nand_reset(&nand->chip, chip_cs); 2116 } 2117 2118 return 0; 2119} 2120 2121static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend, 2122 stm32_fmc2_nfc_resume); 2123 2124static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data = { 2125 .max_ncs = 2, 2126 .set_cdev = stm32_fmc2_nfc_set_cdev, 2127}; 2128 2129static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp25_data = { 2130 .max_ncs = 4, 2131}; 2132 2133static const struct of_device_id stm32_fmc2_nfc_match[] = { 2134 { 2135 .compatible = "st,stm32mp15-fmc2", 2136 .data = &stm32_fmc2_nfc_mp1_data, 2137 }, 2138 { 2139 .compatible = "st,stm32mp1-fmc2-nfc", 2140 .data = &stm32_fmc2_nfc_mp1_data, 2141 }, 2142 { 2143 .compatible = "st,stm32mp25-fmc2-nfc", 2144 .data = &stm32_fmc2_nfc_mp25_data, 2145 }, 2146 {} 2147}; 2148MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match); 2149 2150static struct platform_driver stm32_fmc2_nfc_driver = { 2151 .probe = stm32_fmc2_nfc_probe, 2152 .remove = stm32_fmc2_nfc_remove, 2153 .driver = { 2154 .name = "stm32_fmc2_nfc", 2155 .of_match_table = stm32_fmc2_nfc_match, 2156 .pm = &stm32_fmc2_nfc_pm_ops, 2157 }, 2158}; 2159module_platform_driver(stm32_fmc2_nfc_driver); 2160 2161MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>"); 2162MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 NFC driver"); 2163MODULE_LICENSE("GPL v2");
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