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nand_base.c
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linux-6.19.14/drivers/mtd/nand/raw/nand_base.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Overview: 4 * This is the generic MTD driver for NAND flash devices. It should be 5 * capable of working with almost all NAND chips currently available. 6 * 7 * Additional technical information is available on 8 * http://www.linux-mtd.infradead.org/doc/nand.html 9 * 10 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 11 * 2002-2006 Thomas Gleixner (tglx@kernel.org) 12 * 13 * Credits: 14 * David Woodhouse for adding multichip support 15 * 16 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 17 * rework for 2K page size chips 18 * 19 * TODO: 20 * Enable cached programming for 2k page size chips 21 * Check, if mtd->ecctype should be set to MTD_ECC_HW 22 * if we have HW ECC support. 23 * BBT table is not serialized, has to be fixed 24 */ 25 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 27 28#include <linux/module.h> 29#include <linux/delay.h> 30#include <linux/errno.h> 31#include <linux/err.h> 32#include <linux/sched.h> 33#include <linux/slab.h> 34#include <linux/mm.h> 35#include <linux/types.h> 36#include <linux/mtd/mtd.h> 37#include <linux/mtd/nand.h> 38#include <linux/mtd/nand-ecc-sw-hamming.h> 39#include <linux/mtd/nand-ecc-sw-bch.h> 40#include <linux/interrupt.h> 41#include <linux/bitops.h> 42#include <linux/io.h> 43#include <linux/mtd/partitions.h> 44#include <linux/of.h> 45#include <linux/gpio/consumer.h> 46 47#include "internals.h" 48 49static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page, 50 struct mtd_pairing_info *info) 51{ 52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; 53 int dist = 3; 54 55 if (page == lastpage) 56 dist = 2; 57 58 if (!page || (page & 1)) { 59 info->group = 0; 60 info->pair = (page + 1) / 2; 61 } else { 62 info->group = 1; 63 info->pair = (page + 1 - dist) / 2; 64 } 65 66 return 0; 67} 68 69static int nand_pairing_dist3_get_wunit(struct mtd_info *mtd, 70 const struct mtd_pairing_info *info) 71{ 72 int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2; 73 int page = info->pair * 2; 74 int dist = 3; 75 76 if (!info->group && !info->pair) 77 return 0; 78 79 if (info->pair == lastpair && info->group) 80 dist = 2; 81 82 if (!info->group) 83 page--; 84 else if (info->pair) 85 page += dist - 1; 86 87 if (page >= mtd->erasesize / mtd->writesize) 88 return -EINVAL; 89 90 return page; 91} 92 93const struct mtd_pairing_scheme dist3_pairing_scheme = { 94 .ngroups = 2, 95 .get_info = nand_pairing_dist3_get_info, 96 .get_wunit = nand_pairing_dist3_get_wunit, 97}; 98 99static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len) 100{ 101 int ret = 0; 102 103 /* Start address must align on block boundary */ 104 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { 105 pr_debug("%s: unaligned address\n", __func__); 106 ret = -EINVAL; 107 } 108 109 /* Length must align on block boundary */ 110 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { 111 pr_debug("%s: length not block aligned\n", __func__); 112 ret = -EINVAL; 113 } 114 115 return ret; 116} 117 118/** 119 * nand_extract_bits - Copy unaligned bits from one buffer to another one 120 * @dst: destination buffer 121 * @dst_off: bit offset at which the writing starts 122 * @src: source buffer 123 * @src_off: bit offset at which the reading starts 124 * @nbits: number of bits to copy from @src to @dst 125 * 126 * Copy bits from one memory region to another (overlap authorized). 127 */ 128void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src, 129 unsigned int src_off, unsigned int nbits) 130{ 131 unsigned int tmp, n; 132 133 dst += dst_off / 8; 134 dst_off %= 8; 135 src += src_off / 8; 136 src_off %= 8; 137 138 while (nbits) { 139 n = min3(8 - dst_off, 8 - src_off, nbits); 140 141 tmp = (*src >> src_off) & GENMASK(n - 1, 0); 142 *dst &= ~GENMASK(n - 1 + dst_off, dst_off); 143 *dst |= tmp << dst_off; 144 145 dst_off += n; 146 if (dst_off >= 8) { 147 dst++; 148 dst_off -= 8; 149 } 150 151 src_off += n; 152 if (src_off >= 8) { 153 src++; 154 src_off -= 8; 155 } 156 157 nbits -= n; 158 } 159} 160EXPORT_SYMBOL_GPL(nand_extract_bits); 161 162/** 163 * nand_select_target() - Select a NAND target (A.K.A. die) 164 * @chip: NAND chip object 165 * @cs: the CS line to select. Note that this CS id is always from the chip 166 * PoV, not the controller one 167 * 168 * Select a NAND target so that further operations executed on @chip go to the 169 * selected NAND target. 170 */ 171void nand_select_target(struct nand_chip *chip, unsigned int cs) 172{ 173 /* 174 * cs should always lie between 0 and nanddev_ntargets(), when that's 175 * not the case it's a bug and the caller should be fixed. 176 */ 177 if (WARN_ON(cs > nanddev_ntargets(&chip->base))) 178 return; 179 180 chip->cur_cs = cs; 181 182 if (chip->legacy.select_chip) 183 chip->legacy.select_chip(chip, cs); 184} 185EXPORT_SYMBOL_GPL(nand_select_target); 186 187/** 188 * nand_deselect_target() - Deselect the currently selected target 189 * @chip: NAND chip object 190 * 191 * Deselect the currently selected NAND target. The result of operations 192 * executed on @chip after the target has been deselected is undefined. 193 */ 194void nand_deselect_target(struct nand_chip *chip) 195{ 196 if (chip->legacy.select_chip) 197 chip->legacy.select_chip(chip, -1); 198 199 chip->cur_cs = -1; 200} 201EXPORT_SYMBOL_GPL(nand_deselect_target); 202 203/** 204 * nand_release_device - [GENERIC] release chip 205 * @chip: NAND chip object 206 * 207 * Release chip lock and wake up anyone waiting on the device. 208 */ 209static void nand_release_device(struct nand_chip *chip) 210{ 211 /* Release the controller and the chip */ 212 mutex_unlock(&chip->controller->lock); 213 mutex_unlock(&chip->lock); 214} 215 216/** 217 * nand_bbm_get_next_page - Get the next page for bad block markers 218 * @chip: NAND chip object 219 * @page: First page to start checking for bad block marker usage 220 * 221 * Returns an integer that corresponds to the page offset within a block, for 222 * a page that is used to store bad block markers. If no more pages are 223 * available, -EINVAL is returned. 224 */ 225int nand_bbm_get_next_page(struct nand_chip *chip, int page) 226{ 227 struct mtd_info *mtd = nand_to_mtd(chip); 228 int last_page = ((mtd->erasesize - mtd->writesize) >> 229 chip->page_shift) & chip->pagemask; 230 unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE 231 | NAND_BBM_LASTPAGE; 232 233 if (page == 0 && !(chip->options & bbm_flags)) 234 return 0; 235 if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE) 236 return 0; 237 if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE) 238 return 1; 239 if (page <= last_page && chip->options & NAND_BBM_LASTPAGE) 240 return last_page; 241 242 return -EINVAL; 243} 244 245/** 246 * nand_block_bad - [DEFAULT] Read bad block marker from the chip 247 * @chip: NAND chip object 248 * @ofs: offset from device start 249 * 250 * Check, if the block is bad. 251 */ 252static int nand_block_bad(struct nand_chip *chip, loff_t ofs) 253{ 254 int first_page, page_offset; 255 int res; 256 u8 bad; 257 258 first_page = (int)(ofs >> chip->page_shift) & chip->pagemask; 259 page_offset = nand_bbm_get_next_page(chip, 0); 260 261 while (page_offset >= 0) { 262 res = chip->ecc.read_oob(chip, first_page + page_offset); 263 if (res < 0) 264 return res; 265 266 bad = chip->oob_poi[chip->badblockpos]; 267 268 if (likely(chip->badblockbits == 8)) 269 res = bad != 0xFF; 270 else 271 res = hweight8(bad) < chip->badblockbits; 272 if (res) 273 return res; 274 275 page_offset = nand_bbm_get_next_page(chip, page_offset + 1); 276 } 277 278 return 0; 279} 280 281/** 282 * nand_region_is_secured() - Check if the region is secured 283 * @chip: NAND chip object 284 * @offset: Offset of the region to check 285 * @size: Size of the region to check 286 * 287 * Checks if the region is secured by comparing the offset and size with the 288 * list of secure regions obtained from DT. Returns true if the region is 289 * secured else false. 290 */ 291static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size) 292{ 293 int i; 294 295 /* Skip touching the secure regions if present */ 296 for (i = 0; i < chip->nr_secure_regions; i++) { 297 const struct nand_secure_region *region = &chip->secure_regions[i]; 298 299 if (offset + size <= region->offset || 300 offset >= region->offset + region->size) 301 continue; 302 303 pr_debug("%s: Region 0x%llx - 0x%llx is secured!", 304 __func__, offset, offset + size); 305 306 return true; 307 } 308 309 return false; 310} 311 312static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs) 313{ 314 struct mtd_info *mtd = nand_to_mtd(chip); 315 316 if (chip->options & NAND_NO_BBM_QUIRK) 317 return 0; 318 319 /* Check if the region is secured */ 320 if (nand_region_is_secured(chip, ofs, mtd->erasesize)) 321 return -EIO; 322 323 if (mtd_check_expert_analysis_mode()) 324 return 0; 325 326 if (chip->legacy.block_bad) 327 return chip->legacy.block_bad(chip, ofs); 328 329 return nand_block_bad(chip, ofs); 330} 331 332/** 333 * nand_get_device - [GENERIC] Get chip for selected access 334 * @chip: NAND chip structure 335 * 336 * Lock the device and its controller for exclusive access 337 */ 338static void nand_get_device(struct nand_chip *chip) 339{ 340 /* Wait until the device is resumed. */ 341 while (1) { 342 mutex_lock(&chip->lock); 343 if (!chip->suspended) { 344 mutex_lock(&chip->controller->lock); 345 return; 346 } 347 mutex_unlock(&chip->lock); 348 349 wait_event(chip->resume_wq, !chip->suspended); 350 } 351} 352 353/** 354 * nand_check_wp - [GENERIC] check if the chip is write protected 355 * @chip: NAND chip object 356 * 357 * Check, if the device is write protected. The function expects, that the 358 * device is already selected. 359 */ 360static int nand_check_wp(struct nand_chip *chip) 361{ 362 u8 status; 363 int ret; 364 365 /* Broken xD cards report WP despite being writable */ 366 if (chip->options & NAND_BROKEN_XD) 367 return 0; 368 369 /* controller responsible for NAND write protect */ 370 if (chip->controller->controller_wp) 371 return 0; 372 373 /* Check the WP bit */ 374 ret = nand_status_op(chip, &status); 375 if (ret) 376 return ret; 377 378 return status & NAND_STATUS_WP ? 0 : 1; 379} 380 381/** 382 * nand_fill_oob - [INTERN] Transfer client buffer to oob 383 * @chip: NAND chip object 384 * @oob: oob data buffer 385 * @len: oob data write length 386 * @ops: oob ops structure 387 */ 388static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len, 389 struct mtd_oob_ops *ops) 390{ 391 struct mtd_info *mtd = nand_to_mtd(chip); 392 int ret; 393 394 /* 395 * Initialise to all 0xFF, to avoid the possibility of left over OOB 396 * data from a previous OOB read. 397 */ 398 memset(chip->oob_poi, 0xff, mtd->oobsize); 399 400 switch (ops->mode) { 401 402 case MTD_OPS_PLACE_OOB: 403 case MTD_OPS_RAW: 404 memcpy(chip->oob_poi + ops->ooboffs, oob, len); 405 return oob + len; 406 407 case MTD_OPS_AUTO_OOB: 408 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, 409 ops->ooboffs, len); 410 BUG_ON(ret); 411 return oob + len; 412 413 default: 414 BUG(); 415 } 416 return NULL; 417} 418 419/** 420 * nand_do_write_oob - [MTD Interface] NAND write out-of-band 421 * @chip: NAND chip object 422 * @to: offset to write to 423 * @ops: oob operation description structure 424 * 425 * NAND write out-of-band. 426 */ 427static int nand_do_write_oob(struct nand_chip *chip, loff_t to, 428 struct mtd_oob_ops *ops) 429{ 430 struct mtd_info *mtd = nand_to_mtd(chip); 431 int chipnr, page, status, len, ret; 432 433 pr_debug("%s: to = 0x%08x, len = %i\n", 434 __func__, (unsigned int)to, (int)ops->ooblen); 435 436 len = mtd_oobavail(mtd, ops); 437 438 /* Do not allow write past end of page */ 439 if ((ops->ooboffs + ops->ooblen) > len) { 440 pr_debug("%s: attempt to write past end of page\n", 441 __func__); 442 return -EINVAL; 443 } 444 445 /* Check if the region is secured */ 446 if (nand_region_is_secured(chip, to, ops->ooblen)) 447 return -EIO; 448 449 chipnr = (int)(to >> chip->chip_shift); 450 451 /* 452 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one 453 * of my DiskOnChip 2000 test units) will clear the whole data page too 454 * if we don't do this. I have no clue why, but I seem to have 'fixed' 455 * it in the doc2000 driver in August 1999. dwmw2. 456 */ 457 ret = nand_reset(chip, chipnr); 458 if (ret) 459 return ret; 460 461 nand_select_target(chip, chipnr); 462 463 /* Shift to get page */ 464 page = (int)(to >> chip->page_shift); 465 466 /* Check, if it is write protected */ 467 if (nand_check_wp(chip)) { 468 nand_deselect_target(chip); 469 return -EROFS; 470 } 471 472 /* Invalidate the page cache, if we write to the cached page */ 473 if (page == chip->pagecache.page) 474 chip->pagecache.page = -1; 475 476 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); 477 478 if (ops->mode == MTD_OPS_RAW) 479 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); 480 else 481 status = chip->ecc.write_oob(chip, page & chip->pagemask); 482 483 nand_deselect_target(chip); 484 485 if (status) 486 return status; 487 488 ops->oobretlen = ops->ooblen; 489 490 return 0; 491} 492 493/** 494 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker 495 * @chip: NAND chip object 496 * @ofs: offset from device start 497 * 498 * This is the default implementation, which can be overridden by a hardware 499 * specific driver. It provides the details for writing a bad block marker to a 500 * block. 501 */ 502static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs) 503{ 504 struct mtd_info *mtd = nand_to_mtd(chip); 505 struct mtd_oob_ops ops; 506 uint8_t buf[2] = { 0, 0 }; 507 int ret = 0, res, page_offset; 508 509 memset(&ops, 0, sizeof(ops)); 510 ops.oobbuf = buf; 511 ops.ooboffs = chip->badblockpos; 512 if (chip->options & NAND_BUSWIDTH_16) { 513 ops.ooboffs &= ~0x01; 514 ops.len = ops.ooblen = 2; 515 } else { 516 ops.len = ops.ooblen = 1; 517 } 518 ops.mode = MTD_OPS_PLACE_OOB; 519 520 page_offset = nand_bbm_get_next_page(chip, 0); 521 522 while (page_offset >= 0) { 523 res = nand_do_write_oob(chip, 524 ofs + (page_offset * mtd->writesize), 525 &ops); 526 527 if (!ret) 528 ret = res; 529 530 page_offset = nand_bbm_get_next_page(chip, page_offset + 1); 531 } 532 533 return ret; 534} 535 536/** 537 * nand_markbad_bbm - mark a block by updating the BBM 538 * @chip: NAND chip object 539 * @ofs: offset of the block to mark bad 540 */ 541int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs) 542{ 543 if (chip->legacy.block_markbad) 544 return chip->legacy.block_markbad(chip, ofs); 545 546 return nand_default_block_markbad(chip, ofs); 547} 548 549/** 550 * nand_block_markbad_lowlevel - mark a block bad 551 * @chip: NAND chip object 552 * @ofs: offset from device start 553 * 554 * This function performs the generic NAND bad block marking steps (i.e., bad 555 * block table(s) and/or marker(s)). We only allow the hardware driver to 556 * specify how to write bad block markers to OOB (chip->legacy.block_markbad). 557 * 558 * We try operations in the following order: 559 * 560 * (1) erase the affected block, to allow OOB marker to be written cleanly 561 * (2) write bad block marker to OOB area of affected block (unless flag 562 * NAND_BBT_NO_OOB_BBM is present) 563 * (3) update the BBT 564 * 565 * Note that we retain the first error encountered in (2) or (3), finish the 566 * procedures, and dump the error in the end. 567*/ 568static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs) 569{ 570 struct mtd_info *mtd = nand_to_mtd(chip); 571 int res, ret = 0; 572 573 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { 574 struct erase_info einfo; 575 576 /* Attempt erase before marking OOB */ 577 memset(&einfo, 0, sizeof(einfo)); 578 einfo.addr = ofs; 579 einfo.len = 1ULL << chip->phys_erase_shift; 580 nand_erase_nand(chip, &einfo, 0); 581 582 /* Write bad block marker to OOB */ 583 nand_get_device(chip); 584 585 ret = nand_markbad_bbm(chip, ofs); 586 nand_release_device(chip); 587 } 588 589 /* Mark block bad in BBT */ 590 if (chip->bbt) { 591 res = nand_markbad_bbt(chip, ofs); 592 if (!ret) 593 ret = res; 594 } 595 596 if (!ret) 597 mtd->ecc_stats.badblocks++; 598 599 return ret; 600} 601 602/** 603 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. 604 * @mtd: MTD device structure 605 * @ofs: offset from device start 606 * 607 * Check if the block is marked as reserved. 608 */ 609static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) 610{ 611 struct nand_chip *chip = mtd_to_nand(mtd); 612 613 if (!chip->bbt) 614 return 0; 615 /* Return info from the table */ 616 return nand_isreserved_bbt(chip, ofs); 617} 618 619/** 620 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 621 * @chip: NAND chip object 622 * @ofs: offset from device start 623 * @allowbbt: 1, if its allowed to access the bbt area 624 * 625 * Check, if the block is bad. Either by reading the bad block table or 626 * calling of the scan function. 627 */ 628static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt) 629{ 630 /* Return info from the table */ 631 if (chip->bbt) 632 return nand_isbad_bbt(chip, ofs, allowbbt); 633 634 return nand_isbad_bbm(chip, ofs); 635} 636 637/** 638 * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1 639 * @chip: NAND chip structure 640 * @timeout_ms: Timeout in ms 641 * 642 * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1. 643 * If that does not happen whitin the specified timeout, -ETIMEDOUT is 644 * returned. 645 * 646 * This helper is intended to be used when the controller does not have access 647 * to the NAND R/B pin. 648 * 649 * Be aware that calling this helper from an ->exec_op() implementation means 650 * ->exec_op() must be re-entrant. 651 * 652 * Return 0 if the NAND chip is ready, a negative error otherwise. 653 */ 654int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms) 655{ 656 const struct nand_interface_config *conf; 657 u8 status = 0; 658 int ret; 659 660 if (!nand_has_exec_op(chip)) 661 return -ENOTSUPP; 662 663 /* Wait tWB before polling the STATUS reg. */ 664 conf = nand_get_interface_config(chip); 665 ndelay(NAND_COMMON_TIMING_NS(conf, tWB_max)); 666 667 ret = nand_status_op(chip, NULL); 668 if (ret) 669 return ret; 670 671 /* 672 * +1 below is necessary because if we are now in the last fraction 673 * of jiffy and msecs_to_jiffies is 1 then we will wait only that 674 * small jiffy fraction - possibly leading to false timeout 675 */ 676 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1; 677 do { 678 ret = nand_read_data_op(chip, &status, sizeof(status), true, 679 false); 680 if (ret) 681 break; 682 683 if (status & NAND_STATUS_READY) 684 break; 685 686 /* 687 * Typical lowest execution time for a tR on most NANDs is 10us, 688 * use this as polling delay before doing something smarter (ie. 689 * deriving a delay from the timeout value, timeout_ms/ratio). 690 */ 691 udelay(10); 692 } while (time_before(jiffies, timeout_ms)); 693 694 /* 695 * We have to exit READ_STATUS mode in order to read real data on the 696 * bus in case the WAITRDY instruction is preceding a DATA_IN 697 * instruction. 698 */ 699 nand_exit_status_op(chip); 700 701 if (ret) 702 return ret; 703 704 return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT; 705}; 706EXPORT_SYMBOL_GPL(nand_soft_waitrdy); 707 708/** 709 * nand_gpio_waitrdy - Poll R/B GPIO pin until ready 710 * @chip: NAND chip structure 711 * @gpiod: GPIO descriptor of R/B pin 712 * @timeout_ms: Timeout in ms 713 * 714 * Poll the R/B GPIO pin until it becomes ready. If that does not happen 715 * whitin the specified timeout, -ETIMEDOUT is returned. 716 * 717 * This helper is intended to be used when the controller has access to the 718 * NAND R/B pin over GPIO. 719 * 720 * Return 0 if the R/B pin indicates chip is ready, a negative error otherwise. 721 */ 722int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod, 723 unsigned long timeout_ms) 724{ 725 726 /* 727 * Wait until R/B pin indicates chip is ready or timeout occurs. 728 * +1 below is necessary because if we are now in the last fraction 729 * of jiffy and msecs_to_jiffies is 1 then we will wait only that 730 * small jiffy fraction - possibly leading to false timeout. 731 */ 732 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1; 733 do { 734 if (gpiod_get_value_cansleep(gpiod)) 735 return 0; 736 737 cond_resched(); 738 } while (time_before(jiffies, timeout_ms)); 739 740 return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT; 741}; 742EXPORT_SYMBOL_GPL(nand_gpio_waitrdy); 743 744/** 745 * panic_nand_wait - [GENERIC] wait until the command is done 746 * @chip: NAND chip structure 747 * @timeo: timeout 748 * 749 * Wait for command done. This is a helper function for nand_wait used when 750 * we are in interrupt context. May happen when in panic and trying to write 751 * an oops through mtdoops. 752 */ 753void panic_nand_wait(struct nand_chip *chip, unsigned long timeo) 754{ 755 int i; 756 for (i = 0; i < timeo; i++) { 757 if (chip->legacy.dev_ready) { 758 if (chip->legacy.dev_ready(chip)) 759 break; 760 } else { 761 int ret; 762 u8 status; 763 764 ret = nand_read_data_op(chip, &status, sizeof(status), 765 true, false); 766 if (ret) 767 return; 768 769 if (status & NAND_STATUS_READY) 770 break; 771 } 772 mdelay(1); 773 } 774} 775 776static bool nand_supports_get_features(struct nand_chip *chip, int addr) 777{ 778 return (chip->parameters.supports_set_get_features && 779 test_bit(addr, chip->parameters.get_feature_list)); 780} 781 782static bool nand_supports_set_features(struct nand_chip *chip, int addr) 783{ 784 return (chip->parameters.supports_set_get_features && 785 test_bit(addr, chip->parameters.set_feature_list)); 786} 787 788/** 789 * nand_reset_interface - Reset data interface and timings 790 * @chip: The NAND chip 791 * @chipnr: Internal die id 792 * 793 * Reset the Data interface and timings to ONFI mode 0. 794 * 795 * Returns 0 for success or negative error code otherwise. 796 */ 797static int nand_reset_interface(struct nand_chip *chip, int chipnr) 798{ 799 const struct nand_controller_ops *ops = chip->controller->ops; 800 int ret; 801 802 if (!nand_controller_can_setup_interface(chip)) 803 return 0; 804 805 /* 806 * The ONFI specification says: 807 * " 808 * To transition from NV-DDR or NV-DDR2 to the SDR data 809 * interface, the host shall use the Reset (FFh) command 810 * using SDR timing mode 0. A device in any timing mode is 811 * required to recognize Reset (FFh) command issued in SDR 812 * timing mode 0. 813 * " 814 * 815 * Configure the data interface in SDR mode and set the 816 * timings to timing mode 0. 817 */ 818 819 chip->current_interface_config = nand_get_reset_interface_config(); 820 ret = ops->setup_interface(chip, chipnr, 821 chip->current_interface_config); 822 if (ret) 823 pr_err("Failed to configure data interface to SDR timing mode 0\n"); 824 825 return ret; 826} 827 828/** 829 * nand_setup_interface - Setup the best data interface and timings 830 * @chip: The NAND chip 831 * @chipnr: Internal die id 832 * 833 * Configure what has been reported to be the best data interface and NAND 834 * timings supported by the chip and the driver. 835 * 836 * Returns 0 for success or negative error code otherwise. 837 */ 838static int nand_setup_interface(struct nand_chip *chip, int chipnr) 839{ 840 const struct nand_controller_ops *ops = chip->controller->ops; 841 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { }, request; 842 int ret; 843 844 if (!nand_controller_can_setup_interface(chip)) 845 return 0; 846 847 /* 848 * A nand_reset_interface() put both the NAND chip and the NAND 849 * controller in timings mode 0. If the default mode for this chip is 850 * also 0, no need to proceed to the change again. Plus, at probe time, 851 * nand_setup_interface() uses ->set/get_features() which would 852 * fail anyway as the parameter page is not available yet. 853 */ 854 if (!chip->best_interface_config) 855 return 0; 856 857 request = chip->best_interface_config->timings.mode; 858 if (nand_interface_is_sdr(chip->best_interface_config)) 859 request |= ONFI_DATA_INTERFACE_SDR; 860 else 861 request |= ONFI_DATA_INTERFACE_NVDDR; 862 tmode_param[0] = request; 863 864 /* Change the mode on the chip side (if supported by the NAND chip) */ 865 if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) { 866 nand_select_target(chip, chipnr); 867 ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE, 868 tmode_param); 869 nand_deselect_target(chip); 870 if (ret) 871 return ret; 872 } 873 874 /* Change the mode on the controller side */ 875 ret = ops->setup_interface(chip, chipnr, chip->best_interface_config); 876 if (ret) 877 return ret; 878 879 /* Check the mode has been accepted by the chip, if supported */ 880 if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) 881 goto update_interface_config; 882 883 memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN); 884 nand_select_target(chip, chipnr); 885 ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE, 886 tmode_param); 887 nand_deselect_target(chip); 888 if (ret) 889 goto err_reset_chip; 890 891 if (request != tmode_param[0]) { 892 pr_warn("%s timing mode %d not acknowledged by the NAND chip\n", 893 nand_interface_is_nvddr(chip->best_interface_config) ? "NV-DDR" : "SDR", 894 chip->best_interface_config->timings.mode); 895 pr_debug("NAND chip would work in %s timing mode %d\n", 896 tmode_param[0] & ONFI_DATA_INTERFACE_NVDDR ? "NV-DDR" : "SDR", 897 (unsigned int)ONFI_TIMING_MODE_PARAM(tmode_param[0])); 898 goto err_reset_chip; 899 } 900 901update_interface_config: 902 chip->current_interface_config = chip->best_interface_config; 903 904 return 0; 905 906err_reset_chip: 907 /* 908 * Fallback to mode 0 if the chip explicitly did not ack the chosen 909 * timing mode. 910 */ 911 nand_reset_interface(chip, chipnr); 912 nand_select_target(chip, chipnr); 913 nand_reset_op(chip); 914 nand_deselect_target(chip); 915 916 return ret; 917} 918 919/** 920 * nand_choose_best_sdr_timings - Pick up the best SDR timings that both the 921 * NAND controller and the NAND chip support 922 * @chip: the NAND chip 923 * @iface: the interface configuration (can eventually be updated) 924 * @spec_timings: specific timings, when not fitting the ONFI specification 925 * 926 * If specific timings are provided, use them. Otherwise, retrieve supported 927 * timing modes from ONFI information. 928 */ 929int nand_choose_best_sdr_timings(struct nand_chip *chip, 930 struct nand_interface_config *iface, 931 struct nand_sdr_timings *spec_timings) 932{ 933 const struct nand_controller_ops *ops = chip->controller->ops; 934 int best_mode = 0, mode, ret = -EOPNOTSUPP; 935 936 iface->type = NAND_SDR_IFACE; 937 938 if (spec_timings) { 939 iface->timings.sdr = *spec_timings; 940 iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings); 941 942 /* Verify the controller supports the requested interface */ 943 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, 944 iface); 945 if (!ret) { 946 chip->best_interface_config = iface; 947 return ret; 948 } 949 950 /* Fallback to slower modes */ 951 best_mode = iface->timings.mode; 952 } else if (chip->parameters.onfi) { 953 best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1; 954 } 955 956 for (mode = best_mode; mode >= 0; mode--) { 957 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, mode); 958 959 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, 960 iface); 961 if (!ret) { 962 chip->best_interface_config = iface; 963 break; 964 } 965 } 966 967 return ret; 968} 969 970/** 971 * nand_choose_best_nvddr_timings - Pick up the best NVDDR timings that both the 972 * NAND controller and the NAND chip support 973 * @chip: the NAND chip 974 * @iface: the interface configuration (can eventually be updated) 975 * @spec_timings: specific timings, when not fitting the ONFI specification 976 * 977 * If specific timings are provided, use them. Otherwise, retrieve supported 978 * timing modes from ONFI information. 979 */ 980int nand_choose_best_nvddr_timings(struct nand_chip *chip, 981 struct nand_interface_config *iface, 982 struct nand_nvddr_timings *spec_timings) 983{ 984 const struct nand_controller_ops *ops = chip->controller->ops; 985 int best_mode = 0, mode, ret = -EOPNOTSUPP; 986 987 iface->type = NAND_NVDDR_IFACE; 988 989 if (spec_timings) { 990 iface->timings.nvddr = *spec_timings; 991 iface->timings.mode = onfi_find_closest_nvddr_mode(spec_timings); 992 993 /* Verify the controller supports the requested interface */ 994 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, 995 iface); 996 if (!ret) { 997 chip->best_interface_config = iface; 998 return ret; 999 } 1000 1001 /* Fallback to slower modes */ 1002 best_mode = iface->timings.mode; 1003 } else if (chip->parameters.onfi) { 1004 best_mode = fls(chip->parameters.onfi->nvddr_timing_modes) - 1; 1005 } 1006 1007 for (mode = best_mode; mode >= 0; mode--) { 1008 onfi_fill_interface_config(chip, iface, NAND_NVDDR_IFACE, mode); 1009 1010 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, 1011 iface); 1012 if (!ret) { 1013 chip->best_interface_config = iface; 1014 break; 1015 } 1016 } 1017 1018 return ret; 1019} 1020 1021/** 1022 * nand_choose_best_timings - Pick up the best NVDDR or SDR timings that both 1023 * NAND controller and the NAND chip support 1024 * @chip: the NAND chip 1025 * @iface: the interface configuration (can eventually be updated) 1026 * 1027 * If specific timings are provided, use them. Otherwise, retrieve supported 1028 * timing modes from ONFI information. 1029 */ 1030static int nand_choose_best_timings(struct nand_chip *chip, 1031 struct nand_interface_config *iface) 1032{ 1033 int ret; 1034 1035 /* Try the fastest timings: NV-DDR */ 1036 ret = nand_choose_best_nvddr_timings(chip, iface, NULL); 1037 if (!ret) 1038 return 0; 1039 1040 /* Fallback to SDR timings otherwise */ 1041 return nand_choose_best_sdr_timings(chip, iface, NULL); 1042} 1043 1044/** 1045 * nand_choose_interface_config - find the best data interface and timings 1046 * @chip: The NAND chip 1047 * 1048 * Find the best data interface and NAND timings supported by the chip 1049 * and the driver. Eventually let the NAND manufacturer driver propose his own 1050 * set of timings. 1051 * 1052 * After this function nand_chip->interface_config is initialized with the best 1053 * timing mode available. 1054 * 1055 * Returns 0 for success or negative error code otherwise. 1056 */ 1057static int nand_choose_interface_config(struct nand_chip *chip) 1058{ 1059 struct nand_interface_config *iface; 1060 int ret; 1061 1062 if (!nand_controller_can_setup_interface(chip)) 1063 return 0; 1064 1065 iface = kzalloc(sizeof(*iface), GFP_KERNEL); 1066 if (!iface) 1067 return -ENOMEM; 1068 1069 if (chip->ops.choose_interface_config) 1070 ret = chip->ops.choose_interface_config(chip, iface); 1071 else 1072 ret = nand_choose_best_timings(chip, iface); 1073 1074 if (ret) 1075 kfree(iface); 1076 1077 return ret; 1078} 1079 1080/** 1081 * nand_fill_column_cycles - fill the column cycles of an address 1082 * @chip: The NAND chip 1083 * @addrs: Array of address cycles to fill 1084 * @offset_in_page: The offset in the page 1085 * 1086 * Fills the first or the first two bytes of the @addrs field depending 1087 * on the NAND bus width and the page size. 1088 * 1089 * Returns the number of cycles needed to encode the column, or a negative 1090 * error code in case one of the arguments is invalid. 1091 */ 1092static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs, 1093 unsigned int offset_in_page) 1094{ 1095 struct mtd_info *mtd = nand_to_mtd(chip); 1096 bool ident_stage = !mtd->writesize; 1097 1098 /* Bypass all checks during NAND identification */ 1099 if (likely(!ident_stage)) { 1100 /* Make sure the offset is less than the actual page size. */ 1101 if (offset_in_page > mtd->writesize + mtd->oobsize) 1102 return -EINVAL; 1103 1104 /* 1105 * On small page NANDs, there's a dedicated command to access the OOB 1106 * area, and the column address is relative to the start of the OOB 1107 * area, not the start of the page. Asjust the address accordingly. 1108 */ 1109 if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize) 1110 offset_in_page -= mtd->writesize; 1111 1112 /* 1113 * The offset in page is expressed in bytes, if the NAND bus is 16-bit 1114 * wide, then it must be divided by 2. 1115 */ 1116 if (chip->options & NAND_BUSWIDTH_16) { 1117 if (WARN_ON(offset_in_page % 2)) 1118 return -EINVAL; 1119 1120 offset_in_page /= 2; 1121 } 1122 } 1123 1124 addrs[0] = offset_in_page; 1125 1126 /* 1127 * Small page NANDs use 1 cycle for the columns, while large page NANDs 1128 * need 2 1129 */ 1130 if (!ident_stage && mtd->writesize <= 512) 1131 return 1; 1132 1133 addrs[1] = offset_in_page >> 8; 1134 1135 return 2; 1136} 1137 1138static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page, 1139 unsigned int offset_in_page, void *buf, 1140 unsigned int len) 1141{ 1142 const struct nand_interface_config *conf = 1143 nand_get_interface_config(chip); 1144 struct mtd_info *mtd = nand_to_mtd(chip); 1145 u8 addrs[4]; 1146 struct nand_op_instr instrs[] = { 1147 NAND_OP_CMD(NAND_CMD_READ0, 0), 1148 NAND_OP_ADDR(3, addrs, NAND_COMMON_TIMING_NS(conf, tWB_max)), 1149 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1150 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1151 NAND_OP_DATA_IN(len, buf, 0), 1152 }; 1153 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1154 int ret; 1155 1156 /* Drop the DATA_IN instruction if len is set to 0. */ 1157 if (!len) 1158 op.ninstrs--; 1159 1160 if (offset_in_page >= mtd->writesize) 1161 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; 1162 else if (offset_in_page >= 256 && 1163 !(chip->options & NAND_BUSWIDTH_16)) 1164 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; 1165 1166 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1167 if (ret < 0) 1168 return ret; 1169 1170 addrs[1] = page; 1171 addrs[2] = page >> 8; 1172 1173 if (chip->options & NAND_ROW_ADDR_3) { 1174 addrs[3] = page >> 16; 1175 instrs[1].ctx.addr.naddrs++; 1176 } 1177 1178 return nand_exec_op(chip, &op); 1179} 1180 1181static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page, 1182 unsigned int offset_in_page, void *buf, 1183 unsigned int len) 1184{ 1185 const struct nand_interface_config *conf = 1186 nand_get_interface_config(chip); 1187 u8 addrs[5]; 1188 struct nand_op_instr instrs[] = { 1189 NAND_OP_CMD(NAND_CMD_READ0, 0), 1190 NAND_OP_ADDR(4, addrs, 0), 1191 NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)), 1192 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1193 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1194 NAND_OP_DATA_IN(len, buf, 0), 1195 }; 1196 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1197 int ret; 1198 1199 /* Drop the DATA_IN instruction if len is set to 0. */ 1200 if (!len) 1201 op.ninstrs--; 1202 1203 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1204 if (ret < 0) 1205 return ret; 1206 1207 addrs[2] = page; 1208 addrs[3] = page >> 8; 1209 1210 if (chip->options & NAND_ROW_ADDR_3) { 1211 addrs[4] = page >> 16; 1212 instrs[1].ctx.addr.naddrs++; 1213 } 1214 1215 return nand_exec_op(chip, &op); 1216} 1217 1218static unsigned int rawnand_last_page_of_lun(unsigned int pages_per_lun, unsigned int lun) 1219{ 1220 /* lun is expected to be very small */ 1221 return (lun * pages_per_lun) + pages_per_lun - 1; 1222} 1223 1224static void rawnand_cap_cont_reads(struct nand_chip *chip) 1225{ 1226 struct nand_memory_organization *memorg; 1227 unsigned int ppl, first_lun, last_lun; 1228 1229 memorg = nanddev_get_memorg(&chip->base); 1230 ppl = memorg->pages_per_eraseblock * memorg->eraseblocks_per_lun; 1231 first_lun = chip->cont_read.first_page / ppl; 1232 last_lun = chip->cont_read.last_page / ppl; 1233 1234 /* Prevent sequential cache reads across LUN boundaries */ 1235 if (first_lun != last_lun) 1236 chip->cont_read.pause_page = rawnand_last_page_of_lun(ppl, first_lun); 1237 else 1238 chip->cont_read.pause_page = chip->cont_read.last_page; 1239 1240 if (chip->cont_read.first_page == chip->cont_read.pause_page) { 1241 chip->cont_read.first_page++; 1242 chip->cont_read.pause_page = min(chip->cont_read.last_page, 1243 rawnand_last_page_of_lun(ppl, first_lun + 1)); 1244 } 1245 1246 if (chip->cont_read.first_page >= chip->cont_read.last_page) 1247 chip->cont_read.ongoing = false; 1248} 1249 1250static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int page, 1251 unsigned int offset_in_page, void *buf, 1252 unsigned int len, bool check_only) 1253{ 1254 const struct nand_interface_config *conf = 1255 nand_get_interface_config(chip); 1256 u8 addrs[5]; 1257 struct nand_op_instr start_instrs[] = { 1258 NAND_OP_CMD(NAND_CMD_READ0, 0), 1259 NAND_OP_ADDR(4, addrs, 0), 1260 NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)), 1261 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 0), 1262 NAND_OP_CMD(NAND_CMD_READCACHESEQ, NAND_COMMON_TIMING_NS(conf, tWB_max)), 1263 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1264 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1265 NAND_OP_DATA_IN(len, buf, 0), 1266 }; 1267 struct nand_op_instr cont_instrs[] = { 1268 NAND_OP_CMD(page == chip->cont_read.pause_page ? 1269 NAND_CMD_READCACHEEND : NAND_CMD_READCACHESEQ, 1270 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1271 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1272 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1273 NAND_OP_DATA_IN(len, buf, 0), 1274 }; 1275 struct nand_operation start_op = NAND_OPERATION(chip->cur_cs, start_instrs); 1276 struct nand_operation cont_op = NAND_OPERATION(chip->cur_cs, cont_instrs); 1277 int ret; 1278 1279 if (!len) { 1280 start_op.ninstrs--; 1281 cont_op.ninstrs--; 1282 } 1283 1284 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1285 if (ret < 0) 1286 return ret; 1287 1288 addrs[2] = page; 1289 addrs[3] = page >> 8; 1290 1291 if (chip->options & NAND_ROW_ADDR_3) { 1292 addrs[4] = page >> 16; 1293 start_instrs[1].ctx.addr.naddrs++; 1294 } 1295 1296 /* Check if cache reads are supported */ 1297 if (check_only) { 1298 if (nand_check_op(chip, &start_op) || nand_check_op(chip, &cont_op)) 1299 return -EOPNOTSUPP; 1300 1301 return 0; 1302 } 1303 1304 if (page == chip->cont_read.first_page) 1305 ret = nand_exec_op(chip, &start_op); 1306 else 1307 ret = nand_exec_op(chip, &cont_op); 1308 if (ret) 1309 return ret; 1310 1311 if (!chip->cont_read.ongoing) 1312 return 0; 1313 1314 if (page == chip->cont_read.last_page) { 1315 chip->cont_read.ongoing = false; 1316 } else if (page == chip->cont_read.pause_page) { 1317 chip->cont_read.first_page++; 1318 rawnand_cap_cont_reads(chip); 1319 } 1320 1321 return 0; 1322} 1323 1324static bool rawnand_cont_read_ongoing(struct nand_chip *chip, unsigned int page) 1325{ 1326 return chip->cont_read.ongoing && page >= chip->cont_read.first_page; 1327} 1328 1329/** 1330 * nand_read_page_op - Do a READ PAGE operation 1331 * @chip: The NAND chip 1332 * @page: page to read 1333 * @offset_in_page: offset within the page 1334 * @buf: buffer used to store the data 1335 * @len: length of the buffer 1336 * 1337 * This function issues a READ PAGE operation. 1338 * This function does not select/unselect the CS line. 1339 * 1340 * Returns 0 on success, a negative error code otherwise. 1341 */ 1342int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1343 unsigned int offset_in_page, void *buf, unsigned int len) 1344{ 1345 struct mtd_info *mtd = nand_to_mtd(chip); 1346 1347 if (len && !buf) 1348 return -EINVAL; 1349 1350 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1351 return -EINVAL; 1352 1353 if (nand_has_exec_op(chip)) { 1354 if (mtd->writesize > 512) { 1355 if (rawnand_cont_read_ongoing(chip, page)) 1356 return nand_lp_exec_cont_read_page_op(chip, page, 1357 offset_in_page, 1358 buf, len, false); 1359 else 1360 return nand_lp_exec_read_page_op(chip, page, 1361 offset_in_page, buf, 1362 len); 1363 } 1364 1365 return nand_sp_exec_read_page_op(chip, page, offset_in_page, 1366 buf, len); 1367 } 1368 1369 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page); 1370 if (len) 1371 chip->legacy.read_buf(chip, buf, len); 1372 1373 return 0; 1374} 1375EXPORT_SYMBOL_GPL(nand_read_page_op); 1376 1377/** 1378 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation 1379 * @chip: The NAND chip 1380 * @page: parameter page to read 1381 * @buf: buffer used to store the data 1382 * @len: length of the buffer 1383 * 1384 * This function issues a READ PARAMETER PAGE operation. 1385 * This function does not select/unselect the CS line. 1386 * 1387 * Returns 0 on success, a negative error code otherwise. 1388 */ 1389int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf, 1390 unsigned int len) 1391{ 1392 unsigned int i; 1393 u8 *p = buf; 1394 1395 if (len && !buf) 1396 return -EINVAL; 1397 1398 if (nand_has_exec_op(chip)) { 1399 const struct nand_interface_config *conf = 1400 nand_get_interface_config(chip); 1401 struct nand_op_instr instrs[] = { 1402 NAND_OP_CMD(NAND_CMD_PARAM, 0), 1403 NAND_OP_ADDR(1, &page, 1404 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1405 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1406 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1407 NAND_OP_8BIT_DATA_IN(len, buf, 0), 1408 }; 1409 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1410 1411 /* Drop the DATA_IN instruction if len is set to 0. */ 1412 if (!len) 1413 op.ninstrs--; 1414 1415 return nand_exec_op(chip, &op); 1416 } 1417 1418 chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1); 1419 for (i = 0; i < len; i++) 1420 p[i] = chip->legacy.read_byte(chip); 1421 1422 return 0; 1423} 1424 1425/** 1426 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation 1427 * @chip: The NAND chip 1428 * @offset_in_page: offset within the page 1429 * @buf: buffer used to store the data 1430 * @len: length of the buffer 1431 * @force_8bit: force 8-bit bus access 1432 * 1433 * This function issues a CHANGE READ COLUMN operation. 1434 * This function does not select/unselect the CS line. 1435 * 1436 * Returns 0 on success, a negative error code otherwise. 1437 */ 1438int nand_change_read_column_op(struct nand_chip *chip, 1439 unsigned int offset_in_page, void *buf, 1440 unsigned int len, bool force_8bit) 1441{ 1442 struct mtd_info *mtd = nand_to_mtd(chip); 1443 bool ident_stage = !mtd->writesize; 1444 1445 if (len && !buf) 1446 return -EINVAL; 1447 1448 if (!ident_stage) { 1449 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1450 return -EINVAL; 1451 1452 /* Small page NANDs do not support column change. */ 1453 if (mtd->writesize <= 512) 1454 return -ENOTSUPP; 1455 } 1456 1457 if (nand_has_exec_op(chip)) { 1458 const struct nand_interface_config *conf = 1459 nand_get_interface_config(chip); 1460 u8 addrs[2] = {}; 1461 struct nand_op_instr instrs[] = { 1462 NAND_OP_CMD(NAND_CMD_RNDOUT, 0), 1463 NAND_OP_ADDR(2, addrs, 0), 1464 NAND_OP_CMD(NAND_CMD_RNDOUTSTART, 1465 NAND_COMMON_TIMING_NS(conf, tCCS_min)), 1466 NAND_OP_DATA_IN(len, buf, 0), 1467 }; 1468 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1469 int ret; 1470 1471 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1472 if (ret < 0) 1473 return ret; 1474 1475 /* Drop the DATA_IN instruction if len is set to 0. */ 1476 if (!len) 1477 op.ninstrs--; 1478 1479 instrs[3].ctx.data.force_8bit = force_8bit; 1480 1481 return nand_exec_op(chip, &op); 1482 } 1483 1484 chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1); 1485 if (len) 1486 chip->legacy.read_buf(chip, buf, len); 1487 1488 return 0; 1489} 1490EXPORT_SYMBOL_GPL(nand_change_read_column_op); 1491 1492/** 1493 * nand_read_oob_op - Do a READ OOB operation 1494 * @chip: The NAND chip 1495 * @page: page to read 1496 * @offset_in_oob: offset within the OOB area 1497 * @buf: buffer used to store the data 1498 * @len: length of the buffer 1499 * 1500 * This function issues a READ OOB operation. 1501 * This function does not select/unselect the CS line. 1502 * 1503 * Returns 0 on success, a negative error code otherwise. 1504 */ 1505int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1506 unsigned int offset_in_oob, void *buf, unsigned int len) 1507{ 1508 struct mtd_info *mtd = nand_to_mtd(chip); 1509 1510 if (len && !buf) 1511 return -EINVAL; 1512 1513 if (offset_in_oob + len > mtd->oobsize) 1514 return -EINVAL; 1515 1516 if (nand_has_exec_op(chip)) 1517 return nand_read_page_op(chip, page, 1518 mtd->writesize + offset_in_oob, 1519 buf, len); 1520 1521 chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page); 1522 if (len) 1523 chip->legacy.read_buf(chip, buf, len); 1524 1525 return 0; 1526} 1527EXPORT_SYMBOL_GPL(nand_read_oob_op); 1528 1529static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page, 1530 unsigned int offset_in_page, const void *buf, 1531 unsigned int len, bool prog) 1532{ 1533 const struct nand_interface_config *conf = 1534 nand_get_interface_config(chip); 1535 struct mtd_info *mtd = nand_to_mtd(chip); 1536 u8 addrs[5] = {}; 1537 struct nand_op_instr instrs[] = { 1538 /* 1539 * The first instruction will be dropped if we're dealing 1540 * with a large page NAND and adjusted if we're dealing 1541 * with a small page NAND and the page offset is > 255. 1542 */ 1543 NAND_OP_CMD(NAND_CMD_READ0, 0), 1544 NAND_OP_CMD(NAND_CMD_SEQIN, 0), 1545 NAND_OP_ADDR(0, addrs, NAND_COMMON_TIMING_NS(conf, tADL_min)), 1546 NAND_OP_DATA_OUT(len, buf, 0), 1547 NAND_OP_CMD(NAND_CMD_PAGEPROG, 1548 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1549 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max), 0), 1550 }; 1551 struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip->cur_cs, 1552 instrs); 1553 int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page); 1554 1555 if (naddrs < 0) 1556 return naddrs; 1557 1558 addrs[naddrs++] = page; 1559 addrs[naddrs++] = page >> 8; 1560 if (chip->options & NAND_ROW_ADDR_3) 1561 addrs[naddrs++] = page >> 16; 1562 1563 instrs[2].ctx.addr.naddrs = naddrs; 1564 1565 /* Drop the last two instructions if we're not programming the page. */ 1566 if (!prog) { 1567 op.ninstrs -= 2; 1568 /* Also drop the DATA_OUT instruction if empty. */ 1569 if (!len) 1570 op.ninstrs--; 1571 } 1572 1573 if (mtd->writesize <= 512) { 1574 /* 1575 * Small pages need some more tweaking: we have to adjust the 1576 * first instruction depending on the page offset we're trying 1577 * to access. 1578 */ 1579 if (offset_in_page >= mtd->writesize) 1580 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; 1581 else if (offset_in_page >= 256 && 1582 !(chip->options & NAND_BUSWIDTH_16)) 1583 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; 1584 } else { 1585 /* 1586 * Drop the first command if we're dealing with a large page 1587 * NAND. 1588 */ 1589 op.instrs++; 1590 op.ninstrs--; 1591 } 1592 1593 return nand_exec_op(chip, &op); 1594} 1595 1596/** 1597 * nand_prog_page_begin_op - starts a PROG PAGE operation 1598 * @chip: The NAND chip 1599 * @page: page to write 1600 * @offset_in_page: offset within the page 1601 * @buf: buffer containing the data to write to the page 1602 * @len: length of the buffer 1603 * 1604 * This function issues the first half of a PROG PAGE operation. 1605 * This function does not select/unselect the CS line. 1606 * 1607 * Returns 0 on success, a negative error code otherwise. 1608 */ 1609int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1610 unsigned int offset_in_page, const void *buf, 1611 unsigned int len) 1612{ 1613 struct mtd_info *mtd = nand_to_mtd(chip); 1614 1615 if (len && !buf) 1616 return -EINVAL; 1617 1618 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1619 return -EINVAL; 1620 1621 if (nand_has_exec_op(chip)) 1622 return nand_exec_prog_page_op(chip, page, offset_in_page, buf, 1623 len, false); 1624 1625 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page); 1626 1627 if (buf) 1628 chip->legacy.write_buf(chip, buf, len); 1629 1630 return 0; 1631} 1632EXPORT_SYMBOL_GPL(nand_prog_page_begin_op); 1633 1634/** 1635 * nand_prog_page_end_op - ends a PROG PAGE operation 1636 * @chip: The NAND chip 1637 * 1638 * This function issues the second half of a PROG PAGE operation. 1639 * This function does not select/unselect the CS line. 1640 * 1641 * Returns 0 on success, a negative error code otherwise. 1642 */ 1643int nand_prog_page_end_op(struct nand_chip *chip) 1644{ 1645 int ret; 1646 u8 status; 1647 1648 if (nand_has_exec_op(chip)) { 1649 const struct nand_interface_config *conf = 1650 nand_get_interface_config(chip); 1651 struct nand_op_instr instrs[] = { 1652 NAND_OP_CMD(NAND_CMD_PAGEPROG, 1653 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1654 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max), 1655 0), 1656 }; 1657 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1658 1659 ret = nand_exec_op(chip, &op); 1660 if (ret) 1661 return ret; 1662 1663 ret = nand_status_op(chip, &status); 1664 if (ret) 1665 return ret; 1666 } else { 1667 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); 1668 ret = chip->legacy.waitfunc(chip); 1669 if (ret < 0) 1670 return ret; 1671 1672 status = ret; 1673 } 1674 1675 if (status & NAND_STATUS_FAIL) 1676 return -EIO; 1677 1678 return 0; 1679} 1680EXPORT_SYMBOL_GPL(nand_prog_page_end_op); 1681 1682/** 1683 * nand_prog_page_op - Do a full PROG PAGE operation 1684 * @chip: The NAND chip 1685 * @page: page to write 1686 * @offset_in_page: offset within the page 1687 * @buf: buffer containing the data to write to the page 1688 * @len: length of the buffer 1689 * 1690 * This function issues a full PROG PAGE operation. 1691 * This function does not select/unselect the CS line. 1692 * 1693 * Returns 0 on success, a negative error code otherwise. 1694 */ 1695int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1696 unsigned int offset_in_page, const void *buf, 1697 unsigned int len) 1698{ 1699 struct mtd_info *mtd = nand_to_mtd(chip); 1700 u8 status; 1701 int ret; 1702 1703 if (!len || !buf) 1704 return -EINVAL; 1705 1706 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1707 return -EINVAL; 1708 1709 if (nand_has_exec_op(chip)) { 1710 ret = nand_exec_prog_page_op(chip, page, offset_in_page, buf, 1711 len, true); 1712 if (ret) 1713 return ret; 1714 1715 ret = nand_status_op(chip, &status); 1716 if (ret) 1717 return ret; 1718 } else { 1719 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, 1720 page); 1721 chip->legacy.write_buf(chip, buf, len); 1722 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); 1723 ret = chip->legacy.waitfunc(chip); 1724 if (ret < 0) 1725 return ret; 1726 1727 status = ret; 1728 } 1729 1730 if (status & NAND_STATUS_FAIL) 1731 return -EIO; 1732 1733 return 0; 1734} 1735EXPORT_SYMBOL_GPL(nand_prog_page_op); 1736 1737/** 1738 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation 1739 * @chip: The NAND chip 1740 * @offset_in_page: offset within the page 1741 * @buf: buffer containing the data to send to the NAND 1742 * @len: length of the buffer 1743 * @force_8bit: force 8-bit bus access 1744 * 1745 * This function issues a CHANGE WRITE COLUMN operation. 1746 * This function does not select/unselect the CS line. 1747 * 1748 * Returns 0 on success, a negative error code otherwise. 1749 */ 1750int nand_change_write_column_op(struct nand_chip *chip, 1751 unsigned int offset_in_page, 1752 const void *buf, unsigned int len, 1753 bool force_8bit) 1754{ 1755 struct mtd_info *mtd = nand_to_mtd(chip); 1756 1757 if (len && !buf) 1758 return -EINVAL; 1759 1760 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1761 return -EINVAL; 1762 1763 /* Small page NANDs do not support column change. */ 1764 if (mtd->writesize <= 512) 1765 return -ENOTSUPP; 1766 1767 if (nand_has_exec_op(chip)) { 1768 const struct nand_interface_config *conf = 1769 nand_get_interface_config(chip); 1770 u8 addrs[2]; 1771 struct nand_op_instr instrs[] = { 1772 NAND_OP_CMD(NAND_CMD_RNDIN, 0), 1773 NAND_OP_ADDR(2, addrs, NAND_COMMON_TIMING_NS(conf, tCCS_min)), 1774 NAND_OP_DATA_OUT(len, buf, 0), 1775 }; 1776 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1777 int ret; 1778 1779 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1780 if (ret < 0) 1781 return ret; 1782 1783 instrs[2].ctx.data.force_8bit = force_8bit; 1784 1785 /* Drop the DATA_OUT instruction if len is set to 0. */ 1786 if (!len) 1787 op.ninstrs--; 1788 1789 return nand_exec_op(chip, &op); 1790 } 1791 1792 chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1); 1793 if (len) 1794 chip->legacy.write_buf(chip, buf, len); 1795 1796 return 0; 1797} 1798EXPORT_SYMBOL_GPL(nand_change_write_column_op); 1799 1800/** 1801 * nand_readid_op - Do a READID operation 1802 * @chip: The NAND chip 1803 * @addr: address cycle to pass after the READID command 1804 * @buf: buffer used to store the ID 1805 * @len: length of the buffer 1806 * 1807 * This function sends a READID command and reads back the ID returned by the 1808 * NAND. 1809 * This function does not select/unselect the CS line. 1810 * 1811 * Returns 0 on success, a negative error code otherwise. 1812 */ 1813int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1814 unsigned int len) 1815{ 1816 unsigned int i; 1817 u8 *id = buf, *ddrbuf = NULL; 1818 1819 if (len && !buf) 1820 return -EINVAL; 1821 1822 if (nand_has_exec_op(chip)) { 1823 const struct nand_interface_config *conf = 1824 nand_get_interface_config(chip); 1825 struct nand_op_instr instrs[] = { 1826 NAND_OP_CMD(NAND_CMD_READID, 0), 1827 NAND_OP_ADDR(1, &addr, 1828 NAND_COMMON_TIMING_NS(conf, tADL_min)), 1829 NAND_OP_8BIT_DATA_IN(len, buf, 0), 1830 }; 1831 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1832 int ret; 1833 1834 /* READ_ID data bytes are received twice in NV-DDR mode */ 1835 if (len && nand_interface_is_nvddr(conf)) { 1836 ddrbuf = kcalloc(2, len, GFP_KERNEL); 1837 if (!ddrbuf) 1838 return -ENOMEM; 1839 1840 instrs[2].ctx.data.len *= 2; 1841 instrs[2].ctx.data.buf.in = ddrbuf; 1842 } 1843 1844 /* Drop the DATA_IN instruction if len is set to 0. */ 1845 if (!len) 1846 op.ninstrs--; 1847 1848 ret = nand_exec_op(chip, &op); 1849 if (!ret && len && nand_interface_is_nvddr(conf)) { 1850 for (i = 0; i < len; i++) 1851 id[i] = ddrbuf[i * 2]; 1852 } 1853 1854 kfree(ddrbuf); 1855 1856 return ret; 1857 } 1858 1859 chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1); 1860 1861 for (i = 0; i < len; i++) 1862 id[i] = chip->legacy.read_byte(chip); 1863 1864 return 0; 1865} 1866EXPORT_SYMBOL_GPL(nand_readid_op); 1867 1868/** 1869 * nand_status_op - Do a STATUS operation 1870 * @chip: The NAND chip 1871 * @status: out variable to store the NAND status 1872 * 1873 * This function sends a STATUS command and reads back the status returned by 1874 * the NAND. 1875 * This function does not select/unselect the CS line. 1876 * 1877 * Returns 0 on success, a negative error code otherwise. 1878 */ 1879int nand_status_op(struct nand_chip *chip, u8 *status) 1880{ 1881 if (nand_has_exec_op(chip)) { 1882 const struct nand_interface_config *conf = 1883 nand_get_interface_config(chip); 1884 u8 ddrstatus[2]; 1885 struct nand_op_instr instrs[] = { 1886 NAND_OP_CMD(NAND_CMD_STATUS, 1887 NAND_COMMON_TIMING_NS(conf, tADL_min)), 1888 NAND_OP_8BIT_DATA_IN(1, status, 0), 1889 }; 1890 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1891 int ret; 1892 1893 /* The status data byte will be received twice in NV-DDR mode */ 1894 if (status && nand_interface_is_nvddr(conf)) { 1895 instrs[1].ctx.data.len *= 2; 1896 instrs[1].ctx.data.buf.in = ddrstatus; 1897 } 1898 1899 if (!status) 1900 op.ninstrs--; 1901 1902 ret = nand_exec_op(chip, &op); 1903 if (!ret && status && nand_interface_is_nvddr(conf)) 1904 *status = ddrstatus[0]; 1905 1906 return ret; 1907 } 1908 1909 chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1); 1910 if (status) 1911 *status = chip->legacy.read_byte(chip); 1912 1913 return 0; 1914} 1915EXPORT_SYMBOL_GPL(nand_status_op); 1916 1917/** 1918 * nand_exit_status_op - Exit a STATUS operation 1919 * @chip: The NAND chip 1920 * 1921 * This function sends a READ0 command to cancel the effect of the STATUS 1922 * command to avoid reading only the status until a new read command is sent. 1923 * 1924 * This function does not select/unselect the CS line. 1925 * 1926 * Returns 0 on success, a negative error code otherwise. 1927 */ 1928int nand_exit_status_op(struct nand_chip *chip) 1929{ 1930 if (nand_has_exec_op(chip)) { 1931 struct nand_op_instr instrs[] = { 1932 NAND_OP_CMD(NAND_CMD_READ0, 0), 1933 }; 1934 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1935 1936 return nand_exec_op(chip, &op); 1937 } 1938 1939 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1); 1940 1941 return 0; 1942} 1943EXPORT_SYMBOL_GPL(nand_exit_status_op); 1944 1945/** 1946 * nand_erase_op - Do an erase operation 1947 * @chip: The NAND chip 1948 * @eraseblock: block to erase 1949 * 1950 * This function sends an ERASE command and waits for the NAND to be ready 1951 * before returning. 1952 * This function does not select/unselect the CS line. 1953 * 1954 * Returns 0 on success, a negative error code otherwise. 1955 */ 1956int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock) 1957{ 1958 unsigned int page = eraseblock << 1959 (chip->phys_erase_shift - chip->page_shift); 1960 int ret; 1961 u8 status; 1962 1963 if (nand_has_exec_op(chip)) { 1964 const struct nand_interface_config *conf = 1965 nand_get_interface_config(chip); 1966 u8 addrs[3] = { page, page >> 8, page >> 16 }; 1967 struct nand_op_instr instrs[] = { 1968 NAND_OP_CMD(NAND_CMD_ERASE1, 0), 1969 NAND_OP_ADDR(2, addrs, 0), 1970 NAND_OP_CMD(NAND_CMD_ERASE2, 1971 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1972 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tBERS_max), 1973 0), 1974 }; 1975 struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip->cur_cs, 1976 instrs); 1977 1978 if (chip->options & NAND_ROW_ADDR_3) 1979 instrs[1].ctx.addr.naddrs++; 1980 1981 ret = nand_exec_op(chip, &op); 1982 if (ret) 1983 return ret; 1984 1985 ret = nand_status_op(chip, &status); 1986 if (ret) 1987 return ret; 1988 } else { 1989 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page); 1990 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1); 1991 1992 ret = chip->legacy.waitfunc(chip); 1993 if (ret < 0) 1994 return ret; 1995 1996 status = ret; 1997 } 1998 1999 if (status & NAND_STATUS_FAIL) 2000 return -EIO; 2001 2002 return 0; 2003} 2004EXPORT_SYMBOL_GPL(nand_erase_op); 2005 2006/** 2007 * nand_set_features_op - Do a SET FEATURES operation 2008 * @chip: The NAND chip 2009 * @feature: feature id 2010 * @data: 4 bytes of data 2011 * 2012 * This function sends a SET FEATURES command and waits for the NAND to be 2013 * ready before returning. 2014 * This function does not select/unselect the CS line. 2015 * 2016 * Returns 0 on success, a negative error code otherwise. 2017 */ 2018static int nand_set_features_op(struct nand_chip *chip, u8 feature, 2019 const void *data) 2020{ 2021 const u8 *params = data; 2022 int i, ret; 2023 2024 if (nand_has_exec_op(chip)) { 2025 const struct nand_interface_config *conf = 2026 nand_get_interface_config(chip); 2027 struct nand_op_instr instrs[] = { 2028 NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0), 2029 NAND_OP_ADDR(1, &feature, NAND_COMMON_TIMING_NS(conf, 2030 tADL_min)), 2031 NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data, 2032 NAND_COMMON_TIMING_NS(conf, 2033 tWB_max)), 2034 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max), 2035 0), 2036 }; 2037 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2038 2039 return nand_exec_op(chip, &op); 2040 } 2041 2042 chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1); 2043 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 2044 chip->legacy.write_byte(chip, params[i]); 2045 2046 ret = chip->legacy.waitfunc(chip); 2047 if (ret < 0) 2048 return ret; 2049 2050 if (ret & NAND_STATUS_FAIL) 2051 return -EIO; 2052 2053 return 0; 2054} 2055 2056/** 2057 * nand_get_features_op - Do a GET FEATURES operation 2058 * @chip: The NAND chip 2059 * @feature: feature id 2060 * @data: 4 bytes of data 2061 * 2062 * This function sends a GET FEATURES command and waits for the NAND to be 2063 * ready before returning. 2064 * This function does not select/unselect the CS line. 2065 * 2066 * Returns 0 on success, a negative error code otherwise. 2067 */ 2068static int nand_get_features_op(struct nand_chip *chip, u8 feature, 2069 void *data) 2070{ 2071 u8 *params = data, ddrbuf[ONFI_SUBFEATURE_PARAM_LEN * 2]; 2072 int i; 2073 2074 if (nand_has_exec_op(chip)) { 2075 const struct nand_interface_config *conf = 2076 nand_get_interface_config(chip); 2077 struct nand_op_instr instrs[] = { 2078 NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0), 2079 NAND_OP_ADDR(1, &feature, 2080 NAND_COMMON_TIMING_NS(conf, tWB_max)), 2081 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max), 2082 NAND_COMMON_TIMING_NS(conf, tRR_min)), 2083 NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN, 2084 data, 0), 2085 }; 2086 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2087 int ret; 2088 2089 /* GET_FEATURE data bytes are received twice in NV-DDR mode */ 2090 if (nand_interface_is_nvddr(conf)) { 2091 instrs[3].ctx.data.len *= 2; 2092 instrs[3].ctx.data.buf.in = ddrbuf; 2093 } 2094 2095 ret = nand_exec_op(chip, &op); 2096 if (nand_interface_is_nvddr(conf)) { 2097 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; i++) 2098 params[i] = ddrbuf[i * 2]; 2099 } 2100 2101 return ret; 2102 } 2103 2104 chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1); 2105 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 2106 params[i] = chip->legacy.read_byte(chip); 2107 2108 return 0; 2109} 2110 2111static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms, 2112 unsigned int delay_ns) 2113{ 2114 if (nand_has_exec_op(chip)) { 2115 struct nand_op_instr instrs[] = { 2116 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms), 2117 PSEC_TO_NSEC(delay_ns)), 2118 }; 2119 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2120 2121 return nand_exec_op(chip, &op); 2122 } 2123 2124 /* Apply delay or wait for ready/busy pin */ 2125 if (!chip->legacy.dev_ready) 2126 udelay(chip->legacy.chip_delay); 2127 else 2128 nand_wait_ready(chip); 2129 2130 return 0; 2131} 2132 2133/** 2134 * nand_reset_op - Do a reset operation 2135 * @chip: The NAND chip 2136 * 2137 * This function sends a RESET command and waits for the NAND to be ready 2138 * before returning. 2139 * This function does not select/unselect the CS line. 2140 * 2141 * Returns 0 on success, a negative error code otherwise. 2142 */ 2143int nand_reset_op(struct nand_chip *chip) 2144{ 2145 if (nand_has_exec_op(chip)) { 2146 const struct nand_interface_config *conf = 2147 nand_get_interface_config(chip); 2148 struct nand_op_instr instrs[] = { 2149 NAND_OP_CMD(NAND_CMD_RESET, 2150 NAND_COMMON_TIMING_NS(conf, tWB_max)), 2151 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tRST_max), 2152 0), 2153 }; 2154 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2155 2156 return nand_exec_op(chip, &op); 2157 } 2158 2159 chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1); 2160 2161 return 0; 2162} 2163EXPORT_SYMBOL_GPL(nand_reset_op); 2164 2165/** 2166 * nand_read_data_op - Read data from the NAND 2167 * @chip: The NAND chip 2168 * @buf: buffer used to store the data 2169 * @len: length of the buffer 2170 * @force_8bit: force 8-bit bus access 2171 * @check_only: do not actually run the command, only checks if the 2172 * controller driver supports it 2173 * 2174 * This function does a raw data read on the bus. Usually used after launching 2175 * another NAND operation like nand_read_page_op(). 2176 * This function does not select/unselect the CS line. 2177 * 2178 * Returns 0 on success, a negative error code otherwise. 2179 */ 2180int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 2181 bool force_8bit, bool check_only) 2182{ 2183 if (!len || (!check_only && !buf)) 2184 return -EINVAL; 2185 2186 if (nand_has_exec_op(chip)) { 2187 const struct nand_interface_config *conf = 2188 nand_get_interface_config(chip); 2189 struct nand_op_instr instrs[] = { 2190 NAND_OP_DATA_IN(len, buf, 0), 2191 }; 2192 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2193 u8 *ddrbuf = NULL; 2194 int ret, i; 2195 2196 instrs[0].ctx.data.force_8bit = force_8bit; 2197 2198 /* 2199 * Parameter payloads (ID, status, features, etc) do not go 2200 * through the same pipeline as regular data, hence the 2201 * force_8bit flag must be set and this also indicates that in 2202 * case NV-DDR timings are being used the data will be received 2203 * twice. 2204 */ 2205 if (force_8bit && nand_interface_is_nvddr(conf)) { 2206 ddrbuf = kcalloc(2, len, GFP_KERNEL); 2207 if (!ddrbuf) 2208 return -ENOMEM; 2209 2210 instrs[0].ctx.data.len *= 2; 2211 instrs[0].ctx.data.buf.in = ddrbuf; 2212 } 2213 2214 if (check_only) { 2215 ret = nand_check_op(chip, &op); 2216 kfree(ddrbuf); 2217 return ret; 2218 } 2219 2220 ret = nand_exec_op(chip, &op); 2221 if (!ret && force_8bit && nand_interface_is_nvddr(conf)) { 2222 u8 *dst = buf; 2223 2224 for (i = 0; i < len; i++) 2225 dst[i] = ddrbuf[i * 2]; 2226 } 2227 2228 kfree(ddrbuf); 2229 2230 return ret; 2231 } 2232 2233 if (check_only) 2234 return 0; 2235 2236 if (force_8bit) { 2237 u8 *p = buf; 2238 unsigned int i; 2239 2240 for (i = 0; i < len; i++) 2241 p[i] = chip->legacy.read_byte(chip); 2242 } else { 2243 chip->legacy.read_buf(chip, buf, len); 2244 } 2245 2246 return 0; 2247} 2248EXPORT_SYMBOL_GPL(nand_read_data_op); 2249 2250/** 2251 * nand_write_data_op - Write data from the NAND 2252 * @chip: The NAND chip 2253 * @buf: buffer containing the data to send on the bus 2254 * @len: length of the buffer 2255 * @force_8bit: force 8-bit bus access 2256 * 2257 * This function does a raw data write on the bus. Usually used after launching 2258 * another NAND operation like nand_write_page_begin_op(). 2259 * This function does not select/unselect the CS line. 2260 * 2261 * Returns 0 on success, a negative error code otherwise. 2262 */ 2263int nand_write_data_op(struct nand_chip *chip, const void *buf, 2264 unsigned int len, bool force_8bit) 2265{ 2266 if (!len || !buf) 2267 return -EINVAL; 2268 2269 if (nand_has_exec_op(chip)) { 2270 struct nand_op_instr instrs[] = { 2271 NAND_OP_DATA_OUT(len, buf, 0), 2272 }; 2273 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2274 2275 instrs[0].ctx.data.force_8bit = force_8bit; 2276 2277 return nand_exec_op(chip, &op); 2278 } 2279 2280 if (force_8bit) { 2281 const u8 *p = buf; 2282 unsigned int i; 2283 2284 for (i = 0; i < len; i++) 2285 chip->legacy.write_byte(chip, p[i]); 2286 } else { 2287 chip->legacy.write_buf(chip, buf, len); 2288 } 2289 2290 return 0; 2291} 2292EXPORT_SYMBOL_GPL(nand_write_data_op); 2293 2294/** 2295 * struct nand_op_parser_ctx - Context used by the parser 2296 * @instrs: array of all the instructions that must be addressed 2297 * @ninstrs: length of the @instrs array 2298 * @subop: Sub-operation to be passed to the NAND controller 2299 * 2300 * This structure is used by the core to split NAND operations into 2301 * sub-operations that can be handled by the NAND controller. 2302 */ 2303struct nand_op_parser_ctx { 2304 const struct nand_op_instr *instrs; 2305 unsigned int ninstrs; 2306 struct nand_subop subop; 2307}; 2308 2309/** 2310 * nand_op_parser_must_split_instr - Checks if an instruction must be split 2311 * @pat: the parser pattern element that matches @instr 2312 * @instr: pointer to the instruction to check 2313 * @start_offset: this is an in/out parameter. If @instr has already been 2314 * split, then @start_offset is the offset from which to start 2315 * (either an address cycle or an offset in the data buffer). 2316 * Conversely, if the function returns true (ie. instr must be 2317 * split), this parameter is updated to point to the first 2318 * data/address cycle that has not been taken care of. 2319 * 2320 * Some NAND controllers are limited and cannot send X address cycles with a 2321 * unique operation, or cannot read/write more than Y bytes at the same time. 2322 * In this case, split the instruction that does not fit in a single 2323 * controller-operation into two or more chunks. 2324 * 2325 * Returns true if the instruction must be split, false otherwise. 2326 * The @start_offset parameter is also updated to the offset at which the next 2327 * bundle of instruction must start (if an address or a data instruction). 2328 */ 2329static bool 2330nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat, 2331 const struct nand_op_instr *instr, 2332 unsigned int *start_offset) 2333{ 2334 switch (pat->type) { 2335 case NAND_OP_ADDR_INSTR: 2336 if (!pat->ctx.addr.maxcycles) 2337 break; 2338 2339 if (instr->ctx.addr.naddrs - *start_offset > 2340 pat->ctx.addr.maxcycles) { 2341 *start_offset += pat->ctx.addr.maxcycles; 2342 return true; 2343 } 2344 break; 2345 2346 case NAND_OP_DATA_IN_INSTR: 2347 case NAND_OP_DATA_OUT_INSTR: 2348 if (!pat->ctx.data.maxlen) 2349 break; 2350 2351 if (instr->ctx.data.len - *start_offset > 2352 pat->ctx.data.maxlen) { 2353 *start_offset += pat->ctx.data.maxlen; 2354 return true; 2355 } 2356 break; 2357 2358 default: 2359 break; 2360 } 2361 2362 return false; 2363} 2364 2365/** 2366 * nand_op_parser_match_pat - Checks if a pattern matches the instructions 2367 * remaining in the parser context 2368 * @pat: the pattern to test 2369 * @ctx: the parser context structure to match with the pattern @pat 2370 * 2371 * Check if @pat matches the set or a sub-set of instructions remaining in @ctx. 2372 * Returns true if this is the case, false ortherwise. When true is returned, 2373 * @ctx->subop is updated with the set of instructions to be passed to the 2374 * controller driver. 2375 */ 2376static bool 2377nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat, 2378 struct nand_op_parser_ctx *ctx) 2379{ 2380 unsigned int instr_offset = ctx->subop.first_instr_start_off; 2381 const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs; 2382 const struct nand_op_instr *instr = ctx->subop.instrs; 2383 unsigned int i, ninstrs; 2384 2385 for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) { 2386 /* 2387 * The pattern instruction does not match the operation 2388 * instruction. If the instruction is marked optional in the 2389 * pattern definition, we skip the pattern element and continue 2390 * to the next one. If the element is mandatory, there's no 2391 * match and we can return false directly. 2392 */ 2393 if (instr->type != pat->elems[i].type) { 2394 if (!pat->elems[i].optional) 2395 return false; 2396 2397 continue; 2398 } 2399 2400 /* 2401 * Now check the pattern element constraints. If the pattern is 2402 * not able to handle the whole instruction in a single step, 2403 * we have to split it. 2404 * The last_instr_end_off value comes back updated to point to 2405 * the position where we have to split the instruction (the 2406 * start of the next subop chunk). 2407 */ 2408 if (nand_op_parser_must_split_instr(&pat->elems[i], instr, 2409 &instr_offset)) { 2410 ninstrs++; 2411 i++; 2412 break; 2413 } 2414 2415 instr++; 2416 ninstrs++; 2417 instr_offset = 0; 2418 } 2419 2420 /* 2421 * This can happen if all instructions of a pattern are optional. 2422 * Still, if there's not at least one instruction handled by this 2423 * pattern, this is not a match, and we should try the next one (if 2424 * any). 2425 */ 2426 if (!ninstrs) 2427 return false; 2428 2429 /* 2430 * We had a match on the pattern head, but the pattern may be longer 2431 * than the instructions we're asked to execute. We need to make sure 2432 * there's no mandatory elements in the pattern tail. 2433 */ 2434 for (; i < pat->nelems; i++) { 2435 if (!pat->elems[i].optional) 2436 return false; 2437 } 2438 2439 /* 2440 * We have a match: update the subop structure accordingly and return 2441 * true. 2442 */ 2443 ctx->subop.ninstrs = ninstrs; 2444 ctx->subop.last_instr_end_off = instr_offset; 2445 2446 return true; 2447} 2448 2449#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG) 2450static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx) 2451{ 2452 const struct nand_op_instr *instr; 2453 char *prefix = " "; 2454 unsigned int i; 2455 2456 pr_debug("executing subop (CS%d):\n", ctx->subop.cs); 2457 2458 for (i = 0; i < ctx->ninstrs; i++) { 2459 instr = &ctx->instrs[i]; 2460 2461 if (instr == &ctx->subop.instrs[0]) 2462 prefix = " ->"; 2463 2464 nand_op_trace(prefix, instr); 2465 2466 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1]) 2467 prefix = " "; 2468 } 2469} 2470#else 2471static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx) 2472{ 2473 /* NOP */ 2474} 2475#endif 2476 2477static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a, 2478 const struct nand_op_parser_ctx *b) 2479{ 2480 if (a->subop.ninstrs < b->subop.ninstrs) 2481 return -1; 2482 else if (a->subop.ninstrs > b->subop.ninstrs) 2483 return 1; 2484 2485 if (a->subop.last_instr_end_off < b->subop.last_instr_end_off) 2486 return -1; 2487 else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off) 2488 return 1; 2489 2490 return 0; 2491} 2492 2493/** 2494 * nand_op_parser_exec_op - exec_op parser 2495 * @chip: the NAND chip 2496 * @parser: patterns description provided by the controller driver 2497 * @op: the NAND operation to address 2498 * @check_only: when true, the function only checks if @op can be handled but 2499 * does not execute the operation 2500 * 2501 * Helper function designed to ease integration of NAND controller drivers that 2502 * only support a limited set of instruction sequences. The supported sequences 2503 * are described in @parser, and the framework takes care of splitting @op into 2504 * multiple sub-operations (if required) and pass them back to the ->exec() 2505 * callback of the matching pattern if @check_only is set to false. 2506 * 2507 * NAND controller drivers should call this function from their own ->exec_op() 2508 * implementation. 2509 * 2510 * Returns 0 on success, a negative error code otherwise. A failure can be 2511 * caused by an unsupported operation (none of the supported patterns is able 2512 * to handle the requested operation), or an error returned by one of the 2513 * matching pattern->exec() hook. 2514 */ 2515int nand_op_parser_exec_op(struct nand_chip *chip, 2516 const struct nand_op_parser *parser, 2517 const struct nand_operation *op, bool check_only) 2518{ 2519 struct nand_op_parser_ctx ctx = { 2520 .subop.cs = op->cs, 2521 .subop.instrs = op->instrs, 2522 .instrs = op->instrs, 2523 .ninstrs = op->ninstrs, 2524 }; 2525 unsigned int i; 2526 2527 while (ctx.subop.instrs < op->instrs + op->ninstrs) { 2528 const struct nand_op_parser_pattern *pattern; 2529 struct nand_op_parser_ctx best_ctx; 2530 int ret, best_pattern = -1; 2531 2532 for (i = 0; i < parser->npatterns; i++) { 2533 struct nand_op_parser_ctx test_ctx = ctx; 2534 2535 pattern = &parser->patterns[i]; 2536 if (!nand_op_parser_match_pat(pattern, &test_ctx)) 2537 continue; 2538 2539 if (best_pattern >= 0 && 2540 nand_op_parser_cmp_ctx(&test_ctx, &best_ctx) <= 0) 2541 continue; 2542 2543 best_pattern = i; 2544 best_ctx = test_ctx; 2545 } 2546 2547 if (best_pattern < 0) { 2548 pr_debug("->exec_op() parser: pattern not found!\n"); 2549 return -ENOTSUPP; 2550 } 2551 2552 ctx = best_ctx; 2553 nand_op_parser_trace(&ctx); 2554 2555 if (!check_only) { 2556 pattern = &parser->patterns[best_pattern]; 2557 ret = pattern->exec(chip, &ctx.subop); 2558 if (ret) 2559 return ret; 2560 } 2561 2562 /* 2563 * Update the context structure by pointing to the start of the 2564 * next subop. 2565 */ 2566 ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs; 2567 if (ctx.subop.last_instr_end_off) 2568 ctx.subop.instrs -= 1; 2569 2570 ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off; 2571 } 2572 2573 return 0; 2574} 2575EXPORT_SYMBOL_GPL(nand_op_parser_exec_op); 2576 2577static bool nand_instr_is_data(const struct nand_op_instr *instr) 2578{ 2579 return instr && (instr->type == NAND_OP_DATA_IN_INSTR || 2580 instr->type == NAND_OP_DATA_OUT_INSTR); 2581} 2582 2583static bool nand_subop_instr_is_valid(const struct nand_subop *subop, 2584 unsigned int instr_idx) 2585{ 2586 return subop && instr_idx < subop->ninstrs; 2587} 2588 2589static unsigned int nand_subop_get_start_off(const struct nand_subop *subop, 2590 unsigned int instr_idx) 2591{ 2592 if (instr_idx) 2593 return 0; 2594 2595 return subop->first_instr_start_off; 2596} 2597 2598/** 2599 * nand_subop_get_addr_start_off - Get the start offset in an address array 2600 * @subop: The entire sub-operation 2601 * @instr_idx: Index of the instruction inside the sub-operation 2602 * 2603 * During driver development, one could be tempted to directly use the 2604 * ->addr.addrs field of address instructions. This is wrong as address 2605 * instructions might be split. 2606 * 2607 * Given an address instruction, returns the offset of the first cycle to issue. 2608 */ 2609unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 2610 unsigned int instr_idx) 2611{ 2612 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2613 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) 2614 return 0; 2615 2616 return nand_subop_get_start_off(subop, instr_idx); 2617} 2618EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off); 2619 2620/** 2621 * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert 2622 * @subop: The entire sub-operation 2623 * @instr_idx: Index of the instruction inside the sub-operation 2624 * 2625 * During driver development, one could be tempted to directly use the 2626 * ->addr->naddrs field of a data instruction. This is wrong as instructions 2627 * might be split. 2628 * 2629 * Given an address instruction, returns the number of address cycle to issue. 2630 */ 2631unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 2632 unsigned int instr_idx) 2633{ 2634 int start_off, end_off; 2635 2636 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2637 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) 2638 return 0; 2639 2640 start_off = nand_subop_get_addr_start_off(subop, instr_idx); 2641 2642 if (instr_idx == subop->ninstrs - 1 && 2643 subop->last_instr_end_off) 2644 end_off = subop->last_instr_end_off; 2645 else 2646 end_off = subop->instrs[instr_idx].ctx.addr.naddrs; 2647 2648 return end_off - start_off; 2649} 2650EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc); 2651 2652/** 2653 * nand_subop_get_data_start_off - Get the start offset in a data array 2654 * @subop: The entire sub-operation 2655 * @instr_idx: Index of the instruction inside the sub-operation 2656 * 2657 * During driver development, one could be tempted to directly use the 2658 * ->data->buf.{in,out} field of data instructions. This is wrong as data 2659 * instructions might be split. 2660 * 2661 * Given a data instruction, returns the offset to start from. 2662 */ 2663unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 2664 unsigned int instr_idx) 2665{ 2666 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2667 !nand_instr_is_data(&subop->instrs[instr_idx]))) 2668 return 0; 2669 2670 return nand_subop_get_start_off(subop, instr_idx); 2671} 2672EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off); 2673 2674/** 2675 * nand_subop_get_data_len - Get the number of bytes to retrieve 2676 * @subop: The entire sub-operation 2677 * @instr_idx: Index of the instruction inside the sub-operation 2678 * 2679 * During driver development, one could be tempted to directly use the 2680 * ->data->len field of a data instruction. This is wrong as data instructions 2681 * might be split. 2682 * 2683 * Returns the length of the chunk of data to send/receive. 2684 */ 2685unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 2686 unsigned int instr_idx) 2687{ 2688 int start_off = 0, end_off; 2689 2690 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2691 !nand_instr_is_data(&subop->instrs[instr_idx]))) 2692 return 0; 2693 2694 start_off = nand_subop_get_data_start_off(subop, instr_idx); 2695 2696 if (instr_idx == subop->ninstrs - 1 && 2697 subop->last_instr_end_off) 2698 end_off = subop->last_instr_end_off; 2699 else 2700 end_off = subop->instrs[instr_idx].ctx.data.len; 2701 2702 return end_off - start_off; 2703} 2704EXPORT_SYMBOL_GPL(nand_subop_get_data_len); 2705 2706/** 2707 * nand_reset - Reset and initialize a NAND device 2708 * @chip: The NAND chip 2709 * @chipnr: Internal die id 2710 * 2711 * Save the timings data structure, then apply SDR timings mode 0 (see 2712 * nand_reset_interface for details), do the reset operation, and apply 2713 * back the previous timings. 2714 * 2715 * Returns 0 on success, a negative error code otherwise. 2716 */ 2717int nand_reset(struct nand_chip *chip, int chipnr) 2718{ 2719 int ret; 2720 2721 ret = nand_reset_interface(chip, chipnr); 2722 if (ret) 2723 return ret; 2724 2725 /* 2726 * The CS line has to be released before we can apply the new NAND 2727 * interface settings, hence this weird nand_select_target() 2728 * nand_deselect_target() dance. 2729 */ 2730 nand_select_target(chip, chipnr); 2731 ret = nand_reset_op(chip); 2732 nand_deselect_target(chip); 2733 if (ret) 2734 return ret; 2735 2736 ret = nand_setup_interface(chip, chipnr); 2737 if (ret) 2738 return ret; 2739 2740 return 0; 2741} 2742EXPORT_SYMBOL_GPL(nand_reset); 2743 2744/** 2745 * nand_get_features - wrapper to perform a GET_FEATURE 2746 * @chip: NAND chip info structure 2747 * @addr: feature address 2748 * @subfeature_param: the subfeature parameters, a four bytes array 2749 * 2750 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the 2751 * operation cannot be handled. 2752 */ 2753int nand_get_features(struct nand_chip *chip, int addr, 2754 u8 *subfeature_param) 2755{ 2756 if (!nand_supports_get_features(chip, addr)) 2757 return -ENOTSUPP; 2758 2759 if (chip->legacy.get_features) 2760 return chip->legacy.get_features(chip, addr, subfeature_param); 2761 2762 return nand_get_features_op(chip, addr, subfeature_param); 2763} 2764 2765/** 2766 * nand_set_features - wrapper to perform a SET_FEATURE 2767 * @chip: NAND chip info structure 2768 * @addr: feature address 2769 * @subfeature_param: the subfeature parameters, a four bytes array 2770 * 2771 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the 2772 * operation cannot be handled. 2773 */ 2774int nand_set_features(struct nand_chip *chip, int addr, 2775 u8 *subfeature_param) 2776{ 2777 if (!nand_supports_set_features(chip, addr)) 2778 return -ENOTSUPP; 2779 2780 if (chip->legacy.set_features) 2781 return chip->legacy.set_features(chip, addr, subfeature_param); 2782 2783 return nand_set_features_op(chip, addr, subfeature_param); 2784} 2785 2786/** 2787 * nand_read_page_raw_notsupp - dummy read raw page function 2788 * @chip: nand chip info structure 2789 * @buf: buffer to store read data 2790 * @oob_required: caller requires OOB data read to chip->oob_poi 2791 * @page: page number to read 2792 * 2793 * Returns -ENOTSUPP unconditionally. 2794 */ 2795int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf, 2796 int oob_required, int page) 2797{ 2798 return -ENOTSUPP; 2799} 2800 2801/** 2802 * nand_read_page_raw - [INTERN] read raw page data without ecc 2803 * @chip: nand chip info structure 2804 * @buf: buffer to store read data 2805 * @oob_required: caller requires OOB data read to chip->oob_poi 2806 * @page: page number to read 2807 * 2808 * Not for syndrome calculating ECC controllers, which use a special oob layout. 2809 */ 2810int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 2811 int page) 2812{ 2813 struct mtd_info *mtd = nand_to_mtd(chip); 2814 int ret; 2815 2816 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize); 2817 if (ret) 2818 return ret; 2819 2820 if (oob_required) { 2821 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, 2822 false, false); 2823 if (ret) 2824 return ret; 2825 } 2826 2827 return 0; 2828} 2829EXPORT_SYMBOL(nand_read_page_raw); 2830 2831/** 2832 * nand_monolithic_read_page_raw - Monolithic page read in raw mode 2833 * @chip: NAND chip info structure 2834 * @buf: buffer to store read data 2835 * @oob_required: caller requires OOB data read to chip->oob_poi 2836 * @page: page number to read 2837 * 2838 * This is a raw page read, ie. without any error detection/correction. 2839 * Monolithic means we are requesting all the relevant data (main plus 2840 * eventually OOB) to be loaded in the NAND cache and sent over the 2841 * bus (from the NAND chip to the NAND controller) in a single 2842 * operation. This is an alternative to nand_read_page_raw(), which 2843 * first reads the main data, and if the OOB data is requested too, 2844 * then reads more data on the bus. 2845 */ 2846int nand_monolithic_read_page_raw(struct nand_chip *chip, u8 *buf, 2847 int oob_required, int page) 2848{ 2849 struct mtd_info *mtd = nand_to_mtd(chip); 2850 unsigned int size = mtd->writesize; 2851 u8 *read_buf = buf; 2852 int ret; 2853 2854 if (oob_required) { 2855 size += mtd->oobsize; 2856 2857 if (buf != chip->data_buf) 2858 read_buf = nand_get_data_buf(chip); 2859 } 2860 2861 ret = nand_read_page_op(chip, page, 0, read_buf, size); 2862 if (ret) 2863 return ret; 2864 2865 if (buf != chip->data_buf) 2866 memcpy(buf, read_buf, mtd->writesize); 2867 2868 return 0; 2869} 2870EXPORT_SYMBOL(nand_monolithic_read_page_raw); 2871 2872/** 2873 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc 2874 * @chip: nand chip info structure 2875 * @buf: buffer to store read data 2876 * @oob_required: caller requires OOB data read to chip->oob_poi 2877 * @page: page number to read 2878 * 2879 * We need a special oob layout and handling even when OOB isn't used. 2880 */ 2881static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf, 2882 int oob_required, int page) 2883{ 2884 struct mtd_info *mtd = nand_to_mtd(chip); 2885 int eccsize = chip->ecc.size; 2886 int eccbytes = chip->ecc.bytes; 2887 uint8_t *oob = chip->oob_poi; 2888 int steps, size, ret; 2889 2890 ret = nand_read_page_op(chip, page, 0, NULL, 0); 2891 if (ret) 2892 return ret; 2893 2894 for (steps = chip->ecc.steps; steps > 0; steps--) { 2895 ret = nand_read_data_op(chip, buf, eccsize, false, false); 2896 if (ret) 2897 return ret; 2898 2899 buf += eccsize; 2900 2901 if (chip->ecc.prepad) { 2902 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, 2903 false, false); 2904 if (ret) 2905 return ret; 2906 2907 oob += chip->ecc.prepad; 2908 } 2909 2910 ret = nand_read_data_op(chip, oob, eccbytes, false, false); 2911 if (ret) 2912 return ret; 2913 2914 oob += eccbytes; 2915 2916 if (chip->ecc.postpad) { 2917 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, 2918 false, false); 2919 if (ret) 2920 return ret; 2921 2922 oob += chip->ecc.postpad; 2923 } 2924 } 2925 2926 size = mtd->oobsize - (oob - chip->oob_poi); 2927 if (size) { 2928 ret = nand_read_data_op(chip, oob, size, false, false); 2929 if (ret) 2930 return ret; 2931 } 2932 2933 return 0; 2934} 2935 2936/** 2937 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function 2938 * @chip: nand chip info structure 2939 * @buf: buffer to store read data 2940 * @oob_required: caller requires OOB data read to chip->oob_poi 2941 * @page: page number to read 2942 */ 2943static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf, 2944 int oob_required, int page) 2945{ 2946 struct mtd_info *mtd = nand_to_mtd(chip); 2947 int i, eccsize = chip->ecc.size, ret; 2948 int eccbytes = chip->ecc.bytes; 2949 int eccsteps = chip->ecc.steps; 2950 uint8_t *p = buf; 2951 uint8_t *ecc_calc = chip->ecc.calc_buf; 2952 uint8_t *ecc_code = chip->ecc.code_buf; 2953 unsigned int max_bitflips = 0; 2954 2955 chip->ecc.read_page_raw(chip, buf, 1, page); 2956 2957 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 2958 chip->ecc.calculate(chip, p, &ecc_calc[i]); 2959 2960 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 2961 chip->ecc.total); 2962 if (ret) 2963 return ret; 2964 2965 eccsteps = chip->ecc.steps; 2966 p = buf; 2967 2968 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2969 int stat; 2970 2971 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); 2972 if (stat < 0) { 2973 mtd->ecc_stats.failed++; 2974 } else { 2975 mtd->ecc_stats.corrected += stat; 2976 max_bitflips = max_t(unsigned int, max_bitflips, stat); 2977 } 2978 } 2979 return max_bitflips; 2980} 2981 2982/** 2983 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function 2984 * @chip: nand chip info structure 2985 * @data_offs: offset of requested data within the page 2986 * @readlen: data length 2987 * @bufpoi: buffer to store read data 2988 * @page: page number to read 2989 */ 2990static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs, 2991 uint32_t readlen, uint8_t *bufpoi, int page) 2992{ 2993 struct mtd_info *mtd = nand_to_mtd(chip); 2994 int start_step, end_step, num_steps, ret; 2995 uint8_t *p; 2996 int data_col_addr, i, gaps = 0; 2997 int datafrag_len, eccfrag_len, aligned_len, aligned_pos; 2998 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; 2999 int index, section = 0; 3000 unsigned int max_bitflips = 0; 3001 struct mtd_oob_region oobregion = { }; 3002 3003 /* Column address within the page aligned to ECC size (256bytes) */ 3004 start_step = data_offs / chip->ecc.size; 3005 end_step = (data_offs + readlen - 1) / chip->ecc.size; 3006 num_steps = end_step - start_step + 1; 3007 index = start_step * chip->ecc.bytes; 3008 3009 /* Data size aligned to ECC ecc.size */ 3010 datafrag_len = num_steps * chip->ecc.size; 3011 eccfrag_len = num_steps * chip->ecc.bytes; 3012 3013 data_col_addr = start_step * chip->ecc.size; 3014 /* If we read not a page aligned data */ 3015 p = bufpoi + data_col_addr; 3016 ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len); 3017 if (ret) 3018 return ret; 3019 3020 /* Calculate ECC */ 3021 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) 3022 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]); 3023 3024 /* 3025 * The performance is faster if we position offsets according to 3026 * ecc.pos. Let's make sure that there are no gaps in ECC positions. 3027 */ 3028 ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); 3029 if (ret) 3030 return ret; 3031 3032 if (oobregion.length < eccfrag_len) 3033 gaps = 1; 3034 3035 if (gaps) { 3036 ret = nand_change_read_column_op(chip, mtd->writesize, 3037 chip->oob_poi, mtd->oobsize, 3038 false); 3039 if (ret) 3040 return ret; 3041 } else { 3042 /* 3043 * Send the command to read the particular ECC bytes take care 3044 * about buswidth alignment in read_buf. 3045 */ 3046 aligned_pos = oobregion.offset & ~(busw - 1); 3047 aligned_len = eccfrag_len; 3048 if (oobregion.offset & (busw - 1)) 3049 aligned_len++; 3050 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & 3051 (busw - 1)) 3052 aligned_len++; 3053 3054 ret = nand_change_read_column_op(chip, 3055 mtd->writesize + aligned_pos, 3056 &chip->oob_poi[aligned_pos], 3057 aligned_len, false); 3058 if (ret) 3059 return ret; 3060 } 3061 3062 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf, 3063 chip->oob_poi, index, eccfrag_len); 3064 if (ret) 3065 return ret; 3066 3067 p = bufpoi + data_col_addr; 3068 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { 3069 int stat; 3070 3071 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i], 3072 &chip->ecc.calc_buf[i]); 3073 if (stat == -EBADMSG && 3074 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3075 /* check for empty pages with bitflips */ 3076 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 3077 &chip->ecc.code_buf[i], 3078 chip->ecc.bytes, 3079 NULL, 0, 3080 chip->ecc.strength); 3081 } 3082 3083 if (stat < 0) { 3084 mtd->ecc_stats.failed++; 3085 } else { 3086 mtd->ecc_stats.corrected += stat; 3087 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3088 } 3089 } 3090 return max_bitflips; 3091} 3092 3093/** 3094 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function 3095 * @chip: nand chip info structure 3096 * @buf: buffer to store read data 3097 * @oob_required: caller requires OOB data read to chip->oob_poi 3098 * @page: page number to read 3099 * 3100 * Not for syndrome calculating ECC controllers which need a special oob layout. 3101 */ 3102static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf, 3103 int oob_required, int page) 3104{ 3105 struct mtd_info *mtd = nand_to_mtd(chip); 3106 int i, eccsize = chip->ecc.size, ret; 3107 int eccbytes = chip->ecc.bytes; 3108 int eccsteps = chip->ecc.steps; 3109 uint8_t *p = buf; 3110 uint8_t *ecc_calc = chip->ecc.calc_buf; 3111 uint8_t *ecc_code = chip->ecc.code_buf; 3112 unsigned int max_bitflips = 0; 3113 3114 ret = nand_read_page_op(chip, page, 0, NULL, 0); 3115 if (ret) 3116 return ret; 3117 3118 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3119 chip->ecc.hwctl(chip, NAND_ECC_READ); 3120 3121 ret = nand_read_data_op(chip, p, eccsize, false, false); 3122 if (ret) 3123 return ret; 3124 3125 chip->ecc.calculate(chip, p, &ecc_calc[i]); 3126 } 3127 3128 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, 3129 false); 3130 if (ret) 3131 return ret; 3132 3133 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 3134 chip->ecc.total); 3135 if (ret) 3136 return ret; 3137 3138 eccsteps = chip->ecc.steps; 3139 p = buf; 3140 3141 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3142 int stat; 3143 3144 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); 3145 if (stat == -EBADMSG && 3146 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3147 /* check for empty pages with bitflips */ 3148 stat = nand_check_erased_ecc_chunk(p, eccsize, 3149 &ecc_code[i], eccbytes, 3150 NULL, 0, 3151 chip->ecc.strength); 3152 } 3153 3154 if (stat < 0) { 3155 mtd->ecc_stats.failed++; 3156 } else { 3157 mtd->ecc_stats.corrected += stat; 3158 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3159 } 3160 } 3161 return max_bitflips; 3162} 3163 3164/** 3165 * nand_read_page_hwecc_oob_first - Hardware ECC page read with ECC 3166 * data read from OOB area 3167 * @chip: nand chip info structure 3168 * @buf: buffer to store read data 3169 * @oob_required: caller requires OOB data read to chip->oob_poi 3170 * @page: page number to read 3171 * 3172 * Hardware ECC for large page chips, which requires the ECC data to be 3173 * extracted from the OOB before the actual data is read. 3174 */ 3175int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf, 3176 int oob_required, int page) 3177{ 3178 struct mtd_info *mtd = nand_to_mtd(chip); 3179 int i, eccsize = chip->ecc.size, ret; 3180 int eccbytes = chip->ecc.bytes; 3181 int eccsteps = chip->ecc.steps; 3182 uint8_t *p = buf; 3183 uint8_t *ecc_code = chip->ecc.code_buf; 3184 unsigned int max_bitflips = 0; 3185 3186 /* Read the OOB area first */ 3187 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 3188 if (ret) 3189 return ret; 3190 3191 /* Move read cursor to start of page */ 3192 ret = nand_change_read_column_op(chip, 0, NULL, 0, false); 3193 if (ret) 3194 return ret; 3195 3196 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 3197 chip->ecc.total); 3198 if (ret) 3199 return ret; 3200 3201 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3202 int stat; 3203 3204 chip->ecc.hwctl(chip, NAND_ECC_READ); 3205 3206 ret = nand_read_data_op(chip, p, eccsize, false, false); 3207 if (ret) 3208 return ret; 3209 3210 stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL); 3211 if (stat == -EBADMSG && 3212 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3213 /* check for empty pages with bitflips */ 3214 stat = nand_check_erased_ecc_chunk(p, eccsize, 3215 &ecc_code[i], 3216 eccbytes, NULL, 0, 3217 chip->ecc.strength); 3218 } 3219 3220 if (stat < 0) { 3221 mtd->ecc_stats.failed++; 3222 } else { 3223 mtd->ecc_stats.corrected += stat; 3224 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3225 } 3226 } 3227 return max_bitflips; 3228} 3229EXPORT_SYMBOL_GPL(nand_read_page_hwecc_oob_first); 3230 3231/** 3232 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read 3233 * @chip: nand chip info structure 3234 * @buf: buffer to store read data 3235 * @oob_required: caller requires OOB data read to chip->oob_poi 3236 * @page: page number to read 3237 * 3238 * The hw generator calculates the error syndrome automatically. Therefore we 3239 * need a special oob layout and handling. 3240 */ 3241static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf, 3242 int oob_required, int page) 3243{ 3244 struct mtd_info *mtd = nand_to_mtd(chip); 3245 int ret, i, eccsize = chip->ecc.size; 3246 int eccbytes = chip->ecc.bytes; 3247 int eccsteps = chip->ecc.steps; 3248 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 3249 uint8_t *p = buf; 3250 uint8_t *oob = chip->oob_poi; 3251 unsigned int max_bitflips = 0; 3252 3253 ret = nand_read_page_op(chip, page, 0, NULL, 0); 3254 if (ret) 3255 return ret; 3256 3257 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3258 int stat; 3259 3260 chip->ecc.hwctl(chip, NAND_ECC_READ); 3261 3262 ret = nand_read_data_op(chip, p, eccsize, false, false); 3263 if (ret) 3264 return ret; 3265 3266 if (chip->ecc.prepad) { 3267 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, 3268 false, false); 3269 if (ret) 3270 return ret; 3271 3272 oob += chip->ecc.prepad; 3273 } 3274 3275 chip->ecc.hwctl(chip, NAND_ECC_READSYN); 3276 3277 ret = nand_read_data_op(chip, oob, eccbytes, false, false); 3278 if (ret) 3279 return ret; 3280 3281 stat = chip->ecc.correct(chip, p, oob, NULL); 3282 3283 oob += eccbytes; 3284 3285 if (chip->ecc.postpad) { 3286 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, 3287 false, false); 3288 if (ret) 3289 return ret; 3290 3291 oob += chip->ecc.postpad; 3292 } 3293 3294 if (stat == -EBADMSG && 3295 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3296 /* check for empty pages with bitflips */ 3297 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 3298 oob - eccpadbytes, 3299 eccpadbytes, 3300 NULL, 0, 3301 chip->ecc.strength); 3302 } 3303 3304 if (stat < 0) { 3305 mtd->ecc_stats.failed++; 3306 } else { 3307 mtd->ecc_stats.corrected += stat; 3308 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3309 } 3310 } 3311 3312 /* Calculate remaining oob bytes */ 3313 i = mtd->oobsize - (oob - chip->oob_poi); 3314 if (i) { 3315 ret = nand_read_data_op(chip, oob, i, false, false); 3316 if (ret) 3317 return ret; 3318 } 3319 3320 return max_bitflips; 3321} 3322 3323/** 3324 * nand_transfer_oob - [INTERN] Transfer oob to client buffer 3325 * @chip: NAND chip object 3326 * @oob: oob destination address 3327 * @ops: oob ops structure 3328 * @len: size of oob to transfer 3329 */ 3330static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, 3331 struct mtd_oob_ops *ops, size_t len) 3332{ 3333 struct mtd_info *mtd = nand_to_mtd(chip); 3334 int ret; 3335 3336 switch (ops->mode) { 3337 3338 case MTD_OPS_PLACE_OOB: 3339 case MTD_OPS_RAW: 3340 memcpy(oob, chip->oob_poi + ops->ooboffs, len); 3341 return oob + len; 3342 3343 case MTD_OPS_AUTO_OOB: 3344 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, 3345 ops->ooboffs, len); 3346 BUG_ON(ret); 3347 return oob + len; 3348 3349 default: 3350 BUG(); 3351 } 3352 return NULL; 3353} 3354 3355static void rawnand_enable_cont_reads(struct nand_chip *chip, unsigned int page, 3356 u32 readlen, int col) 3357{ 3358 struct mtd_info *mtd = nand_to_mtd(chip); 3359 unsigned int first_page, last_page; 3360 3361 chip->cont_read.ongoing = false; 3362 3363 if (!chip->controller->supported_op.cont_read) 3364 return; 3365 3366 /* 3367 * Don't bother making any calculations if the length is too small. 3368 * Side effect: avoids possible integer underflows below. 3369 */ 3370 if (readlen < (2 * mtd->writesize)) 3371 return; 3372 3373 /* Derive the page where continuous read should start (the first full page read) */ 3374 first_page = page; 3375 if (col) 3376 first_page++; 3377 3378 /* Derive the page where continuous read should stop (the last full page read) */ 3379 last_page = page + ((col + readlen) / mtd->writesize) - 1; 3380 3381 /* Configure and enable continuous read when suitable */ 3382 if (first_page < last_page) { 3383 chip->cont_read.first_page = first_page; 3384 chip->cont_read.last_page = last_page; 3385 chip->cont_read.ongoing = true; 3386 /* May reset the ongoing flag */ 3387 rawnand_cap_cont_reads(chip); 3388 } 3389} 3390 3391static void rawnand_cont_read_skip_first_page(struct nand_chip *chip, unsigned int page) 3392{ 3393 if (!chip->cont_read.ongoing || page != chip->cont_read.first_page) 3394 return; 3395 3396 chip->cont_read.first_page++; 3397 rawnand_cap_cont_reads(chip); 3398} 3399 3400/** 3401 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode 3402 * @chip: NAND chip object 3403 * @retry_mode: the retry mode to use 3404 * 3405 * Some vendors supply a special command to shift the Vt threshold, to be used 3406 * when there are too many bitflips in a page (i.e., ECC error). After setting 3407 * a new threshold, the host should retry reading the page. 3408 */ 3409static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode) 3410{ 3411 pr_debug("setting READ RETRY mode %d\n", retry_mode); 3412 3413 if (retry_mode >= chip->read_retries) 3414 return -EINVAL; 3415 3416 if (!chip->ops.setup_read_retry) 3417 return -EOPNOTSUPP; 3418 3419 return chip->ops.setup_read_retry(chip, retry_mode); 3420} 3421 3422static void nand_wait_readrdy(struct nand_chip *chip) 3423{ 3424 const struct nand_interface_config *conf; 3425 3426 if (!(chip->options & NAND_NEED_READRDY)) 3427 return; 3428 3429 conf = nand_get_interface_config(chip); 3430 WARN_ON(nand_wait_rdy_op(chip, NAND_COMMON_TIMING_MS(conf, tR_max), 0)); 3431} 3432 3433/** 3434 * nand_do_read_ops - [INTERN] Read data with ECC 3435 * @chip: NAND chip object 3436 * @from: offset to read from 3437 * @ops: oob ops structure 3438 * 3439 * Internal function. Called with chip held. 3440 */ 3441static int nand_do_read_ops(struct nand_chip *chip, loff_t from, 3442 struct mtd_oob_ops *ops) 3443{ 3444 int chipnr, page, realpage, col, bytes, aligned, oob_required; 3445 struct mtd_info *mtd = nand_to_mtd(chip); 3446 int ret = 0; 3447 uint32_t readlen = ops->len; 3448 uint32_t oobreadlen = ops->ooblen; 3449 uint32_t max_oobsize = mtd_oobavail(mtd, ops); 3450 3451 uint8_t *bufpoi, *oob, *buf; 3452 int use_bounce_buf; 3453 unsigned int max_bitflips = 0; 3454 int retry_mode = 0; 3455 bool ecc_fail = false; 3456 3457 /* Check if the region is secured */ 3458 if (nand_region_is_secured(chip, from, readlen)) 3459 return -EIO; 3460 3461 chipnr = (int)(from >> chip->chip_shift); 3462 nand_select_target(chip, chipnr); 3463 3464 realpage = (int)(from >> chip->page_shift); 3465 page = realpage & chip->pagemask; 3466 3467 col = (int)(from & (mtd->writesize - 1)); 3468 3469 buf = ops->datbuf; 3470 oob = ops->oobbuf; 3471 oob_required = oob ? 1 : 0; 3472 3473 if (likely(ops->mode != MTD_OPS_RAW)) 3474 rawnand_enable_cont_reads(chip, page, readlen, col); 3475 3476 while (1) { 3477 struct mtd_ecc_stats ecc_stats = mtd->ecc_stats; 3478 3479 bytes = min(mtd->writesize - col, readlen); 3480 aligned = (bytes == mtd->writesize); 3481 3482 if (!aligned) 3483 use_bounce_buf = 1; 3484 else if (chip->options & NAND_USES_DMA) 3485 use_bounce_buf = !virt_addr_valid(buf) || 3486 !IS_ALIGNED((unsigned long)buf, 3487 chip->buf_align); 3488 else 3489 use_bounce_buf = 0; 3490 3491 /* Is the current page in the buffer? */ 3492 if (realpage != chip->pagecache.page || oob) { 3493 bufpoi = use_bounce_buf ? chip->data_buf : buf; 3494 3495 if (use_bounce_buf && aligned) 3496 pr_debug("%s: using read bounce buffer for buf@%p\n", 3497 __func__, buf); 3498 3499read_retry: 3500 /* 3501 * Now read the page into the buffer. Absent an error, 3502 * the read methods return max bitflips per ecc step. 3503 */ 3504 if (unlikely(ops->mode == MTD_OPS_RAW)) 3505 ret = chip->ecc.read_page_raw(chip, bufpoi, 3506 oob_required, 3507 page); 3508 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && 3509 !oob) 3510 ret = chip->ecc.read_subpage(chip, col, bytes, 3511 bufpoi, page); 3512 else 3513 ret = chip->ecc.read_page(chip, bufpoi, 3514 oob_required, page); 3515 if (ret < 0) { 3516 if (use_bounce_buf) 3517 /* Invalidate page cache */ 3518 chip->pagecache.page = -1; 3519 break; 3520 } 3521 3522 /* 3523 * Copy back the data in the initial buffer when reading 3524 * partial pages or when a bounce buffer is required. 3525 */ 3526 if (use_bounce_buf) { 3527 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && 3528 !(mtd->ecc_stats.failed - ecc_stats.failed) && 3529 (ops->mode != MTD_OPS_RAW)) { 3530 chip->pagecache.page = realpage; 3531 chip->pagecache.bitflips = ret; 3532 } else { 3533 /* Invalidate page cache */ 3534 chip->pagecache.page = -1; 3535 } 3536 memcpy(buf, bufpoi + col, bytes); 3537 } 3538 3539 if (unlikely(oob)) { 3540 int toread = min(oobreadlen, max_oobsize); 3541 3542 if (toread) { 3543 oob = nand_transfer_oob(chip, oob, ops, 3544 toread); 3545 oobreadlen -= toread; 3546 } 3547 } 3548 3549 nand_wait_readrdy(chip); 3550 3551 if (mtd->ecc_stats.failed - ecc_stats.failed) { 3552 if (retry_mode + 1 < chip->read_retries) { 3553 retry_mode++; 3554 ret = nand_setup_read_retry(chip, 3555 retry_mode); 3556 if (ret < 0) 3557 break; 3558 3559 /* Reset ecc_stats; retry */ 3560 mtd->ecc_stats = ecc_stats; 3561 goto read_retry; 3562 } else { 3563 /* No more retry modes; real failure */ 3564 ecc_fail = true; 3565 } 3566 } 3567 3568 buf += bytes; 3569 max_bitflips = max_t(unsigned int, max_bitflips, ret); 3570 } else { 3571 memcpy(buf, chip->data_buf + col, bytes); 3572 buf += bytes; 3573 max_bitflips = max_t(unsigned int, max_bitflips, 3574 chip->pagecache.bitflips); 3575 3576 rawnand_cont_read_skip_first_page(chip, page); 3577 } 3578 3579 readlen -= bytes; 3580 3581 /* Reset to retry mode 0 */ 3582 if (retry_mode) { 3583 ret = nand_setup_read_retry(chip, 0); 3584 if (ret < 0) 3585 break; 3586 retry_mode = 0; 3587 } 3588 3589 if (!readlen) 3590 break; 3591 3592 /* For subsequent reads align to page boundary */ 3593 col = 0; 3594 /* Increment page address */ 3595 realpage++; 3596 3597 page = realpage & chip->pagemask; 3598 /* Check, if we cross a chip boundary */ 3599 if (!page) { 3600 chipnr++; 3601 nand_deselect_target(chip); 3602 nand_select_target(chip, chipnr); 3603 } 3604 } 3605 nand_deselect_target(chip); 3606 3607 if (WARN_ON_ONCE(chip->cont_read.ongoing)) 3608 chip->cont_read.ongoing = false; 3609 3610 ops->retlen = ops->len - (size_t) readlen; 3611 if (oob) 3612 ops->oobretlen = ops->ooblen - oobreadlen; 3613 3614 if (ret < 0) 3615 return ret; 3616 3617 if (ecc_fail) 3618 return -EBADMSG; 3619 3620 return max_bitflips; 3621} 3622 3623/** 3624 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function 3625 * @chip: nand chip info structure 3626 * @page: page number to read 3627 */ 3628int nand_read_oob_std(struct nand_chip *chip, int page) 3629{ 3630 struct mtd_info *mtd = nand_to_mtd(chip); 3631 3632 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 3633} 3634EXPORT_SYMBOL(nand_read_oob_std); 3635 3636/** 3637 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC 3638 * with syndromes 3639 * @chip: nand chip info structure 3640 * @page: page number to read 3641 */ 3642static int nand_read_oob_syndrome(struct nand_chip *chip, int page) 3643{ 3644 struct mtd_info *mtd = nand_to_mtd(chip); 3645 int length = mtd->oobsize; 3646 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 3647 int eccsize = chip->ecc.size; 3648 uint8_t *bufpoi = chip->oob_poi; 3649 int i, toread, sndrnd = 0, pos, ret; 3650 3651 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0); 3652 if (ret) 3653 return ret; 3654 3655 for (i = 0; i < chip->ecc.steps; i++) { 3656 if (sndrnd) { 3657 int ret; 3658 3659 pos = eccsize + i * (eccsize + chunk); 3660 if (mtd->writesize > 512) 3661 ret = nand_change_read_column_op(chip, pos, 3662 NULL, 0, 3663 false); 3664 else 3665 ret = nand_read_page_op(chip, page, pos, NULL, 3666 0); 3667 3668 if (ret) 3669 return ret; 3670 } else 3671 sndrnd = 1; 3672 toread = min_t(int, length, chunk); 3673 3674 ret = nand_read_data_op(chip, bufpoi, toread, false, false); 3675 if (ret) 3676 return ret; 3677 3678 bufpoi += toread; 3679 length -= toread; 3680 } 3681 if (length > 0) { 3682 ret = nand_read_data_op(chip, bufpoi, length, false, false); 3683 if (ret) 3684 return ret; 3685 } 3686 3687 return 0; 3688} 3689 3690/** 3691 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function 3692 * @chip: nand chip info structure 3693 * @page: page number to write 3694 */ 3695int nand_write_oob_std(struct nand_chip *chip, int page) 3696{ 3697 struct mtd_info *mtd = nand_to_mtd(chip); 3698 3699 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, 3700 mtd->oobsize); 3701} 3702EXPORT_SYMBOL(nand_write_oob_std); 3703 3704/** 3705 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC 3706 * with syndrome - only for large page flash 3707 * @chip: nand chip info structure 3708 * @page: page number to write 3709 */ 3710static int nand_write_oob_syndrome(struct nand_chip *chip, int page) 3711{ 3712 struct mtd_info *mtd = nand_to_mtd(chip); 3713 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 3714 int eccsize = chip->ecc.size, length = mtd->oobsize; 3715 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; 3716 const uint8_t *bufpoi = chip->oob_poi; 3717 3718 /* 3719 * data-ecc-data-ecc ... ecc-oob 3720 * or 3721 * data-pad-ecc-pad-data-pad .... ecc-pad-oob 3722 */ 3723 if (!chip->ecc.prepad && !chip->ecc.postpad) { 3724 pos = steps * (eccsize + chunk); 3725 steps = 0; 3726 } else 3727 pos = eccsize; 3728 3729 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0); 3730 if (ret) 3731 return ret; 3732 3733 for (i = 0; i < steps; i++) { 3734 if (sndcmd) { 3735 if (mtd->writesize <= 512) { 3736 uint32_t fill = 0xFFFFFFFF; 3737 3738 len = eccsize; 3739 while (len > 0) { 3740 int num = min_t(int, len, 4); 3741 3742 ret = nand_write_data_op(chip, &fill, 3743 num, false); 3744 if (ret) 3745 return ret; 3746 3747 len -= num; 3748 } 3749 } else { 3750 pos = eccsize + i * (eccsize + chunk); 3751 ret = nand_change_write_column_op(chip, pos, 3752 NULL, 0, 3753 false); 3754 if (ret) 3755 return ret; 3756 } 3757 } else 3758 sndcmd = 1; 3759 len = min_t(int, length, chunk); 3760 3761 ret = nand_write_data_op(chip, bufpoi, len, false); 3762 if (ret) 3763 return ret; 3764 3765 bufpoi += len; 3766 length -= len; 3767 } 3768 if (length > 0) { 3769 ret = nand_write_data_op(chip, bufpoi, length, false); 3770 if (ret) 3771 return ret; 3772 } 3773 3774 return nand_prog_page_end_op(chip); 3775} 3776 3777/** 3778 * nand_do_read_oob - [INTERN] NAND read out-of-band 3779 * @chip: NAND chip object 3780 * @from: offset to read from 3781 * @ops: oob operations description structure 3782 * 3783 * NAND read out-of-band data from the spare area. 3784 */ 3785static int nand_do_read_oob(struct nand_chip *chip, loff_t from, 3786 struct mtd_oob_ops *ops) 3787{ 3788 struct mtd_info *mtd = nand_to_mtd(chip); 3789 unsigned int max_bitflips = 0; 3790 int page, realpage, chipnr; 3791 struct mtd_ecc_stats stats; 3792 int readlen = ops->ooblen; 3793 int len; 3794 uint8_t *buf = ops->oobbuf; 3795 int ret = 0; 3796 3797 pr_debug("%s: from = 0x%08Lx, len = %i\n", 3798 __func__, (unsigned long long)from, readlen); 3799 3800 /* Check if the region is secured */ 3801 if (nand_region_is_secured(chip, from, readlen)) 3802 return -EIO; 3803 3804 stats = mtd->ecc_stats; 3805 3806 len = mtd_oobavail(mtd, ops); 3807 3808 chipnr = (int)(from >> chip->chip_shift); 3809 nand_select_target(chip, chipnr); 3810 3811 /* Shift to get page */ 3812 realpage = (int)(from >> chip->page_shift); 3813 page = realpage & chip->pagemask; 3814 3815 while (1) { 3816 if (ops->mode == MTD_OPS_RAW) 3817 ret = chip->ecc.read_oob_raw(chip, page); 3818 else 3819 ret = chip->ecc.read_oob(chip, page); 3820 3821 if (ret < 0) 3822 break; 3823 3824 len = min(len, readlen); 3825 buf = nand_transfer_oob(chip, buf, ops, len); 3826 3827 nand_wait_readrdy(chip); 3828 3829 max_bitflips = max_t(unsigned int, max_bitflips, ret); 3830 3831 readlen -= len; 3832 if (!readlen) 3833 break; 3834 3835 /* Increment page address */ 3836 realpage++; 3837 3838 page = realpage & chip->pagemask; 3839 /* Check, if we cross a chip boundary */ 3840 if (!page) { 3841 chipnr++; 3842 nand_deselect_target(chip); 3843 nand_select_target(chip, chipnr); 3844 } 3845 } 3846 nand_deselect_target(chip); 3847 3848 ops->oobretlen = ops->ooblen - readlen; 3849 3850 if (ret < 0) 3851 return ret; 3852 3853 if (mtd->ecc_stats.failed - stats.failed) 3854 return -EBADMSG; 3855 3856 return max_bitflips; 3857} 3858 3859/** 3860 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band 3861 * @mtd: MTD device structure 3862 * @from: offset to read from 3863 * @ops: oob operation description structure 3864 * 3865 * NAND read data and/or out-of-band data. 3866 */ 3867static int nand_read_oob(struct mtd_info *mtd, loff_t from, 3868 struct mtd_oob_ops *ops) 3869{ 3870 struct nand_chip *chip = mtd_to_nand(mtd); 3871 struct mtd_ecc_stats old_stats; 3872 int ret; 3873 3874 ops->retlen = 0; 3875 3876 if (ops->mode != MTD_OPS_PLACE_OOB && 3877 ops->mode != MTD_OPS_AUTO_OOB && 3878 ops->mode != MTD_OPS_RAW) 3879 return -ENOTSUPP; 3880 3881 nand_get_device(chip); 3882 3883 old_stats = mtd->ecc_stats; 3884 3885 if (!ops->datbuf) 3886 ret = nand_do_read_oob(chip, from, ops); 3887 else 3888 ret = nand_do_read_ops(chip, from, ops); 3889 3890 if (ops->stats) { 3891 ops->stats->uncorrectable_errors += 3892 mtd->ecc_stats.failed - old_stats.failed; 3893 ops->stats->corrected_bitflips += 3894 mtd->ecc_stats.corrected - old_stats.corrected; 3895 } 3896 3897 nand_release_device(chip); 3898 return ret; 3899} 3900 3901/** 3902 * nand_write_page_raw_notsupp - dummy raw page write function 3903 * @chip: nand chip info structure 3904 * @buf: data buffer 3905 * @oob_required: must write chip->oob_poi to OOB 3906 * @page: page number to write 3907 * 3908 * Returns -ENOTSUPP unconditionally. 3909 */ 3910int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf, 3911 int oob_required, int page) 3912{ 3913 return -ENOTSUPP; 3914} 3915 3916/** 3917 * nand_write_page_raw - [INTERN] raw page write function 3918 * @chip: nand chip info structure 3919 * @buf: data buffer 3920 * @oob_required: must write chip->oob_poi to OOB 3921 * @page: page number to write 3922 * 3923 * Not for syndrome calculating ECC controllers, which use a special oob layout. 3924 */ 3925int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 3926 int oob_required, int page) 3927{ 3928 struct mtd_info *mtd = nand_to_mtd(chip); 3929 int ret; 3930 3931 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); 3932 if (ret) 3933 return ret; 3934 3935 if (oob_required) { 3936 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, 3937 false); 3938 if (ret) 3939 return ret; 3940 } 3941 3942 return nand_prog_page_end_op(chip); 3943} 3944EXPORT_SYMBOL(nand_write_page_raw); 3945 3946/** 3947 * nand_monolithic_write_page_raw - Monolithic page write in raw mode 3948 * @chip: NAND chip info structure 3949 * @buf: data buffer to write 3950 * @oob_required: must write chip->oob_poi to OOB 3951 * @page: page number to write 3952 * 3953 * This is a raw page write, ie. without any error detection/correction. 3954 * Monolithic means we are requesting all the relevant data (main plus 3955 * eventually OOB) to be sent over the bus and effectively programmed 3956 * into the NAND chip arrays in a single operation. This is an 3957 * alternative to nand_write_page_raw(), which first sends the main 3958 * data, then eventually send the OOB data by latching more data 3959 * cycles on the NAND bus, and finally sends the program command to 3960 * synchronyze the NAND chip cache. 3961 */ 3962int nand_monolithic_write_page_raw(struct nand_chip *chip, const u8 *buf, 3963 int oob_required, int page) 3964{ 3965 struct mtd_info *mtd = nand_to_mtd(chip); 3966 unsigned int size = mtd->writesize; 3967 u8 *write_buf = (u8 *)buf; 3968 3969 if (oob_required) { 3970 size += mtd->oobsize; 3971 3972 if (buf != chip->data_buf) { 3973 write_buf = nand_get_data_buf(chip); 3974 memcpy(write_buf, buf, mtd->writesize); 3975 } 3976 } 3977 3978 return nand_prog_page_op(chip, page, 0, write_buf, size); 3979} 3980EXPORT_SYMBOL(nand_monolithic_write_page_raw); 3981 3982/** 3983 * nand_write_page_raw_syndrome - [INTERN] raw page write function 3984 * @chip: nand chip info structure 3985 * @buf: data buffer 3986 * @oob_required: must write chip->oob_poi to OOB 3987 * @page: page number to write 3988 * 3989 * We need a special oob layout and handling even when ECC isn't checked. 3990 */ 3991static int nand_write_page_raw_syndrome(struct nand_chip *chip, 3992 const uint8_t *buf, int oob_required, 3993 int page) 3994{ 3995 struct mtd_info *mtd = nand_to_mtd(chip); 3996 int eccsize = chip->ecc.size; 3997 int eccbytes = chip->ecc.bytes; 3998 uint8_t *oob = chip->oob_poi; 3999 int steps, size, ret; 4000 4001 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 4002 if (ret) 4003 return ret; 4004 4005 for (steps = chip->ecc.steps; steps > 0; steps--) { 4006 ret = nand_write_data_op(chip, buf, eccsize, false); 4007 if (ret) 4008 return ret; 4009 4010 buf += eccsize; 4011 4012 if (chip->ecc.prepad) { 4013 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, 4014 false); 4015 if (ret) 4016 return ret; 4017 4018 oob += chip->ecc.prepad; 4019 } 4020 4021 ret = nand_write_data_op(chip, oob, eccbytes, false); 4022 if (ret) 4023 return ret; 4024 4025 oob += eccbytes; 4026 4027 if (chip->ecc.postpad) { 4028 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, 4029 false); 4030 if (ret) 4031 return ret; 4032 4033 oob += chip->ecc.postpad; 4034 } 4035 } 4036 4037 size = mtd->oobsize - (oob - chip->oob_poi); 4038 if (size) { 4039 ret = nand_write_data_op(chip, oob, size, false); 4040 if (ret) 4041 return ret; 4042 } 4043 4044 return nand_prog_page_end_op(chip); 4045} 4046/** 4047 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function 4048 * @chip: nand chip info structure 4049 * @buf: data buffer 4050 * @oob_required: must write chip->oob_poi to OOB 4051 * @page: page number to write 4052 */ 4053static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf, 4054 int oob_required, int page) 4055{ 4056 struct mtd_info *mtd = nand_to_mtd(chip); 4057 int i, eccsize = chip->ecc.size, ret; 4058 int eccbytes = chip->ecc.bytes; 4059 int eccsteps = chip->ecc.steps; 4060 uint8_t *ecc_calc = chip->ecc.calc_buf; 4061 const uint8_t *p = buf; 4062 4063 /* Software ECC calculation */ 4064 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 4065 chip->ecc.calculate(chip, p, &ecc_calc[i]); 4066 4067 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 4068 chip->ecc.total); 4069 if (ret) 4070 return ret; 4071 4072 return chip->ecc.write_page_raw(chip, buf, 1, page); 4073} 4074 4075/** 4076 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function 4077 * @chip: nand chip info structure 4078 * @buf: data buffer 4079 * @oob_required: must write chip->oob_poi to OOB 4080 * @page: page number to write 4081 */ 4082static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf, 4083 int oob_required, int page) 4084{ 4085 struct mtd_info *mtd = nand_to_mtd(chip); 4086 int i, eccsize = chip->ecc.size, ret; 4087 int eccbytes = chip->ecc.bytes; 4088 int eccsteps = chip->ecc.steps; 4089 uint8_t *ecc_calc = chip->ecc.calc_buf; 4090 const uint8_t *p = buf; 4091 4092 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 4093 if (ret) 4094 return ret; 4095 4096 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 4097 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 4098 4099 ret = nand_write_data_op(chip, p, eccsize, false); 4100 if (ret) 4101 return ret; 4102 4103 chip->ecc.calculate(chip, p, &ecc_calc[i]); 4104 } 4105 4106 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 4107 chip->ecc.total); 4108 if (ret) 4109 return ret; 4110 4111 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 4112 if (ret) 4113 return ret; 4114 4115 return nand_prog_page_end_op(chip); 4116} 4117 4118 4119/** 4120 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write 4121 * @chip: nand chip info structure 4122 * @offset: column address of subpage within the page 4123 * @data_len: data length 4124 * @buf: data buffer 4125 * @oob_required: must write chip->oob_poi to OOB 4126 * @page: page number to write 4127 */ 4128static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset, 4129 uint32_t data_len, const uint8_t *buf, 4130 int oob_required, int page) 4131{ 4132 struct mtd_info *mtd = nand_to_mtd(chip); 4133 uint8_t *oob_buf = chip->oob_poi; 4134 uint8_t *ecc_calc = chip->ecc.calc_buf; 4135 int ecc_size = chip->ecc.size; 4136 int ecc_bytes = chip->ecc.bytes; 4137 int ecc_steps = chip->ecc.steps; 4138 uint32_t start_step = offset / ecc_size; 4139 uint32_t end_step = (offset + data_len - 1) / ecc_size; 4140 int oob_bytes = mtd->oobsize / ecc_steps; 4141 int step, ret; 4142 4143 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 4144 if (ret) 4145 return ret; 4146 4147 for (step = 0; step < ecc_steps; step++) { 4148 /* configure controller for WRITE access */ 4149 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 4150 4151 /* write data (untouched subpages already masked by 0xFF) */ 4152 ret = nand_write_data_op(chip, buf, ecc_size, false); 4153 if (ret) 4154 return ret; 4155 4156 /* mask ECC of un-touched subpages by padding 0xFF */ 4157 if ((step < start_step) || (step > end_step)) 4158 memset(ecc_calc, 0xff, ecc_bytes); 4159 else 4160 chip->ecc.calculate(chip, buf, ecc_calc); 4161 4162 /* mask OOB of un-touched subpages by padding 0xFF */ 4163 /* if oob_required, preserve OOB metadata of written subpage */ 4164 if (!oob_required || (step < start_step) || (step > end_step)) 4165 memset(oob_buf, 0xff, oob_bytes); 4166 4167 buf += ecc_size; 4168 ecc_calc += ecc_bytes; 4169 oob_buf += oob_bytes; 4170 } 4171 4172 /* copy calculated ECC for whole page to chip->buffer->oob */ 4173 /* this include masked-value(0xFF) for unwritten subpages */ 4174 ecc_calc = chip->ecc.calc_buf; 4175 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 4176 chip->ecc.total); 4177 if (ret) 4178 return ret; 4179 4180 /* write OOB buffer to NAND device */ 4181 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 4182 if (ret) 4183 return ret; 4184 4185 return nand_prog_page_end_op(chip); 4186} 4187 4188 4189/** 4190 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write 4191 * @chip: nand chip info structure 4192 * @buf: data buffer 4193 * @oob_required: must write chip->oob_poi to OOB 4194 * @page: page number to write 4195 * 4196 * The hw generator calculates the error syndrome automatically. Therefore we 4197 * need a special oob layout and handling. 4198 */ 4199static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf, 4200 int oob_required, int page) 4201{ 4202 struct mtd_info *mtd = nand_to_mtd(chip); 4203 int i, eccsize = chip->ecc.size; 4204 int eccbytes = chip->ecc.bytes; 4205 int eccsteps = chip->ecc.steps; 4206 const uint8_t *p = buf; 4207 uint8_t *oob = chip->oob_poi; 4208 int ret; 4209 4210 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 4211 if (ret) 4212 return ret; 4213 4214 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 4215 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 4216 4217 ret = nand_write_data_op(chip, p, eccsize, false); 4218 if (ret) 4219 return ret; 4220 4221 if (chip->ecc.prepad) { 4222 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, 4223 false); 4224 if (ret) 4225 return ret; 4226 4227 oob += chip->ecc.prepad; 4228 } 4229 4230 chip->ecc.calculate(chip, p, oob); 4231 4232 ret = nand_write_data_op(chip, oob, eccbytes, false); 4233 if (ret) 4234 return ret; 4235 4236 oob += eccbytes; 4237 4238 if (chip->ecc.postpad) { 4239 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, 4240 false); 4241 if (ret) 4242 return ret; 4243 4244 oob += chip->ecc.postpad; 4245 } 4246 } 4247 4248 /* Calculate remaining oob bytes */ 4249 i = mtd->oobsize - (oob - chip->oob_poi); 4250 if (i) { 4251 ret = nand_write_data_op(chip, oob, i, false); 4252 if (ret) 4253 return ret; 4254 } 4255 4256 return nand_prog_page_end_op(chip); 4257} 4258 4259/** 4260 * nand_write_page - write one page 4261 * @chip: NAND chip descriptor 4262 * @offset: address offset within the page 4263 * @data_len: length of actual data to be written 4264 * @buf: the data to write 4265 * @oob_required: must write chip->oob_poi to OOB 4266 * @page: page number to write 4267 * @raw: use _raw version of write_page 4268 */ 4269static int nand_write_page(struct nand_chip *chip, uint32_t offset, 4270 int data_len, const uint8_t *buf, int oob_required, 4271 int page, int raw) 4272{ 4273 struct mtd_info *mtd = nand_to_mtd(chip); 4274 int status, subpage; 4275 4276 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && 4277 chip->ecc.write_subpage) 4278 subpage = offset || (data_len < mtd->writesize); 4279 else 4280 subpage = 0; 4281 4282 if (unlikely(raw)) 4283 status = chip->ecc.write_page_raw(chip, buf, oob_required, 4284 page); 4285 else if (subpage) 4286 status = chip->ecc.write_subpage(chip, offset, data_len, buf, 4287 oob_required, page); 4288 else 4289 status = chip->ecc.write_page(chip, buf, oob_required, page); 4290 4291 if (status < 0) 4292 return status; 4293 4294 return 0; 4295} 4296 4297#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) 4298 4299/** 4300 * nand_do_write_ops - [INTERN] NAND write with ECC 4301 * @chip: NAND chip object 4302 * @to: offset to write to 4303 * @ops: oob operations description structure 4304 * 4305 * NAND write with ECC. 4306 */ 4307static int nand_do_write_ops(struct nand_chip *chip, loff_t to, 4308 struct mtd_oob_ops *ops) 4309{ 4310 struct mtd_info *mtd = nand_to_mtd(chip); 4311 int chipnr, realpage, page, column; 4312 uint32_t writelen = ops->len; 4313 4314 uint32_t oobwritelen = ops->ooblen; 4315 uint32_t oobmaxlen = mtd_oobavail(mtd, ops); 4316 4317 uint8_t *oob = ops->oobbuf; 4318 uint8_t *buf = ops->datbuf; 4319 int ret; 4320 int oob_required = oob ? 1 : 0; 4321 4322 ops->retlen = 0; 4323 if (!writelen) 4324 return 0; 4325 4326 /* Reject writes, which are not page aligned */ 4327 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { 4328 pr_notice("%s: attempt to write non page aligned data\n", 4329 __func__); 4330 return -EINVAL; 4331 } 4332 4333 /* Check if the region is secured */ 4334 if (nand_region_is_secured(chip, to, writelen)) 4335 return -EIO; 4336 4337 column = to & (mtd->writesize - 1); 4338 4339 chipnr = (int)(to >> chip->chip_shift); 4340 nand_select_target(chip, chipnr); 4341 4342 /* Check, if it is write protected */ 4343 if (nand_check_wp(chip)) { 4344 ret = -EIO; 4345 goto err_out; 4346 } 4347 4348 realpage = (int)(to >> chip->page_shift); 4349 page = realpage & chip->pagemask; 4350 4351 /* Invalidate the page cache, when we write to the cached page */ 4352 if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) && 4353 ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len)) 4354 chip->pagecache.page = -1; 4355 4356 /* Don't allow multipage oob writes with offset */ 4357 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { 4358 ret = -EINVAL; 4359 goto err_out; 4360 } 4361 4362 while (1) { 4363 int bytes = mtd->writesize; 4364 uint8_t *wbuf = buf; 4365 int use_bounce_buf; 4366 int part_pagewr = (column || writelen < mtd->writesize); 4367 4368 if (part_pagewr) 4369 use_bounce_buf = 1; 4370 else if (chip->options & NAND_USES_DMA) 4371 use_bounce_buf = !virt_addr_valid(buf) || 4372 !IS_ALIGNED((unsigned long)buf, 4373 chip->buf_align); 4374 else 4375 use_bounce_buf = 0; 4376 4377 /* 4378 * Copy the data from the initial buffer when doing partial page 4379 * writes or when a bounce buffer is required. 4380 */ 4381 if (use_bounce_buf) { 4382 pr_debug("%s: using write bounce buffer for buf@%p\n", 4383 __func__, buf); 4384 if (part_pagewr) 4385 bytes = min_t(int, bytes - column, writelen); 4386 wbuf = nand_get_data_buf(chip); 4387 memset(wbuf, 0xff, mtd->writesize); 4388 memcpy(&wbuf[column], buf, bytes); 4389 } 4390 4391 if (unlikely(oob)) { 4392 size_t len = min(oobwritelen, oobmaxlen); 4393 oob = nand_fill_oob(chip, oob, len, ops); 4394 oobwritelen -= len; 4395 } else { 4396 /* We still need to erase leftover OOB data */ 4397 memset(chip->oob_poi, 0xff, mtd->oobsize); 4398 } 4399 4400 ret = nand_write_page(chip, column, bytes, wbuf, 4401 oob_required, page, 4402 (ops->mode == MTD_OPS_RAW)); 4403 if (ret) 4404 break; 4405 4406 writelen -= bytes; 4407 if (!writelen) 4408 break; 4409 4410 column = 0; 4411 buf += bytes; 4412 realpage++; 4413 4414 page = realpage & chip->pagemask; 4415 /* Check, if we cross a chip boundary */ 4416 if (!page) { 4417 chipnr++; 4418 nand_deselect_target(chip); 4419 nand_select_target(chip, chipnr); 4420 } 4421 } 4422 4423 ops->retlen = ops->len - writelen; 4424 if (unlikely(oob)) 4425 ops->oobretlen = ops->ooblen; 4426 4427err_out: 4428 nand_deselect_target(chip); 4429 return ret; 4430} 4431 4432/** 4433 * panic_nand_write - [MTD Interface] NAND write with ECC 4434 * @mtd: MTD device structure 4435 * @to: offset to write to 4436 * @len: number of bytes to write 4437 * @retlen: pointer to variable to store the number of written bytes 4438 * @buf: the data to write 4439 * 4440 * NAND write with ECC. Used when performing writes in interrupt context, this 4441 * may for example be called by mtdoops when writing an oops while in panic. 4442 */ 4443static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, 4444 size_t *retlen, const uint8_t *buf) 4445{ 4446 struct nand_chip *chip = mtd_to_nand(mtd); 4447 int chipnr = (int)(to >> chip->chip_shift); 4448 struct mtd_oob_ops ops; 4449 int ret; 4450 4451 nand_select_target(chip, chipnr); 4452 4453 /* Wait for the device to get ready */ 4454 panic_nand_wait(chip, 400); 4455 4456 memset(&ops, 0, sizeof(ops)); 4457 ops.len = len; 4458 ops.datbuf = (uint8_t *)buf; 4459 ops.mode = MTD_OPS_PLACE_OOB; 4460 4461 ret = nand_do_write_ops(chip, to, &ops); 4462 4463 *retlen = ops.retlen; 4464 return ret; 4465} 4466 4467/** 4468 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band 4469 * @mtd: MTD device structure 4470 * @to: offset to write to 4471 * @ops: oob operation description structure 4472 */ 4473static int nand_write_oob(struct mtd_info *mtd, loff_t to, 4474 struct mtd_oob_ops *ops) 4475{ 4476 struct nand_chip *chip = mtd_to_nand(mtd); 4477 int ret = 0; 4478 4479 ops->retlen = 0; 4480 4481 nand_get_device(chip); 4482 4483 switch (ops->mode) { 4484 case MTD_OPS_PLACE_OOB: 4485 case MTD_OPS_AUTO_OOB: 4486 case MTD_OPS_RAW: 4487 break; 4488 4489 default: 4490 goto out; 4491 } 4492 4493 if (!ops->datbuf) 4494 ret = nand_do_write_oob(chip, to, ops); 4495 else 4496 ret = nand_do_write_ops(chip, to, ops); 4497 4498out: 4499 nand_release_device(chip); 4500 return ret; 4501} 4502 4503/** 4504 * nand_erase - [MTD Interface] erase block(s) 4505 * @mtd: MTD device structure 4506 * @instr: erase instruction 4507 * 4508 * Erase one ore more blocks. 4509 */ 4510static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) 4511{ 4512 return nand_erase_nand(mtd_to_nand(mtd), instr, 0); 4513} 4514 4515/** 4516 * nand_erase_nand - [INTERN] erase block(s) 4517 * @chip: NAND chip object 4518 * @instr: erase instruction 4519 * @allowbbt: allow erasing the bbt area 4520 * 4521 * Erase one ore more blocks. 4522 */ 4523int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr, 4524 int allowbbt) 4525{ 4526 int page, pages_per_block, ret, chipnr; 4527 loff_t len; 4528 4529 pr_debug("%s: start = 0x%012llx, len = %llu\n", 4530 __func__, (unsigned long long)instr->addr, 4531 (unsigned long long)instr->len); 4532 4533 if (check_offs_len(chip, instr->addr, instr->len)) 4534 return -EINVAL; 4535 4536 /* Check if the region is secured */ 4537 if (nand_region_is_secured(chip, instr->addr, instr->len)) 4538 return -EIO; 4539 4540 /* Grab the lock and see if the device is available */ 4541 nand_get_device(chip); 4542 4543 /* Shift to get first page */ 4544 page = (int)(instr->addr >> chip->page_shift); 4545 chipnr = (int)(instr->addr >> chip->chip_shift); 4546 4547 /* Calculate pages in each block */ 4548 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 4549 4550 /* Select the NAND device */ 4551 nand_select_target(chip, chipnr); 4552 4553 /* Check, if it is write protected */ 4554 if (nand_check_wp(chip)) { 4555 pr_debug("%s: device is write protected!\n", 4556 __func__); 4557 ret = -EIO; 4558 goto erase_exit; 4559 } 4560 4561 /* Loop through the pages */ 4562 len = instr->len; 4563 4564 while (len) { 4565 loff_t ofs = (loff_t)page << chip->page_shift; 4566 4567 /* Check if we have a bad block, we do not erase bad blocks! */ 4568 if (nand_block_checkbad(chip, ((loff_t) page) << 4569 chip->page_shift, allowbbt)) { 4570 pr_warn("%s: attempt to erase a bad block at 0x%08llx\n", 4571 __func__, (unsigned long long)ofs); 4572 ret = -EIO; 4573 goto erase_exit; 4574 } 4575 4576 /* 4577 * Invalidate the page cache, if we erase the block which 4578 * contains the current cached page. 4579 */ 4580 if (page <= chip->pagecache.page && chip->pagecache.page < 4581 (page + pages_per_block)) 4582 chip->pagecache.page = -1; 4583 4584 ret = nand_erase_op(chip, (page & chip->pagemask) >> 4585 (chip->phys_erase_shift - chip->page_shift)); 4586 if (ret) { 4587 pr_debug("%s: failed erase, page 0x%08x\n", 4588 __func__, page); 4589 instr->fail_addr = ofs; 4590 goto erase_exit; 4591 } 4592 4593 /* Increment page address and decrement length */ 4594 len -= (1ULL << chip->phys_erase_shift); 4595 page += pages_per_block; 4596 4597 /* Check, if we cross a chip boundary */ 4598 if (len && !(page & chip->pagemask)) { 4599 chipnr++; 4600 nand_deselect_target(chip); 4601 nand_select_target(chip, chipnr); 4602 } 4603 } 4604 4605 ret = 0; 4606erase_exit: 4607 4608 /* Deselect and wake up anyone waiting on the device */ 4609 nand_deselect_target(chip); 4610 nand_release_device(chip); 4611 4612 /* Return more or less happy */ 4613 return ret; 4614} 4615 4616/** 4617 * nand_sync - [MTD Interface] sync 4618 * @mtd: MTD device structure 4619 * 4620 * Sync is actually a wait for chip ready function. 4621 */ 4622static void nand_sync(struct mtd_info *mtd) 4623{ 4624 struct nand_chip *chip = mtd_to_nand(mtd); 4625 4626 pr_debug("%s: called\n", __func__); 4627 4628 /* Grab the lock and see if the device is available */ 4629 nand_get_device(chip); 4630 /* Release it and go back */ 4631 nand_release_device(chip); 4632} 4633 4634/** 4635 * nand_block_isbad - [MTD Interface] Check if block at offset is bad 4636 * @mtd: MTD device structure 4637 * @offs: offset relative to mtd start 4638 */ 4639static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 4640{ 4641 struct nand_chip *chip = mtd_to_nand(mtd); 4642 int chipnr = (int)(offs >> chip->chip_shift); 4643 int ret; 4644 4645 /* Select the NAND device */ 4646 nand_get_device(chip); 4647 4648 nand_select_target(chip, chipnr); 4649 4650 ret = nand_block_checkbad(chip, offs, 0); 4651 4652 nand_deselect_target(chip); 4653 nand_release_device(chip); 4654 4655 return ret; 4656} 4657 4658/** 4659 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad 4660 * @mtd: MTD device structure 4661 * @ofs: offset relative to mtd start 4662 */ 4663static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) 4664{ 4665 int ret; 4666 4667 ret = nand_block_isbad(mtd, ofs); 4668 if (ret) { 4669 /* If it was bad already, return success and do nothing */ 4670 if (ret > 0) 4671 return 0; 4672 return ret; 4673 } 4674 4675 return nand_block_markbad_lowlevel(mtd_to_nand(mtd), ofs); 4676} 4677 4678/** 4679 * nand_suspend - [MTD Interface] Suspend the NAND flash 4680 * @mtd: MTD device structure 4681 * 4682 * Returns 0 for success or negative error code otherwise. 4683 */ 4684static int nand_suspend(struct mtd_info *mtd) 4685{ 4686 struct nand_chip *chip = mtd_to_nand(mtd); 4687 int ret = 0; 4688 4689 mutex_lock(&chip->lock); 4690 if (chip->ops.suspend) 4691 ret = chip->ops.suspend(chip); 4692 if (!ret) 4693 chip->suspended = 1; 4694 mutex_unlock(&chip->lock); 4695 4696 return ret; 4697} 4698 4699/** 4700 * nand_resume - [MTD Interface] Resume the NAND flash 4701 * @mtd: MTD device structure 4702 */ 4703static void nand_resume(struct mtd_info *mtd) 4704{ 4705 struct nand_chip *chip = mtd_to_nand(mtd); 4706 4707 mutex_lock(&chip->lock); 4708 if (chip->suspended) { 4709 if (chip->ops.resume) 4710 chip->ops.resume(chip); 4711 chip->suspended = 0; 4712 } else { 4713 pr_err("%s called for a chip which is not in suspended state\n", 4714 __func__); 4715 } 4716 mutex_unlock(&chip->lock); 4717 4718 wake_up_all(&chip->resume_wq); 4719} 4720 4721/** 4722 * nand_shutdown - [MTD Interface] Finish the current NAND operation and 4723 * prevent further operations 4724 * @mtd: MTD device structure 4725 */ 4726static void nand_shutdown(struct mtd_info *mtd) 4727{ 4728 nand_suspend(mtd); 4729} 4730 4731/** 4732 * nand_lock - [MTD Interface] Lock the NAND flash 4733 * @mtd: MTD device structure 4734 * @ofs: offset byte address 4735 * @len: number of bytes to lock (must be a multiple of block/page size) 4736 */ 4737static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 4738{ 4739 struct nand_chip *chip = mtd_to_nand(mtd); 4740 int ret; 4741 4742 if (!chip->ops.lock_area) 4743 return -ENOTSUPP; 4744 4745 nand_get_device(chip); 4746 ret = chip->ops.lock_area(chip, ofs, len); 4747 nand_release_device(chip); 4748 4749 return ret; 4750} 4751 4752/** 4753 * nand_unlock - [MTD Interface] Unlock the NAND flash 4754 * @mtd: MTD device structure 4755 * @ofs: offset byte address 4756 * @len: number of bytes to unlock (must be a multiple of block/page size) 4757 */ 4758static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 4759{ 4760 struct nand_chip *chip = mtd_to_nand(mtd); 4761 int ret; 4762 4763 if (!chip->ops.unlock_area) 4764 return -ENOTSUPP; 4765 4766 nand_get_device(chip); 4767 ret = chip->ops.unlock_area(chip, ofs, len); 4768 nand_release_device(chip); 4769 4770 return ret; 4771} 4772 4773/* Set default functions */ 4774static void nand_set_defaults(struct nand_chip *chip) 4775{ 4776 /* If no controller is provided, use the dummy, legacy one. */ 4777 if (!chip->controller) { 4778 chip->controller = &chip->legacy.dummy_controller; 4779 nand_controller_init(chip->controller); 4780 } 4781 4782 nand_legacy_set_defaults(chip); 4783 4784 if (!chip->buf_align) 4785 chip->buf_align = 1; 4786} 4787 4788/* Sanitize ONFI strings so we can safely print them */ 4789void sanitize_string(uint8_t *s, size_t len) 4790{ 4791 ssize_t i; 4792 4793 /* Null terminate */ 4794 s[len - 1] = 0; 4795 4796 /* Remove non printable chars */ 4797 for (i = 0; i < len - 1; i++) { 4798 if (s[i] < ' ' || s[i] > 127) 4799 s[i] = '?'; 4800 } 4801 4802 /* Remove trailing spaces */ 4803 strim(s); 4804} 4805 4806/* 4807 * nand_id_has_period - Check if an ID string has a given wraparound period 4808 * @id_data: the ID string 4809 * @arrlen: the length of the @id_data array 4810 * @period: the period of repitition 4811 * 4812 * Check if an ID string is repeated within a given sequence of bytes at 4813 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a 4814 * period of 3). This is a helper function for nand_id_len(). Returns non-zero 4815 * if the repetition has a period of @period; otherwise, returns zero. 4816 */ 4817static int nand_id_has_period(u8 *id_data, int arrlen, int period) 4818{ 4819 int i, j; 4820 for (i = 0; i < period; i++) 4821 for (j = i + period; j < arrlen; j += period) 4822 if (id_data[i] != id_data[j]) 4823 return 0; 4824 return 1; 4825} 4826 4827/* 4828 * nand_id_len - Get the length of an ID string returned by CMD_READID 4829 * @id_data: the ID string 4830 * @arrlen: the length of the @id_data array 4831 4832 * Returns the length of the ID string, according to known wraparound/trailing 4833 * zero patterns. If no pattern exists, returns the length of the array. 4834 */ 4835static int nand_id_len(u8 *id_data, int arrlen) 4836{ 4837 int last_nonzero, period; 4838 4839 /* Find last non-zero byte */ 4840 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) 4841 if (id_data[last_nonzero]) 4842 break; 4843 4844 /* All zeros */ 4845 if (last_nonzero < 0) 4846 return 0; 4847 4848 /* Calculate wraparound period */ 4849 for (period = 1; period < arrlen; period++) 4850 if (nand_id_has_period(id_data, arrlen, period)) 4851 break; 4852 4853 /* There's a repeated pattern */ 4854 if (period < arrlen) 4855 return period; 4856 4857 /* There are trailing zeros */ 4858 if (last_nonzero < arrlen - 1) 4859 return last_nonzero + 1; 4860 4861 /* No pattern detected */ 4862 return arrlen; 4863} 4864 4865/* Extract the bits of per cell from the 3rd byte of the extended ID */ 4866static int nand_get_bits_per_cell(u8 cellinfo) 4867{ 4868 int bits; 4869 4870 bits = cellinfo & NAND_CI_CELLTYPE_MSK; 4871 bits >>= NAND_CI_CELLTYPE_SHIFT; 4872 return bits + 1; 4873} 4874 4875/* 4876 * Many new NAND share similar device ID codes, which represent the size of the 4877 * chip. The rest of the parameters must be decoded according to generic or 4878 * manufacturer-specific "extended ID" decoding patterns. 4879 */ 4880void nand_decode_ext_id(struct nand_chip *chip) 4881{ 4882 struct nand_memory_organization *memorg; 4883 struct mtd_info *mtd = nand_to_mtd(chip); 4884 int extid; 4885 u8 *id_data = chip->id.data; 4886 4887 memorg = nanddev_get_memorg(&chip->base); 4888 4889 /* The 3rd id byte holds MLC / multichip data */ 4890 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 4891 /* The 4th id byte is the important one */ 4892 extid = id_data[3]; 4893 4894 /* Calc pagesize */ 4895 memorg->pagesize = 1024 << (extid & 0x03); 4896 mtd->writesize = memorg->pagesize; 4897 extid >>= 2; 4898 /* Calc oobsize */ 4899 memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); 4900 mtd->oobsize = memorg->oobsize; 4901 extid >>= 2; 4902 /* Calc blocksize. Blocksize is multiples of 64KiB */ 4903 memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) / 4904 memorg->pagesize; 4905 mtd->erasesize = (64 * 1024) << (extid & 0x03); 4906 extid >>= 2; 4907 /* Get buswidth information */ 4908 if (extid & 0x1) 4909 chip->options |= NAND_BUSWIDTH_16; 4910} 4911EXPORT_SYMBOL_GPL(nand_decode_ext_id); 4912 4913/* 4914 * Old devices have chip data hardcoded in the device ID table. nand_decode_id 4915 * decodes a matching ID table entry and assigns the MTD size parameters for 4916 * the chip. 4917 */ 4918static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) 4919{ 4920 struct mtd_info *mtd = nand_to_mtd(chip); 4921 struct nand_memory_organization *memorg; 4922 4923 memorg = nanddev_get_memorg(&chip->base); 4924 4925 memorg->pages_per_eraseblock = type->erasesize / type->pagesize; 4926 mtd->erasesize = type->erasesize; 4927 memorg->pagesize = type->pagesize; 4928 mtd->writesize = memorg->pagesize; 4929 memorg->oobsize = memorg->pagesize / 32; 4930 mtd->oobsize = memorg->oobsize; 4931 4932 /* All legacy ID NAND are small-page, SLC */ 4933 memorg->bits_per_cell = 1; 4934} 4935 4936/* 4937 * Set the bad block marker/indicator (BBM/BBI) patterns according to some 4938 * heuristic patterns using various detected parameters (e.g., manufacturer, 4939 * page size, cell-type information). 4940 */ 4941static void nand_decode_bbm_options(struct nand_chip *chip) 4942{ 4943 struct mtd_info *mtd = nand_to_mtd(chip); 4944 4945 /* Set the bad block position */ 4946 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) 4947 chip->badblockpos = NAND_BBM_POS_LARGE; 4948 else 4949 chip->badblockpos = NAND_BBM_POS_SMALL; 4950} 4951 4952static inline bool is_full_id_nand(struct nand_flash_dev *type) 4953{ 4954 return type->id_len; 4955} 4956 4957static bool find_full_id_nand(struct nand_chip *chip, 4958 struct nand_flash_dev *type) 4959{ 4960 struct nand_device *base = &chip->base; 4961 struct nand_ecc_props requirements; 4962 struct mtd_info *mtd = nand_to_mtd(chip); 4963 struct nand_memory_organization *memorg; 4964 u8 *id_data = chip->id.data; 4965 4966 memorg = nanddev_get_memorg(&chip->base); 4967 4968 if (!strncmp(type->id, id_data, type->id_len)) { 4969 memorg->pagesize = type->pagesize; 4970 mtd->writesize = memorg->pagesize; 4971 memorg->pages_per_eraseblock = type->erasesize / 4972 type->pagesize; 4973 mtd->erasesize = type->erasesize; 4974 memorg->oobsize = type->oobsize; 4975 mtd->oobsize = memorg->oobsize; 4976 4977 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 4978 memorg->eraseblocks_per_lun = 4979 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, 4980 memorg->pagesize * 4981 memorg->pages_per_eraseblock); 4982 chip->options |= type->options; 4983 requirements.strength = NAND_ECC_STRENGTH(type); 4984 requirements.step_size = NAND_ECC_STEP(type); 4985 nanddev_set_ecc_requirements(base, &requirements); 4986 4987 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); 4988 if (!chip->parameters.model) 4989 return false; 4990 4991 return true; 4992 } 4993 return false; 4994} 4995 4996/* 4997 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC 4998 * compliant and does not have a full-id or legacy-id entry in the nand_ids 4999 * table. 5000 */ 5001static void nand_manufacturer_detect(struct nand_chip *chip) 5002{ 5003 /* 5004 * Try manufacturer detection if available and use 5005 * nand_decode_ext_id() otherwise. 5006 */ 5007 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && 5008 chip->manufacturer.desc->ops->detect) { 5009 struct nand_memory_organization *memorg; 5010 5011 memorg = nanddev_get_memorg(&chip->base); 5012 5013 /* The 3rd id byte holds MLC / multichip data */ 5014 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); 5015 chip->manufacturer.desc->ops->detect(chip); 5016 } else { 5017 nand_decode_ext_id(chip); 5018 } 5019} 5020 5021/* 5022 * Manufacturer initialization. This function is called for all NANDs including 5023 * ONFI and JEDEC compliant ones. 5024 * Manufacturer drivers should put all their specific initialization code in 5025 * their ->init() hook. 5026 */ 5027static int nand_manufacturer_init(struct nand_chip *chip) 5028{ 5029 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || 5030 !chip->manufacturer.desc->ops->init) 5031 return 0; 5032 5033 return chip->manufacturer.desc->ops->init(chip); 5034} 5035 5036/* 5037 * Manufacturer cleanup. This function is called for all NANDs including 5038 * ONFI and JEDEC compliant ones. 5039 * Manufacturer drivers should put all their specific cleanup code in their 5040 * ->cleanup() hook. 5041 */ 5042static void nand_manufacturer_cleanup(struct nand_chip *chip) 5043{ 5044 /* Release manufacturer private data */ 5045 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && 5046 chip->manufacturer.desc->ops->cleanup) 5047 chip->manufacturer.desc->ops->cleanup(chip); 5048} 5049 5050static const char * 5051nand_manufacturer_name(const struct nand_manufacturer_desc *manufacturer_desc) 5052{ 5053 return manufacturer_desc ? manufacturer_desc->name : "Unknown"; 5054} 5055 5056static void rawnand_check_data_only_read_support(struct nand_chip *chip) 5057{ 5058 /* Use an arbitrary size for the check */ 5059 if (!nand_read_data_op(chip, NULL, SZ_512, true, true)) 5060 chip->controller->supported_op.data_only_read = 1; 5061} 5062 5063static void rawnand_early_check_supported_ops(struct nand_chip *chip) 5064{ 5065 /* The supported_op fields should not be set by individual drivers */ 5066 WARN_ON_ONCE(chip->controller->supported_op.data_only_read); 5067 5068 if (!nand_has_exec_op(chip)) 5069 return; 5070 5071 rawnand_check_data_only_read_support(chip); 5072} 5073 5074static void rawnand_check_cont_read_support(struct nand_chip *chip) 5075{ 5076 struct mtd_info *mtd = nand_to_mtd(chip); 5077 5078 if (!chip->parameters.supports_read_cache) 5079 return; 5080 5081 if (chip->read_retries) 5082 return; 5083 5084 if (!nand_lp_exec_cont_read_page_op(chip, 0, 0, NULL, 5085 mtd->writesize, true)) 5086 chip->controller->supported_op.cont_read = 1; 5087} 5088 5089static void rawnand_late_check_supported_ops(struct nand_chip *chip) 5090{ 5091 /* The supported_op fields should not be set by individual drivers */ 5092 WARN_ON_ONCE(chip->controller->supported_op.cont_read); 5093 5094 /* 5095 * Too many devices do not support sequential cached reads with on-die 5096 * ECC correction enabled, so in this case refuse to perform the 5097 * automation. 5098 */ 5099 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE) 5100 return; 5101 5102 if (!nand_has_exec_op(chip)) 5103 return; 5104 5105 /* 5106 * For now, continuous reads can only be used with the core page helpers. 5107 * This can be extended later. 5108 */ 5109 if (!(chip->ecc.read_page == nand_read_page_hwecc || 5110 chip->ecc.read_page == nand_read_page_syndrome || 5111 chip->ecc.read_page == nand_read_page_swecc)) 5112 return; 5113 5114 rawnand_check_cont_read_support(chip); 5115} 5116 5117/* 5118 * Get the flash and manufacturer id and lookup if the type is supported. 5119 */ 5120static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) 5121{ 5122 const struct nand_manufacturer_desc *manufacturer_desc; 5123 struct mtd_info *mtd = nand_to_mtd(chip); 5124 struct nand_memory_organization *memorg; 5125 int busw, ret; 5126 u8 *id_data = chip->id.data; 5127 u8 maf_id, dev_id; 5128 u64 targetsize; 5129 5130 /* 5131 * Let's start by initializing memorg fields that might be left 5132 * unassigned by the ID-based detection logic. 5133 */ 5134 memorg = nanddev_get_memorg(&chip->base); 5135 memorg->planes_per_lun = 1; 5136 memorg->luns_per_target = 1; 5137 5138 /* 5139 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 5140 * after power-up. 5141 */ 5142 ret = nand_reset(chip, 0); 5143 if (ret) 5144 return ret; 5145 5146 /* Select the device */ 5147 nand_select_target(chip, 0); 5148 5149 rawnand_early_check_supported_ops(chip); 5150 5151 /* Send the command for reading device ID */ 5152 ret = nand_readid_op(chip, 0, id_data, 2); 5153 if (ret) 5154 return ret; 5155 5156 /* Read manufacturer and device IDs */ 5157 maf_id = id_data[0]; 5158 dev_id = id_data[1]; 5159 5160 /* 5161 * Try again to make sure, as some systems the bus-hold or other 5162 * interface concerns can cause random data which looks like a 5163 * possibly credible NAND flash to appear. If the two results do 5164 * not match, ignore the device completely. 5165 */ 5166 5167 /* Read entire ID string */ 5168 ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data)); 5169 if (ret) 5170 return ret; 5171 5172 if (id_data[0] != maf_id || id_data[1] != dev_id) { 5173 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", 5174 maf_id, dev_id, id_data[0], id_data[1]); 5175 return -ENODEV; 5176 } 5177 5178 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); 5179 5180 /* Try to identify manufacturer */ 5181 manufacturer_desc = nand_get_manufacturer_desc(maf_id); 5182 chip->manufacturer.desc = manufacturer_desc; 5183 5184 if (!type) 5185 type = nand_flash_ids; 5186 5187 /* 5188 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic 5189 * override it. 5190 * This is required to make sure initial NAND bus width set by the 5191 * NAND controller driver is coherent with the real NAND bus width 5192 * (extracted by auto-detection code). 5193 */ 5194 busw = chip->options & NAND_BUSWIDTH_16; 5195 5196 /* 5197 * The flag is only set (never cleared), reset it to its default value 5198 * before starting auto-detection. 5199 */ 5200 chip->options &= ~NAND_BUSWIDTH_16; 5201 5202 for (; type->name != NULL; type++) { 5203 if (is_full_id_nand(type)) { 5204 if (find_full_id_nand(chip, type)) 5205 goto ident_done; 5206 } else if (dev_id == type->dev_id) { 5207 break; 5208 } 5209 } 5210 5211 if (!type->name || !type->pagesize) { 5212 /* Check if the chip is ONFI compliant */ 5213 ret = nand_onfi_detect(chip); 5214 if (ret < 0) 5215 return ret; 5216 else if (ret) 5217 goto ident_done; 5218 5219 /* Check if the chip is JEDEC compliant */ 5220 ret = nand_jedec_detect(chip); 5221 if (ret < 0) 5222 return ret; 5223 else if (ret) 5224 goto ident_done; 5225 } 5226 5227 if (!type->name) 5228 return -ENODEV; 5229 5230 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); 5231 if (!chip->parameters.model) 5232 return -ENOMEM; 5233 5234 if (!type->pagesize) 5235 nand_manufacturer_detect(chip); 5236 else 5237 nand_decode_id(chip, type); 5238 5239 /* Get chip options */ 5240 chip->options |= type->options; 5241 5242 memorg->eraseblocks_per_lun = 5243 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, 5244 memorg->pagesize * 5245 memorg->pages_per_eraseblock); 5246 5247ident_done: 5248 if (!mtd->name) 5249 mtd->name = chip->parameters.model; 5250 5251 if (chip->options & NAND_BUSWIDTH_AUTO) { 5252 WARN_ON(busw & NAND_BUSWIDTH_16); 5253 nand_set_defaults(chip); 5254 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { 5255 /* 5256 * Check, if buswidth is correct. Hardware drivers should set 5257 * chip correct! 5258 */ 5259 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 5260 maf_id, dev_id); 5261 pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc), 5262 mtd->name); 5263 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8, 5264 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); 5265 ret = -EINVAL; 5266 5267 goto free_detect_allocation; 5268 } 5269 5270 nand_decode_bbm_options(chip); 5271 5272 /* Calculate the address shift from the page size */ 5273 chip->page_shift = ffs(mtd->writesize) - 1; 5274 /* Convert chipsize to number of pages per chip -1 */ 5275 targetsize = nanddev_target_size(&chip->base); 5276 chip->pagemask = (targetsize >> chip->page_shift) - 1; 5277 5278 chip->bbt_erase_shift = chip->phys_erase_shift = 5279 ffs(mtd->erasesize) - 1; 5280 if (targetsize & 0xffffffff) 5281 chip->chip_shift = ffs((unsigned)targetsize) - 1; 5282 else { 5283 chip->chip_shift = ffs((unsigned)(targetsize >> 32)); 5284 chip->chip_shift += 32 - 1; 5285 } 5286 5287 if (chip->chip_shift - chip->page_shift > 16) 5288 chip->options |= NAND_ROW_ADDR_3; 5289 5290 chip->badblockbits = 8; 5291 5292 nand_legacy_adjust_cmdfunc(chip); 5293 5294 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 5295 maf_id, dev_id); 5296 pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc), 5297 chip->parameters.model); 5298 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", 5299 (int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", 5300 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); 5301 return 0; 5302 5303free_detect_allocation: 5304 kfree(chip->parameters.model); 5305 5306 return ret; 5307} 5308 5309static enum nand_ecc_engine_type 5310of_get_rawnand_ecc_engine_type_legacy(struct device_node *np) 5311{ 5312 enum nand_ecc_legacy_mode { 5313 NAND_ECC_INVALID, 5314 NAND_ECC_NONE, 5315 NAND_ECC_SOFT, 5316 NAND_ECC_SOFT_BCH, 5317 NAND_ECC_HW, 5318 NAND_ECC_HW_SYNDROME, 5319 NAND_ECC_ON_DIE, 5320 }; 5321 const char * const nand_ecc_legacy_modes[] = { 5322 [NAND_ECC_NONE] = "none", 5323 [NAND_ECC_SOFT] = "soft", 5324 [NAND_ECC_SOFT_BCH] = "soft_bch", 5325 [NAND_ECC_HW] = "hw", 5326 [NAND_ECC_HW_SYNDROME] = "hw_syndrome", 5327 [NAND_ECC_ON_DIE] = "on-die", 5328 }; 5329 enum nand_ecc_legacy_mode eng_type; 5330 const char *pm; 5331 int err; 5332 5333 err = of_property_read_string(np, "nand-ecc-mode", &pm); 5334 if (err) 5335 return NAND_ECC_ENGINE_TYPE_INVALID; 5336 5337 for (eng_type = NAND_ECC_NONE; 5338 eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) { 5339 if (!strcasecmp(pm, nand_ecc_legacy_modes[eng_type])) { 5340 switch (eng_type) { 5341 case NAND_ECC_NONE: 5342 return NAND_ECC_ENGINE_TYPE_NONE; 5343 case NAND_ECC_SOFT: 5344 case NAND_ECC_SOFT_BCH: 5345 return NAND_ECC_ENGINE_TYPE_SOFT; 5346 case NAND_ECC_HW: 5347 case NAND_ECC_HW_SYNDROME: 5348 return NAND_ECC_ENGINE_TYPE_ON_HOST; 5349 case NAND_ECC_ON_DIE: 5350 return NAND_ECC_ENGINE_TYPE_ON_DIE; 5351 default: 5352 break; 5353 } 5354 } 5355 } 5356 5357 return NAND_ECC_ENGINE_TYPE_INVALID; 5358} 5359 5360static enum nand_ecc_placement 5361of_get_rawnand_ecc_placement_legacy(struct device_node *np) 5362{ 5363 const char *pm; 5364 int err; 5365 5366 err = of_property_read_string(np, "nand-ecc-mode", &pm); 5367 if (!err) { 5368 if (!strcasecmp(pm, "hw_syndrome")) 5369 return NAND_ECC_PLACEMENT_INTERLEAVED; 5370 } 5371 5372 return NAND_ECC_PLACEMENT_UNKNOWN; 5373} 5374 5375static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np) 5376{ 5377 const char *pm; 5378 int err; 5379 5380 err = of_property_read_string(np, "nand-ecc-mode", &pm); 5381 if (!err) { 5382 if (!strcasecmp(pm, "soft")) 5383 return NAND_ECC_ALGO_HAMMING; 5384 else if (!strcasecmp(pm, "soft_bch")) 5385 return NAND_ECC_ALGO_BCH; 5386 } 5387 5388 return NAND_ECC_ALGO_UNKNOWN; 5389} 5390 5391static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip) 5392{ 5393 struct device_node *dn = nand_get_flash_node(chip); 5394 struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf; 5395 5396 if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID) 5397 user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn); 5398 5399 if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN) 5400 user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn); 5401 5402 if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN) 5403 user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn); 5404} 5405 5406static int of_get_nand_bus_width(struct nand_chip *chip) 5407{ 5408 struct device_node *dn = nand_get_flash_node(chip); 5409 u32 val; 5410 int ret; 5411 5412 ret = of_property_read_u32(dn, "nand-bus-width", &val); 5413 if (ret == -EINVAL) 5414 /* Buswidth defaults to 8 if the property does not exist .*/ 5415 return 0; 5416 else if (ret) 5417 return ret; 5418 5419 if (val == 16) 5420 chip->options |= NAND_BUSWIDTH_16; 5421 else if (val != 8) 5422 return -EINVAL; 5423 return 0; 5424} 5425 5426static int of_get_nand_secure_regions(struct nand_chip *chip) 5427{ 5428 struct device_node *dn = nand_get_flash_node(chip); 5429 struct property *prop; 5430 int nr_elem, i, j; 5431 5432 /* Only proceed if the "secure-regions" property is present in DT */ 5433 prop = of_find_property(dn, "secure-regions", NULL); 5434 if (!prop) 5435 return 0; 5436 5437 nr_elem = of_property_count_elems_of_size(dn, "secure-regions", sizeof(u64)); 5438 if (nr_elem <= 0) 5439 return nr_elem; 5440 5441 chip->nr_secure_regions = nr_elem / 2; 5442 chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions), 5443 GFP_KERNEL); 5444 if (!chip->secure_regions) 5445 return -ENOMEM; 5446 5447 for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) { 5448 of_property_read_u64_index(dn, "secure-regions", j, 5449 &chip->secure_regions[i].offset); 5450 of_property_read_u64_index(dn, "secure-regions", j + 1, 5451 &chip->secure_regions[i].size); 5452 } 5453 5454 return 0; 5455} 5456 5457/** 5458 * rawnand_dt_parse_gpio_cs - Parse the gpio-cs property of a controller 5459 * @dev: Device that will be parsed. Also used for managed allocations. 5460 * @cs_array: Array of GPIO desc pointers allocated on success 5461 * @ncs_array: Number of entries in @cs_array updated on success. 5462 * @return 0 on success, an error otherwise. 5463 */ 5464int rawnand_dt_parse_gpio_cs(struct device *dev, struct gpio_desc ***cs_array, 5465 unsigned int *ncs_array) 5466{ 5467 struct gpio_desc **descs; 5468 int ndescs, i; 5469 5470 ndescs = gpiod_count(dev, "cs"); 5471 if (ndescs < 0) { 5472 dev_dbg(dev, "No valid cs-gpios property\n"); 5473 return 0; 5474 } 5475 5476 descs = devm_kcalloc(dev, ndescs, sizeof(*descs), GFP_KERNEL); 5477 if (!descs) 5478 return -ENOMEM; 5479 5480 for (i = 0; i < ndescs; i++) { 5481 descs[i] = gpiod_get_index_optional(dev, "cs", i, 5482 GPIOD_OUT_HIGH); 5483 if (IS_ERR(descs[i])) 5484 return PTR_ERR(descs[i]); 5485 } 5486 5487 *ncs_array = ndescs; 5488 *cs_array = descs; 5489 5490 return 0; 5491} 5492EXPORT_SYMBOL(rawnand_dt_parse_gpio_cs); 5493 5494static int rawnand_dt_init(struct nand_chip *chip) 5495{ 5496 struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip)); 5497 struct device_node *dn = nand_get_flash_node(chip); 5498 int ret; 5499 5500 if (!dn) 5501 return 0; 5502 5503 ret = of_get_nand_bus_width(chip); 5504 if (ret) 5505 return ret; 5506 5507 if (of_property_read_bool(dn, "nand-is-boot-medium")) 5508 chip->options |= NAND_IS_BOOT_MEDIUM; 5509 5510 if (of_property_read_bool(dn, "nand-on-flash-bbt")) 5511 chip->bbt_options |= NAND_BBT_USE_FLASH; 5512 5513 of_get_nand_ecc_user_config(nand); 5514 of_get_nand_ecc_legacy_user_config(chip); 5515 5516 /* 5517 * If neither the user nor the NAND controller have requested a specific 5518 * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST. 5519 */ 5520 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 5521 5522 /* 5523 * Use the user requested engine type, unless there is none, in this 5524 * case default to the NAND controller choice, otherwise fallback to 5525 * the raw NAND default one. 5526 */ 5527 if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID) 5528 chip->ecc.engine_type = nand->ecc.user_conf.engine_type; 5529 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) 5530 chip->ecc.engine_type = nand->ecc.defaults.engine_type; 5531 5532 chip->ecc.placement = nand->ecc.user_conf.placement; 5533 chip->ecc.algo = nand->ecc.user_conf.algo; 5534 chip->ecc.strength = nand->ecc.user_conf.strength; 5535 chip->ecc.size = nand->ecc.user_conf.step_size; 5536 5537 return 0; 5538} 5539 5540/** 5541 * nand_scan_ident - Scan for the NAND device 5542 * @chip: NAND chip object 5543 * @maxchips: number of chips to scan for 5544 * @table: alternative NAND ID table 5545 * 5546 * This is the first phase of the normal nand_scan() function. It reads the 5547 * flash ID and sets up MTD fields accordingly. 5548 * 5549 * This helper used to be called directly from controller drivers that needed 5550 * to tweak some ECC-related parameters before nand_scan_tail(). This separation 5551 * prevented dynamic allocations during this phase which was unconvenient and 5552 * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks. 5553 */ 5554static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips, 5555 struct nand_flash_dev *table) 5556{ 5557 struct mtd_info *mtd = nand_to_mtd(chip); 5558 struct nand_memory_organization *memorg; 5559 int nand_maf_id, nand_dev_id; 5560 unsigned int i; 5561 int ret; 5562 5563 memorg = nanddev_get_memorg(&chip->base); 5564 5565 /* Assume all dies are deselected when we enter nand_scan_ident(). */ 5566 chip->cur_cs = -1; 5567 5568 mutex_init(&chip->lock); 5569 init_waitqueue_head(&chip->resume_wq); 5570 5571 /* Enforce the right timings for reset/detection */ 5572 chip->current_interface_config = nand_get_reset_interface_config(); 5573 5574 ret = rawnand_dt_init(chip); 5575 if (ret) 5576 return ret; 5577 5578 if (!mtd->name && mtd->dev.parent) 5579 mtd->name = dev_name(mtd->dev.parent); 5580 5581 /* Set the default functions */ 5582 nand_set_defaults(chip); 5583 5584 ret = nand_legacy_check_hooks(chip); 5585 if (ret) 5586 return ret; 5587 5588 memorg->ntargets = maxchips; 5589 5590 /* Read the flash type */ 5591 ret = nand_detect(chip, table); 5592 if (ret) { 5593 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) 5594 pr_warn("No NAND device found\n"); 5595 nand_deselect_target(chip); 5596 return ret; 5597 } 5598 5599 nand_maf_id = chip->id.data[0]; 5600 nand_dev_id = chip->id.data[1]; 5601 5602 nand_deselect_target(chip); 5603 5604 /* Check for a chip array */ 5605 for (i = 1; i < maxchips; i++) { 5606 u8 id[2]; 5607 5608 /* See comment in nand_get_flash_type for reset */ 5609 ret = nand_reset(chip, i); 5610 if (ret) 5611 break; 5612 5613 nand_select_target(chip, i); 5614 /* Send the command for reading device ID */ 5615 ret = nand_readid_op(chip, 0, id, sizeof(id)); 5616 if (ret) 5617 break; 5618 /* Read manufacturer and device IDs */ 5619 if (nand_maf_id != id[0] || nand_dev_id != id[1]) { 5620 nand_deselect_target(chip); 5621 break; 5622 } 5623 nand_deselect_target(chip); 5624 } 5625 if (i > 1) 5626 pr_info("%d chips detected\n", i); 5627 5628 /* Store the number of chips and calc total size for mtd */ 5629 memorg->ntargets = i; 5630 mtd->size = i * nanddev_target_size(&chip->base); 5631 5632 return 0; 5633} 5634 5635static void nand_scan_ident_cleanup(struct nand_chip *chip) 5636{ 5637 kfree(chip->parameters.model); 5638 kfree(chip->parameters.onfi); 5639} 5640 5641int rawnand_sw_hamming_init(struct nand_chip *chip) 5642{ 5643 struct nand_ecc_sw_hamming_conf *engine_conf; 5644 struct nand_device *base = &chip->base; 5645 int ret; 5646 5647 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 5648 base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING; 5649 base->ecc.user_conf.strength = chip->ecc.strength; 5650 base->ecc.user_conf.step_size = chip->ecc.size; 5651 5652 ret = nand_ecc_sw_hamming_init_ctx(base); 5653 if (ret) 5654 return ret; 5655 5656 engine_conf = base->ecc.ctx.priv; 5657 5658 if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER) 5659 engine_conf->sm_order = true; 5660 5661 chip->ecc.size = base->ecc.ctx.conf.step_size; 5662 chip->ecc.strength = base->ecc.ctx.conf.strength; 5663 chip->ecc.total = base->ecc.ctx.total; 5664 chip->ecc.steps = nanddev_get_ecc_nsteps(base); 5665 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); 5666 5667 return 0; 5668} 5669EXPORT_SYMBOL(rawnand_sw_hamming_init); 5670 5671int rawnand_sw_hamming_calculate(struct nand_chip *chip, 5672 const unsigned char *buf, 5673 unsigned char *code) 5674{ 5675 struct nand_device *base = &chip->base; 5676 5677 return nand_ecc_sw_hamming_calculate(base, buf, code); 5678} 5679EXPORT_SYMBOL(rawnand_sw_hamming_calculate); 5680 5681int rawnand_sw_hamming_correct(struct nand_chip *chip, 5682 unsigned char *buf, 5683 unsigned char *read_ecc, 5684 unsigned char *calc_ecc) 5685{ 5686 struct nand_device *base = &chip->base; 5687 5688 return nand_ecc_sw_hamming_correct(base, buf, read_ecc, calc_ecc); 5689} 5690EXPORT_SYMBOL(rawnand_sw_hamming_correct); 5691 5692void rawnand_sw_hamming_cleanup(struct nand_chip *chip) 5693{ 5694 struct nand_device *base = &chip->base; 5695 5696 nand_ecc_sw_hamming_cleanup_ctx(base); 5697} 5698EXPORT_SYMBOL(rawnand_sw_hamming_cleanup); 5699 5700int rawnand_sw_bch_init(struct nand_chip *chip) 5701{ 5702 struct nand_device *base = &chip->base; 5703 const struct nand_ecc_props *ecc_conf = nanddev_get_ecc_conf(base); 5704 int ret; 5705 5706 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 5707 base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH; 5708 base->ecc.user_conf.step_size = chip->ecc.size; 5709 base->ecc.user_conf.strength = chip->ecc.strength; 5710 5711 ret = nand_ecc_sw_bch_init_ctx(base); 5712 if (ret) 5713 return ret; 5714 5715 chip->ecc.size = ecc_conf->step_size; 5716 chip->ecc.strength = ecc_conf->strength; 5717 chip->ecc.total = base->ecc.ctx.total; 5718 chip->ecc.steps = nanddev_get_ecc_nsteps(base); 5719 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); 5720 5721 return 0; 5722} 5723EXPORT_SYMBOL(rawnand_sw_bch_init); 5724 5725static int rawnand_sw_bch_calculate(struct nand_chip *chip, 5726 const unsigned char *buf, 5727 unsigned char *code) 5728{ 5729 struct nand_device *base = &chip->base; 5730 5731 return nand_ecc_sw_bch_calculate(base, buf, code); 5732} 5733 5734int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf, 5735 unsigned char *read_ecc, unsigned char *calc_ecc) 5736{ 5737 struct nand_device *base = &chip->base; 5738 5739 return nand_ecc_sw_bch_correct(base, buf, read_ecc, calc_ecc); 5740} 5741EXPORT_SYMBOL(rawnand_sw_bch_correct); 5742 5743void rawnand_sw_bch_cleanup(struct nand_chip *chip) 5744{ 5745 struct nand_device *base = &chip->base; 5746 5747 nand_ecc_sw_bch_cleanup_ctx(base); 5748} 5749EXPORT_SYMBOL(rawnand_sw_bch_cleanup); 5750 5751static int nand_set_ecc_on_host_ops(struct nand_chip *chip) 5752{ 5753 struct nand_ecc_ctrl *ecc = &chip->ecc; 5754 5755 switch (ecc->placement) { 5756 case NAND_ECC_PLACEMENT_UNKNOWN: 5757 case NAND_ECC_PLACEMENT_OOB: 5758 /* Use standard hwecc read page function? */ 5759 if (!ecc->read_page) 5760 ecc->read_page = nand_read_page_hwecc; 5761 if (!ecc->write_page) 5762 ecc->write_page = nand_write_page_hwecc; 5763 if (!ecc->read_page_raw) 5764 ecc->read_page_raw = nand_read_page_raw; 5765 if (!ecc->write_page_raw) 5766 ecc->write_page_raw = nand_write_page_raw; 5767 if (!ecc->read_oob) 5768 ecc->read_oob = nand_read_oob_std; 5769 if (!ecc->write_oob) 5770 ecc->write_oob = nand_write_oob_std; 5771 if (!ecc->read_subpage) 5772 ecc->read_subpage = nand_read_subpage; 5773 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) 5774 ecc->write_subpage = nand_write_subpage_hwecc; 5775 fallthrough; 5776 5777 case NAND_ECC_PLACEMENT_INTERLEAVED: 5778 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 5779 (!ecc->read_page || 5780 ecc->read_page == nand_read_page_hwecc || 5781 !ecc->write_page || 5782 ecc->write_page == nand_write_page_hwecc)) { 5783 WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); 5784 return -EINVAL; 5785 } 5786 /* Use standard syndrome read/write page function? */ 5787 if (!ecc->read_page) 5788 ecc->read_page = nand_read_page_syndrome; 5789 if (!ecc->write_page) 5790 ecc->write_page = nand_write_page_syndrome; 5791 if (!ecc->read_page_raw) 5792 ecc->read_page_raw = nand_read_page_raw_syndrome; 5793 if (!ecc->write_page_raw) 5794 ecc->write_page_raw = nand_write_page_raw_syndrome; 5795 if (!ecc->read_oob) 5796 ecc->read_oob = nand_read_oob_syndrome; 5797 if (!ecc->write_oob) 5798 ecc->write_oob = nand_write_oob_syndrome; 5799 break; 5800 5801 default: 5802 pr_warn("Invalid NAND_ECC_PLACEMENT %d\n", 5803 ecc->placement); 5804 return -EINVAL; 5805 } 5806 5807 return 0; 5808} 5809 5810static int nand_set_ecc_soft_ops(struct nand_chip *chip) 5811{ 5812 struct mtd_info *mtd = nand_to_mtd(chip); 5813 struct nand_device *nanddev = mtd_to_nanddev(mtd); 5814 struct nand_ecc_ctrl *ecc = &chip->ecc; 5815 int ret; 5816 5817 if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT)) 5818 return -EINVAL; 5819 5820 switch (ecc->algo) { 5821 case NAND_ECC_ALGO_HAMMING: 5822 ecc->calculate = rawnand_sw_hamming_calculate; 5823 ecc->correct = rawnand_sw_hamming_correct; 5824 ecc->read_page = nand_read_page_swecc; 5825 ecc->read_subpage = nand_read_subpage; 5826 ecc->write_page = nand_write_page_swecc; 5827 if (!ecc->read_page_raw) 5828 ecc->read_page_raw = nand_read_page_raw; 5829 if (!ecc->write_page_raw) 5830 ecc->write_page_raw = nand_write_page_raw; 5831 ecc->read_oob = nand_read_oob_std; 5832 ecc->write_oob = nand_write_oob_std; 5833 if (!ecc->size) 5834 ecc->size = 256; 5835 ecc->bytes = 3; 5836 ecc->strength = 1; 5837 5838 if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)) 5839 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; 5840 5841 ret = rawnand_sw_hamming_init(chip); 5842 if (ret) { 5843 WARN(1, "Hamming ECC initialization failed!\n"); 5844 return ret; 5845 } 5846 5847 return 0; 5848 case NAND_ECC_ALGO_BCH: 5849 if (!IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) { 5850 WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n"); 5851 return -EINVAL; 5852 } 5853 ecc->calculate = rawnand_sw_bch_calculate; 5854 ecc->correct = rawnand_sw_bch_correct; 5855 ecc->read_page = nand_read_page_swecc; 5856 ecc->read_subpage = nand_read_subpage; 5857 ecc->write_page = nand_write_page_swecc; 5858 if (!ecc->read_page_raw) 5859 ecc->read_page_raw = nand_read_page_raw; 5860 if (!ecc->write_page_raw) 5861 ecc->write_page_raw = nand_write_page_raw; 5862 ecc->read_oob = nand_read_oob_std; 5863 ecc->write_oob = nand_write_oob_std; 5864 5865 /* 5866 * We can only maximize ECC config when the default layout is 5867 * used, otherwise we don't know how many bytes can really be 5868 * used. 5869 */ 5870 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH && 5871 mtd->ooblayout != nand_get_large_page_ooblayout()) 5872 nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH; 5873 5874 ret = rawnand_sw_bch_init(chip); 5875 if (ret) { 5876 WARN(1, "BCH ECC initialization failed!\n"); 5877 return ret; 5878 } 5879 5880 return 0; 5881 default: 5882 WARN(1, "Unsupported ECC algorithm!\n"); 5883 return -EINVAL; 5884 } 5885} 5886 5887/** 5888 * nand_check_ecc_caps - check the sanity of preset ECC settings 5889 * @chip: nand chip info structure 5890 * @caps: ECC caps info structure 5891 * @oobavail: OOB size that the ECC engine can use 5892 * 5893 * When ECC step size and strength are already set, check if they are supported 5894 * by the controller and the calculated ECC bytes fit within the chip's OOB. 5895 * On success, the calculated ECC bytes is set. 5896 */ 5897static int 5898nand_check_ecc_caps(struct nand_chip *chip, 5899 const struct nand_ecc_caps *caps, int oobavail) 5900{ 5901 struct mtd_info *mtd = nand_to_mtd(chip); 5902 const struct nand_ecc_step_info *stepinfo; 5903 int preset_step = chip->ecc.size; 5904 int preset_strength = chip->ecc.strength; 5905 int ecc_bytes, nsteps = mtd->writesize / preset_step; 5906 int i, j; 5907 5908 for (i = 0; i < caps->nstepinfos; i++) { 5909 stepinfo = &caps->stepinfos[i]; 5910 5911 if (stepinfo->stepsize != preset_step) 5912 continue; 5913 5914 for (j = 0; j < stepinfo->nstrengths; j++) { 5915 if (stepinfo->strengths[j] != preset_strength) 5916 continue; 5917 5918 ecc_bytes = caps->calc_ecc_bytes(preset_step, 5919 preset_strength); 5920 if (WARN_ON_ONCE(ecc_bytes < 0)) 5921 return ecc_bytes; 5922 5923 if (ecc_bytes * nsteps > oobavail) { 5924 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", 5925 preset_step, preset_strength); 5926 return -ENOSPC; 5927 } 5928 5929 chip->ecc.bytes = ecc_bytes; 5930 5931 return 0; 5932 } 5933 } 5934 5935 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", 5936 preset_step, preset_strength); 5937 5938 return -ENOTSUPP; 5939} 5940 5941/** 5942 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes 5943 * @chip: nand chip info structure 5944 * @caps: ECC engine caps info structure 5945 * @oobavail: OOB size that the ECC engine can use 5946 * 5947 * If a chip's ECC requirement is provided, try to meet it with the least 5948 * number of ECC bytes (i.e. with the largest number of OOB-free bytes). 5949 * On success, the chosen ECC settings are set. 5950 */ 5951static int 5952nand_match_ecc_req(struct nand_chip *chip, 5953 const struct nand_ecc_caps *caps, int oobavail) 5954{ 5955 const struct nand_ecc_props *requirements = 5956 nanddev_get_ecc_requirements(&chip->base); 5957 struct mtd_info *mtd = nand_to_mtd(chip); 5958 const struct nand_ecc_step_info *stepinfo; 5959 int req_step = requirements->step_size; 5960 int req_strength = requirements->strength; 5961 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; 5962 int best_step = 0, best_strength = 0, best_ecc_bytes = 0; 5963 int best_ecc_bytes_total = INT_MAX; 5964 int i, j; 5965 5966 /* No information provided by the NAND chip */ 5967 if (!req_step || !req_strength) 5968 return -ENOTSUPP; 5969 5970 /* number of correctable bits the chip requires in a page */ 5971 req_corr = mtd->writesize / req_step * req_strength; 5972 5973 for (i = 0; i < caps->nstepinfos; i++) { 5974 stepinfo = &caps->stepinfos[i]; 5975 step_size = stepinfo->stepsize; 5976 5977 for (j = 0; j < stepinfo->nstrengths; j++) { 5978 strength = stepinfo->strengths[j]; 5979 5980 /* 5981 * If both step size and strength are smaller than the 5982 * chip's requirement, it is not easy to compare the 5983 * resulted reliability. 5984 */ 5985 if (step_size < req_step && strength < req_strength) 5986 continue; 5987 5988 if (mtd->writesize % step_size) 5989 continue; 5990 5991 nsteps = mtd->writesize / step_size; 5992 5993 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 5994 if (WARN_ON_ONCE(ecc_bytes < 0)) 5995 continue; 5996 ecc_bytes_total = ecc_bytes * nsteps; 5997 5998 if (ecc_bytes_total > oobavail || 5999 strength * nsteps < req_corr) 6000 continue; 6001 6002 /* 6003 * We assume the best is to meet the chip's requrement 6004 * with the least number of ECC bytes. 6005 */ 6006 if (ecc_bytes_total < best_ecc_bytes_total) { 6007 best_ecc_bytes_total = ecc_bytes_total; 6008 best_step = step_size; 6009 best_strength = strength; 6010 best_ecc_bytes = ecc_bytes; 6011 } 6012 } 6013 } 6014 6015 if (best_ecc_bytes_total == INT_MAX) 6016 return -ENOTSUPP; 6017 6018 chip->ecc.size = best_step; 6019 chip->ecc.strength = best_strength; 6020 chip->ecc.bytes = best_ecc_bytes; 6021 6022 return 0; 6023} 6024 6025/** 6026 * nand_maximize_ecc - choose the max ECC strength available 6027 * @chip: nand chip info structure 6028 * @caps: ECC engine caps info structure 6029 * @oobavail: OOB size that the ECC engine can use 6030 * 6031 * Choose the max ECC strength that is supported on the controller, and can fit 6032 * within the chip's OOB. On success, the chosen ECC settings are set. 6033 */ 6034static int 6035nand_maximize_ecc(struct nand_chip *chip, 6036 const struct nand_ecc_caps *caps, int oobavail) 6037{ 6038 struct mtd_info *mtd = nand_to_mtd(chip); 6039 const struct nand_ecc_step_info *stepinfo; 6040 int step_size, strength, nsteps, ecc_bytes, corr; 6041 int best_corr = 0; 6042 int best_step = 0; 6043 int best_strength = 0, best_ecc_bytes = 0; 6044 int i, j; 6045 6046 for (i = 0; i < caps->nstepinfos; i++) { 6047 stepinfo = &caps->stepinfos[i]; 6048 step_size = stepinfo->stepsize; 6049 6050 /* If chip->ecc.size is already set, respect it */ 6051 if (chip->ecc.size && step_size != chip->ecc.size) 6052 continue; 6053 6054 for (j = 0; j < stepinfo->nstrengths; j++) { 6055 strength = stepinfo->strengths[j]; 6056 6057 if (mtd->writesize % step_size) 6058 continue; 6059 6060 nsteps = mtd->writesize / step_size; 6061 6062 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 6063 if (WARN_ON_ONCE(ecc_bytes < 0)) 6064 continue; 6065 6066 if (ecc_bytes * nsteps > oobavail) 6067 continue; 6068 6069 corr = strength * nsteps; 6070 6071 /* 6072 * If the number of correctable bits is the same, 6073 * bigger step_size has more reliability. 6074 */ 6075 if (corr > best_corr || 6076 (corr == best_corr && step_size > best_step)) { 6077 best_corr = corr; 6078 best_step = step_size; 6079 best_strength = strength; 6080 best_ecc_bytes = ecc_bytes; 6081 } 6082 } 6083 } 6084 6085 if (!best_corr) 6086 return -ENOTSUPP; 6087 6088 chip->ecc.size = best_step; 6089 chip->ecc.strength = best_strength; 6090 chip->ecc.bytes = best_ecc_bytes; 6091 6092 return 0; 6093} 6094 6095/** 6096 * nand_ecc_choose_conf - Set the ECC strength and ECC step size 6097 * @chip: nand chip info structure 6098 * @caps: ECC engine caps info structure 6099 * @oobavail: OOB size that the ECC engine can use 6100 * 6101 * Choose the ECC configuration according to following logic. 6102 * 6103 * 1. If both ECC step size and ECC strength are already set (usually by DT) 6104 * then check if it is supported by this controller. 6105 * 2. If the user provided the nand-ecc-maximize property, then select maximum 6106 * ECC strength. 6107 * 3. Otherwise, try to match the ECC step size and ECC strength closest 6108 * to the chip's requirement. If available OOB size can't fit the chip 6109 * requirement then fallback to the maximum ECC step size and ECC strength. 6110 * 6111 * On success, the chosen ECC settings are set. 6112 */ 6113int nand_ecc_choose_conf(struct nand_chip *chip, 6114 const struct nand_ecc_caps *caps, int oobavail) 6115{ 6116 struct mtd_info *mtd = nand_to_mtd(chip); 6117 struct nand_device *nanddev = mtd_to_nanddev(mtd); 6118 6119 if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize)) 6120 return -EINVAL; 6121 6122 if (chip->ecc.size && chip->ecc.strength) 6123 return nand_check_ecc_caps(chip, caps, oobavail); 6124 6125 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) 6126 return nand_maximize_ecc(chip, caps, oobavail); 6127 6128 if (!nand_match_ecc_req(chip, caps, oobavail)) 6129 return 0; 6130 6131 return nand_maximize_ecc(chip, caps, oobavail); 6132} 6133EXPORT_SYMBOL_GPL(nand_ecc_choose_conf); 6134 6135static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos) 6136{ 6137 struct nand_chip *chip = container_of(nand, struct nand_chip, 6138 base); 6139 unsigned int eb = nanddev_pos_to_row(nand, pos); 6140 int ret; 6141 6142 eb >>= nand->rowconv.eraseblock_addr_shift; 6143 6144 nand_select_target(chip, pos->target); 6145 ret = nand_erase_op(chip, eb); 6146 nand_deselect_target(chip); 6147 6148 return ret; 6149} 6150 6151static int rawnand_markbad(struct nand_device *nand, 6152 const struct nand_pos *pos) 6153{ 6154 struct nand_chip *chip = container_of(nand, struct nand_chip, 6155 base); 6156 6157 return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); 6158} 6159 6160static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos) 6161{ 6162 struct nand_chip *chip = container_of(nand, struct nand_chip, 6163 base); 6164 int ret; 6165 6166 nand_select_target(chip, pos->target); 6167 ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); 6168 nand_deselect_target(chip); 6169 6170 return ret; 6171} 6172 6173static const struct nand_ops rawnand_ops = { 6174 .erase = rawnand_erase, 6175 .markbad = rawnand_markbad, 6176 .isbad = rawnand_isbad, 6177}; 6178 6179/** 6180 * nand_scan_tail - Scan for the NAND device 6181 * @chip: NAND chip object 6182 * 6183 * This is the second phase of the normal nand_scan() function. It fills out 6184 * all the uninitialized function pointers with the defaults and scans for a 6185 * bad block table if appropriate. 6186 */ 6187static int nand_scan_tail(struct nand_chip *chip) 6188{ 6189 struct mtd_info *mtd = nand_to_mtd(chip); 6190 struct nand_device *base = &chip->base; 6191 struct nand_ecc_ctrl *ecc = &chip->ecc; 6192 int ret, i; 6193 6194 /* New bad blocks should be marked in OOB, flash-based BBT, or both */ 6195 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && 6196 !(chip->bbt_options & NAND_BBT_USE_FLASH))) { 6197 return -EINVAL; 6198 } 6199 6200 chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); 6201 if (!chip->data_buf) 6202 return -ENOMEM; 6203 6204 /* 6205 * FIXME: some NAND manufacturer drivers expect the first die to be 6206 * selected when manufacturer->init() is called. They should be fixed 6207 * to explictly select the relevant die when interacting with the NAND 6208 * chip. 6209 */ 6210 nand_select_target(chip, 0); 6211 ret = nand_manufacturer_init(chip); 6212 nand_deselect_target(chip); 6213 if (ret) 6214 goto err_free_buf; 6215 6216 /* Set the internal oob buffer location, just after the page data */ 6217 chip->oob_poi = chip->data_buf + mtd->writesize; 6218 6219 /* 6220 * If no default placement scheme is given, select an appropriate one. 6221 */ 6222 if (!mtd->ooblayout && 6223 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 6224 ecc->algo == NAND_ECC_ALGO_BCH) && 6225 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 6226 ecc->algo == NAND_ECC_ALGO_HAMMING)) { 6227 switch (mtd->oobsize) { 6228 case 8: 6229 case 16: 6230 mtd_set_ooblayout(mtd, nand_get_small_page_ooblayout()); 6231 break; 6232 case 64: 6233 case 128: 6234 mtd_set_ooblayout(mtd, 6235 nand_get_large_page_hamming_ooblayout()); 6236 break; 6237 default: 6238 /* 6239 * Expose the whole OOB area to users if ECC_NONE 6240 * is passed. We could do that for all kind of 6241 * ->oobsize, but we must keep the old large/small 6242 * page with ECC layout when ->oobsize <= 128 for 6243 * compatibility reasons. 6244 */ 6245 if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) { 6246 mtd_set_ooblayout(mtd, 6247 nand_get_large_page_ooblayout()); 6248 break; 6249 } 6250 6251 WARN(1, "No oob scheme defined for oobsize %d\n", 6252 mtd->oobsize); 6253 ret = -EINVAL; 6254 goto err_nand_manuf_cleanup; 6255 } 6256 } 6257 6258 /* 6259 * Check ECC mode, default to software if 3byte/512byte hardware ECC is 6260 * selected and we have 256 byte pagesize fallback to software ECC 6261 */ 6262 6263 switch (ecc->engine_type) { 6264 case NAND_ECC_ENGINE_TYPE_ON_HOST: 6265 ret = nand_set_ecc_on_host_ops(chip); 6266 if (ret) 6267 goto err_nand_manuf_cleanup; 6268 6269 if (mtd->writesize >= ecc->size) { 6270 if (!ecc->strength) { 6271 WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); 6272 ret = -EINVAL; 6273 goto err_nand_manuf_cleanup; 6274 } 6275 break; 6276 } 6277 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", 6278 ecc->size, mtd->writesize); 6279 ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 6280 ecc->algo = NAND_ECC_ALGO_HAMMING; 6281 fallthrough; 6282 6283 case NAND_ECC_ENGINE_TYPE_SOFT: 6284 ret = nand_set_ecc_soft_ops(chip); 6285 if (ret) 6286 goto err_nand_manuf_cleanup; 6287 break; 6288 6289 case NAND_ECC_ENGINE_TYPE_ON_DIE: 6290 if (!ecc->read_page || !ecc->write_page) { 6291 WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); 6292 ret = -EINVAL; 6293 goto err_nand_manuf_cleanup; 6294 } 6295 if (!ecc->read_oob) 6296 ecc->read_oob = nand_read_oob_std; 6297 if (!ecc->write_oob) 6298 ecc->write_oob = nand_write_oob_std; 6299 break; 6300 6301 case NAND_ECC_ENGINE_TYPE_NONE: 6302 pr_warn("NAND_ECC_ENGINE_TYPE_NONE selected by board driver. This is not recommended!\n"); 6303 ecc->read_page = nand_read_page_raw; 6304 ecc->write_page = nand_write_page_raw; 6305 ecc->read_oob = nand_read_oob_std; 6306 ecc->read_page_raw = nand_read_page_raw; 6307 ecc->write_page_raw = nand_write_page_raw; 6308 ecc->write_oob = nand_write_oob_std; 6309 ecc->size = mtd->writesize; 6310 ecc->bytes = 0; 6311 ecc->strength = 0; 6312 break; 6313 6314 default: 6315 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type); 6316 ret = -EINVAL; 6317 goto err_nand_manuf_cleanup; 6318 } 6319 6320 if (ecc->correct || ecc->calculate) { 6321 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL); 6322 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL); 6323 if (!ecc->calc_buf || !ecc->code_buf) { 6324 ret = -ENOMEM; 6325 goto err_nand_manuf_cleanup; 6326 } 6327 } 6328 6329 /* For many systems, the standard OOB write also works for raw */ 6330 if (!ecc->read_oob_raw) 6331 ecc->read_oob_raw = ecc->read_oob; 6332 if (!ecc->write_oob_raw) 6333 ecc->write_oob_raw = ecc->write_oob; 6334 6335 /* Propagate ECC info to the generic NAND and MTD layers */ 6336 mtd->ecc_strength = ecc->strength; 6337 if (!base->ecc.ctx.conf.strength) 6338 base->ecc.ctx.conf.strength = ecc->strength; 6339 mtd->ecc_step_size = ecc->size; 6340 if (!base->ecc.ctx.conf.step_size) 6341 base->ecc.ctx.conf.step_size = ecc->size; 6342 6343 /* 6344 * Set the number of read / write steps for one page depending on ECC 6345 * mode. 6346 */ 6347 if (!ecc->steps) 6348 ecc->steps = mtd->writesize / ecc->size; 6349 if (!base->ecc.ctx.nsteps) 6350 base->ecc.ctx.nsteps = ecc->steps; 6351 6352 /* 6353 * Validity check: Warn if ECC parameters are not compatible with page size. 6354 * Due to the custom handling of ECC blocks in certain controllers the check 6355 * may result in an expected failure. 6356 */ 6357 if (ecc->steps * ecc->size != mtd->writesize) 6358 pr_warn("ECC parameters may be invalid in reference to underlying NAND chip\n"); 6359 6360 if (!ecc->total) { 6361 ecc->total = ecc->steps * ecc->bytes; 6362 chip->base.ecc.ctx.total = ecc->total; 6363 } 6364 6365 if (ecc->total > mtd->oobsize) { 6366 WARN(1, "Total number of ECC bytes exceeded oobsize\n"); 6367 ret = -EINVAL; 6368 goto err_nand_manuf_cleanup; 6369 } 6370 6371 /* 6372 * The number of bytes available for a client to place data into 6373 * the out of band area. 6374 */ 6375 ret = mtd_ooblayout_count_freebytes(mtd); 6376 if (ret < 0) 6377 ret = 0; 6378 6379 mtd->oobavail = ret; 6380 6381 /* ECC sanity check: warn if it's too weak */ 6382 if (!nand_ecc_is_strong_enough(&chip->base)) 6383 pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n", 6384 mtd->name, chip->ecc.strength, chip->ecc.size, 6385 nanddev_get_ecc_requirements(&chip->base)->strength, 6386 nanddev_get_ecc_requirements(&chip->base)->step_size); 6387 6388 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ 6389 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { 6390 switch (ecc->steps) { 6391 case 2: 6392 mtd->subpage_sft = 1; 6393 break; 6394 case 4: 6395 case 8: 6396 case 16: 6397 mtd->subpage_sft = 2; 6398 break; 6399 } 6400 } 6401 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; 6402 6403 /* Invalidate the pagebuffer reference */ 6404 chip->pagecache.page = -1; 6405 6406 /* Large page NAND with SOFT_ECC should support subpage reads */ 6407 switch (ecc->engine_type) { 6408 case NAND_ECC_ENGINE_TYPE_SOFT: 6409 if (chip->page_shift > 9) 6410 chip->options |= NAND_SUBPAGE_READ; 6411 break; 6412 6413 default: 6414 break; 6415 } 6416 6417 ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner); 6418 if (ret) 6419 goto err_nand_manuf_cleanup; 6420 6421 /* Adjust the MTD_CAP_ flags when NAND_ROM is set. */ 6422 if (chip->options & NAND_ROM) 6423 mtd->flags = MTD_CAP_ROM; 6424 6425 /* Fill in remaining MTD driver data */ 6426 mtd->_erase = nand_erase; 6427 mtd->_point = NULL; 6428 mtd->_unpoint = NULL; 6429 mtd->_panic_write = panic_nand_write; 6430 mtd->_read_oob = nand_read_oob; 6431 mtd->_write_oob = nand_write_oob; 6432 mtd->_sync = nand_sync; 6433 mtd->_lock = nand_lock; 6434 mtd->_unlock = nand_unlock; 6435 mtd->_suspend = nand_suspend; 6436 mtd->_resume = nand_resume; 6437 mtd->_reboot = nand_shutdown; 6438 mtd->_block_isreserved = nand_block_isreserved; 6439 mtd->_block_isbad = nand_block_isbad; 6440 mtd->_block_markbad = nand_block_markbad; 6441 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; 6442 6443 /* 6444 * Initialize bitflip_threshold to its default prior scan_bbt() call. 6445 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be 6446 * properly set. 6447 */ 6448 if (!mtd->bitflip_threshold) 6449 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); 6450 6451 /* Find the fastest data interface for this chip */ 6452 ret = nand_choose_interface_config(chip); 6453 if (ret) 6454 goto err_nanddev_cleanup; 6455 6456 /* Enter fastest possible mode on all dies. */ 6457 for (i = 0; i < nanddev_ntargets(&chip->base); i++) { 6458 ret = nand_setup_interface(chip, i); 6459 if (ret) 6460 goto err_free_interface_config; 6461 } 6462 6463 rawnand_late_check_supported_ops(chip); 6464 6465 /* 6466 * Look for secure regions in the NAND chip. These regions are supposed 6467 * to be protected by a secure element like Trustzone. So the read/write 6468 * accesses to these regions will be blocked in the runtime by this 6469 * driver. 6470 */ 6471 ret = of_get_nand_secure_regions(chip); 6472 if (ret) 6473 goto err_free_interface_config; 6474 6475 /* Check, if we should skip the bad block table scan */ 6476 if (chip->options & NAND_SKIP_BBTSCAN) 6477 return 0; 6478 6479 /* Build bad block table */ 6480 ret = nand_create_bbt(chip); 6481 if (ret) 6482 goto err_free_secure_regions; 6483 6484 return 0; 6485 6486err_free_secure_regions: 6487 kfree(chip->secure_regions); 6488 6489err_free_interface_config: 6490 kfree(chip->best_interface_config); 6491 6492err_nanddev_cleanup: 6493 nanddev_cleanup(&chip->base); 6494 6495err_nand_manuf_cleanup: 6496 nand_manufacturer_cleanup(chip); 6497 6498err_free_buf: 6499 kfree(chip->data_buf); 6500 kfree(ecc->code_buf); 6501 kfree(ecc->calc_buf); 6502 6503 return ret; 6504} 6505 6506static int nand_attach(struct nand_chip *chip) 6507{ 6508 if (chip->controller->ops && chip->controller->ops->attach_chip) 6509 return chip->controller->ops->attach_chip(chip); 6510 6511 return 0; 6512} 6513 6514static void nand_detach(struct nand_chip *chip) 6515{ 6516 if (chip->controller->ops && chip->controller->ops->detach_chip) 6517 chip->controller->ops->detach_chip(chip); 6518} 6519 6520/** 6521 * nand_scan_with_ids - [NAND Interface] Scan for the NAND device 6522 * @chip: NAND chip object 6523 * @maxchips: number of chips to scan for. 6524 * @ids: optional flash IDs table 6525 * 6526 * This fills out all the uninitialized function pointers with the defaults. 6527 * The flash ID is read and the mtd/chip structures are filled with the 6528 * appropriate values. 6529 */ 6530int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips, 6531 struct nand_flash_dev *ids) 6532{ 6533 int ret; 6534 6535 if (!maxchips) 6536 return -EINVAL; 6537 6538 ret = nand_scan_ident(chip, maxchips, ids); 6539 if (ret) 6540 return ret; 6541 6542 ret = nand_attach(chip); 6543 if (ret) 6544 goto cleanup_ident; 6545 6546 ret = nand_scan_tail(chip); 6547 if (ret) 6548 goto detach_chip; 6549 6550 return 0; 6551 6552detach_chip: 6553 nand_detach(chip); 6554cleanup_ident: 6555 nand_scan_ident_cleanup(chip); 6556 6557 return ret; 6558} 6559EXPORT_SYMBOL(nand_scan_with_ids); 6560 6561/** 6562 * nand_cleanup - [NAND Interface] Free resources held by the NAND device 6563 * @chip: NAND chip object 6564 */ 6565void nand_cleanup(struct nand_chip *chip) 6566{ 6567 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) { 6568 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) 6569 rawnand_sw_hamming_cleanup(chip); 6570 else if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 6571 rawnand_sw_bch_cleanup(chip); 6572 } 6573 6574 nanddev_cleanup(&chip->base); 6575 6576 /* Free secure regions data */ 6577 kfree(chip->secure_regions); 6578 6579 /* Free bad block table memory */ 6580 kfree(chip->bbt); 6581 kfree(chip->data_buf); 6582 kfree(chip->ecc.code_buf); 6583 kfree(chip->ecc.calc_buf); 6584 6585 /* Free bad block descriptor memory */ 6586 if (chip->badblock_pattern && chip->badblock_pattern->options 6587 & NAND_BBT_DYNAMICSTRUCT) 6588 kfree(chip->badblock_pattern); 6589 6590 /* Free the data interface */ 6591 kfree(chip->best_interface_config); 6592 6593 /* Free manufacturer priv data. */ 6594 nand_manufacturer_cleanup(chip); 6595 6596 /* Free controller specific allocations after chip identification */ 6597 nand_detach(chip); 6598 6599 /* Free identification phase allocations */ 6600 nand_scan_ident_cleanup(chip); 6601} 6602 6603EXPORT_SYMBOL_GPL(nand_cleanup); 6604 6605MODULE_LICENSE("GPL"); 6606MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); 6607MODULE_AUTHOR("Thomas Gleixner <tglx@kernel.org>"); 6608MODULE_DESCRIPTION("Generic NAND flash driver code");
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