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lpc32xx_slc.c
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linux-6.19.14/drivers/mtd/nand/raw/lpc32xx_slc.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * NXP LPC32XX NAND SLC driver 4 * 5 * Authors: 6 * Kevin Wells <kevin.wells@nxp.com> 7 * Roland Stigge <stigge@antcom.de> 8 * 9 * Copyright © 2011 NXP Semiconductors 10 * Copyright © 2012 Roland Stigge 11 */ 12 13#include <linux/slab.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/mtd/mtd.h> 17#include <linux/mtd/rawnand.h> 18#include <linux/mtd/partitions.h> 19#include <linux/clk.h> 20#include <linux/err.h> 21#include <linux/delay.h> 22#include <linux/io.h> 23#include <linux/mm.h> 24#include <linux/dma-mapping.h> 25#include <linux/dmaengine.h> 26#include <linux/gpio/consumer.h> 27#include <linux/of.h> 28#include <linux/mtd/lpc32xx_slc.h> 29 30#define LPC32XX_MODNAME "lpc32xx-nand" 31 32/********************************************************************** 33* SLC NAND controller register offsets 34**********************************************************************/ 35 36#define SLC_DATA(x) (x + 0x000) 37#define SLC_ADDR(x) (x + 0x004) 38#define SLC_CMD(x) (x + 0x008) 39#define SLC_STOP(x) (x + 0x00C) 40#define SLC_CTRL(x) (x + 0x010) 41#define SLC_CFG(x) (x + 0x014) 42#define SLC_STAT(x) (x + 0x018) 43#define SLC_INT_STAT(x) (x + 0x01C) 44#define SLC_IEN(x) (x + 0x020) 45#define SLC_ISR(x) (x + 0x024) 46#define SLC_ICR(x) (x + 0x028) 47#define SLC_TAC(x) (x + 0x02C) 48#define SLC_TC(x) (x + 0x030) 49#define SLC_ECC(x) (x + 0x034) 50#define SLC_DMA_DATA(x) (x + 0x038) 51 52/********************************************************************** 53* slc_ctrl register definitions 54**********************************************************************/ 55#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */ 56#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ 57#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */ 58 59/********************************************************************** 60* slc_cfg register definitions 61**********************************************************************/ 62#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */ 63#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ 64#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */ 65#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */ 66#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ 67#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */ 68 69/********************************************************************** 70* slc_stat register definitions 71**********************************************************************/ 72#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ 73#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */ 74#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */ 75 76/********************************************************************** 77* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions 78**********************************************************************/ 79#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */ 80#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */ 81 82/********************************************************************** 83* slc_tac register definitions 84**********************************************************************/ 85/* Computation of clock cycles on basis of controller and device clock rates */ 86#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s) 87 88/* Clock setting for RDY write sample wait time in 2*n clocks */ 89#define SLCTAC_WDR(n) (((n) & 0xF) << 28) 90/* Write pulse width in clock cycles, 1 to 16 clocks */ 91#define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24)) 92/* Write hold time of control and data signals, 1 to 16 clocks */ 93#define SLCTAC_WHOLD(c, n) (SLCTAC_CLOCKS(c, n, 20)) 94/* Write setup time of control and data signals, 1 to 16 clocks */ 95#define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16)) 96/* Clock setting for RDY read sample wait time in 2*n clocks */ 97#define SLCTAC_RDR(n) (((n) & 0xF) << 12) 98/* Read pulse width in clock cycles, 1 to 16 clocks */ 99#define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8)) 100/* Read hold time of control and data signals, 1 to 16 clocks */ 101#define SLCTAC_RHOLD(c, n) (SLCTAC_CLOCKS(c, n, 4)) 102/* Read setup time of control and data signals, 1 to 16 clocks */ 103#define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0)) 104 105/********************************************************************** 106* slc_ecc register definitions 107**********************************************************************/ 108/* ECC line party fetch macro */ 109#define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF) 110#define SLCECC_TO_COLPAR(n) ((n) & 0x3F) 111 112/* 113 * DMA requires storage space for the DMA local buffer and the hardware ECC 114 * storage area. The DMA local buffer is only used if DMA mapping fails 115 * during runtime. 116 */ 117#define LPC32XX_DMA_DATA_SIZE 4096 118#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4) 119 120/* Number of bytes used for ECC stored in NAND per 256 bytes */ 121#define LPC32XX_SLC_DEV_ECC_BYTES 3 122 123/* 124 * If the NAND base clock frequency can't be fetched, this frequency will be 125 * used instead as the base. This rate is used to setup the timing registers 126 * used for NAND accesses. 127 */ 128#define LPC32XX_DEF_BUS_RATE 133250000 129 130/* Milliseconds for DMA FIFO timeout (unlikely anyway) */ 131#define LPC32XX_DMA_TIMEOUT 100 132 133/* 134 * NAND ECC Layout for small page NAND devices 135 * Note: For large and huge page devices, the default layouts are used 136 */ 137static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section, 138 struct mtd_oob_region *oobregion) 139{ 140 if (section) 141 return -ERANGE; 142 143 oobregion->length = 6; 144 oobregion->offset = 10; 145 146 return 0; 147} 148 149static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section, 150 struct mtd_oob_region *oobregion) 151{ 152 if (section > 1) 153 return -ERANGE; 154 155 if (!section) { 156 oobregion->offset = 0; 157 oobregion->length = 4; 158 } else { 159 oobregion->offset = 6; 160 oobregion->length = 4; 161 } 162 163 return 0; 164} 165 166static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = { 167 .ecc = lpc32xx_ooblayout_ecc, 168 .free = lpc32xx_ooblayout_free, 169}; 170 171static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 172static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 173 174/* 175 * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6 176 * Note: Large page devices used the default layout 177 */ 178static struct nand_bbt_descr bbt_smallpage_main_descr = { 179 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 180 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 181 .offs = 0, 182 .len = 4, 183 .veroffs = 6, 184 .maxblocks = 4, 185 .pattern = bbt_pattern 186}; 187 188static struct nand_bbt_descr bbt_smallpage_mirror_descr = { 189 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 190 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 191 .offs = 0, 192 .len = 4, 193 .veroffs = 6, 194 .maxblocks = 4, 195 .pattern = mirror_pattern 196}; 197 198/* 199 * NAND platform configuration structure 200 */ 201struct lpc32xx_nand_cfg_slc { 202 uint32_t wdr_clks; 203 uint32_t wwidth; 204 uint32_t whold; 205 uint32_t wsetup; 206 uint32_t rdr_clks; 207 uint32_t rwidth; 208 uint32_t rhold; 209 uint32_t rsetup; 210 struct mtd_partition *parts; 211 unsigned num_parts; 212}; 213 214struct lpc32xx_nand_host { 215 struct nand_chip nand_chip; 216 struct lpc32xx_slc_platform_data *pdata; 217 struct clk *clk; 218 struct gpio_desc *wp_gpio; 219 void __iomem *io_base; 220 struct lpc32xx_nand_cfg_slc *ncfg; 221 222 struct completion comp; 223 struct dma_chan *dma_chan; 224 uint32_t dma_buf_len; 225 struct dma_slave_config dma_slave_config; 226 struct scatterlist sgl; 227 228 /* 229 * DMA and CPU addresses of ECC work area and data buffer 230 */ 231 uint32_t *ecc_buf; 232 uint8_t *data_buf; 233 dma_addr_t io_base_dma; 234}; 235 236static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) 237{ 238 uint32_t clkrate, tmp; 239 240 /* Reset SLC controller */ 241 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); 242 udelay(1000); 243 244 /* Basic setup */ 245 writel(0, SLC_CFG(host->io_base)); 246 writel(0, SLC_IEN(host->io_base)); 247 writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN), 248 SLC_ICR(host->io_base)); 249 250 /* Get base clock for SLC block */ 251 clkrate = clk_get_rate(host->clk); 252 if (clkrate == 0) 253 clkrate = LPC32XX_DEF_BUS_RATE; 254 255 /* Compute clock setup values */ 256 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) | 257 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) | 258 SLCTAC_WHOLD(clkrate, host->ncfg->whold) | 259 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) | 260 SLCTAC_RDR(host->ncfg->rdr_clks) | 261 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) | 262 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) | 263 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup); 264 writel(tmp, SLC_TAC(host->io_base)); 265} 266 267/* 268 * Hardware specific access to control lines 269 */ 270static void lpc32xx_nand_cmd_ctrl(struct nand_chip *chip, int cmd, 271 unsigned int ctrl) 272{ 273 uint32_t tmp; 274 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 275 276 /* Does CE state need to be changed? */ 277 tmp = readl(SLC_CFG(host->io_base)); 278 if (ctrl & NAND_NCE) 279 tmp |= SLCCFG_CE_LOW; 280 else 281 tmp &= ~SLCCFG_CE_LOW; 282 writel(tmp, SLC_CFG(host->io_base)); 283 284 if (cmd != NAND_CMD_NONE) { 285 if (ctrl & NAND_CLE) 286 writel(cmd, SLC_CMD(host->io_base)); 287 else 288 writel(cmd, SLC_ADDR(host->io_base)); 289 } 290} 291 292/* 293 * Read the Device Ready pin 294 */ 295static int lpc32xx_nand_device_ready(struct nand_chip *chip) 296{ 297 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 298 int rdy = 0; 299 300 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0) 301 rdy = 1; 302 303 return rdy; 304} 305 306/* 307 * Enable NAND write protect 308 */ 309static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) 310{ 311 if (host->wp_gpio) 312 gpiod_set_value_cansleep(host->wp_gpio, 1); 313} 314 315/* 316 * Disable NAND write protect 317 */ 318static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) 319{ 320 if (host->wp_gpio) 321 gpiod_set_value_cansleep(host->wp_gpio, 0); 322} 323 324/* 325 * Prepares SLC for transfers with H/W ECC enabled 326 */ 327static void lpc32xx_nand_ecc_enable(struct nand_chip *chip, int mode) 328{ 329 /* Hardware ECC is enabled automatically in hardware as needed */ 330} 331 332/* 333 * Calculates the ECC for the data 334 */ 335static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip, 336 const unsigned char *buf, 337 unsigned char *code) 338{ 339 /* 340 * ECC is calculated automatically in hardware during syndrome read 341 * and write operations, so it doesn't need to be calculated here. 342 */ 343 return 0; 344} 345 346/* 347 * Read a single byte from NAND device 348 */ 349static uint8_t lpc32xx_nand_read_byte(struct nand_chip *chip) 350{ 351 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 352 353 return (uint8_t)readl(SLC_DATA(host->io_base)); 354} 355 356/* 357 * Simple device read without ECC 358 */ 359static void lpc32xx_nand_read_buf(struct nand_chip *chip, u_char *buf, int len) 360{ 361 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 362 363 /* Direct device read with no ECC */ 364 while (len-- > 0) 365 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base)); 366} 367 368/* 369 * Simple device write without ECC 370 */ 371static void lpc32xx_nand_write_buf(struct nand_chip *chip, const uint8_t *buf, 372 int len) 373{ 374 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 375 376 /* Direct device write with no ECC */ 377 while (len-- > 0) 378 writel((uint32_t)*buf++, SLC_DATA(host->io_base)); 379} 380 381/* 382 * Read the OOB data from the device without ECC using FIFO method 383 */ 384static int lpc32xx_nand_read_oob_syndrome(struct nand_chip *chip, int page) 385{ 386 struct mtd_info *mtd = nand_to_mtd(chip); 387 388 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 389} 390 391/* 392 * Write the OOB data to the device without ECC using FIFO method 393 */ 394static int lpc32xx_nand_write_oob_syndrome(struct nand_chip *chip, int page) 395{ 396 struct mtd_info *mtd = nand_to_mtd(chip); 397 398 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, 399 mtd->oobsize); 400} 401 402/* 403 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC 404 */ 405static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) 406{ 407 int i; 408 409 for (i = 0; i < (count * 3); i += 3) { 410 uint32_t ce = ecc[i / 3]; 411 ce = ~(ce << 2) & 0xFFFFFF; 412 spare[i + 2] = (uint8_t)(ce & 0xFF); 413 ce >>= 8; 414 spare[i + 1] = (uint8_t)(ce & 0xFF); 415 ce >>= 8; 416 spare[i] = (uint8_t)(ce & 0xFF); 417 } 418} 419 420static void lpc32xx_dma_complete_func(void *completion) 421{ 422 complete(completion); 423} 424 425static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma, 426 void *mem, int len, enum dma_transfer_direction dir) 427{ 428 struct nand_chip *chip = mtd_to_nand(mtd); 429 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 430 struct dma_async_tx_descriptor *desc; 431 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 432 int res; 433 434 host->dma_slave_config.direction = dir; 435 host->dma_slave_config.src_addr = dma; 436 host->dma_slave_config.dst_addr = dma; 437 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 438 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 439 host->dma_slave_config.src_maxburst = 4; 440 host->dma_slave_config.dst_maxburst = 4; 441 /* DMA controller does flow control: */ 442 host->dma_slave_config.device_fc = false; 443 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { 444 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); 445 return -ENXIO; 446 } 447 448 sg_init_one(&host->sgl, mem, len); 449 450 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, 451 DMA_BIDIRECTIONAL); 452 if (res != 1) { 453 dev_err(mtd->dev.parent, "Failed to map sg list\n"); 454 return -ENXIO; 455 } 456 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, 457 flags); 458 if (!desc) { 459 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); 460 goto out1; 461 } 462 463 init_completion(&host->comp); 464 desc->callback = lpc32xx_dma_complete_func; 465 desc->callback_param = &host->comp; 466 467 dmaengine_submit(desc); 468 dma_async_issue_pending(host->dma_chan); 469 470 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000)); 471 472 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, 473 DMA_BIDIRECTIONAL); 474 475 return 0; 476out1: 477 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, 478 DMA_BIDIRECTIONAL); 479 return -ENXIO; 480} 481 482/* 483 * DMA read/write transfers with ECC support 484 */ 485static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages, 486 int read) 487{ 488 struct nand_chip *chip = mtd_to_nand(mtd); 489 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 490 int i, status = 0; 491 unsigned long timeout; 492 int res; 493 enum dma_transfer_direction dir = 494 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 495 uint8_t *dma_buf; 496 bool dma_mapped; 497 498 if ((void *)buf <= high_memory) { 499 dma_buf = buf; 500 dma_mapped = true; 501 } else { 502 dma_buf = host->data_buf; 503 dma_mapped = false; 504 if (!read) 505 memcpy(host->data_buf, buf, mtd->writesize); 506 } 507 508 if (read) { 509 writel(readl(SLC_CFG(host->io_base)) | 510 SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | 511 SLCCFG_DMA_BURST, SLC_CFG(host->io_base)); 512 } else { 513 writel((readl(SLC_CFG(host->io_base)) | 514 SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) & 515 ~SLCCFG_DMA_DIR, 516 SLC_CFG(host->io_base)); 517 } 518 519 /* Clear initial ECC */ 520 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base)); 521 522 /* Transfer size is data area only */ 523 writel(mtd->writesize, SLC_TC(host->io_base)); 524 525 /* Start transfer in the NAND controller */ 526 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START, 527 SLC_CTRL(host->io_base)); 528 529 for (i = 0; i < chip->ecc.steps; i++) { 530 /* Data */ 531 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma), 532 dma_buf + i * chip->ecc.size, 533 mtd->writesize / chip->ecc.steps, dir); 534 if (res) 535 return res; 536 537 /* Always _read_ ECC */ 538 if (i == chip->ecc.steps - 1) 539 break; 540 if (!read) /* ECC availability delayed on write */ 541 udelay(10); 542 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma), 543 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM); 544 if (res) 545 return res; 546 } 547 548 /* 549 * According to NXP, the DMA can be finished here, but the NAND 550 * controller may still have buffered data. After porting to using the 551 * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty) 552 * appears to be always true, according to tests. Keeping the check for 553 * safety reasons for now. 554 */ 555 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) { 556 dev_warn(mtd->dev.parent, "FIFO not empty!\n"); 557 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT); 558 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) && 559 time_before(jiffies, timeout)) 560 cpu_relax(); 561 if (!time_before(jiffies, timeout)) { 562 dev_err(mtd->dev.parent, "FIFO held data too long\n"); 563 status = -EIO; 564 } 565 } 566 567 /* Read last calculated ECC value */ 568 if (!read) 569 udelay(10); 570 host->ecc_buf[chip->ecc.steps - 1] = 571 readl(SLC_ECC(host->io_base)); 572 573 /* Flush DMA */ 574 dmaengine_terminate_all(host->dma_chan); 575 576 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO || 577 readl(SLC_TC(host->io_base))) { 578 /* Something is left in the FIFO, something is wrong */ 579 dev_err(mtd->dev.parent, "DMA FIFO failure\n"); 580 status = -EIO; 581 } 582 583 /* Stop DMA & HW ECC */ 584 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START, 585 SLC_CTRL(host->io_base)); 586 writel(readl(SLC_CFG(host->io_base)) & 587 ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | 588 SLCCFG_DMA_BURST), SLC_CFG(host->io_base)); 589 590 if (!dma_mapped && read) 591 memcpy(buf, host->data_buf, mtd->writesize); 592 593 return status; 594} 595 596/* 597 * Read the data and OOB data from the device, use ECC correction with the 598 * data, disable ECC for the OOB data 599 */ 600static int lpc32xx_nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf, 601 int oob_required, int page) 602{ 603 struct mtd_info *mtd = nand_to_mtd(chip); 604 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 605 struct mtd_oob_region oobregion = { }; 606 int stat, i, status, error; 607 uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE]; 608 609 /* Issue read command */ 610 nand_read_page_op(chip, page, 0, NULL, 0); 611 612 /* Read data and oob, calculate ECC */ 613 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1); 614 615 /* Get OOB data */ 616 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize); 617 618 /* Convert to stored ECC format */ 619 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps); 620 621 /* Pointer to ECC data retrieved from NAND spare area */ 622 error = mtd_ooblayout_ecc(mtd, 0, &oobregion); 623 if (error) 624 return error; 625 626 oobecc = chip->oob_poi + oobregion.offset; 627 628 for (i = 0; i < chip->ecc.steps; i++) { 629 stat = chip->ecc.correct(chip, buf, oobecc, 630 &tmpecc[i * chip->ecc.bytes]); 631 if (stat < 0) 632 mtd->ecc_stats.failed++; 633 else 634 mtd->ecc_stats.corrected += stat; 635 636 buf += chip->ecc.size; 637 oobecc += chip->ecc.bytes; 638 } 639 640 return status; 641} 642 643/* 644 * Read the data and OOB data from the device, no ECC correction with the 645 * data or OOB data 646 */ 647static int lpc32xx_nand_read_page_raw_syndrome(struct nand_chip *chip, 648 uint8_t *buf, int oob_required, 649 int page) 650{ 651 struct mtd_info *mtd = nand_to_mtd(chip); 652 653 /* Issue read command */ 654 nand_read_page_op(chip, page, 0, NULL, 0); 655 656 /* Raw reads can just use the FIFO interface */ 657 chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps); 658 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize); 659 660 return 0; 661} 662 663/* 664 * Write the data and OOB data to the device, use ECC with the data, 665 * disable ECC for the OOB data 666 */ 667static int lpc32xx_nand_write_page_syndrome(struct nand_chip *chip, 668 const uint8_t *buf, 669 int oob_required, int page) 670{ 671 struct mtd_info *mtd = nand_to_mtd(chip); 672 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 673 struct mtd_oob_region oobregion = { }; 674 uint8_t *pb; 675 int error; 676 677 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 678 679 /* Write data, calculate ECC on outbound data */ 680 error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0); 681 if (error) 682 return error; 683 684 /* 685 * The calculated ECC needs some manual work done to it before 686 * committing it to NAND. Process the calculated ECC and place 687 * the resultant values directly into the OOB buffer. */ 688 error = mtd_ooblayout_ecc(mtd, 0, &oobregion); 689 if (error) 690 return error; 691 692 pb = chip->oob_poi + oobregion.offset; 693 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps); 694 695 /* Write ECC data to device */ 696 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); 697 698 return nand_prog_page_end_op(chip); 699} 700 701/* 702 * Write the data and OOB data to the device, no ECC correction with the 703 * data or OOB data 704 */ 705static int lpc32xx_nand_write_page_raw_syndrome(struct nand_chip *chip, 706 const uint8_t *buf, 707 int oob_required, int page) 708{ 709 struct mtd_info *mtd = nand_to_mtd(chip); 710 711 /* Raw writes can just use the FIFO interface */ 712 nand_prog_page_begin_op(chip, page, 0, buf, 713 chip->ecc.size * chip->ecc.steps); 714 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); 715 716 return nand_prog_page_end_op(chip); 717} 718 719static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) 720{ 721 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip); 722 dma_cap_mask_t mask; 723 724 host->dma_chan = dma_request_chan(mtd->dev.parent, "rx-tx"); 725 if (IS_ERR(host->dma_chan)) { 726 /* fallback to request using platform data */ 727 if (!host->pdata || !host->pdata->dma_filter) { 728 dev_err(mtd->dev.parent, "no DMA platform data\n"); 729 return -ENOENT; 730 } 731 732 dma_cap_zero(mask); 733 dma_cap_set(DMA_SLAVE, mask); 734 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, "nand-slc"); 735 736 if (!host->dma_chan) { 737 dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); 738 return -EBUSY; 739 } 740 } 741 742 return 0; 743} 744 745static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) 746{ 747 struct lpc32xx_nand_cfg_slc *ncfg; 748 struct device_node *np = dev->of_node; 749 750 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL); 751 if (!ncfg) 752 return NULL; 753 754 of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks); 755 of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth); 756 of_property_read_u32(np, "nxp,whold", &ncfg->whold); 757 of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup); 758 of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks); 759 of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth); 760 of_property_read_u32(np, "nxp,rhold", &ncfg->rhold); 761 of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup); 762 763 if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold || 764 !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth || 765 !ncfg->rhold || !ncfg->rsetup) { 766 dev_err(dev, "chip parameters not specified correctly\n"); 767 return NULL; 768 } 769 770 return ncfg; 771} 772 773static int lpc32xx_nand_attach_chip(struct nand_chip *chip) 774{ 775 struct mtd_info *mtd = nand_to_mtd(chip); 776 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 777 778 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 779 return 0; 780 781 /* OOB and ECC CPU and DMA work areas */ 782 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE); 783 784 /* 785 * Small page FLASH has a unique OOB layout, but large and huge 786 * page FLASH use the standard layout. Small page FLASH uses a 787 * custom BBT marker layout. 788 */ 789 if (mtd->writesize <= 512) 790 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops); 791 792 chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 793 /* These sizes remain the same regardless of page size */ 794 chip->ecc.size = 256; 795 chip->ecc.strength = 1; 796 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES; 797 chip->ecc.prepad = 0; 798 chip->ecc.postpad = 0; 799 chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome; 800 chip->ecc.read_page = lpc32xx_nand_read_page_syndrome; 801 chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome; 802 chip->ecc.write_page = lpc32xx_nand_write_page_syndrome; 803 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; 804 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; 805 chip->ecc.calculate = lpc32xx_nand_ecc_calculate; 806 chip->ecc.correct = rawnand_sw_hamming_correct; 807 chip->ecc.hwctl = lpc32xx_nand_ecc_enable; 808 809 /* 810 * Use a custom BBT marker setup for small page FLASH that 811 * won't interfere with the ECC layout. Large and huge page 812 * FLASH use the standard layout. 813 */ 814 if ((chip->bbt_options & NAND_BBT_USE_FLASH) && 815 mtd->writesize <= 512) { 816 chip->bbt_td = &bbt_smallpage_main_descr; 817 chip->bbt_md = &bbt_smallpage_mirror_descr; 818 } 819 820 return 0; 821} 822 823static const struct nand_controller_ops lpc32xx_nand_controller_ops = { 824 .attach_chip = lpc32xx_nand_attach_chip, 825}; 826 827/* 828 * Probe for NAND controller 829 */ 830static int lpc32xx_nand_probe(struct platform_device *pdev) 831{ 832 struct lpc32xx_nand_host *host; 833 struct mtd_info *mtd; 834 struct nand_chip *chip; 835 struct resource *rc; 836 int res; 837 838 /* Allocate memory for the device structure (and zero it) */ 839 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 840 if (!host) 841 return -ENOMEM; 842 843 host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc); 844 if (IS_ERR(host->io_base)) 845 return PTR_ERR(host->io_base); 846 847 host->io_base_dma = rc->start; 848 if (pdev->dev.of_node) 849 host->ncfg = lpc32xx_parse_dt(&pdev->dev); 850 if (!host->ncfg) { 851 dev_err(&pdev->dev, 852 "Missing or bad NAND config from device tree\n"); 853 return -ENOENT; 854 } 855 856 /* Start with WP disabled, if available */ 857 host->wp_gpio = devm_gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW); 858 res = PTR_ERR_OR_ZERO(host->wp_gpio); 859 if (res) { 860 if (res != -EPROBE_DEFER) 861 dev_err(&pdev->dev, "WP GPIO is not available: %d\n", 862 res); 863 return res; 864 } 865 866 gpiod_set_consumer_name(host->wp_gpio, "NAND WP"); 867 868 host->pdata = dev_get_platdata(&pdev->dev); 869 870 chip = &host->nand_chip; 871 mtd = nand_to_mtd(chip); 872 nand_set_controller_data(chip, host); 873 nand_set_flash_node(chip, pdev->dev.of_node); 874 mtd->owner = THIS_MODULE; 875 mtd->dev.parent = &pdev->dev; 876 877 /* Get NAND clock */ 878 host->clk = devm_clk_get_enabled(&pdev->dev, NULL); 879 if (IS_ERR(host->clk)) { 880 dev_err(&pdev->dev, "Clock failure\n"); 881 res = -ENOENT; 882 goto enable_wp; 883 } 884 885 /* Set NAND IO addresses and command/ready functions */ 886 chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base); 887 chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base); 888 chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl; 889 chip->legacy.dev_ready = lpc32xx_nand_device_ready; 890 chip->legacy.chip_delay = 20; /* 20us command delay time */ 891 892 /* Init NAND controller */ 893 lpc32xx_nand_setup(host); 894 895 platform_set_drvdata(pdev, host); 896 897 /* NAND callbacks for LPC32xx SLC hardware */ 898 chip->legacy.read_byte = lpc32xx_nand_read_byte; 899 chip->legacy.read_buf = lpc32xx_nand_read_buf; 900 chip->legacy.write_buf = lpc32xx_nand_write_buf; 901 902 /* 903 * Allocate a large enough buffer for a single huge page plus 904 * extra space for the spare area and ECC storage area 905 */ 906 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE; 907 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len, 908 GFP_KERNEL); 909 if (host->data_buf == NULL) { 910 res = -ENOMEM; 911 goto enable_wp; 912 } 913 914 res = lpc32xx_nand_dma_setup(host); 915 if (res) { 916 res = -EIO; 917 goto enable_wp; 918 } 919 920 /* Find NAND device */ 921 chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops; 922 res = nand_scan(chip, 1); 923 if (res) 924 goto release_dma; 925 926 mtd->name = "nxp_lpc3220_slc"; 927 res = mtd_device_register(mtd, host->ncfg->parts, 928 host->ncfg->num_parts); 929 if (res) 930 goto cleanup_nand; 931 932 return 0; 933 934cleanup_nand: 935 nand_cleanup(chip); 936release_dma: 937 dma_release_channel(host->dma_chan); 938enable_wp: 939 lpc32xx_wp_enable(host); 940 941 return res; 942} 943 944/* 945 * Remove NAND device. 946 */ 947static void lpc32xx_nand_remove(struct platform_device *pdev) 948{ 949 uint32_t tmp; 950 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 951 struct nand_chip *chip = &host->nand_chip; 952 int ret; 953 954 ret = mtd_device_unregister(nand_to_mtd(chip)); 955 WARN_ON(ret); 956 nand_cleanup(chip); 957 dma_release_channel(host->dma_chan); 958 959 /* Force CE high */ 960 tmp = readl(SLC_CTRL(host->io_base)); 961 tmp &= ~SLCCFG_CE_LOW; 962 writel(tmp, SLC_CTRL(host->io_base)); 963 964 lpc32xx_wp_enable(host); 965} 966 967static int lpc32xx_nand_resume(struct platform_device *pdev) 968{ 969 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 970 int ret; 971 972 /* Re-enable NAND clock */ 973 ret = clk_prepare_enable(host->clk); 974 if (ret) 975 return ret; 976 977 /* Fresh init of NAND controller */ 978 lpc32xx_nand_setup(host); 979 980 /* Disable write protect */ 981 lpc32xx_wp_disable(host); 982 983 return 0; 984} 985 986static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) 987{ 988 uint32_t tmp; 989 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 990 991 /* Force CE high */ 992 tmp = readl(SLC_CTRL(host->io_base)); 993 tmp &= ~SLCCFG_CE_LOW; 994 writel(tmp, SLC_CTRL(host->io_base)); 995 996 /* Enable write protect for safety */ 997 lpc32xx_wp_enable(host); 998 999 /* Disable clock */ 1000 clk_disable_unprepare(host->clk); 1001 1002 return 0; 1003} 1004 1005static const struct of_device_id lpc32xx_nand_match[] = { 1006 { .compatible = "nxp,lpc3220-slc" }, 1007 { /* sentinel */ }, 1008}; 1009MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); 1010 1011static struct platform_driver lpc32xx_nand_driver = { 1012 .probe = lpc32xx_nand_probe, 1013 .remove = lpc32xx_nand_remove, 1014 .resume = pm_ptr(lpc32xx_nand_resume), 1015 .suspend = pm_ptr(lpc32xx_nand_suspend), 1016 .driver = { 1017 .name = LPC32XX_MODNAME, 1018 .of_match_table = lpc32xx_nand_match, 1019 }, 1020}; 1021 1022module_platform_driver(lpc32xx_nand_driver); 1023 1024MODULE_LICENSE("GPL"); 1025MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 1026MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 1027MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
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