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tmio_mmc.h

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linux-6.19.14/drivers/mmc/host/tmio_mmc.h C 
  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Driver for the MMC / SD / SDIO cell found in:
  4 *
  5 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
  6 *
  7 * Copyright (C) 2015-19 Renesas Electronics Corporation
  8 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
  9 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
 10 * Copyright (C) 2007 Ian Molton
 11 * Copyright (C) 2004 Ian Molton
 12 */
 13
 14#ifndef TMIO_MMC_H
 15#define TMIO_MMC_H
 16
 17#include <linux/dmaengine.h>
 18#include <linux/highmem.h>
 19#include <linux/io.h>
 20#include <linux/mutex.h>
 21#include <linux/pagemap.h>
 22#include <linux/scatterlist.h>
 23#include <linux/spinlock.h>
 24#include <linux/interrupt.h>
 25#include <linux/workqueue.h>
 26
 27#define CTL_SD_CMD 0x00
 28#define CTL_ARG_REG 0x04
 29#define CTL_STOP_INTERNAL_ACTION 0x08
 30#define CTL_XFER_BLK_COUNT 0xa
 31#define CTL_RESPONSE 0x0c
 32/* driver merges STATUS and following STATUS2 */
 33#define CTL_STATUS 0x1c
 34/* driver merges IRQ_MASK and following IRQ_MASK2 */
 35#define CTL_IRQ_MASK 0x20
 36#define CTL_SD_CARD_CLK_CTL 0x24
 37#define CTL_SD_XFER_LEN 0x26
 38#define CTL_SD_MEM_CARD_OPT 0x28
 39#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
 40#define CTL_SD_DATA_PORT 0x30
 41#define CTL_TRANSACTION_CTL 0x34
 42#define CTL_SDIO_STATUS 0x36
 43#define CTL_SDIO_IRQ_MASK 0x38
 44#define CTL_DMA_ENABLE 0xd8
 45#define CTL_RESET_SD 0xe0
 46#define CTL_VERSION 0xe2
 47#define CTL_SDIF_MODE 0xe6 /* only known on R-Car 2+ */
 48#define CTL_SD_STATUS 0xf2 /* only known on RZ/{G2L,G3E,V2H} */
 49
 50/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
 51#define TMIO_STOP_STP		BIT(0)
 52#define TMIO_STOP_SEC		BIT(8)
 53
 54/* Definitions for values the CTL_STATUS register can take */
 55#define TMIO_STAT_CMDRESPEND    BIT(0)
 56#define TMIO_STAT_DATAEND       BIT(2)
 57#define TMIO_STAT_CARD_REMOVE   BIT(3)
 58#define TMIO_STAT_CARD_INSERT   BIT(4)
 59#define TMIO_STAT_SIGSTATE      BIT(5)
 60#define TMIO_STAT_WRPROTECT     BIT(7)
 61#define TMIO_STAT_CARD_REMOVE_A BIT(8)
 62#define TMIO_STAT_CARD_INSERT_A BIT(9)
 63#define TMIO_STAT_SIGSTATE_A    BIT(10)
 64
 65/* These belong technically to CTL_STATUS2, but the driver merges them */
 66#define TMIO_STAT_CMD_IDX_ERR   BIT(16)
 67#define TMIO_STAT_CRCFAIL       BIT(17)
 68#define TMIO_STAT_STOPBIT_ERR   BIT(18)
 69#define TMIO_STAT_DATATIMEOUT   BIT(19)
 70#define TMIO_STAT_RXOVERFLOW    BIT(20)
 71#define TMIO_STAT_TXUNDERRUN    BIT(21)
 72#define TMIO_STAT_CMDTIMEOUT    BIT(22)
 73#define TMIO_STAT_DAT0		BIT(23)	/* only known on R-Car so far */
 74#define TMIO_STAT_RXRDY         BIT(24)
 75#define TMIO_STAT_TXRQ          BIT(25)
 76#define TMIO_STAT_ALWAYS_SET_27	BIT(27) /* only known on R-Car 2+ so far */
 77#define TMIO_STAT_ILL_FUNC      BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
 78#define TMIO_STAT_SCLKDIVEN     BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
 79#define TMIO_STAT_CMD_BUSY      BIT(30)
 80#define TMIO_STAT_ILL_ACCESS    BIT(31)
 81
 82/* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
 83#define	CLK_CTL_DIV_MASK	0xff
 84#define	CLK_CTL_SCLKEN		BIT(8)
 85
 86/* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
 87#define CARD_OPT_TOP_MASK	0xf0
 88#define CARD_OPT_TOP_SHIFT	4
 89#define CARD_OPT_EXTOP		BIT(9) /* first appeared on R-Car Gen3 SDHI */
 90#define CARD_OPT_WIDTH8		BIT(13)
 91#define CARD_OPT_ALWAYS1	BIT(14)
 92#define CARD_OPT_WIDTH		BIT(15)
 93
 94/* Definitions for values the CTL_SDIO_STATUS register can take */
 95#define TMIO_SDIO_STAT_IOIRQ	0x0001
 96#define TMIO_SDIO_STAT_EXPUB52	0x4000
 97#define TMIO_SDIO_STAT_EXWT	0x8000
 98#define TMIO_SDIO_MASK_ALL	0xc007
 99
100#define TMIO_SDIO_SETBITS_MASK	0x0006
101
102/* Definitions for values the CTL_DMA_ENABLE register can take */
103#define DMA_ENABLE_DMASDRW	BIT(1)
104
105/* Definitions for values the CTL_SDIF_MODE register can take */
106#define SDIF_MODE_HS400		BIT(0) /* only known on R-Car 2+ */
107
108/* Definitions for values the CTL_SD_STATUS register can take */
109#define SD_STATUS_PWEN		BIT(0) /* only known on RZ/{G3E,V2H} */
110#define SD_STATUS_IOVS		BIT(16) /* only known on RZ/{G3E,V2H} */
111
112/* Define some IRQ masks */
113/* This is the mask used at reset by the chip */
114#define TMIO_MASK_ALL           0x837f031d
115#define TMIO_MASK_ALL_RCAR2	0x8b7f031d
116#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
117#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
118#define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
119		TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
120#define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
121
122#define TMIO_MAX_BLK_SIZE 512
123
124struct tmio_mmc_data;
125struct tmio_mmc_host;
126
127struct tmio_mmc_dma_ops {
128	void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
129	void (*enable)(struct tmio_mmc_host *host, bool enable);
130	void (*request)(struct tmio_mmc_host *host,
131			struct tmio_mmc_data *pdata);
132	void (*release)(struct tmio_mmc_host *host);
133	void (*abort)(struct tmio_mmc_host *host);
134	void (*dataend)(struct tmio_mmc_host *host);
135
136	/* optional */
137	void (*end)(struct tmio_mmc_host *host);	/* held host->lock */
138	bool (*dma_irq)(struct tmio_mmc_host *host);
139};
140
141struct tmio_mmc_host {
142	void __iomem *ctl;
143	struct mmc_command      *cmd;
144	struct mmc_request      *mrq;
145	struct mmc_data         *data;
146	struct mmc_host         *mmc;
147	struct mmc_host_ops     ops;
148
149	/* pio related stuff */
150	struct scatterlist      *sg_ptr;
151	struct scatterlist      *sg_orig;
152	unsigned int            sg_len;
153	unsigned int            sg_off;
154	unsigned int		bus_shift;
155
156	struct platform_device *pdev;
157	struct tmio_mmc_data *pdata;
158
159	/* DMA support */
160	bool			dma_on;
161	struct dma_chan		*chan_rx;
162	struct dma_chan		*chan_tx;
163	struct work_struct	dma_issue;
164	struct scatterlist	bounce_sg;
165	u8			*bounce_buf;
166
167	/* Track lost interrupts */
168	struct delayed_work	delayed_reset_work;
169	struct work_struct	done;
170
171	/* Cache */
172	u32			sdcard_irq_mask;
173	u32			sdio_irq_mask;
174	unsigned int		clk_cache;
175	u32			sdcard_irq_setbit_mask;
176	u32			sdcard_irq_mask_all;
177
178	spinlock_t		lock;		/* protect host private data */
179	unsigned long		last_req_ts;
180	struct mutex		ios_lock;	/* protect set_ios() context */
181	bool			native_hotplug;
182	bool			sdio_irq_enabled;
183
184	/* Mandatory callback */
185	int (*clk_enable)(struct tmio_mmc_host *host);
186	void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
187
188	/* Optional callbacks */
189	void (*clk_disable)(struct tmio_mmc_host *host);
190	int (*multi_io_quirk)(struct mmc_card *card,
191			      unsigned int direction, int blk_size);
192	int (*write16_hook)(struct tmio_mmc_host *host, int addr);
193	void (*reset)(struct tmio_mmc_host *host, bool preserve);
194	bool (*check_retune)(struct tmio_mmc_host *host, struct mmc_request *mrq);
195	void (*fixup_request)(struct tmio_mmc_host *host, struct mmc_request *mrq);
196	unsigned int (*get_timeout_cycles)(struct tmio_mmc_host *host);
197	void (*sdio_irq)(struct tmio_mmc_host *host);
198
199	const struct tmio_mmc_dma_ops *dma_ops;
200};
201
202struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
203					  struct tmio_mmc_data *pdata);
204int tmio_mmc_host_probe(struct tmio_mmc_host *host);
205void tmio_mmc_host_remove(struct tmio_mmc_host *host);
206void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
207
208void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
209void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
210irqreturn_t tmio_mmc_irq(int irq, void *devid);
211
212int tmio_mmc_host_runtime_suspend(struct device *dev);
213int tmio_mmc_host_runtime_resume(struct device *dev);
214
215static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
216{
217	return ioread16(host->ctl + (addr << host->bus_shift));
218}
219
220static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
221				      u16 *buf, int count)
222{
223	ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
224}
225
226static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
227					      int addr)
228{
229	return ioread16(host->ctl + (addr << host->bus_shift)) |
230	       ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
231}
232
233static inline u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
234{
235	return ioread32(host->ctl + (addr << host->bus_shift));
236}
237
238static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
239				      u32 *buf, int count)
240{
241	ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
242}
243
244#ifdef CONFIG_64BIT
245static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
246				      u64 *buf, int count)
247{
248	readsq(host->ctl + (addr << host->bus_shift), buf, count);
249}
250
251static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
252				       const u64 *buf, int count)
253{
254	writesq(host->ctl + (addr << host->bus_shift), buf, count);
255}
256#endif
257
258static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
259				   u16 val)
260{
261	/* If there is a hook and it returns non-zero then there
262	 * is an error and the write should be skipped
263	 */
264	if (host->write16_hook && host->write16_hook(host, addr))
265		return;
266	iowrite16(val, host->ctl + (addr << host->bus_shift));
267}
268
269static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
270				       u16 *buf, int count)
271{
272	iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
273}
274
275static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
276						int addr, u32 val)
277{
278	if (addr == CTL_IRQ_MASK || addr == CTL_STATUS)
279		val |= host->sdcard_irq_setbit_mask;
280
281	iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
282	iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
283}
284
285static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
286{
287	iowrite32(val, host->ctl + (addr << host->bus_shift));
288}
289
290static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
291				       const u32 *buf, int count)
292{
293	iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
294}
295
296#endif
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