sdhci_f_sdh30.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * linux/drivers/mmc/host/sdhci_f_sdh30.c
  4 *
  5 * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
  6 *              Vincent Yang <vincent.yang@tw.fujitsu.com>
  7 * Copyright (C) 2015 Linaro Ltd  Andy Green <andy.green@linaro.org>
  8 * Copyright (C) 2019 Socionext Inc.
  9 */
 10
 11#include <linux/acpi.h>
 12#include <linux/err.h>
 13#include <linux/delay.h>
 14#include <linux/module.h>
 15#include <linux/of.h>
 16#include <linux/property.h>
 17#include <linux/clk.h>
 18#include <linux/reset.h>
 19
 20#include "sdhci-pltfm.h"
 21#include "sdhci_f_sdh30.h"
 22
 23struct f_sdhost_priv {
 24	struct clk *clk_iface;
 25	struct clk *clk;
 26	struct reset_control *rst;
 27	u32 vendor_hs200;
 28	struct device *dev;
 29	bool enable_cmd_dat_delay;
 30};
 31
 32static void *sdhci_f_sdhost_priv(struct sdhci_host *host)
 33{
 34	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 35
 36	return sdhci_pltfm_priv(pltfm_host);
 37}
 38
 39static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
 40{
 41	struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
 42	u32 ctrl = 0;
 43
 44	usleep_range(2500, 3000);
 45	ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
 46	ctrl |= F_SDH30_CRES_O_DN;
 47	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
 48	ctrl |= F_SDH30_MSEL_O_1_8;
 49	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
 50
 51	ctrl &= ~F_SDH30_CRES_O_DN;
 52	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
 53	usleep_range(2500, 3000);
 54
 55	if (priv->vendor_hs200) {
 56		dev_info(priv->dev, "%s: setting hs200\n", __func__);
 57		ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
 58		ctrl |= priv->vendor_hs200;
 59		sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
 60	}
 61
 62	ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
 63	ctrl |= F_SDH30_CMD_CHK_DIS;
 64	sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
 65}
 66
 67static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
 68{
 69	return F_SDH30_MIN_CLOCK;
 70}
 71
 72static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
 73{
 74	struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
 75	u32 ctl;
 76
 77	if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
 78		sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
 79
 80	sdhci_reset(host, mask);
 81
 82	if (priv->enable_cmd_dat_delay) {
 83		ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
 84		ctl |= F_SDH30_CMD_DAT_DELAY;
 85		sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
 86	}
 87
 88	if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) &&
 89	    !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 90		ctl = sdhci_readl(host, F_SDH30_TEST);
 91		ctl |= F_SDH30_FORCE_CARD_INSERT;
 92		sdhci_writel(host, ctl, F_SDH30_TEST);
 93	}
 94}
 95
 96static const struct sdhci_ops sdhci_f_sdh30_ops = {
 97	.voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
 98	.get_min_clock = sdhci_f_sdh30_get_min_clock,
 99	.reset = sdhci_f_sdh30_reset,
100	.set_clock = sdhci_set_clock,
101	.set_bus_width = sdhci_set_bus_width,
102	.set_uhs_signaling = sdhci_set_uhs_signaling,
103};
104
105static const struct sdhci_pltfm_data sdhci_f_sdh30_pltfm_data = {
106	.ops = &sdhci_f_sdh30_ops,
107	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
108		| SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
109	.quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE
110		|  SDHCI_QUIRK2_TUNING_WORK_AROUND,
111};
112
113static int sdhci_f_sdh30_probe(struct platform_device *pdev)
114{
115	struct sdhci_host *host;
116	struct device *dev = &pdev->dev;
117	int ctrl = 0, ret = 0;
118	struct f_sdhost_priv *priv;
119	struct sdhci_pltfm_host *pltfm_host;
120	u32 reg = 0;
121
122	host = sdhci_pltfm_init(pdev, &sdhci_f_sdh30_pltfm_data,
123				sizeof(struct f_sdhost_priv));
124	if (IS_ERR(host))
125		return PTR_ERR(host);
126
127	pltfm_host = sdhci_priv(host);
128	priv = sdhci_pltfm_priv(pltfm_host);
129	priv->dev = dev;
130
131	priv->enable_cmd_dat_delay = device_property_read_bool(dev,
132						"fujitsu,cmd-dat-delay-select");
133
134	ret = mmc_of_parse(host->mmc);
135	if (ret)
136		return ret;
137
138	if (dev_of_node(dev)) {
139		sdhci_get_of_property(pdev);
140
141		priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
142		if (IS_ERR(priv->clk_iface))
143			return PTR_ERR(priv->clk_iface);
144
145		ret = clk_prepare_enable(priv->clk_iface);
146		if (ret)
147			return ret;
148
149		priv->clk = devm_clk_get(&pdev->dev, "core");
150		if (IS_ERR(priv->clk)) {
151			ret = PTR_ERR(priv->clk);
152			goto err_clk;
153		}
154
155		ret = clk_prepare_enable(priv->clk);
156		if (ret)
157			goto err_clk;
158
159		priv->rst = devm_reset_control_get_optional_shared(dev, NULL);
160		if (IS_ERR(priv->rst)) {
161			ret = PTR_ERR(priv->rst);
162			goto err_rst;
163		}
164
165		ret = reset_control_deassert(priv->rst);
166		if (ret)
167			goto err_rst;
168	}
169
170	/* init vendor specific regs */
171	ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
172	ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
173		F_SDH30_AHB_INCR_4;
174	ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
175	sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
176
177	reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
178	sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
179	msleep(20);
180	sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
181
182	reg = sdhci_readl(host, SDHCI_CAPABILITIES);
183	if (reg & SDHCI_CAN_DO_8BIT)
184		priv->vendor_hs200 = F_SDH30_EMMC_HS200;
185
186	if (!(reg & SDHCI_TIMEOUT_CLK_MASK))
187		host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
188
189	ret = sdhci_add_host(host);
190	if (ret)
191		goto err_add_host;
192
193	return 0;
194
195err_add_host:
196	reset_control_assert(priv->rst);
197err_rst:
198	clk_disable_unprepare(priv->clk);
199err_clk:
200	clk_disable_unprepare(priv->clk_iface);
201	return ret;
202}
203
204static void sdhci_f_sdh30_remove(struct platform_device *pdev)
205{
206	struct sdhci_host *host = platform_get_drvdata(pdev);
207	struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
208	struct clk *clk_iface = priv->clk_iface;
209	struct reset_control *rst = priv->rst;
210	struct clk *clk = priv->clk;
211
212	sdhci_pltfm_remove(pdev);
213
214	reset_control_assert(rst);
215	clk_disable_unprepare(clk);
216	clk_disable_unprepare(clk_iface);
217}
218
219#ifdef CONFIG_OF
220static const struct of_device_id f_sdh30_dt_ids[] = {
221	{ .compatible = "fujitsu,mb86s70-sdhci-3.0" },
222	{ .compatible = "socionext,f-sdh30-e51-mmc" },
223	{ /* sentinel */ }
224};
225MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
226#endif
227
228#ifdef CONFIG_ACPI
229static const struct acpi_device_id f_sdh30_acpi_ids[] = {
230	{ "SCX0002" },
231	{ /* sentinel */ }
232};
233MODULE_DEVICE_TABLE(acpi, f_sdh30_acpi_ids);
234#endif
235
236static struct platform_driver sdhci_f_sdh30_driver = {
237	.driver = {
238		.name = "f_sdh30",
239		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
240		.of_match_table = of_match_ptr(f_sdh30_dt_ids),
241		.acpi_match_table = ACPI_PTR(f_sdh30_acpi_ids),
242		.pm	= &sdhci_pltfm_pmops,
243	},
244	.probe = sdhci_f_sdh30_probe,
245	.remove = sdhci_f_sdh30_remove,
246};
247
248module_platform_driver(sdhci_f_sdh30_driver);
249
250MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
251MODULE_LICENSE("GPL v2");
252MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD., Socionext Inc.");
253MODULE_ALIAS("platform:f_sdh30");