sdhci-xenon.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Driver for Marvell Xenon SDHC as a platform device
  4 *
  5 * Copyright (C) 2016 Marvell, All Rights Reserved.
  6 *
  7 * Author:	Hu Ziji <huziji@marvell.com>
  8 * Date:	2016-8-24
  9 *
 10 * Inspired by Jisheng Zhang <jszhang@marvell.com>
 11 * Special thanks to Video BG4 project team.
 12 */
 13
 14#include <linux/acpi.h>
 15#include <linux/delay.h>
 16#include <linux/ktime.h>
 17#include <linux/module.h>
 18#include <linux/of.h>
 19#include <linux/pm.h>
 20#include <linux/pm_runtime.h>
 21#include <linux/mm.h>
 22#include <linux/dma-mapping.h>
 23
 24#include "sdhci-pltfm.h"
 25#include "sdhci-xenon.h"
 26
 27static int xenon_enable_internal_clk(struct sdhci_host *host)
 28{
 29	u32 reg;
 30	ktime_t timeout;
 31
 32	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
 33	reg |= SDHCI_CLOCK_INT_EN;
 34	sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
 35	/* Wait max 20 ms */
 36	timeout = ktime_add_ms(ktime_get(), 20);
 37	while (1) {
 38		bool timedout = ktime_after(ktime_get(), timeout);
 39
 40		reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 41		if (reg & SDHCI_CLOCK_INT_STABLE)
 42			break;
 43		if (timedout) {
 44			dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
 45			return -ETIMEDOUT;
 46		}
 47		usleep_range(900, 1100);
 48	}
 49
 50	return 0;
 51}
 52
 53/* Set SDCLK-off-while-idle */
 54static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
 55				     unsigned char sdhc_id, bool enable)
 56{
 57	u32 reg;
 58	u32 mask;
 59
 60	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
 61	/* Get the bit shift basing on the SDHC index */
 62	mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
 63	if (enable)
 64		reg |= mask;
 65	else
 66		reg &= ~mask;
 67
 68	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
 69}
 70
 71/* Enable/Disable the Auto Clock Gating function */
 72static void xenon_set_acg(struct sdhci_host *host, bool enable)
 73{
 74	u32 reg;
 75
 76	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
 77	if (enable)
 78		reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
 79	else
 80		reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
 81	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
 82}
 83
 84/* Enable this SDHC */
 85static void xenon_enable_sdhc(struct sdhci_host *host,
 86			      unsigned char sdhc_id)
 87{
 88	u32 reg;
 89
 90	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
 91	reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
 92	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
 93
 94	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
 95	/*
 96	 * Force to clear BUS_TEST to
 97	 * skip bus_test_pre and bus_test_post
 98	 */
 99	host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
100}
101
102/* Disable this SDHC */
103static void xenon_disable_sdhc(struct sdhci_host *host,
104			       unsigned char sdhc_id)
105{
106	u32 reg;
107
108	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
109	reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
110	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
111}
112
113/* Enable Parallel Transfer Mode */
114static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
115					    unsigned char sdhc_id)
116{
117	u32 reg;
118
119	reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
120	reg |= BIT(sdhc_id);
121	sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
122}
123
124/* Mask command conflict error */
125static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
126{
127	u32  reg;
128
129	reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
130	reg |= XENON_MASK_CMD_CONFLICT_ERR;
131	sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
132}
133
134static void xenon_retune_setup(struct sdhci_host *host)
135{
136	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
137	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
138	u32 reg;
139
140	/* Disable the Re-Tuning Request functionality */
141	reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
142	reg &= ~XENON_RETUNING_COMPATIBLE;
143	sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
144
145	/* Disable the Re-tuning Interrupt */
146	reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
147	reg &= ~SDHCI_INT_RETUNE;
148	sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
149	reg = sdhci_readl(host, SDHCI_INT_ENABLE);
150	reg &= ~SDHCI_INT_RETUNE;
151	sdhci_writel(host, reg, SDHCI_INT_ENABLE);
152
153	/* Force to use Tuning Mode 1 */
154	host->tuning_mode = SDHCI_TUNING_MODE_1;
155	/* Set re-tuning period */
156	host->tuning_count = 1 << (priv->tuning_count - 1);
157}
158
159/*
160 * Operations inside struct sdhci_ops
161 */
162/* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
163static void xenon_reset_exit(struct sdhci_host *host,
164			     unsigned char sdhc_id, u8 mask)
165{
166	/* Only SOFTWARE RESET ALL will clear the register setting */
167	if (!(mask & SDHCI_RESET_ALL))
168		return;
169
170	/* Disable tuning request and auto-retuning again */
171	xenon_retune_setup(host);
172
173	/*
174	 * The ACG should be turned off at the early init time, in order
175	 * to solve a possible issues with the 1.8V regulator stabilization.
176	 * The feature is enabled in later stage.
177	 */
178	xenon_set_acg(host, false);
179
180	xenon_set_sdclk_off_idle(host, sdhc_id, false);
181
182	xenon_mask_cmd_conflict_err(host);
183}
184
185static void xenon_reset(struct sdhci_host *host, u8 mask)
186{
187	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
188	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
189
190	sdhci_reset(host, mask);
191	xenon_reset_exit(host, priv->sdhc_id, mask);
192}
193
194/*
195 * Xenon defines different values for HS200 and HS400
196 * in Host_Control_2
197 */
198static void xenon_set_uhs_signaling(struct sdhci_host *host,
199				    unsigned int timing)
200{
201	u16 ctrl_2;
202
203	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
204	/* Select Bus Speed Mode for host */
205	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
206	if (timing == MMC_TIMING_MMC_HS200)
207		ctrl_2 |= XENON_CTRL_HS200;
208	else if (timing == MMC_TIMING_UHS_SDR104)
209		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
210	else if (timing == MMC_TIMING_UHS_SDR12)
211		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
212	else if (timing == MMC_TIMING_UHS_SDR25)
213		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
214	else if (timing == MMC_TIMING_UHS_SDR50)
215		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
216	else if ((timing == MMC_TIMING_UHS_DDR50) ||
217		 (timing == MMC_TIMING_MMC_DDR52))
218		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
219	else if (timing == MMC_TIMING_MMC_HS400)
220		ctrl_2 |= XENON_CTRL_HS400;
221	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
222}
223
224static void xenon_set_power(struct sdhci_host *host, unsigned char mode,
225		unsigned short vdd)
226{
227	struct mmc_host *mmc = host->mmc;
228	u8 pwr = host->pwr;
229
230	sdhci_set_power_noreg(host, mode, vdd);
231
232	if (host->pwr == pwr)
233		return;
234
235	if (host->pwr == 0)
236		vdd = 0;
237
238	if (!IS_ERR(mmc->supply.vmmc))
239		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
240}
241
242static void xenon_voltage_switch(struct sdhci_host *host)
243{
244	/* Wait for 5ms after set 1.8V signal enable bit */
245	usleep_range(5000, 5500);
246}
247
248static unsigned int xenon_get_max_clock(struct sdhci_host *host)
249{
250	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
251
252	if (pltfm_host->clk)
253		return sdhci_pltfm_clk_get_max_clock(host);
254	else
255		return pltfm_host->clock;
256}
257
258static const struct sdhci_ops sdhci_xenon_ops = {
259	.voltage_switch		= xenon_voltage_switch,
260	.set_clock		= sdhci_set_clock,
261	.set_power		= xenon_set_power,
262	.set_bus_width		= sdhci_set_bus_width,
263	.reset			= xenon_reset,
264	.set_uhs_signaling	= xenon_set_uhs_signaling,
265	.get_max_clock		= xenon_get_max_clock,
266};
267
268static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
269	.ops = &sdhci_xenon_ops,
270	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
271		  SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
272		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
273};
274
275/*
276 * Xenon Specific Operations in mmc_host_ops
277 */
278static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
279{
280	struct sdhci_host *host = mmc_priv(mmc);
281	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
282	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
283	u32 reg;
284
285	/*
286	 * HS400/HS200/eMMC HS doesn't have Preset Value register.
287	 * However, sdhci_set_ios will read HS400/HS200 Preset register.
288	 * Disable Preset Value register for HS400/HS200.
289	 * eMMC HS with preset_enabled set will trigger a bug in
290	 * get_preset_value().
291	 */
292	if ((ios->timing == MMC_TIMING_MMC_HS400) ||
293	    (ios->timing == MMC_TIMING_MMC_HS200) ||
294	    (ios->timing == MMC_TIMING_MMC_HS)) {
295		host->preset_enabled = false;
296		host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
297		host->flags &= ~SDHCI_PV_ENABLED;
298
299		reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
300		reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
301		sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
302	} else {
303		host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
304	}
305
306	sdhci_set_ios(mmc, ios);
307	xenon_phy_adj(host, ios);
308
309	if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
310		xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
311}
312
313static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
314					     struct mmc_ios *ios)
315{
316	struct sdhci_host *host = mmc_priv(mmc);
317
318	/*
319	 * Before SD/SDIO set signal voltage, SD bus clock should be
320	 * disabled. However, sdhci_set_clock will also disable the Internal
321	 * clock in mmc_set_signal_voltage().
322	 * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
323	 * Thus here manually enable internal clock.
324	 *
325	 * After switch completes, it is unnecessary to disable internal clock,
326	 * since keeping internal clock active obeys SD spec.
327	 */
328	xenon_enable_internal_clk(host);
329
330	xenon_soc_pad_ctrl(host, ios->signal_voltage);
331
332	/*
333	 * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
334	 * Thus SDHCI_CTRL_VDD_180 bit might not work then.
335	 * Skip the standard voltage switch to avoid any issue.
336	 */
337	if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
338		return 0;
339
340	return sdhci_start_signal_voltage_switch(mmc, ios);
341}
342
343/*
344 * Update card type.
345 * priv->init_card_type will be used in PHY timing adjustment.
346 */
347static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
348{
349	struct sdhci_host *host = mmc_priv(mmc);
350	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
351	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
352
353	/* Update card type*/
354	priv->init_card_type = card->type;
355}
356
357static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
358{
359	struct sdhci_host *host = mmc_priv(mmc);
360
361	if (host->timing == MMC_TIMING_UHS_DDR50 ||
362		host->timing == MMC_TIMING_MMC_DDR52)
363		return 0;
364
365	/*
366	 * Currently force Xenon driver back to support mode 1 only,
367	 * even though Xenon might claim to support mode 2 or mode 3.
368	 * It requires more time to test mode 2/mode 3 on more platforms.
369	 */
370	if (host->tuning_mode != SDHCI_TUNING_MODE_1)
371		xenon_retune_setup(host);
372
373	return sdhci_execute_tuning(mmc, opcode);
374}
375
376static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
377{
378	struct sdhci_host *host = mmc_priv(mmc);
379	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
380	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
381	u32 reg;
382	u8 sdhc_id = priv->sdhc_id;
383
384	sdhci_enable_sdio_irq(mmc, enable);
385
386	if (enable) {
387		/*
388		 * Set SDIO Card Inserted indication
389		 * to enable detecting SDIO async irq.
390		 */
391		reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
392		reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
393		sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
394	} else {
395		/* Clear SDIO Card Inserted indication */
396		reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
397		reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
398		sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
399	}
400}
401
402static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
403{
404	host->mmc_host_ops.set_ios = xenon_set_ios;
405	host->mmc_host_ops.start_signal_voltage_switch =
406			xenon_start_signal_voltage_switch;
407	host->mmc_host_ops.init_card = xenon_init_card;
408	host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
409	host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
410}
411
412/*
413 * Parse Xenon specific DT properties:
414 * sdhc-id: the index of current SDHC.
415 *	    Refer to XENON_SYS_CFG_INFO register
416 * tun-count: the interval between re-tuning
417 */
418static int xenon_probe_params(struct platform_device *pdev)
419{
420	struct device *dev = &pdev->dev;
421	struct sdhci_host *host = platform_get_drvdata(pdev);
422	struct mmc_host *mmc = host->mmc;
423	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
424	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
425	u32 sdhc_id, nr_sdhc;
426	u32 tuning_count;
427	struct sysinfo si;
428
429	/* Disable HS200 on Armada AP806 */
430	if (priv->hw_version == XENON_AP806)
431		host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
432
433	sdhc_id = 0x0;
434	if (!device_property_read_u32(dev, "marvell,xenon-sdhc-id", &sdhc_id)) {
435		nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
436		nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
437		if (unlikely(sdhc_id > nr_sdhc)) {
438			dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
439				sdhc_id, nr_sdhc);
440			return -EINVAL;
441		}
442	}
443	priv->sdhc_id = sdhc_id;
444
445	tuning_count = XENON_DEF_TUNING_COUNT;
446	if (!device_property_read_u32(dev, "marvell,xenon-tun-count",
447				      &tuning_count)) {
448		if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
449			dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
450				XENON_DEF_TUNING_COUNT);
451			tuning_count = XENON_DEF_TUNING_COUNT;
452		}
453	}
454	priv->tuning_count = tuning_count;
455
456	/*
457	 * AC5/X/IM HW has only 31-bits passed in the crossbar switch.
458	 * If we have more than 2GB of memory, this means we might pass
459	 * memory pointers which are above 2GB and which cannot be properly
460	 * represented. In this case, disable ADMA, 64-bit DMA and allow only SDMA.
461	 * This effectively will enable bounce buffer quirk in the
462	 * generic SDHCI driver, which will make sure DMA is only done
463	 * from supported memory regions:
464	 */
465	if (priv->hw_version == XENON_AC5) {
466		si_meminfo(&si);
467		if (si.totalram * si.mem_unit > SZ_2G) {
468			host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
469			host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA;
470		}
471	}
472
473	return xenon_phy_parse_params(dev, host);
474}
475
476static int xenon_sdhc_prepare(struct sdhci_host *host)
477{
478	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
479	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
480	u8 sdhc_id = priv->sdhc_id;
481
482	/* Enable SDHC */
483	xenon_enable_sdhc(host, sdhc_id);
484
485	/* Enable ACG */
486	xenon_set_acg(host, true);
487
488	/* Enable Parallel Transfer Mode */
489	xenon_enable_sdhc_parallel_tran(host, sdhc_id);
490
491	/* Disable SDCLK-Off-While-Idle before card init */
492	xenon_set_sdclk_off_idle(host, sdhc_id, false);
493
494	xenon_mask_cmd_conflict_err(host);
495
496	return 0;
497}
498
499static void xenon_sdhc_unprepare(struct sdhci_host *host)
500{
501	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
502	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
503	u8 sdhc_id = priv->sdhc_id;
504
505	/* disable SDHC */
506	xenon_disable_sdhc(host, sdhc_id);
507}
508
509static int xenon_probe(struct platform_device *pdev)
510{
511	struct sdhci_pltfm_host *pltfm_host;
512	struct device *dev = &pdev->dev;
513	struct sdhci_host *host;
514	struct xenon_priv *priv;
515	int err;
516
517	host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
518				sizeof(struct xenon_priv));
519	if (IS_ERR(host))
520		return PTR_ERR(host);
521
522	pltfm_host = sdhci_priv(host);
523	priv = sdhci_pltfm_priv(pltfm_host);
524
525	priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev);
526
527	/*
528	 * Link Xenon specific mmc_host_ops function,
529	 * to replace standard ones in sdhci_ops.
530	 */
531	xenon_replace_mmc_host_ops(host);
532
533	if (dev->of_node) {
534		pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
535		if (IS_ERR(pltfm_host->clk))
536			return dev_err_probe(&pdev->dev, PTR_ERR(pltfm_host->clk),
537					     "Failed to setup input clk.\n");
538
539		err = clk_prepare_enable(pltfm_host->clk);
540		if (err)
541			return err;
542
543		priv->axi_clk = devm_clk_get(&pdev->dev, "axi");
544		if (IS_ERR(priv->axi_clk)) {
545			err = PTR_ERR(priv->axi_clk);
546			if (err == -EPROBE_DEFER)
547				goto err_clk;
548		} else {
549			err = clk_prepare_enable(priv->axi_clk);
550			if (err)
551				goto err_clk;
552		}
553	}
554
555	err = mmc_of_parse(host->mmc);
556	if (err)
557		goto err_clk_axi;
558
559	sdhci_get_property(pdev);
560
561	xenon_set_acg(host, false);
562
563	/* Xenon specific parameters parse */
564	err = xenon_probe_params(pdev);
565	if (err)
566		goto err_clk_axi;
567
568	err = xenon_sdhc_prepare(host);
569	if (err)
570		goto err_clk_axi;
571
572	pm_runtime_get_noresume(&pdev->dev);
573	pm_runtime_set_active(&pdev->dev);
574	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
575	pm_runtime_use_autosuspend(&pdev->dev);
576	pm_runtime_enable(&pdev->dev);
577	pm_suspend_ignore_children(&pdev->dev, 1);
578
579	err = sdhci_add_host(host);
580	if (err)
581		goto remove_sdhc;
582
583	pm_runtime_put_autosuspend(&pdev->dev);
584	/*
585	 * If we previously detected AC5 with over 2GB of memory,
586	 * then we disable ADMA and 64-bit DMA.
587	 * This means generic SDHCI driver has set the DMA mask to
588	 * 32-bit. Since DDR starts at 0x2_0000_0000, we must use
589	 * 34-bit DMA mask to access this DDR memory:
590	 */
591	if (priv->hw_version == XENON_AC5 &&
592	    host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
593		dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));
594
595	return 0;
596
597remove_sdhc:
598	pm_runtime_disable(&pdev->dev);
599	pm_runtime_put_noidle(&pdev->dev);
600	xenon_sdhc_unprepare(host);
601err_clk_axi:
602	clk_disable_unprepare(priv->axi_clk);
603err_clk:
604	clk_disable_unprepare(pltfm_host->clk);
605	return err;
606}
607
608static void xenon_remove(struct platform_device *pdev)
609{
610	struct sdhci_host *host = platform_get_drvdata(pdev);
611	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
612	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
613
614	pm_runtime_get_sync(&pdev->dev);
615	pm_runtime_disable(&pdev->dev);
616	pm_runtime_put_noidle(&pdev->dev);
617
618	sdhci_remove_host(host, 0);
619
620	xenon_sdhc_unprepare(host);
621	clk_disable_unprepare(priv->axi_clk);
622	clk_disable_unprepare(pltfm_host->clk);
623}
624
625static int xenon_suspend(struct device *dev)
626{
627	struct sdhci_host *host = dev_get_drvdata(dev);
628	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
629	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
630	int ret;
631
632	ret = pm_runtime_force_suspend(dev);
633
634	priv->restore_needed = true;
635	return ret;
636}
637
638static int xenon_runtime_suspend(struct device *dev)
639{
640	struct sdhci_host *host = dev_get_drvdata(dev);
641	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
642	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
643
644	sdhci_runtime_suspend_host(host);
645
646	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
647		mmc_retune_needed(host->mmc);
648
649	clk_disable_unprepare(pltfm_host->clk);
650	/*
651	 * Need to update the priv->clock here, or when runtime resume
652	 * back, phy don't aware the clock change and won't adjust phy
653	 * which will cause cmd err
654	 */
655	priv->clock = 0;
656	return 0;
657}
658
659static int xenon_runtime_resume(struct device *dev)
660{
661	struct sdhci_host *host = dev_get_drvdata(dev);
662	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
663	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
664	int ret;
665
666	ret = clk_prepare_enable(pltfm_host->clk);
667	if (ret) {
668		dev_err(dev, "can't enable mainck\n");
669		return ret;
670	}
671
672	if (priv->restore_needed) {
673		ret = xenon_sdhc_prepare(host);
674		if (ret)
675			goto out;
676		priv->restore_needed = false;
677	}
678
679	sdhci_runtime_resume_host(host, 0);
680	return 0;
681out:
682	clk_disable_unprepare(pltfm_host->clk);
683	return ret;
684}
685
686static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = {
687	SYSTEM_SLEEP_PM_OPS(xenon_suspend, pm_runtime_force_resume)
688	RUNTIME_PM_OPS(xenon_runtime_suspend, xenon_runtime_resume, NULL)
689};
690
691static const struct of_device_id sdhci_xenon_dt_ids[] = {
692	{ .compatible = "marvell,armada-ap806-sdhci", .data = (void *)XENON_AP806},
693	{ .compatible = "marvell,armada-ap807-sdhci", .data = (void *)XENON_AP807},
694	{ .compatible = "marvell,armada-cp110-sdhci", .data =  (void *)XENON_CP110},
695	{ .compatible = "marvell,armada-3700-sdhci", .data =  (void *)XENON_A3700},
696	{ .compatible = "marvell,ac5-sdhci",	     .data =  (void *)XENON_AC5},
697	{}
698};
699MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
700
701#ifdef CONFIG_ACPI
702static const struct acpi_device_id sdhci_xenon_acpi_ids[] = {
703	{ .id = "MRVL0002", XENON_AP806},
704	{ .id = "MRVL0003", XENON_AP807},
705	{ .id = "MRVL0004", XENON_CP110},
706	{}
707};
708MODULE_DEVICE_TABLE(acpi, sdhci_xenon_acpi_ids);
709#endif
710
711static struct platform_driver sdhci_xenon_driver = {
712	.driver	= {
713		.name	= "xenon-sdhci",
714		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
715		.of_match_table = sdhci_xenon_dt_ids,
716		.acpi_match_table = ACPI_PTR(sdhci_xenon_acpi_ids),
717		.pm = pm_ptr(&sdhci_xenon_dev_pm_ops),
718	},
719	.probe	= xenon_probe,
720	.remove = xenon_remove,
721};
722
723module_platform_driver(sdhci_xenon_driver);
724
725MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
726MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
727MODULE_LICENSE("GPL v2");