sdhci-sprd.c

  1// SPDX-License-Identifier: GPL-2.0
  2//
  3// Secure Digital Host Controller
  4//
  5// Copyright (C) 2018 Spreadtrum, Inc.
  6// Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
  7
  8#include <linux/delay.h>
  9#include <linux/dma-mapping.h>
 10#include <linux/highmem.h>
 11#include <linux/iopoll.h>
 12#include <linux/mmc/host.h>
 13#include <linux/mmc/mmc.h>
 14#include <linux/module.h>
 15#include <linux/of.h>
 16#include <linux/pinctrl/consumer.h>
 17#include <linux/platform_device.h>
 18#include <linux/pm_runtime.h>
 19#include <linux/regulator/consumer.h>
 20#include <linux/slab.h>
 21
 22#include "sdhci-pltfm.h"
 23#include "mmc_hsq.h"
 24
 25/* SDHCI_ARGUMENT2 register high 16bit */
 26#define SDHCI_SPRD_ARG2_STUFF		GENMASK(31, 16)
 27
 28#define SDHCI_SPRD_REG_32_DLL_CFG	0x200
 29#define  SDHCI_SPRD_DLL_ALL_CPST_EN	(BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
 30#define  SDHCI_SPRD_DLL_EN		BIT(21)
 31#define  SDHCI_SPRD_DLL_SEARCH_MODE	BIT(16)
 32#define  SDHCI_SPRD_DLL_INIT_COUNT	0xc00
 33#define  SDHCI_SPRD_DLL_PHASE_INTERNAL	0x3
 34
 35#define SDHCI_SPRD_REG_32_DLL_DLY	0x204
 36
 37#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET	0x208
 38#define  SDHCIBSPRD_IT_WR_DLY_INV		BIT(5)
 39#define  SDHCI_SPRD_BIT_CMD_DLY_INV		BIT(13)
 40#define  SDHCI_SPRD_BIT_POSRD_DLY_INV		BIT(21)
 41#define  SDHCI_SPRD_BIT_NEGRD_DLY_INV		BIT(29)
 42
 43#define SDHCI_SPRD_REG_32_DLL_STS0	0x210
 44#define SDHCI_SPRD_DLL_LOCKED		BIT(18)
 45
 46#define SDHCI_SPRD_REG_32_BUSY_POSI		0x250
 47#define  SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN	BIT(25)
 48#define  SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN	BIT(24)
 49
 50#define SDHCI_SPRD_REG_DEBOUNCE		0x28C
 51#define  SDHCI_SPRD_BIT_DLL_BAK		BIT(0)
 52#define  SDHCI_SPRD_BIT_DLL_VAL		BIT(1)
 53
 54#define  SDHCI_SPRD_INT_SIGNAL_MASK	0x1B7F410B
 55
 56/* SDHCI_HOST_CONTROL2 */
 57#define  SDHCI_SPRD_CTRL_HS200		0x0005
 58#define  SDHCI_SPRD_CTRL_HS400		0x0006
 59#define  SDHCI_SPRD_CTRL_HS400ES	0x0007
 60
 61/*
 62 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
 63 * reserved, and only used on Spreadtrum's design, the hardware cannot work
 64 * if this bit is cleared.
 65 * 1 : normal work
 66 * 0 : hardware reset
 67 */
 68#define  SDHCI_HW_RESET_CARD		BIT(3)
 69
 70#define SDHCI_SPRD_MAX_CUR		0xFFFFFF
 71#define SDHCI_SPRD_CLK_MAX_DIV		1023
 72
 73#define SDHCI_SPRD_CLK_DEF_RATE		26000000
 74#define SDHCI_SPRD_PHY_DLL_CLK		52000000
 75
 76#define SDHCI_SPRD_MAX_RANGE		0xff
 77#define SDHCI_SPRD_CMD_DLY_MASK		GENMASK(15, 8)
 78#define SDHCI_SPRD_POSRD_DLY_MASK	GENMASK(23, 16)
 79#define SDHCI_SPRD_CPST_EN		GENMASK(27, 24)
 80
 81struct sdhci_sprd_host {
 82	u32 version;
 83	struct clk *clk_sdio;
 84	struct clk *clk_enable;
 85	struct clk *clk_2x_enable;
 86	struct pinctrl *pinctrl;
 87	struct pinctrl_state *pins_uhs;
 88	struct pinctrl_state *pins_default;
 89	u32 base_rate;
 90	int flags; /* backup of host attribute */
 91	u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
 92};
 93
 94enum sdhci_sprd_tuning_type {
 95	SDHCI_SPRD_TUNING_SD_HS_CMD,
 96	SDHCI_SPRD_TUNING_SD_HS_DATA,
 97};
 98
 99struct sdhci_sprd_phy_cfg {
100	const char *property;
101	u8 timing;
102};
103
104static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
105	{ "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
106	{ "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
107	{ "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
108	{ "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
109	{ "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
110	{ "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
111	{ "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
112	{ "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
113	{ "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
114};
115
116#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
117
118static void sdhci_sprd_init_config(struct sdhci_host *host)
119{
120	u16 val;
121
122	/* set dll backup mode */
123	val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
124	val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
125	sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
126}
127
128static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
129{
130	if (unlikely(reg == SDHCI_MAX_CURRENT))
131		return SDHCI_SPRD_MAX_CUR;
132
133	return readl_relaxed(host->ioaddr + reg);
134}
135
136static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
137{
138	/* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
139	if (unlikely(reg == SDHCI_MAX_CURRENT))
140		return;
141
142	if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
143		val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
144
145	writel_relaxed(val, host->ioaddr + reg);
146}
147
148static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
149{
150	/* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
151	if (unlikely(reg == SDHCI_BLOCK_COUNT))
152		return;
153
154	writew_relaxed(val, host->ioaddr + reg);
155}
156
157static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
158{
159	/*
160	 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
161	 * standard specification, sdhci_reset() write this register directly
162	 * without checking other reserved bits, that will clear BIT(3) which
163	 * is defined as hardware reset on Spreadtrum's platform and clearing
164	 * it by mistake will lead the card not work. So here we need to work
165	 * around it.
166	 */
167	if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
168		if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
169			val |= SDHCI_HW_RESET_CARD;
170	}
171
172	writeb_relaxed(val, host->ioaddr + reg);
173}
174
175static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
176{
177	u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
178
179	ctrl &= ~SDHCI_CLOCK_CARD_EN;
180	sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
181}
182
183static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
184{
185	u16 ctrl;
186
187	ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
188	ctrl |= SDHCI_CLOCK_CARD_EN;
189	sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
190}
191
192static inline void
193sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
194{
195	u32 dll_dly_offset;
196
197	dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
198	if (en)
199		dll_dly_offset |= mask;
200	else
201		dll_dly_offset &= ~mask;
202	sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
203}
204
205static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
206{
207	u32 div;
208
209	/* select 2x clock source */
210	if (base_clk <= clk * 2)
211		return 0;
212
213	div = (u32) (base_clk / (clk * 2));
214
215	if ((base_clk / div) > (clk * 2))
216		div++;
217
218	if (div % 2)
219		div = (div + 1) / 2;
220	else
221		div = div / 2;
222
223	if (div > SDHCI_SPRD_CLK_MAX_DIV)
224		div = SDHCI_SPRD_CLK_MAX_DIV;
225
226	return div;
227}
228
229static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
230					unsigned int clk)
231{
232	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
233	u32 div, val, mask;
234
235	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
236
237	div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
238	div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
239	sdhci_enable_clk(host, div);
240
241	val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
242	mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
243	/* Enable CLK_AUTO when the clock is greater than 400K. */
244	if (clk > 400000) {
245		if (mask != (val & mask)) {
246			val |= mask;
247			sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
248		}
249	} else {
250		if (val & mask) {
251			val &= ~mask;
252			sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
253		}
254	}
255}
256
257static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
258{
259	u32 tmp;
260
261	tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
262	tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
263	sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
264	/* wait 1ms */
265	usleep_range(1000, 1250);
266
267	tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
268	tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
269		SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
270	sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
271	/* wait 1ms */
272	usleep_range(1000, 1250);
273
274	tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
275	tmp |= SDHCI_SPRD_DLL_EN;
276	sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
277	/* wait 1ms */
278	usleep_range(1000, 1250);
279
280	if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED),
281		2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) {
282		pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc));
283		pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n",
284			 mmc_hostname(host->mmc),
285			 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0),
286			 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG));
287	}
288}
289
290static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
291{
292	bool en = false, clk_changed = false;
293
294	if (clock == 0) {
295		sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
296	} else if (clock != host->clock) {
297		sdhci_sprd_sd_clk_off(host);
298		_sdhci_sprd_set_clock(host, clock);
299
300		if (clock <= 400000)
301			en = true;
302		sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
303					  SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
304		clk_changed = true;
305	} else {
306		_sdhci_sprd_set_clock(host, clock);
307	}
308
309	/*
310	 * According to the Spreadtrum SD host specification, when we changed
311	 * the clock to be more than 52M, we should enable the PHY DLL which
312	 * is used to track the clock frequency to make the clock work more
313	 * stable. Otherwise deviation may occur of the higher clock.
314	 */
315	if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
316		sdhci_sprd_enable_phy_dll(host);
317}
318
319static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
320{
321	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
322
323	return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
324}
325
326static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
327{
328	return 100000;
329}
330
331static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
332					 unsigned int timing)
333{
334	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
335	struct mmc_host *mmc = host->mmc;
336	u32 *p = sprd_host->phy_delay;
337	u16 ctrl_2;
338
339	if (timing == host->timing)
340		return;
341
342	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
343	/* Select Bus Speed Mode for host */
344	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
345	switch (timing) {
346	case MMC_TIMING_UHS_SDR12:
347		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
348		break;
349	case MMC_TIMING_MMC_HS:
350	case MMC_TIMING_SD_HS:
351	case MMC_TIMING_UHS_SDR25:
352		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
353		break;
354	case MMC_TIMING_UHS_SDR50:
355		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
356		break;
357	case MMC_TIMING_UHS_SDR104:
358		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
359		break;
360	case MMC_TIMING_UHS_DDR50:
361	case MMC_TIMING_MMC_DDR52:
362		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
363		break;
364	case MMC_TIMING_MMC_HS200:
365		ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
366		break;
367	case MMC_TIMING_MMC_HS400:
368		ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
369		break;
370	default:
371		break;
372	}
373
374	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
375
376	if (!mmc->ios.enhanced_strobe)
377		sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
378}
379
380static void sdhci_sprd_hw_reset(struct sdhci_host *host)
381{
382	int val;
383
384	/*
385	 * Note: don't use sdhci_writeb() API here since it is redirected to
386	 * sdhci_sprd_writeb() in which we have a workaround for
387	 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
388	 * not be cleared.
389	 */
390	val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
391	val &= ~SDHCI_HW_RESET_CARD;
392	writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
393	/* wait for 10 us */
394	usleep_range(10, 20);
395
396	val |= SDHCI_HW_RESET_CARD;
397	writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
398	usleep_range(300, 500);
399}
400
401static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
402{
403	/* The Spredtrum controller actual maximum timeout count is 1 << 31 */
404	return 1 << 31;
405}
406
407static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
408{
409	return 0;
410}
411
412static void sdhci_sprd_request_done(struct sdhci_host *host,
413				    struct mmc_request *mrq)
414{
415	/* Validate if the request was from software queue firstly. */
416	if (mmc_hsq_finalize_request(host->mmc, mrq))
417		return;
418
419	mmc_request_done(host->mmc, mrq);
420}
421
422static void sdhci_sprd_set_power(struct sdhci_host *host, unsigned char mode,
423				 unsigned short vdd)
424{
425	struct mmc_host *mmc = host->mmc;
426
427	switch (mode) {
428	case MMC_POWER_OFF:
429		mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, 0);
430
431		mmc_regulator_disable_vqmmc(mmc);
432		break;
433	case MMC_POWER_ON:
434		mmc_regulator_enable_vqmmc(mmc);
435		break;
436	case MMC_POWER_UP:
437		mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, vdd);
438		break;
439	}
440}
441
442static const struct sdhci_ops sdhci_sprd_ops = {
443	.read_l = sdhci_sprd_readl,
444	.write_l = sdhci_sprd_writel,
445	.write_w = sdhci_sprd_writew,
446	.write_b = sdhci_sprd_writeb,
447	.set_clock = sdhci_sprd_set_clock,
448	.set_power = sdhci_sprd_set_power,
449	.get_max_clock = sdhci_sprd_get_max_clock,
450	.get_min_clock = sdhci_sprd_get_min_clock,
451	.set_bus_width = sdhci_set_bus_width,
452	.reset = sdhci_reset,
453	.set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
454	.hw_reset = sdhci_sprd_hw_reset,
455	.get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
456	.get_ro = sdhci_sprd_get_ro,
457	.request_done = sdhci_sprd_request_done,
458};
459
460static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
461					struct mmc_request *mrq)
462{
463	struct sdhci_host *host = mmc_priv(mmc);
464	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
465
466	host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
467
468	/*
469	 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
470	 * block count register which doesn't support stuff bits of
471	 * CMD23 argument on Spreadtrum's sd host controller.
472	 */
473	if (host->version >= SDHCI_SPEC_410 &&
474	    mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
475	    (host->flags & SDHCI_AUTO_CMD23))
476		host->flags &= ~SDHCI_AUTO_CMD23;
477}
478
479static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
480{
481	sdhci_sprd_check_auto_cmd23(mmc, mrq);
482
483	sdhci_request(mmc, mrq);
484}
485
486static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
487				     struct mmc_request *mrq)
488{
489	sdhci_sprd_check_auto_cmd23(mmc, mrq);
490
491	return sdhci_request_atomic(mmc, mrq);
492}
493
494static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
495{
496	struct sdhci_host *host = mmc_priv(mmc);
497	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
498	int ret;
499
500	if (!IS_ERR(mmc->supply.vqmmc)) {
501		ret = mmc_regulator_set_vqmmc(mmc, ios);
502		if (ret < 0) {
503			pr_err("%s: Switching signalling voltage failed\n",
504			       mmc_hostname(mmc));
505			return ret;
506		}
507	}
508
509	if (IS_ERR(sprd_host->pinctrl))
510		goto reset;
511
512	switch (ios->signal_voltage) {
513	case MMC_SIGNAL_VOLTAGE_180:
514		ret = pinctrl_select_state(sprd_host->pinctrl,
515					   sprd_host->pins_uhs);
516		if (ret) {
517			pr_err("%s: failed to select uhs pin state\n",
518			       mmc_hostname(mmc));
519			return ret;
520		}
521		break;
522
523	default:
524		fallthrough;
525	case MMC_SIGNAL_VOLTAGE_330:
526		ret = pinctrl_select_state(sprd_host->pinctrl,
527					   sprd_host->pins_default);
528		if (ret) {
529			pr_err("%s: failed to select default pin state\n",
530			       mmc_hostname(mmc));
531			return ret;
532		}
533		break;
534	}
535
536	/* Wait for 300 ~ 500 us for pin state stable */
537	usleep_range(300, 500);
538
539reset:
540	sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
541
542	return 0;
543}
544
545static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
546					     struct mmc_ios *ios)
547{
548	struct sdhci_host *host = mmc_priv(mmc);
549	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
550	u32 *p = sprd_host->phy_delay;
551	u16 ctrl_2;
552
553	if (!ios->enhanced_strobe)
554		return;
555
556	sdhci_sprd_sd_clk_off(host);
557
558	/* Set HS400 enhanced strobe mode */
559	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
560	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
561	ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
562	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
563
564	sdhci_sprd_sd_clk_on(host);
565
566	/* Set the PHY DLL delay value for HS400 enhanced strobe mode */
567	sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
568		     SDHCI_SPRD_REG_32_DLL_DLY);
569}
570
571static int mmc_send_tuning_cmd(struct mmc_card *card)
572{
573	return mmc_send_status(card, NULL);
574}
575
576static int mmc_send_tuning_data(struct mmc_card *card)
577{
578	u8 *status;
579	int ret;
580
581	status = kmalloc(64, GFP_KERNEL);
582	if (!status)
583		return -ENOMEM;
584
585	ret = mmc_sd_switch(card, 0, 0, 0, status);
586
587	kfree(status);
588
589	return ret;
590}
591
592static int sdhci_sprd_get_best_clk_sample(struct mmc_host *mmc, u8 *value)
593{
594	int range_end = SDHCI_SPRD_MAX_RANGE;
595	int range_length = 0;
596	int middle_range = 0;
597	int count = 0;
598	int i;
599
600	for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) {
601		if (value[i]) {
602			pr_debug("%s: tuning ok: %d\n", mmc_hostname(mmc), i);
603			count++;
604		} else {
605			pr_debug("%s: tuning fail: %d\n", mmc_hostname(mmc), i);
606			if (range_length < count) {
607				range_length = count;
608				range_end = i - 1;
609				count = 0;
610			}
611		}
612	}
613
614	if (!count)
615		return -EIO;
616
617	if (count > range_length) {
618		range_length = count;
619		range_end = i - 1;
620	}
621
622	middle_range = range_end - (range_length - 1) / 2;
623
624	return middle_range;
625}
626
627static int sdhci_sprd_tuning(struct mmc_host *mmc, struct mmc_card *card,
628			enum sdhci_sprd_tuning_type type)
629{
630	struct sdhci_host *host = mmc_priv(mmc);
631	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
632	u32 *p = sprd_host->phy_delay;
633	u32 dll_cfg, dll_dly;
634	int best_clk_sample;
635	int err = 0;
636	u8 *value;
637	int i;
638
639	value = kmalloc(SDHCI_SPRD_MAX_RANGE + 1, GFP_KERNEL);
640	if (!value)
641		return -ENOMEM;
642
643	sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
644
645	dll_cfg = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
646	dll_cfg &= ~SDHCI_SPRD_CPST_EN;
647	sdhci_writel(host, dll_cfg, SDHCI_SPRD_REG_32_DLL_CFG);
648
649	dll_dly = p[mmc->ios.timing];
650
651	for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) {
652		if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) {
653			dll_dly &= ~SDHCI_SPRD_CMD_DLY_MASK;
654			dll_dly |= ((i << 8) & SDHCI_SPRD_CMD_DLY_MASK);
655		} else {
656			dll_dly &= ~SDHCI_SPRD_POSRD_DLY_MASK;
657			dll_dly |= ((i << 16) & SDHCI_SPRD_POSRD_DLY_MASK);
658		}
659
660		sdhci_writel(host, dll_dly, SDHCI_SPRD_REG_32_DLL_DLY);
661
662		if (type == SDHCI_SPRD_TUNING_SD_HS_CMD)
663			value[i] = !mmc_send_tuning_cmd(card);
664		else
665			value[i] = !mmc_send_tuning_data(card);
666	}
667
668	best_clk_sample = sdhci_sprd_get_best_clk_sample(mmc, value);
669	if (best_clk_sample < 0) {
670		dev_err(mmc_dev(host->mmc), "all tuning phase fail!\n");
671		err = best_clk_sample;
672		goto out;
673	}
674
675	if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) {
676		p[mmc->ios.timing] &= ~SDHCI_SPRD_CMD_DLY_MASK;
677		p[mmc->ios.timing] |= ((best_clk_sample << 8) & SDHCI_SPRD_CMD_DLY_MASK);
678	} else {
679		p[mmc->ios.timing] &= ~(SDHCI_SPRD_POSRD_DLY_MASK);
680		p[mmc->ios.timing] |= ((best_clk_sample << 16) & SDHCI_SPRD_POSRD_DLY_MASK);
681	}
682
683	pr_debug("%s: the best clk sample %d, delay value 0x%08x\n",
684			mmc_hostname(host->mmc), best_clk_sample, p[mmc->ios.timing]);
685
686out:
687	sdhci_writel(host, p[mmc->ios.timing], SDHCI_SPRD_REG_32_DLL_DLY);
688
689	kfree(value);
690
691	return err;
692}
693
694static int sdhci_sprd_prepare_sd_hs_cmd_tuning(struct mmc_host *mmc, struct mmc_card *card)
695{
696	return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_CMD);
697}
698
699static int sdhci_sprd_execute_sd_hs_data_tuning(struct mmc_host *mmc, struct mmc_card *card)
700{
701	return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_DATA);
702}
703
704static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
705				       struct device_node *np)
706{
707	u32 *p = sprd_host->phy_delay;
708	int ret, i, index;
709	u32 val[4];
710
711	for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
712		ret = of_property_read_u32_array(np,
713				sdhci_sprd_phy_cfgs[i].property, val, 4);
714		if (ret)
715			continue;
716
717		index = sdhci_sprd_phy_cfgs[i].timing;
718		p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
719	}
720}
721
722static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
723	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
724		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
725	.quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
726		   SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
727		   SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728	.ops = &sdhci_sprd_ops,
729};
730
731static int sdhci_sprd_probe(struct platform_device *pdev)
732{
733	struct sdhci_host *host;
734	struct sdhci_sprd_host *sprd_host;
735	struct mmc_hsq *hsq;
736	struct clk *clk;
737	int ret = 0;
738
739	host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
740	if (IS_ERR(host))
741		return PTR_ERR(host);
742
743	host->dma_mask = DMA_BIT_MASK(64);
744	pdev->dev.dma_mask = &host->dma_mask;
745	host->mmc_host_ops.request = sdhci_sprd_request;
746	host->mmc_host_ops.hs400_enhanced_strobe =
747		sdhci_sprd_hs400_enhanced_strobe;
748	host->mmc_host_ops.prepare_sd_hs_tuning =
749		sdhci_sprd_prepare_sd_hs_cmd_tuning;
750	host->mmc_host_ops.execute_sd_hs_tuning =
751		sdhci_sprd_execute_sd_hs_data_tuning;
752
753	/*
754	 * We can not use the standard ops to change and detect the voltage
755	 * signal for Spreadtrum SD host controller, since our voltage regulator
756	 * for I/O is fixed in hardware, that means we do not need control
757	 * the standard SD host controller to change the I/O voltage.
758	 */
759	host->mmc_host_ops.start_signal_voltage_switch =
760		sdhci_sprd_voltage_switch;
761
762	host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
763		MMC_CAP_WAIT_WHILE_BUSY;
764
765	ret = mmc_of_parse(host->mmc);
766	if (ret)
767		return ret;
768
769	if (!mmc_card_is_removable(host->mmc))
770		host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
771	else
772		host->always_defer_done = true;
773
774	sprd_host = TO_SPRD_HOST(host);
775	sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
776
777	sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
778	if (!IS_ERR(sprd_host->pinctrl)) {
779		sprd_host->pins_uhs =
780			pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
781		if (IS_ERR(sprd_host->pins_uhs))
782			return PTR_ERR(sprd_host->pins_uhs);
783
784		sprd_host->pins_default =
785			pinctrl_lookup_state(sprd_host->pinctrl, "default");
786		if (IS_ERR(sprd_host->pins_default))
787			return PTR_ERR(sprd_host->pins_default);
788	}
789
790	clk = devm_clk_get(&pdev->dev, "sdio");
791	if (IS_ERR(clk))
792		return PTR_ERR(clk);
793	sprd_host->clk_sdio = clk;
794	sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
795	if (!sprd_host->base_rate)
796		sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
797
798	clk = devm_clk_get(&pdev->dev, "enable");
799	if (IS_ERR(clk))
800		return PTR_ERR(clk);
801	sprd_host->clk_enable = clk;
802
803	clk = devm_clk_get(&pdev->dev, "2x_enable");
804	if (!IS_ERR(clk))
805		sprd_host->clk_2x_enable = clk;
806
807	ret = clk_prepare_enable(sprd_host->clk_sdio);
808	if (ret)
809		return ret;
810
811	ret = clk_prepare_enable(sprd_host->clk_enable);
812	if (ret)
813		goto clk_disable;
814
815	ret = clk_prepare_enable(sprd_host->clk_2x_enable);
816	if (ret)
817		goto clk_disable2;
818
819	sdhci_sprd_init_config(host);
820	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
821	sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
822			       SDHCI_VENDOR_VER_SHIFT);
823
824	pm_runtime_get_noresume(&pdev->dev);
825	pm_runtime_set_active(&pdev->dev);
826	pm_runtime_enable(&pdev->dev);
827	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
828	pm_runtime_use_autosuspend(&pdev->dev);
829	pm_suspend_ignore_children(&pdev->dev, 1);
830
831	sdhci_enable_v4_mode(host);
832
833	/*
834	 * Supply the existing CAPS, but clear the UHS-I modes. This
835	 * will allow these modes to be specified only by device
836	 * tree properties through mmc_of_parse().
837	 */
838	sdhci_read_caps(host);
839	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
840			 SDHCI_SUPPORT_DDR50);
841
842	ret = mmc_regulator_get_supply(host->mmc);
843	if (ret)
844		goto pm_runtime_disable;
845
846	ret = sdhci_setup_host(host);
847	if (ret)
848		goto pm_runtime_disable;
849
850	sprd_host->flags = host->flags;
851
852	hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
853	if (!hsq) {
854		ret = -ENOMEM;
855		goto err_cleanup_host;
856	}
857
858	ret = mmc_hsq_init(hsq, host->mmc);
859	if (ret)
860		goto err_cleanup_host;
861
862	ret = __sdhci_add_host(host);
863	if (ret)
864		goto err_cleanup_host;
865
866	pm_runtime_put_autosuspend(&pdev->dev);
867
868	return 0;
869
870err_cleanup_host:
871	sdhci_cleanup_host(host);
872
873pm_runtime_disable:
874	pm_runtime_put_noidle(&pdev->dev);
875	pm_runtime_disable(&pdev->dev);
876	pm_runtime_set_suspended(&pdev->dev);
877
878	clk_disable_unprepare(sprd_host->clk_2x_enable);
879
880clk_disable2:
881	clk_disable_unprepare(sprd_host->clk_enable);
882
883clk_disable:
884	clk_disable_unprepare(sprd_host->clk_sdio);
885	return ret;
886}
887
888static void sdhci_sprd_remove(struct platform_device *pdev)
889{
890	struct sdhci_host *host = platform_get_drvdata(pdev);
891	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
892
893	sdhci_remove_host(host, 0);
894
895	clk_disable_unprepare(sprd_host->clk_sdio);
896	clk_disable_unprepare(sprd_host->clk_enable);
897	clk_disable_unprepare(sprd_host->clk_2x_enable);
898}
899
900static const struct of_device_id sdhci_sprd_of_match[] = {
901	{ .compatible = "sprd,sdhci-r11", },
902	{ }
903};
904MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
905
906static int sdhci_sprd_runtime_suspend(struct device *dev)
907{
908	struct sdhci_host *host = dev_get_drvdata(dev);
909	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
910
911	mmc_hsq_suspend(host->mmc);
912	sdhci_runtime_suspend_host(host);
913
914	clk_disable_unprepare(sprd_host->clk_sdio);
915	clk_disable_unprepare(sprd_host->clk_enable);
916	clk_disable_unprepare(sprd_host->clk_2x_enable);
917
918	return 0;
919}
920
921static int sdhci_sprd_runtime_resume(struct device *dev)
922{
923	struct sdhci_host *host = dev_get_drvdata(dev);
924	struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
925	int ret;
926
927	ret = clk_prepare_enable(sprd_host->clk_2x_enable);
928	if (ret)
929		return ret;
930
931	ret = clk_prepare_enable(sprd_host->clk_enable);
932	if (ret)
933		goto clk_2x_disable;
934
935	ret = clk_prepare_enable(sprd_host->clk_sdio);
936	if (ret)
937		goto clk_disable;
938
939	sdhci_runtime_resume_host(host, 1);
940	mmc_hsq_resume(host->mmc);
941
942	return 0;
943
944clk_disable:
945	clk_disable_unprepare(sprd_host->clk_enable);
946
947clk_2x_disable:
948	clk_disable_unprepare(sprd_host->clk_2x_enable);
949
950	return ret;
951}
952
953static const struct dev_pm_ops sdhci_sprd_pm_ops = {
954	SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
955	RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, sdhci_sprd_runtime_resume, NULL)
956};
957
958static struct platform_driver sdhci_sprd_driver = {
959	.probe = sdhci_sprd_probe,
960	.remove = sdhci_sprd_remove,
961	.driver = {
962		.name = "sdhci_sprd_r11",
963		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
964		.of_match_table = sdhci_sprd_of_match,
965		.pm = pm_ptr(&sdhci_sprd_pm_ops),
966	},
967};
968module_platform_driver(sdhci_sprd_driver);
969
970MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
971MODULE_LICENSE("GPL v2");
972MODULE_ALIAS("platform:sdhci-sprd-r11");