sdhci-s3c.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* linux/drivers/mmc/host/sdhci-s3c.c
  3 *
  4 * Copyright 2008 Openmoko Inc.
  5 * Copyright 2008 Simtec Electronics
  6 *      Ben Dooks <ben@simtec.co.uk>
  7 *      http://armlinux.simtec.co.uk/
  8 *
  9 * SDHCI (HSMMC) support for Samsung SoC
 10 */
 11
 12#include <linux/spinlock.h>
 13#include <linux/delay.h>
 14#include <linux/dma-mapping.h>
 15#include <linux/platform_device.h>
 16#include <linux/platform_data/mmc-sdhci-s3c.h>
 17#include <linux/slab.h>
 18#include <linux/clk.h>
 19#include <linux/io.h>
 20#include <linux/module.h>
 21#include <linux/of.h>
 22#include <linux/pm.h>
 23#include <linux/pm_runtime.h>
 24
 25#include <linux/mmc/host.h>
 26
 27#include "sdhci.h"
 28
 29#define MAX_BUS_CLK	(4)
 30
 31#define S3C_SDHCI_CONTROL2			(0x80)
 32#define S3C_SDHCI_CONTROL3			(0x84)
 33#define S3C64XX_SDHCI_CONTROL4			(0x8C)
 34
 35#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR	BIT(31)
 36#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK		BIT(30)
 37#define S3C_SDHCI_CTRL2_CDINVRXD3		BIT(29)
 38#define S3C_SDHCI_CTRL2_SLCARDOUT		BIT(28)
 39
 40#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK		(0xf << 24)
 41#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT		(24)
 42#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x)		((_x) << 24)
 43
 44#define S3C_SDHCI_CTRL2_LVLDAT_MASK		(0xff << 16)
 45#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT		(16)
 46#define S3C_SDHCI_CTRL2_LVLDAT(_x)		((_x) << 16)
 47
 48#define S3C_SDHCI_CTRL2_ENFBCLKTX		BIT(15)
 49#define S3C_SDHCI_CTRL2_ENFBCLKRX		BIT(14)
 50#define S3C_SDHCI_CTRL2_SDCDSEL			BIT(13)
 51#define S3C_SDHCI_CTRL2_SDSIGPC			BIT(12)
 52#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART	BIT(11)
 53
 54#define S3C_SDHCI_CTRL2_DFCNT_MASK		(0x3 << 9)
 55#define S3C_SDHCI_CTRL2_DFCNT_SHIFT		(9)
 56#define S3C_SDHCI_CTRL2_DFCNT_NONE		(0x0 << 9)
 57#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK		(0x1 << 9)
 58#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK		(0x2 << 9)
 59#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK		(0x3 << 9)
 60
 61#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD		BIT(8)
 62#define S3C_SDHCI_CTRL2_RWAITMODE		BIT(7)
 63#define S3C_SDHCI_CTRL2_DISBUFRD		BIT(6)
 64
 65#define S3C_SDHCI_CTRL2_SELBASECLK_MASK		(0x3 << 4)
 66#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT	(4)
 67#define S3C_SDHCI_CTRL2_PWRSYNC			BIT(3)
 68#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON		BIT(1)
 69#define S3C_SDHCI_CTRL2_HWINITFIN		BIT(0)
 70
 71#define S3C_SDHCI_CTRL3_FCSEL3			BIT(31)
 72#define S3C_SDHCI_CTRL3_FCSEL2			BIT(23)
 73#define S3C_SDHCI_CTRL3_FCSEL1			BIT(15)
 74#define S3C_SDHCI_CTRL3_FCSEL0			BIT(7)
 75
 76#define S3C_SDHCI_CTRL3_FIA3_MASK		(0x7f << 24)
 77#define S3C_SDHCI_CTRL3_FIA3_SHIFT		(24)
 78#define S3C_SDHCI_CTRL3_FIA3(_x)		((_x) << 24)
 79
 80#define S3C_SDHCI_CTRL3_FIA2_MASK		(0x7f << 16)
 81#define S3C_SDHCI_CTRL3_FIA2_SHIFT		(16)
 82#define S3C_SDHCI_CTRL3_FIA2(_x)		((_x) << 16)
 83
 84#define S3C_SDHCI_CTRL3_FIA1_MASK		(0x7f << 8)
 85#define S3C_SDHCI_CTRL3_FIA1_SHIFT		(8)
 86#define S3C_SDHCI_CTRL3_FIA1(_x)		((_x) << 8)
 87
 88#define S3C_SDHCI_CTRL3_FIA0_MASK		(0x7f << 0)
 89#define S3C_SDHCI_CTRL3_FIA0_SHIFT		(0)
 90#define S3C_SDHCI_CTRL3_FIA0(_x)		((_x) << 0)
 91
 92#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK	(0x3 << 16)
 93#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT	(16)
 94#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA	(0x0 << 16)
 95#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA	(0x1 << 16)
 96#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA	(0x2 << 16)
 97#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA	(0x3 << 16)
 98
 99#define S3C64XX_SDHCI_CONTROL4_BUSY		(1)
100
101/**
102 * struct sdhci_s3c - S3C SDHCI instance
103 * @host: The SDHCI host created
104 * @pdev: The platform device we where created from.
105 * @ioarea: The resource created when we claimed the IO area.
106 * @pdata: The platform data for this controller.
107 * @cur_clk: The index of the current bus clock.
108 * @ext_cd_irq: External card detect interrupt.
109 * @clk_io: The clock for the internal bus interface.
110 * @clk_rates: Clock frequencies.
111 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
112 * @no_divider: No or non-standard internal clock divider.
113 */
114struct sdhci_s3c {
115	struct sdhci_host	*host;
116	struct platform_device	*pdev;
117	struct resource		*ioarea;
118	struct s3c_sdhci_platdata *pdata;
119	int			cur_clk;
120	int			ext_cd_irq;
121
122	struct clk		*clk_io;
123	struct clk		*clk_bus[MAX_BUS_CLK];
124	unsigned long		clk_rates[MAX_BUS_CLK];
125
126	bool			no_divider;
127};
128
129/**
130 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
131 * @sdhci_quirks: sdhci host specific quirks.
132 * @no_divider: no or non-standard internal clock divider.
133 * @ops: sdhci_ops to use for this variant
134 *
135 * Specifies platform specific configuration of sdhci controller.
136 * Note: A structure for driver specific platform data is used for future
137 * expansion of its usage.
138 */
139struct sdhci_s3c_drv_data {
140	unsigned int		sdhci_quirks;
141	bool			no_divider;
142	const struct sdhci_ops	*ops;
143};
144
145static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
146{
147	return sdhci_priv(host);
148}
149
150/**
151 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
152 * @host: The SDHCI host instance.
153 *
154 * Callback to return the maximum clock rate acheivable by the controller.
155*/
156static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
157{
158	struct sdhci_s3c *ourhost = to_s3c(host);
159	unsigned long rate, max = 0;
160	int src;
161
162	for (src = 0; src < MAX_BUS_CLK; src++) {
163		rate = ourhost->clk_rates[src];
164		if (rate > max)
165			max = rate;
166	}
167
168	return max;
169}
170
171/**
172 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
173 * @ourhost: Our SDHCI instance.
174 * @src: The source clock index.
175 * @wanted: The clock frequency wanted.
176 */
177static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
178					     unsigned int src,
179					     unsigned int wanted)
180{
181	unsigned long rate;
182	struct clk *clksrc = ourhost->clk_bus[src];
183	int shift;
184
185	if (IS_ERR(clksrc))
186		return UINT_MAX;
187
188	/*
189	 * If controller uses a non-standard clock division, find the best clock
190	 * speed possible with selected clock source and skip the division.
191	 */
192	if (ourhost->no_divider) {
193		rate = clk_round_rate(clksrc, wanted);
194		return wanted - rate;
195	}
196
197	rate = ourhost->clk_rates[src];
198
199	for (shift = 0; shift <= 8; ++shift) {
200		if ((rate >> shift) <= wanted)
201			break;
202	}
203
204	if (shift > 8) {
205		dev_dbg(&ourhost->pdev->dev,
206			"clk %d: rate %ld, min rate %lu > wanted %u\n",
207			src, rate, rate / 256, wanted);
208		return UINT_MAX;
209	}
210
211	dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
212		src, rate, wanted, rate >> shift);
213
214	return wanted - (rate >> shift);
215}
216
217/**
218 * sdhci_s3c_set_clock - callback on clock change
219 * @host: The SDHCI host being changed
220 * @clock: The clock rate being requested.
221 *
222 * When the card's clock is going to be changed, look at the new frequency
223 * and find the best clock source to go with it.
224*/
225static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
226{
227	struct sdhci_s3c *ourhost = to_s3c(host);
228	unsigned int best = UINT_MAX;
229	unsigned int delta;
230	int best_src = 0;
231	int src;
232	u32 ctrl;
233
234	host->mmc->actual_clock = 0;
235
236	/* don't bother if the clock is going off. */
237	if (clock == 0) {
238		sdhci_set_clock(host, clock);
239		return;
240	}
241
242	for (src = 0; src < MAX_BUS_CLK; src++) {
243		delta = sdhci_s3c_consider_clock(ourhost, src, clock);
244		if (delta < best) {
245			best = delta;
246			best_src = src;
247		}
248	}
249
250	dev_dbg(&ourhost->pdev->dev,
251		"selected source %d, clock %d, delta %d\n",
252		 best_src, clock, best);
253
254	/* select the new clock source */
255	if (ourhost->cur_clk != best_src) {
256		struct clk *clk = ourhost->clk_bus[best_src];
257
258		clk_prepare_enable(clk);
259		if (ourhost->cur_clk >= 0)
260			clk_disable_unprepare(
261					ourhost->clk_bus[ourhost->cur_clk]);
262
263		ourhost->cur_clk = best_src;
264		host->max_clk = ourhost->clk_rates[best_src];
265	}
266
267	/* turn clock off to card before changing clock source */
268	writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
269
270	ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
271	ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
272	ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
273	writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
274
275	/* reprogram default hardware configuration */
276	writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
277		host->ioaddr + S3C64XX_SDHCI_CONTROL4);
278
279	ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
280	ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
281		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
282		  S3C_SDHCI_CTRL2_ENFBCLKRX |
283		  S3C_SDHCI_CTRL2_DFCNT_NONE |
284		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
285	writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
286
287	/* reconfigure the controller for new clock rate */
288	ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
289	if (clock < 25 * 1000000)
290		ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
291	writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
292
293	sdhci_set_clock(host, clock);
294}
295
296/**
297 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
298 * @host: The SDHCI host being queried
299 *
300 * To init mmc host properly a minimal clock value is needed. For high system
301 * bus clock's values the standard formula gives values out of allowed range.
302 * The clock still can be set to lower values, if clock source other then
303 * system bus is selected.
304*/
305static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
306{
307	struct sdhci_s3c *ourhost = to_s3c(host);
308	unsigned long rate, min = ULONG_MAX;
309	int src;
310
311	for (src = 0; src < MAX_BUS_CLK; src++) {
312		rate = ourhost->clk_rates[src] / 256;
313		if (!rate)
314			continue;
315		if (rate < min)
316			min = rate;
317	}
318
319	return min;
320}
321
322/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
323static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
324{
325	struct sdhci_s3c *ourhost = to_s3c(host);
326	unsigned long rate, max = 0;
327	int src;
328
329	for (src = 0; src < MAX_BUS_CLK; src++) {
330		struct clk *clk;
331
332		clk = ourhost->clk_bus[src];
333		if (IS_ERR(clk))
334			continue;
335
336		rate = clk_round_rate(clk, ULONG_MAX);
337		if (rate > max)
338			max = rate;
339	}
340
341	return max;
342}
343
344/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
345static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
346{
347	struct sdhci_s3c *ourhost = to_s3c(host);
348	unsigned long rate, min = ULONG_MAX;
349	int src;
350
351	for (src = 0; src < MAX_BUS_CLK; src++) {
352		struct clk *clk;
353
354		clk = ourhost->clk_bus[src];
355		if (IS_ERR(clk))
356			continue;
357
358		rate = clk_round_rate(clk, 0);
359		if (rate < min)
360			min = rate;
361	}
362
363	return min;
364}
365
366/* sdhci_cmu_set_clock - callback on clock change.*/
367static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
368{
369	struct sdhci_s3c *ourhost = to_s3c(host);
370	struct device *dev = &ourhost->pdev->dev;
371	unsigned long timeout;
372	u16 clk = 0;
373	int ret;
374
375	host->mmc->actual_clock = 0;
376
377	/* If the clock is going off, set to 0 at clock control register */
378	if (clock == 0) {
379		sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
380		return;
381	}
382
383	sdhci_s3c_set_clock(host, clock);
384
385	/* Reset SD Clock Enable */
386	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
387	clk &= ~SDHCI_CLOCK_CARD_EN;
388	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
389
390	ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
391	if (ret != 0) {
392		dev_err(dev, "%s: failed to set clock rate %uHz\n",
393			mmc_hostname(host->mmc), clock);
394		return;
395	}
396
397	clk = SDHCI_CLOCK_INT_EN;
398	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
399
400	/* Wait max 20 ms */
401	timeout = 20;
402	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
403		& SDHCI_CLOCK_INT_STABLE)) {
404		if (timeout == 0) {
405			dev_err(dev, "%s: Internal clock never stabilised.\n",
406				mmc_hostname(host->mmc));
407			return;
408		}
409		timeout--;
410		mdelay(1);
411	}
412
413	clk |= SDHCI_CLOCK_CARD_EN;
414	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
415}
416
417static const struct sdhci_ops sdhci_s3c_ops_s3c6410 = {
418	.get_max_clock		= sdhci_s3c_get_max_clk,
419	.set_clock		= sdhci_s3c_set_clock,
420	.get_min_clock		= sdhci_s3c_get_min_clock,
421	.set_bus_width		= sdhci_set_bus_width,
422	.reset			= sdhci_reset,
423	.set_uhs_signaling	= sdhci_set_uhs_signaling,
424};
425
426static const struct sdhci_ops sdhci_s3c_ops_exynos4 __maybe_unused = {
427	.get_max_clock		= sdhci_cmu_get_max_clock,
428	.set_clock		= sdhci_cmu_set_clock,
429	.get_min_clock		= sdhci_cmu_get_min_clock,
430	.set_bus_width		= sdhci_set_bus_width,
431	.reset			= sdhci_reset,
432	.set_uhs_signaling	= sdhci_set_uhs_signaling,
433};
434
435#ifdef CONFIG_OF
436static int sdhci_s3c_parse_dt(struct device *dev,
437		struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
438{
439	struct device_node *node = dev->of_node;
440	u32 max_width;
441
442	/* if the bus-width property is not specified, assume width as 1 */
443	if (of_property_read_u32(node, "bus-width", &max_width))
444		max_width = 1;
445	pdata->max_width = max_width;
446
447	/* get the card detection method */
448	if (of_property_read_bool(node, "broken-cd")) {
449		pdata->cd_type = S3C_SDHCI_CD_NONE;
450		return 0;
451	}
452
453	if (of_property_read_bool(node, "non-removable")) {
454		pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
455		return 0;
456	}
457
458	if (of_property_present(node, "cd-gpios"))
459		return 0;
460
461	/* assuming internal card detect that will be configured by pinctrl */
462	pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
463	return 0;
464}
465#else
466static int sdhci_s3c_parse_dt(struct device *dev,
467		struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
468{
469	return -EINVAL;
470}
471#endif
472
473static inline const struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
474			struct platform_device *pdev)
475{
476#ifdef CONFIG_OF
477	if (pdev->dev.of_node)
478		return of_device_get_match_data(&pdev->dev);
479#endif
480	return (const struct sdhci_s3c_drv_data *)
481			platform_get_device_id(pdev)->driver_data;
482}
483
484static int sdhci_s3c_probe(struct platform_device *pdev)
485{
486	struct s3c_sdhci_platdata *pdata;
487	const struct sdhci_s3c_drv_data *drv_data;
488	struct device *dev = &pdev->dev;
489	struct sdhci_host *host;
490	struct sdhci_s3c *sc;
491	int ret, irq, ptr, clks;
492
493	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
494		dev_err(dev, "no device data specified\n");
495		return -ENOENT;
496	}
497
498	irq = platform_get_irq(pdev, 0);
499	if (irq < 0)
500		return irq;
501
502	host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
503	if (IS_ERR(host)) {
504		dev_err(dev, "sdhci_alloc_host() failed\n");
505		return PTR_ERR(host);
506	}
507	sc = sdhci_priv(host);
508
509	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
510	if (!pdata)
511		return -ENOMEM;
512
513	if (pdev->dev.of_node) {
514		ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
515		if (ret)
516			return ret;
517	} else {
518		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
519	}
520
521	drv_data = sdhci_s3c_get_driver_data(pdev);
522
523	sc->host = host;
524	sc->pdev = pdev;
525	sc->pdata = pdata;
526	sc->cur_clk = -1;
527
528	platform_set_drvdata(pdev, host);
529
530	sc->clk_io = devm_clk_get(dev, "hsmmc");
531	if (IS_ERR(sc->clk_io)) {
532		dev_err(dev, "failed to get io clock\n");
533		return PTR_ERR(sc->clk_io);
534	}
535
536	/* enable the local io clock and keep it running for the moment. */
537	clk_prepare_enable(sc->clk_io);
538
539	for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
540		char name[14];
541
542		snprintf(name, 14, "mmc_busclk.%d", ptr);
543		sc->clk_bus[ptr] = devm_clk_get(dev, name);
544		if (IS_ERR(sc->clk_bus[ptr]))
545			continue;
546
547		clks++;
548		sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
549
550		dev_info(dev, "clock source %d: %s (%ld Hz)\n",
551				ptr, name, sc->clk_rates[ptr]);
552	}
553
554	if (clks == 0) {
555		dev_err(dev, "failed to find any bus clocks\n");
556		ret = -ENOENT;
557		goto err_no_busclks;
558	}
559
560	host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
561	if (IS_ERR(host->ioaddr)) {
562		ret = PTR_ERR(host->ioaddr);
563		goto err_req_regs;
564	}
565
566	/* Ensure we have minimal gpio selected CMD/CLK/Detect */
567	if (pdata->cfg_gpio)
568		pdata->cfg_gpio(pdev, pdata->max_width);
569
570	host->hw_name = "samsung-hsmmc";
571	host->ops = &sdhci_s3c_ops_s3c6410;
572	host->quirks = 0;
573	host->quirks2 = 0;
574	host->irq = irq;
575
576	/* Setup quirks for the controller */
577	host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
578	host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
579	if (drv_data) {
580		host->quirks |= drv_data->sdhci_quirks;
581		host->ops = drv_data->ops;
582		sc->no_divider = drv_data->no_divider;
583	}
584
585#ifndef CONFIG_MMC_SDHCI_S3C_DMA
586
587	/* we currently see overruns on errors, so disable the SDMA
588	 * support as well. */
589	host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
590
591#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
592
593	/* It seems we do not get an DATA transfer complete on non-busy
594	 * transfers, not sure if this is a problem with this specific
595	 * SDHCI block, or a missing configuration that needs to be set. */
596	host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
597
598	/* This host supports the Auto CMD12 */
599	host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
600
601	/* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
602	host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
603
604	if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
605	    pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
606		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
607
608	if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
609		host->mmc->caps = MMC_CAP_NONREMOVABLE;
610
611	switch (pdata->max_width) {
612	case 8:
613		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
614		fallthrough;
615	case 4:
616		host->mmc->caps |= MMC_CAP_4_BIT_DATA;
617		break;
618	}
619
620	if (pdata->pm_caps)
621		host->mmc->pm_caps |= pdata->pm_caps;
622
623	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
624			 SDHCI_QUIRK_32BIT_DMA_SIZE);
625
626	/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
627	host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
628
629	/* It supports additional host capabilities if needed */
630	if (pdata->host_caps)
631		host->mmc->caps |= pdata->host_caps;
632
633	if (pdata->host_caps2)
634		host->mmc->caps2 |= pdata->host_caps2;
635
636	pm_runtime_enable(&pdev->dev);
637	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
638	pm_runtime_use_autosuspend(&pdev->dev);
639	pm_suspend_ignore_children(&pdev->dev, 1);
640
641	ret = mmc_of_parse(host->mmc);
642	if (ret)
643		goto err_req_regs;
644
645	ret = sdhci_add_host(host);
646	if (ret)
647		goto err_req_regs;
648
649#ifdef CONFIG_PM
650	if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
651		clk_disable_unprepare(sc->clk_io);
652#endif
653	return 0;
654
655 err_req_regs:
656	pm_runtime_disable(&pdev->dev);
657
658 err_no_busclks:
659	clk_disable_unprepare(sc->clk_io);
660
661	return ret;
662}
663
664static void sdhci_s3c_remove(struct platform_device *pdev)
665{
666	struct sdhci_host *host =  platform_get_drvdata(pdev);
667	struct sdhci_s3c *sc = sdhci_priv(host);
668
669	if (sc->ext_cd_irq)
670		free_irq(sc->ext_cd_irq, sc);
671
672#ifdef CONFIG_PM
673	if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
674		clk_prepare_enable(sc->clk_io);
675#endif
676	sdhci_remove_host(host, 1);
677
678	pm_runtime_dont_use_autosuspend(&pdev->dev);
679	pm_runtime_disable(&pdev->dev);
680
681	clk_disable_unprepare(sc->clk_io);
682}
683
684static int sdhci_s3c_suspend(struct device *dev)
685{
686	struct sdhci_host *host = dev_get_drvdata(dev);
687
688	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
689		mmc_retune_needed(host->mmc);
690
691	return sdhci_suspend_host(host);
692}
693
694static int sdhci_s3c_resume(struct device *dev)
695{
696	struct sdhci_host *host = dev_get_drvdata(dev);
697
698	return sdhci_resume_host(host);
699}
700
701static int sdhci_s3c_runtime_suspend(struct device *dev)
702{
703	struct sdhci_host *host = dev_get_drvdata(dev);
704	struct sdhci_s3c *ourhost = to_s3c(host);
705	struct clk *busclk = ourhost->clk_io;
706
707	sdhci_runtime_suspend_host(host);
708
709	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
710		mmc_retune_needed(host->mmc);
711
712	if (ourhost->cur_clk >= 0)
713		clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
714	clk_disable_unprepare(busclk);
715	return 0;
716}
717
718static int sdhci_s3c_runtime_resume(struct device *dev)
719{
720	struct sdhci_host *host = dev_get_drvdata(dev);
721	struct sdhci_s3c *ourhost = to_s3c(host);
722	struct clk *busclk = ourhost->clk_io;
723
724	clk_prepare_enable(busclk);
725	if (ourhost->cur_clk >= 0)
726		clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
727	sdhci_runtime_resume_host(host, 0);
728	return 0;
729}
730
731static const struct dev_pm_ops sdhci_s3c_pmops = {
732	SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
733	RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, NULL)
734};
735
736static const struct platform_device_id sdhci_s3c_driver_ids[] = {
737	{
738		.name		= "s3c-sdhci",
739		.driver_data	= (kernel_ulong_t)NULL,
740	},
741	{ }
742};
743MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
744
745#ifdef CONFIG_OF
746static const struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
747	.no_divider = true,
748	.ops = &sdhci_s3c_ops_exynos4,
749};
750
751static const struct of_device_id sdhci_s3c_dt_match[] = {
752	{ .compatible = "samsung,s3c6410-sdhci", },
753	{ .compatible = "samsung,exynos4210-sdhci",
754		.data = &exynos4_sdhci_drv_data },
755	{},
756};
757MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
758#endif
759
760static struct platform_driver sdhci_s3c_driver = {
761	.probe		= sdhci_s3c_probe,
762	.remove		= sdhci_s3c_remove,
763	.id_table	= sdhci_s3c_driver_ids,
764	.driver		= {
765		.name	= "s3c-sdhci",
766		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
767		.of_match_table = of_match_ptr(sdhci_s3c_dt_match),
768		.pm	= pm_ptr(&sdhci_s3c_pmops),
769	},
770};
771
772module_platform_driver(sdhci_s3c_driver);
773
774MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
775MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
776MODULE_LICENSE("GPL v2");