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sdhci-pci-gli.c
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linux-6.19.14/drivers/mmc/host/sdhci-pci-gli.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10#include <linux/bitfield.h> 11#include <linux/bits.h> 12#include <linux/pci.h> 13#include <linux/mmc/mmc.h> 14#include <linux/delay.h> 15#include <linux/of.h> 16#include <linux/iopoll.h> 17#include "sdhci.h" 18#include "sdhci-cqhci.h" 19#include "sdhci-pci.h" 20#include "cqhci.h" 21#include "sdhci-uhs2.h" 22 23/* Genesys Logic extra registers */ 24#define SDHCI_GLI_9750_WT 0x800 25#define SDHCI_GLI_9750_WT_EN BIT(0) 26#define GLI_9750_WT_EN_ON 0x1 27#define GLI_9750_WT_EN_OFF 0x0 28 29#define SDHCI_GLI_9750_CFG2 0x848 30#define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 31#define GLI_9750_CFG2_L1DLY_VALUE 0x1F 32 33#define SDHCI_GLI_9750_DRIVING 0x860 34#define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 35#define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 36#define GLI_9750_DRIVING_1_VALUE 0xFFF 37#define GLI_9750_DRIVING_2_VALUE 0x3 38#define SDHCI_GLI_9750_SEL_1 BIT(29) 39#define SDHCI_GLI_9750_SEL_2 BIT(31) 40#define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 41 42#define SDHCI_GLI_9750_PLL 0x864 43#define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 44#define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 45#define SDHCI_GLI_9750_PLL_DIR BIT(15) 46#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 47#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 48#define GLI_9750_PLL_TX2_INV_VALUE 0x1 49#define GLI_9750_PLL_TX2_DLY_VALUE 0x0 50#define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 51#define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 52 53#define SDHCI_GLI_9750_PLLSSC 0x86C 54#define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 55 56#define SDHCI_GLI_9750_SW_CTRL 0x874 57#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 58#define GLI_9750_SW_CTRL_4_VALUE 0x3 59 60#define SDHCI_GLI_9750_MISC 0x878 61#define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 62#define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 63#define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 64#define GLI_9750_MISC_TX1_INV_VALUE 0x0 65#define GLI_9750_MISC_RX_INV_ON 0x1 66#define GLI_9750_MISC_RX_INV_OFF 0x0 67#define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 68#define GLI_9750_MISC_TX1_DLY_VALUE 0x5 69#define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) 70 71#define SDHCI_GLI_9750_GM_BURST_SIZE 0x510 72#define SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT GENMASK(17, 16) 73 74#define SDHCI_GLI_9750_TUNING_CONTROL 0x540 75#define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 76#define GLI_9750_TUNING_CONTROL_EN_ON 0x1 77#define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 78#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 79#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 80#define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 81#define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 82 83#define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 84#define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 85#define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 86 87#define SDHCI_GLI_9763E_CTRL_HS400 0x7 88 89#define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 90#define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 91 92#define PCIE_GLI_9763E_VHS 0x884 93#define GLI_9763E_VHS_REV GENMASK(19, 16) 94#define GLI_9763E_VHS_REV_R 0x0 95#define GLI_9763E_VHS_REV_M 0x1 96#define GLI_9763E_VHS_REV_W 0x2 97#define PCIE_GLI_9763E_MB 0x888 98#define GLI_9763E_MB_CMDQ_OFF BIT(19) 99#define GLI_9763E_MB_ERP_ON BIT(7) 100#define PCIE_GLI_9763E_SCR 0x8E0 101#define GLI_9763E_SCR_AXI_REQ BIT(9) 102 103#define PCIE_GLI_9763E_CFG 0x8A0 104#define GLI_9763E_CFG_LPSN_DIS BIT(12) 105 106#define PCIE_GLI_9763E_CFG2 0x8A4 107#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 108#define GLI_9763E_CFG2_L1DLY_MID 0x54 109 110#define PCIE_GLI_9763E_MMC_CTRL 0x960 111#define GLI_9763E_HS400_SLOW BIT(3) 112 113#define PCIE_GLI_9763E_CLKRXDLY 0x934 114#define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 115#define GLI_9763E_HS400_RXDLY_5 0x5 116 117#define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 118#define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 119 SDHCI_TRNS_BLK_CNT_EN | \ 120 SDHCI_TRNS_DMA) 121 122#define PCI_GLI_9755_WT 0x800 123#define PCI_GLI_9755_WT_EN BIT(0) 124#define GLI_9755_WT_EN_ON 0x1 125#define GLI_9755_WT_EN_OFF 0x0 126 127#define PCI_GLI_9755_PECONF 0x44 128#define PCI_GLI_9755_LFCLK GENMASK(14, 12) 129#define PCI_GLI_9755_DMACLK BIT(29) 130#define PCI_GLI_9755_INVERT_CD BIT(30) 131#define PCI_GLI_9755_INVERT_WP BIT(31) 132 133#define PCI_GLI_9755_CFG2 0x48 134#define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 135#define GLI_9755_CFG2_L1DLY_VALUE 0x1F 136 137#define PCI_GLI_9755_PLL 0x64 138#define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 139#define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 140#define PCI_GLI_9755_PLL_DIR BIT(15) 141#define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 142#define PCI_GLI_9755_PLLSSC_EN BIT(31) 143 144#define PCI_GLI_9755_PLLSSC 0x68 145#define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 146#define PCI_GLI_9755_PLLSSC_RTL BIT(24) 147#define GLI_9755_PLLSSC_RTL_VALUE 0x1 148#define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) 149#define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 150#define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) 151#define GLI_9755_PLLSSC_RECV_VALUE 0x0 152#define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) 153#define GLI_9755_PLLSSC_TRAN_VALUE 0x3 154 155#define PCI_GLI_9755_UHS2_PLL 0x6C 156#define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8) 157#define GLI_9755_UHS2_PLL_SSC_VALUE 0x0 158#define PCI_GLI_9755_UHS2_PLL_DELAY BIT(18) 159#define GLI_9755_UHS2_PLL_DELAY_VALUE 0x1 160#define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) 161#define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 162 163#define PCI_GLI_9755_SerDes 0x70 164#define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0) 165#define GLI_9755_UHS2_SERDES_INTR_VALUE 0x3 166#define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(3) 167#define GLI_9755_UHS2_SERDES_ZC1_VALUE 0x0 168#define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4) 169#define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB 170#define GLI_9755_UHS2_SERDES_ZC2_SANDISK 0x0 171#define PCI_GLI_9755_SCP_DIS BIT(19) 172#define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) 173#define GLI_9755_UHS2_SERDES_TRAN_VALUE 0xC 174#define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28) 175#define GLI_9755_UHS2_SERDES_RECV_VALUE 0xF 176 177#define PCI_GLI_9755_MISC 0x78 178#define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 179 180#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL 0x508 181#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK BIT(0) 182#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE GENMASK(21, 16) 183#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE 0x05 184#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE 0x3F 185#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE GENMASK(23, 22) 186#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS 0x2 187#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS 0x3 188 189#define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 190#define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) 191 192#define PCIE_GLI_9767_VHS 0x884 193#define GLI_9767_VHS_REV GENMASK(19, 16) 194#define GLI_9767_VHS_REV_R 0x0 195#define GLI_9767_VHS_REV_M 0x1 196#define GLI_9767_VHS_REV_W 0x2 197 198#define PCIE_GLI_9767_COM_MAILBOX 0x888 199#define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1) 200 201#define PCIE_GLI_9767_CFG 0x8A0 202#define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12) 203 204#define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8 205#define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6) 206#define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10) 207 208#define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0 209#define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0) 210#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12) 211#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7 212#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28) 213#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3 214 215#define PCIE_GLI_9767_SCR 0x8E0 216#define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6) 217#define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7) 218#define PCIE_GLI_9767_SCR_AXI_REQ BIT(9) 219#define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10) 220#define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16) 221#define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17) 222#define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) 223#define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30) 224 225#define PCIE_GLI_9767_RESET_REG 0x8E4 226#define PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET BIT(0) 227 228#define PCIE_GLI_9767_UHS2_PHY_SET_REG1 0x90C 229#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR GENMASK(31, 29) 230#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE 0x3 231 232#define PCIE_GLI_9767_SDHC_CAP 0x91C 233#define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5) 234 235#define PCIE_GLI_9767_SD_PLL_CTL 0x938 236#define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0) 237#define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12) 238#define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16) 239#define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19) 240#define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24) 241 242#define PCIE_GLI_9767_SD_PLL_CTL2 0x93C 243#define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16) 244 245#define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940 246#define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0) 247#define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) 248 249#define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 250#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5) 251#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL BIT(8) 252#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16) 253#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 254 255#define PCIE_GLI_9767_UHS2_PHY_SET_REG2 0x948 256#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING GENMASK(22, 21) 257#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE 0x0 258 259#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950 260#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) 261 262#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954 263#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0) 264 265#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 266#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0) 267 268#define PCIE_GLI_9767_UHS2_CTL1 0x95C 269#define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS BIT(5) 270#define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE 0x1 271#define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL BIT(6) 272#define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE 0x1 273#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN GENMASK(10, 7) 274#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE 0x3 275#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV GENMASK(14, 11) 276#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE 0xf 277#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS GENMASK(16, 15) 278#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE 0x0 279#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV GENMASK(18, 17) 280#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE 0x0 281#define PCIE_GLI_9767_UHS2_CTL1_PDRST BIT(25) 282#define PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE 0x1 283 284#define PCIE_GLI_9767_UHS2_CTL2 0x964 285#define PCIE_GLI_9767_UHS2_CTL2_ZC GENMASK(3, 0) 286#define PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE 0xb 287#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL BIT(6) 288#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE 0x1 289#define PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN BIT(13) 290#define PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE BIT(14) 291 292#define GLI_MAX_TUNING_LOOP 40 293 294/* Genesys Logic chipset */ 295static void sdhci_gli_mask_replay_timer_timeout(struct pci_dev *pdev) 296{ 297 int aer; 298 u32 value; 299 300 /* mask the replay timer timeout of AER */ 301 aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 302 if (aer) { 303 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); 304 value |= PCI_ERR_COR_REP_TIMER; 305 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); 306 } 307} 308 309static inline void gl9750_wt_on(struct sdhci_host *host) 310{ 311 u32 wt_value; 312 u32 wt_enable; 313 314 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 315 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 316 317 if (wt_enable == GLI_9750_WT_EN_ON) 318 return; 319 320 wt_value &= ~SDHCI_GLI_9750_WT_EN; 321 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 322 323 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 324} 325 326static inline void gl9750_wt_off(struct sdhci_host *host) 327{ 328 u32 wt_value; 329 u32 wt_enable; 330 331 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 332 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 333 334 if (wt_enable == GLI_9750_WT_EN_OFF) 335 return; 336 337 wt_value &= ~SDHCI_GLI_9750_WT_EN; 338 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 339 340 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 341} 342 343static void gli_set_9750(struct sdhci_host *host) 344{ 345 u32 driving_value; 346 u32 pll_value; 347 u32 sw_ctrl_value; 348 u32 misc_value; 349 u32 parameter_value; 350 u32 control_value; 351 u32 burst_value; 352 u16 ctrl2; 353 354 gl9750_wt_on(host); 355 356 /* clear R_OSRC_Lmt to avoid DMA write corruption */ 357 burst_value = sdhci_readl(host, SDHCI_GLI_9750_GM_BURST_SIZE); 358 burst_value &= ~SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT; 359 sdhci_writel(host, burst_value, SDHCI_GLI_9750_GM_BURST_SIZE); 360 361 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 362 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 363 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 364 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 365 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 366 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 367 368 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 369 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 370 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 371 GLI_9750_DRIVING_1_VALUE); 372 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 373 GLI_9750_DRIVING_2_VALUE); 374 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 375 driving_value |= SDHCI_GLI_9750_SEL_2; 376 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 377 378 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 379 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 380 GLI_9750_SW_CTRL_4_VALUE); 381 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 382 383 /* reset the tuning flow after reinit and before starting tuning */ 384 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 385 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 386 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 387 GLI_9750_PLL_TX2_INV_VALUE); 388 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 389 GLI_9750_PLL_TX2_DLY_VALUE); 390 391 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 392 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 393 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 394 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 395 GLI_9750_MISC_TX1_INV_VALUE); 396 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 397 GLI_9750_MISC_RX_INV_VALUE); 398 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 399 GLI_9750_MISC_TX1_DLY_VALUE); 400 401 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 402 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 403 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 404 405 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 406 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 407 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 408 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 409 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 410 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 411 412 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 413 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 414 415 /* disable tuned clk */ 416 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 417 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 418 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 419 420 /* enable tuning parameters control */ 421 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 422 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 423 GLI_9750_TUNING_CONTROL_EN_ON); 424 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 425 426 /* write tuning parameters */ 427 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 428 429 /* disable tuning parameters control */ 430 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 431 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 432 GLI_9750_TUNING_CONTROL_EN_OFF); 433 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 434 435 /* clear tuned clk */ 436 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 437 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 438 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 439 440 gl9750_wt_off(host); 441} 442 443static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 444{ 445 u32 misc_value; 446 447 gl9750_wt_on(host); 448 449 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 450 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 451 if (b) { 452 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 453 GLI_9750_MISC_RX_INV_ON); 454 } else { 455 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 456 GLI_9750_MISC_RX_INV_OFF); 457 } 458 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 459 460 gl9750_wt_off(host); 461} 462 463static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 464{ 465 int i; 466 int rx_inv; 467 468 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 469 gli_set_9750_rx_inv(host, !!rx_inv); 470 sdhci_start_tuning(host); 471 472 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 473 u16 ctrl; 474 475 sdhci_send_tuning(host, opcode); 476 477 if (!host->tuning_done) { 478 sdhci_abort_tuning(host, opcode); 479 break; 480 } 481 482 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 483 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 484 if (ctrl & SDHCI_CTRL_TUNED_CLK) 485 return 0; /* Success! */ 486 break; 487 } 488 } 489 } 490 if (!host->tuning_done) { 491 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 492 mmc_hostname(host->mmc)); 493 return -ETIMEDOUT; 494 } 495 496 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 497 mmc_hostname(host->mmc)); 498 sdhci_reset_tuning(host); 499 500 return -EAGAIN; 501} 502 503static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 504{ 505 host->mmc->retune_period = 0; 506 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 507 host->mmc->retune_period = host->tuning_count; 508 509 gli_set_9750(host); 510 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 511 sdhci_end_tuning(host); 512 513 return 0; 514} 515 516static void gl9750_disable_ssc_pll(struct sdhci_host *host) 517{ 518 u32 pll; 519 520 gl9750_wt_on(host); 521 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 522 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 523 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 524 gl9750_wt_off(host); 525} 526 527static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 528{ 529 u32 pll; 530 531 gl9750_wt_on(host); 532 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 533 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 534 SDHCI_GLI_9750_PLL_PDIV | 535 SDHCI_GLI_9750_PLL_DIR); 536 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 537 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 538 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 539 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 540 gl9750_wt_off(host); 541 542 /* wait for pll stable */ 543 mdelay(1); 544} 545 546static bool gl9750_ssc_enable(struct sdhci_host *host) 547{ 548 u32 misc; 549 u8 off; 550 551 gl9750_wt_on(host); 552 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); 553 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc); 554 gl9750_wt_off(host); 555 556 return !off; 557} 558 559static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 560{ 561 u32 pll; 562 u32 ssc; 563 564 gl9750_wt_on(host); 565 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 566 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 567 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 568 SDHCI_GLI_9750_PLLSSC_EN); 569 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 570 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 571 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 572 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 573 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 574 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 575 gl9750_wt_off(host); 576} 577 578static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 579{ 580 bool enable = gl9750_ssc_enable(host); 581 582 /* set pll to 205MHz and ssc */ 583 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); 584 gl9750_set_pll(host, 0x1, 0x246, 0x0); 585} 586 587static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 588{ 589 bool enable = gl9750_ssc_enable(host); 590 591 /* set pll to 100MHz and ssc */ 592 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 593 gl9750_set_pll(host, 0x1, 0x244, 0x1); 594} 595 596static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 597{ 598 bool enable = gl9750_ssc_enable(host); 599 600 /* set pll to 50MHz and ssc */ 601 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 602 gl9750_set_pll(host, 0x1, 0x244, 0x3); 603} 604 605static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 606{ 607 struct mmc_ios *ios = &host->mmc->ios; 608 u16 clk; 609 610 host->mmc->actual_clock = 0; 611 612 gl9750_disable_ssc_pll(host); 613 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 614 615 if (clock == 0) 616 return; 617 618 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 619 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 620 host->mmc->actual_clock = 205000000; 621 gl9750_set_ssc_pll_205mhz(host); 622 } else if (clock == 100000000) { 623 gl9750_set_ssc_pll_100mhz(host); 624 } else if (clock == 50000000) { 625 gl9750_set_ssc_pll_50mhz(host); 626 } 627 628 sdhci_enable_clk(host, clk); 629} 630 631static void gl9750_hw_setting(struct sdhci_host *host) 632{ 633 struct sdhci_pci_slot *slot = sdhci_priv(host); 634 struct pci_dev *pdev; 635 u32 value; 636 637 pdev = slot->chip->pdev; 638 639 gl9750_wt_on(host); 640 641 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 642 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 643 /* set ASPM L1 entry delay to 7.9us */ 644 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 645 GLI_9750_CFG2_L1DLY_VALUE); 646 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 647 648 /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ 649 pci_set_power_state(pdev, PCI_D3hot); 650 pci_set_power_state(pdev, PCI_D0); 651 652 /* mask the replay timer timeout of AER */ 653 sdhci_gli_mask_replay_timer_timeout(pdev); 654 655 gl9750_wt_off(host); 656} 657 658static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 659{ 660 int ret; 661 662 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 663 PCI_IRQ_MSI | PCI_IRQ_MSIX); 664 if (ret < 0) { 665 pr_warn("%s: enable PCI MSI failed, error=%d\n", 666 mmc_hostname(slot->host->mmc), ret); 667 return; 668 } 669 670 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 671} 672 673static inline void gl9755_wt_on(struct pci_dev *pdev) 674{ 675 u32 wt_value; 676 u32 wt_enable; 677 678 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 679 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 680 681 if (wt_enable == GLI_9755_WT_EN_ON) 682 return; 683 684 wt_value &= ~PCI_GLI_9755_WT_EN; 685 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 686 687 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 688} 689 690static inline void gl9755_wt_off(struct pci_dev *pdev) 691{ 692 u32 wt_value; 693 u32 wt_enable; 694 695 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 696 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 697 698 if (wt_enable == GLI_9755_WT_EN_OFF) 699 return; 700 701 wt_value &= ~PCI_GLI_9755_WT_EN; 702 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 703 704 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 705} 706 707static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 708{ 709 u32 pll; 710 711 gl9755_wt_on(pdev); 712 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 713 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 714 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 715 gl9755_wt_off(pdev); 716} 717 718static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 719{ 720 u32 pll; 721 722 gl9755_wt_on(pdev); 723 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 724 pll &= ~(PCI_GLI_9755_PLL_LDIV | 725 PCI_GLI_9755_PLL_PDIV | 726 PCI_GLI_9755_PLL_DIR); 727 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 728 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 729 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 730 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 731 gl9755_wt_off(pdev); 732 733 /* wait for pll stable */ 734 mdelay(1); 735} 736 737static bool gl9755_ssc_enable(struct pci_dev *pdev) 738{ 739 u32 misc; 740 u8 off; 741 742 gl9755_wt_on(pdev); 743 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); 744 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); 745 gl9755_wt_off(pdev); 746 747 return !off; 748} 749 750static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 751{ 752 u32 pll; 753 u32 ssc; 754 755 gl9755_wt_on(pdev); 756 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 757 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 758 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 759 PCI_GLI_9755_PLLSSC_EN); 760 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 761 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 762 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 763 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 764 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 765 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 766 gl9755_wt_off(pdev); 767} 768 769static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 770{ 771 bool enable = gl9755_ssc_enable(pdev); 772 773 /* set pll to 205MHz and ssc */ 774 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); 775 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 776} 777 778static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 779{ 780 bool enable = gl9755_ssc_enable(pdev); 781 782 /* set pll to 100MHz and ssc */ 783 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 784 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 785} 786 787static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 788{ 789 bool enable = gl9755_ssc_enable(pdev); 790 791 /* set pll to 50MHz and ssc */ 792 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 793 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 794} 795 796static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 797{ 798 struct sdhci_pci_slot *slot = sdhci_priv(host); 799 struct mmc_ios *ios = &host->mmc->ios; 800 struct pci_dev *pdev; 801 u16 clk; 802 803 pdev = slot->chip->pdev; 804 host->mmc->actual_clock = 0; 805 806 gl9755_disable_ssc_pll(pdev); 807 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 808 809 if (clock == 0) 810 return; 811 812 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 813 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 814 host->mmc->actual_clock = 205000000; 815 gl9755_set_ssc_pll_205mhz(pdev); 816 } else if (clock == 100000000) { 817 gl9755_set_ssc_pll_100mhz(pdev); 818 } else if (clock == 50000000) { 819 gl9755_set_ssc_pll_50mhz(pdev); 820 } 821 822 sdhci_enable_clk(host, clk); 823} 824 825static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 826{ 827 struct pci_dev *pdev = slot->chip->pdev; 828 u32 value; 829 830 gl9755_wt_on(pdev); 831 832 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 833 /* 834 * Apple ARM64 platforms using these chips may have 835 * inverted CD/WP detection. 836 */ 837 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 838 value |= PCI_GLI_9755_INVERT_CD; 839 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 840 value |= PCI_GLI_9755_INVERT_WP; 841 value &= ~PCI_GLI_9755_LFCLK; 842 value &= ~PCI_GLI_9755_DMACLK; 843 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 844 845 /* enable short circuit protection */ 846 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 847 value &= ~PCI_GLI_9755_SCP_DIS; 848 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 849 850 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 851 value &= ~PCI_GLI_9755_CFG2_L1DLY; 852 /* set ASPM L1 entry delay to 7.9us */ 853 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 854 GLI_9755_CFG2_L1DLY_VALUE); 855 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 856 857 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ 858 pci_set_power_state(pdev, PCI_D3hot); 859 pci_set_power_state(pdev, PCI_D0); 860 861 /* mask the replay timer timeout of AER */ 862 sdhci_gli_mask_replay_timer_timeout(pdev); 863 864 gl9755_wt_off(pdev); 865} 866 867static void gl9755_vendor_init(struct sdhci_host *host) 868{ 869 struct sdhci_pci_slot *slot = sdhci_priv(host); 870 struct pci_dev *pdev = slot->chip->pdev; 871 u32 serdes; 872 u32 pllssc; 873 u32 uhs2_pll; 874 875 gl9755_wt_on(pdev); 876 877 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); 878 serdes &= ~PCI_GLI_9755_UHS2_SERDES_TRAN; 879 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN, 880 GLI_9755_UHS2_SERDES_TRAN_VALUE); 881 serdes &= ~PCI_GLI_9755_UHS2_SERDES_RECV; 882 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV, 883 GLI_9755_UHS2_SERDES_RECV_VALUE); 884 serdes &= ~PCI_GLI_9755_UHS2_SERDES_INTR; 885 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR, 886 GLI_9755_UHS2_SERDES_INTR_VALUE); 887 serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC1; 888 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, 889 GLI_9755_UHS2_SERDES_ZC1_VALUE); 890 serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC2; 891 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, 892 GLI_9755_UHS2_SERDES_ZC2_DEFAULT); 893 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); 894 895 pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll); 896 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_SSC; 897 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC, 898 GLI_9755_UHS2_PLL_SSC_VALUE); 899 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_DELAY; 900 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY, 901 GLI_9755_UHS2_PLL_DELAY_VALUE); 902 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_PDRST; 903 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST, 904 GLI_9755_UHS2_PLL_PDRST_VALUE); 905 pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll); 906 907 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc); 908 pllssc &= ~PCI_GLI_9755_PLLSSC_RTL; 909 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL, 910 GLI_9755_PLLSSC_RTL_VALUE); 911 pllssc &= ~PCI_GLI_9755_PLLSSC_TRANS_PASS; 912 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS, 913 GLI_9755_PLLSSC_TRANS_PASS_VALUE); 914 pllssc &= ~PCI_GLI_9755_PLLSSC_RECV; 915 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV, 916 GLI_9755_PLLSSC_RECV_VALUE); 917 pllssc &= ~PCI_GLI_9755_PLLSSC_TRAN; 918 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN, 919 GLI_9755_PLLSSC_TRAN_VALUE); 920 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); 921 922 gl9755_wt_off(pdev); 923} 924 925static void sdhci_gli_pre_detect_init(struct sdhci_host *host) 926{ 927 /* Need more time on UHS2 detect flow */ 928 sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL); 929} 930 931static void sdhci_gli_overcurrent_event_enable(struct sdhci_host *host, bool enable) 932{ 933 u32 mask; 934 935 mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); 936 if (enable) 937 mask |= SDHCI_INT_BUS_POWER; 938 else 939 mask &= ~SDHCI_INT_BUS_POWER; 940 941 sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); 942 943 mask = sdhci_readl(host, SDHCI_INT_ENABLE); 944 if (enable) 945 mask |= SDHCI_INT_BUS_POWER; 946 else 947 mask &= ~SDHCI_INT_BUS_POWER; 948 949 sdhci_writel(host, mask, SDHCI_INT_ENABLE); 950} 951 952static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, 953 unsigned short vdd) 954{ 955 u8 pwr = 0; 956 957 if (mode != MMC_POWER_OFF) { 958 pwr = sdhci_get_vdd_value(vdd); 959 if (!pwr) 960 WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); 961 pwr |= SDHCI_VDD2_POWER_180; 962 } 963 964 if (host->pwr == pwr) 965 return; 966 967 host->pwr = pwr; 968 969 if (pwr == 0) { 970 sdhci_gli_overcurrent_event_enable(host, false); 971 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 972 } else { 973 sdhci_gli_overcurrent_event_enable(host, false); 974 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 975 976 pwr |= (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); 977 978 sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); 979 /* wait stable */ 980 mdelay(5); 981 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 982 /* wait stable */ 983 mdelay(5); 984 sdhci_gli_overcurrent_event_enable(host, true); 985 } 986} 987 988static bool sdhci_wait_clock_stable(struct sdhci_host *host) 989{ 990 u16 clk = 0; 991 992 if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), 993 10, 20000, false, host, SDHCI_CLOCK_CONTROL)) { 994 pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); 995 sdhci_dumpregs(host); 996 return false; 997 } 998 return true; 999} 1000 1001static void sdhci_gli_enable_internal_clock(struct sdhci_host *host) 1002{ 1003 u16 ctrl2; 1004 1005 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1006 1007 sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); 1008 1009 if (!((ctrl2 & SDHCI_CTRL_V4_MODE) && 1010 (ctrl2 & SDHCI_CTRL_UHS2_ENABLE))) { 1011 sdhci_wait_clock_stable(host); 1012 sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2); 1013 } 1014} 1015 1016static int sdhci_gli_wait_software_reset_done(struct sdhci_host *host, u8 mask) 1017{ 1018 u8 rst; 1019 1020 /* hw clears the bit when it's done */ 1021 if (read_poll_timeout_atomic(sdhci_readb, rst, !(rst & mask), 1022 10, 100000, false, host, SDHCI_SOFTWARE_RESET)) { 1023 pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); 1024 sdhci_dumpregs(host); 1025 /* manual clear */ 1026 sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET); 1027 return -ETIMEDOUT; 1028 } 1029 1030 return 0; 1031} 1032 1033static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host) 1034{ 1035 /* do this on UHS2 mode */ 1036 if (host->mmc->uhs2_sd_tran) { 1037 sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); 1038 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1039 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1040 sdhci_uhs2_clear_set_irqs(host, 1041 SDHCI_INT_ALL_MASK, 1042 SDHCI_UHS2_INT_ERROR_MASK); 1043 } 1044} 1045 1046static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask) 1047{ 1048 /* need internal clock */ 1049 if (mask & SDHCI_RESET_ALL) 1050 sdhci_gli_enable_internal_clock(host); 1051 1052 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1053 1054 /* reset sd-tran on UHS2 mode if need to reset cmd/data */ 1055 if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA)) 1056 sdhci_gli_uhs2_reset_sd_tran(host); 1057 1058 if (mask & SDHCI_RESET_ALL) 1059 host->clock = 0; 1060 1061 sdhci_gli_wait_software_reset_done(host, mask); 1062} 1063 1064static inline void gl9767_vhs_read(struct pci_dev *pdev) 1065{ 1066 u32 vhs_enable; 1067 u32 vhs_value; 1068 1069 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 1070 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 1071 1072 if (vhs_enable == GLI_9767_VHS_REV_R) 1073 return; 1074 1075 vhs_value &= ~GLI_9767_VHS_REV; 1076 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R); 1077 1078 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 1079} 1080 1081static inline void gl9767_vhs_write(struct pci_dev *pdev) 1082{ 1083 u32 vhs_enable; 1084 u32 vhs_value; 1085 1086 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 1087 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 1088 1089 if (vhs_enable == GLI_9767_VHS_REV_W) 1090 return; 1091 1092 vhs_value &= ~GLI_9767_VHS_REV; 1093 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W); 1094 1095 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 1096} 1097 1098static bool gl9767_ssc_enable(struct pci_dev *pdev) 1099{ 1100 u32 value; 1101 u8 enable; 1102 1103 gl9767_vhs_write(pdev); 1104 1105 pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value); 1106 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value); 1107 1108 gl9767_vhs_read(pdev); 1109 1110 return enable; 1111} 1112 1113static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 1114{ 1115 u32 pll; 1116 u32 ssc; 1117 1118 gl9767_vhs_write(pdev); 1119 1120 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1121 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); 1122 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING | 1123 PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 1124 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; 1125 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) | 1126 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable); 1127 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); 1128 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); 1129 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1130 1131 gl9767_vhs_read(pdev); 1132} 1133 1134static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 1135{ 1136 u32 pll; 1137 1138 gl9767_vhs_write(pdev); 1139 1140 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1141 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV | 1142 PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV | 1143 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN); 1144 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) | 1145 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) | 1146 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir); 1147 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1148 1149 gl9767_vhs_read(pdev); 1150 1151 /* wait for pll stable */ 1152 usleep_range(1000, 1100); 1153} 1154 1155static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev) 1156{ 1157 bool enable = gl9767_ssc_enable(pdev); 1158 1159 /* set pll to 205MHz and ssc */ 1160 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3); 1161 gl9767_set_pll(pdev, 0x1, 0x246, 0x0); 1162} 1163 1164static void gl9767_disable_ssc_pll(struct pci_dev *pdev) 1165{ 1166 u32 pll; 1167 1168 gl9767_vhs_write(pdev); 1169 1170 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1171 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 1172 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1173 1174 gl9767_vhs_read(pdev); 1175} 1176 1177static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable) 1178{ 1179 u32 value; 1180 1181 gl9767_vhs_write(pdev); 1182 1183 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1184 if (enable) 1185 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1186 else 1187 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1188 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1189 1190 gl9767_vhs_read(pdev); 1191} 1192 1193static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert) 1194{ 1195 struct sdhci_pci_slot *slot = sdhci_priv(host); 1196 struct pci_dev *pdev = slot->chip->pdev; 1197 u32 value, set, clr; 1198 1199 if (assert) { 1200 /* Assert reset, set RESETN and clean RESETN_VALUE */ 1201 set = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; 1202 clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; 1203 } else { 1204 /* De-assert reset, clean RESETN and set RESETN_VALUE */ 1205 set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; 1206 clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; 1207 } 1208 1209 gl9767_vhs_write(pdev); 1210 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); 1211 value |= set; 1212 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); 1213 value &= ~clr; 1214 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); 1215 gl9767_vhs_read(pdev); 1216} 1217 1218static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) 1219{ 1220 u8 pwr = 0; 1221 1222 if (mode != MMC_POWER_OFF) { 1223 pwr = sdhci_get_vdd_value(vdd); 1224 if (!pwr) 1225 WARN(1, "%s: Invalid vdd %#x\n", 1226 mmc_hostname(host->mmc), vdd); 1227 pwr |= SDHCI_VDD2_POWER_180; 1228 } 1229 1230 if (host->pwr == pwr) 1231 return; 1232 1233 host->pwr = pwr; 1234 1235 if (pwr == 0) { 1236 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1237 } else { 1238 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1239 1240 pwr |= SDHCI_POWER_ON; 1241 sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); 1242 usleep_range(5000, 6250); 1243 1244 /* Assert reset */ 1245 sdhci_gl9767_uhs2_phy_reset(host, true); 1246 pwr |= SDHCI_VDD2_POWER_ON; 1247 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1248 usleep_range(5000, 6250); 1249 } 1250} 1251 1252static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) 1253{ 1254 struct sdhci_pci_slot *slot = sdhci_priv(host); 1255 struct mmc_ios *ios = &host->mmc->ios; 1256 struct pci_dev *pdev; 1257 u16 clk; 1258 1259 pdev = slot->chip->pdev; 1260 host->mmc->actual_clock = 0; 1261 1262 gl9767_set_low_power_negotiation(pdev, false); 1263 gl9767_disable_ssc_pll(pdev); 1264 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1265 1266 if (clock == 0) { 1267 gl9767_set_low_power_negotiation(pdev, true); 1268 return; 1269 } 1270 1271 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1272 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 1273 host->mmc->actual_clock = 205000000; 1274 gl9767_set_ssc_pll_205mhz(pdev); 1275 } 1276 1277 sdhci_enable_clk(host, clk); 1278 1279 if (mmc_card_uhs2(host->mmc)) 1280 /* De-assert reset */ 1281 sdhci_gl9767_uhs2_phy_reset(host, false); 1282 1283 gl9767_set_low_power_negotiation(pdev, true); 1284} 1285 1286static void sdhci_gl9767_set_card_detect_debounce_time(struct sdhci_host *host) 1287{ 1288 u32 value; 1289 1290 value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1291 value &= ~(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE | 1292 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE); 1293 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) 1294 value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, 1295 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE) | 1296 FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, 1297 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS); 1298 else 1299 value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, 1300 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE) | 1301 FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, 1302 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS); 1303 sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1304} 1305 1306static void sdhci_gl9767_card_event(struct sdhci_host *host) 1307{ 1308 sdhci_gl9767_set_card_detect_debounce_time(host); 1309} 1310 1311static void gli_set_9767(struct sdhci_host *host) 1312{ 1313 u32 value; 1314 1315 value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE); 1316 value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET; 1317 sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE); 1318 1319 value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1320 value &= ~SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK; 1321 sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1322 1323 sdhci_gl9767_set_card_detect_debounce_time(host); 1324} 1325 1326static void gl9767_hw_setting(struct sdhci_pci_slot *slot) 1327{ 1328 struct pci_dev *pdev = slot->chip->pdev; 1329 u32 value; 1330 1331 gl9767_vhs_write(pdev); 1332 1333 pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value); 1334 value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 1335 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE | 1336 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL); 1337 1338 value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 1339 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE, 1340 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) | 1341 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL, 1342 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE); 1343 pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value); 1344 1345 pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value); 1346 value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 | 1347 PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 | 1348 PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN); 1349 1350 value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST | 1351 PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST | 1352 PCIE_GLI_9767_SCR_AXI_REQ | 1353 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN | 1354 PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF; 1355 pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value); 1356 1357 gl9767_vhs_read(pdev); 1358} 1359 1360static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask) 1361{ 1362 struct sdhci_pci_slot *slot = sdhci_priv(host); 1363 struct pci_dev *pdev = slot->chip->pdev; 1364 u32 value; 1365 1366 /* need internal clock */ 1367 if (mask & SDHCI_RESET_ALL) { 1368 sdhci_gli_enable_internal_clock(host); 1369 1370 gl9767_vhs_write(pdev); 1371 1372 pci_read_config_dword(pdev, PCIE_GLI_9767_RESET_REG, &value); 1373 value &= ~PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET; 1374 pci_write_config_dword(pdev, PCIE_GLI_9767_RESET_REG, value); 1375 1376 if (read_poll_timeout_atomic(pci_read_config_dword, value, 1377 !(value & PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET), 1378 1, 5, true, pdev, PCIE_GLI_9767_RESET_REG, &value)) { 1379 pr_warn("%s: %s: Reset SDHC AHB and TL-AMBA failure.\n", 1380 __func__, mmc_hostname(host->mmc)); 1381 gl9767_vhs_read(pdev); 1382 return; 1383 } 1384 gl9767_vhs_read(pdev); 1385 } 1386 1387 if (mmc_card_uhs2(host->mmc)) { 1388 if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) { 1389 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1390 sdhci_gli_uhs2_reset_sd_tran(host); 1391 sdhci_gli_wait_software_reset_done(host, mask); 1392 } else { 1393 sdhci_uhs2_reset(host, mask); 1394 } 1395 } else { 1396 sdhci_reset(host, mask); 1397 } 1398 1399 gli_set_9767(host); 1400} 1401 1402static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 1403{ 1404 struct sdhci_host *host = mmc_priv(mmc); 1405 struct sdhci_pci_slot *slot = sdhci_priv(host); 1406 struct pci_dev *pdev; 1407 u32 value; 1408 int i; 1409 1410 pdev = slot->chip->pdev; 1411 1412 if (mmc->ops->get_ro(mmc)) { 1413 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 1414 return 0; 1415 } 1416 1417 gl9767_vhs_write(pdev); 1418 1419 pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value); 1420 value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN); 1421 pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value); 1422 1423 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1424 value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME; 1425 value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME, 1426 PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE); 1427 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1428 1429 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1430 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE; 1431 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value); 1432 1433 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value); 1434 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN; 1435 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value); 1436 1437 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value); 1438 value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN; 1439 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value); 1440 1441 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1442 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1443 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1444 1445 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1446 value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1447 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1448 1449 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1450 value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1451 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1452 1453 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1454 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE; 1455 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1456 1457 for (i = 0; i < 2; i++) { 1458 usleep_range(10000, 10100); 1459 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1460 if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) { 1461 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, 1462 value); 1463 break; 1464 } 1465 } 1466 1467 pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value); 1468 if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) { 1469 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1470 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE; 1471 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1472 } else { 1473 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 1474 1475 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1476 value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1477 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1478 1479 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1480 value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1481 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1482 } 1483 1484 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1485 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1486 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1487 gl9767_vhs_read(pdev); 1488 1489 return 0; 1490} 1491 1492static void gl9767_vendor_init(struct sdhci_host *host) 1493{ 1494 struct sdhci_pci_slot *slot = sdhci_priv(host); 1495 struct pci_dev *pdev = slot->chip->pdev; 1496 u32 value; 1497 1498 gl9767_vhs_write(pdev); 1499 1500 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, &value); 1501 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR, 1502 PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE); 1503 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, value); 1504 1505 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, &value); 1506 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING, 1507 PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE); 1508 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, value); 1509 1510 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, &value); 1511 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS, 1512 PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE) | 1513 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL, 1514 PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE) | 1515 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN, 1516 PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE) | 1517 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV, 1518 PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE) | 1519 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS, 1520 PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE) | 1521 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_RECV, 1522 PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE) | 1523 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_PDRST, 1524 PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE); 1525 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, value); 1526 1527 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); 1528 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC, 1529 PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE) | 1530 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC_CTL, 1531 PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE); 1532 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); 1533 1534 gl9767_vhs_read(pdev); 1535} 1536 1537static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) 1538{ 1539 struct sdhci_pci_slot *slot = sdhci_priv(host); 1540 struct pci_dev *pdev = slot->chip->pdev; 1541 u32 value; 1542 1543 if (mmc_card_uhs2(host->mmc)) { 1544 gl9767_vhs_write(pdev); 1545 1546 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1547 value |= PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | 1548 PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL; 1549 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1550 1551 gl9767_vhs_read(pdev); 1552 1553 sdhci_gli_overcurrent_event_enable(host, false); 1554 __gl9767_uhs2_set_power(host, mode, vdd); 1555 sdhci_gli_overcurrent_event_enable(host, true); 1556 } else { 1557 gl9767_vhs_write(pdev); 1558 1559 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1560 value &= ~(PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | 1561 PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL); 1562 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1563 1564 gl9767_vhs_read(pdev); 1565 1566 sdhci_gli_overcurrent_event_enable(host, false); 1567 sdhci_set_power(host, mode, vdd); 1568 sdhci_gli_overcurrent_event_enable(host, true); 1569 } 1570} 1571 1572static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 1573{ 1574 struct sdhci_host *host = slot->host; 1575 1576 gl9750_hw_setting(host); 1577 gli_pcie_enable_msi(slot); 1578 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1579 sdhci_enable_v4_mode(host); 1580 1581 return 0; 1582} 1583 1584static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 1585{ 1586 struct sdhci_host *host = slot->host; 1587 1588 gl9755_hw_setting(slot); 1589 gli_pcie_enable_msi(slot); 1590 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1591 sdhci_enable_v4_mode(host); 1592 gl9755_vendor_init(host); 1593 1594 return 0; 1595} 1596 1597static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot) 1598{ 1599 struct sdhci_host *host = slot->host; 1600 1601 gli_set_9767(host); 1602 gl9767_hw_setting(slot); 1603 gli_pcie_enable_msi(slot); 1604 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1605 host->mmc->caps2 |= MMC_CAP2_SD_EXP; 1606 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; 1607 sdhci_enable_v4_mode(host); 1608 gl9767_vendor_init(host); 1609 1610 return 0; 1611} 1612 1613static void sdhci_gli_voltage_switch(struct sdhci_host *host) 1614{ 1615 /* 1616 * According to Section 3.6.1 signal voltage switch procedure in 1617 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1618 * follows: 1619 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1620 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1621 * period. 1622 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1623 * step (12). 1624 * 1625 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1626 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 1627 * 1628 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 1629 * slightly longer than 5ms before the control register reports that 1630 * 1.8V is ready, and far longer still before the card will actually 1631 * work reliably. 1632 */ 1633 usleep_range(100000, 110000); 1634} 1635 1636static void sdhci_gl9767_voltage_switch(struct sdhci_host *host) 1637{ 1638 /* 1639 * According to Section 3.6.1 signal voltage switch procedure in 1640 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1641 * follows: 1642 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1643 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1644 * period. 1645 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1646 * step (12). 1647 * 1648 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1649 * to ensure 1.8V signal enable bit is set by GL9767. 1650 * 1651 */ 1652 usleep_range(5000, 5500); 1653} 1654 1655static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 1656{ 1657 sdhci_reset(host, mask); 1658 gli_set_9750(host); 1659} 1660 1661static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 1662{ 1663 u32 value; 1664 1665 value = readl(host->ioaddr + reg); 1666 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 1667 value |= 0xc8; 1668 1669 return value; 1670} 1671 1672static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 1673 struct mmc_ios *ios) 1674{ 1675 struct sdhci_host *host = mmc_priv(mmc); 1676 u32 val; 1677 1678 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 1679 if (ios->enhanced_strobe) 1680 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 1681 else 1682 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 1683 1684 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 1685} 1686 1687static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, 1688 bool enable) 1689{ 1690 struct pci_dev *pdev = slot->chip->pdev; 1691 u32 value; 1692 1693 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1694 value &= ~GLI_9763E_VHS_REV; 1695 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1696 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1697 1698 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value); 1699 1700 if (enable) 1701 value &= ~GLI_9763E_CFG_LPSN_DIS; 1702 else 1703 value |= GLI_9763E_CFG_LPSN_DIS; 1704 1705 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value); 1706 1707 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1708 value &= ~GLI_9763E_VHS_REV; 1709 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1710 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1711} 1712 1713static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 1714 unsigned int timing) 1715{ 1716 u16 ctrl_2; 1717 1718 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1719 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1720 if (timing == MMC_TIMING_MMC_HS200) 1721 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1722 else if (timing == MMC_TIMING_MMC_HS) 1723 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1724 else if (timing == MMC_TIMING_MMC_DDR52) 1725 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1726 else if (timing == MMC_TIMING_MMC_HS400) 1727 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 1728 1729 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1730} 1731 1732static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 1733{ 1734 sdhci_dumpregs(mmc_priv(mmc)); 1735} 1736 1737static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 1738{ 1739 struct cqhci_host *cq_host = mmc->cqe_private; 1740 u32 value; 1741 1742 value = cqhci_readl(cq_host, CQHCI_CFG); 1743 value |= CQHCI_ENABLE; 1744 cqhci_writel(cq_host, value, CQHCI_CFG); 1745} 1746 1747static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 1748{ 1749 struct sdhci_host *host = mmc_priv(mmc); 1750 1751 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1752 sdhci_cqe_enable(mmc); 1753} 1754 1755static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 1756{ 1757 int cmd_error = 0; 1758 int data_error = 0; 1759 1760 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1761 return intmask; 1762 1763 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1764 1765 return 0; 1766} 1767 1768static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 1769{ 1770 struct sdhci_host *host = mmc_priv(mmc); 1771 struct cqhci_host *cq_host = mmc->cqe_private; 1772 u32 value; 1773 1774 value = cqhci_readl(cq_host, CQHCI_CFG); 1775 value &= ~CQHCI_ENABLE; 1776 cqhci_writel(cq_host, value, CQHCI_CFG); 1777 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1778} 1779 1780static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 1781 .enable = sdhci_gl9763e_cqe_enable, 1782 .disable = sdhci_cqe_disable, 1783 .dumpregs = sdhci_gl9763e_dumpregs, 1784 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 1785 .post_disable = sdhci_gl9763e_cqe_post_disable, 1786}; 1787 1788static int gl9763e_add_host(struct sdhci_pci_slot *slot) 1789{ 1790 struct device *dev = &slot->chip->pdev->dev; 1791 struct sdhci_host *host = slot->host; 1792 struct cqhci_host *cq_host; 1793 bool dma64; 1794 int ret; 1795 1796 ret = sdhci_setup_host(host); 1797 if (ret) 1798 return ret; 1799 1800 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 1801 if (!cq_host) { 1802 ret = -ENOMEM; 1803 goto cleanup; 1804 } 1805 1806 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 1807 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 1808 1809 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1810 if (dma64) 1811 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1812 1813 ret = cqhci_init(cq_host, host->mmc, dma64); 1814 if (ret) 1815 goto cleanup; 1816 1817 ret = __sdhci_add_host(host); 1818 if (ret) 1819 goto cleanup; 1820 1821 /* Disable LPM negotiation to avoid entering L1 state. */ 1822 gl9763e_set_low_power_negotiation(slot, false); 1823 1824 return 0; 1825 1826cleanup: 1827 sdhci_cleanup_host(host); 1828 return ret; 1829} 1830 1831static void gl9763e_hw_setting(struct sdhci_pci_slot *slot) 1832{ 1833 struct pci_dev *pdev = slot->chip->pdev; 1834 u32 value; 1835 1836 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1837 value &= ~GLI_9763E_VHS_REV; 1838 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1839 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1840 1841 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 1842 value |= GLI_9763E_SCR_AXI_REQ; 1843 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 1844 1845 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 1846 value &= ~GLI_9763E_HS400_SLOW; 1847 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 1848 1849 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 1850 value &= ~GLI_9763E_CFG2_L1DLY; 1851 /* set ASPM L1 entry delay to 21us */ 1852 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 1853 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 1854 1855 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 1856 value &= ~GLI_9763E_HS400_RXDLY; 1857 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 1858 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 1859 1860 /* mask the replay timer timeout of AER */ 1861 sdhci_gli_mask_replay_timer_timeout(pdev); 1862 1863 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1864 value &= ~GLI_9763E_VHS_REV; 1865 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1866 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1867} 1868 1869#ifdef CONFIG_PM 1870static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip) 1871{ 1872 struct sdhci_pci_slot *slot = chip->slots[0]; 1873 struct sdhci_host *host = slot->host; 1874 u16 clock; 1875 1876 /* Enable LPM negotiation to allow entering L1 state */ 1877 gl9763e_set_low_power_negotiation(slot, true); 1878 1879 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1880 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN); 1881 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1882 1883 return 0; 1884} 1885 1886static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip) 1887{ 1888 struct sdhci_pci_slot *slot = chip->slots[0]; 1889 struct sdhci_host *host = slot->host; 1890 u16 clock; 1891 1892 if (host->mmc->ios.power_mode != MMC_POWER_ON) 1893 return 0; 1894 1895 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1896 1897 clock |= SDHCI_CLOCK_PLL_EN; 1898 clock &= ~SDHCI_CLOCK_INT_STABLE; 1899 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1900 1901 /* Wait max 150 ms */ 1902 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), 1903 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) { 1904 pr_err("%s: PLL clock never stabilised.\n", 1905 mmc_hostname(host->mmc)); 1906 sdhci_dumpregs(host); 1907 } 1908 1909 clock |= SDHCI_CLOCK_CARD_EN; 1910 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1911 1912 /* Disable LPM negotiation to avoid entering L1 state. */ 1913 gl9763e_set_low_power_negotiation(slot, false); 1914 1915 return 0; 1916} 1917#endif 1918 1919#ifdef CONFIG_PM_SLEEP 1920static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 1921{ 1922 struct sdhci_pci_slot *slot = chip->slots[0]; 1923 1924 pci_free_irq_vectors(slot->chip->pdev); 1925 gli_pcie_enable_msi(slot); 1926 1927 return sdhci_pci_resume_host(chip); 1928} 1929 1930static int gl9763e_resume(struct sdhci_pci_chip *chip) 1931{ 1932 struct sdhci_pci_slot *slot = chip->slots[0]; 1933 int ret; 1934 1935 ret = sdhci_pci_gli_resume(chip); 1936 if (ret) 1937 return ret; 1938 1939 ret = cqhci_resume(slot->host->mmc); 1940 if (ret) 1941 return ret; 1942 1943 /* 1944 * Disable LPM negotiation to bring device back in sync 1945 * with its runtime_pm state. 1946 */ 1947 gl9763e_set_low_power_negotiation(slot, false); 1948 1949 return 0; 1950} 1951 1952static int gl9763e_suspend(struct sdhci_pci_chip *chip) 1953{ 1954 struct sdhci_pci_slot *slot = chip->slots[0]; 1955 int ret; 1956 1957 /* 1958 * Certain SoCs can suspend only with the bus in low- 1959 * power state, notably x86 SoCs when using S0ix. 1960 * Re-enable LPM negotiation to allow entering L1 state 1961 * and entering system suspend. 1962 */ 1963 gl9763e_set_low_power_negotiation(slot, true); 1964 1965 ret = cqhci_suspend(slot->host->mmc); 1966 if (ret) 1967 goto err_suspend; 1968 1969 ret = sdhci_suspend_host(slot->host); 1970 if (ret) 1971 goto err_suspend_host; 1972 1973 return 0; 1974 1975err_suspend_host: 1976 cqhci_resume(slot->host->mmc); 1977err_suspend: 1978 gl9763e_set_low_power_negotiation(slot, false); 1979 return ret; 1980} 1981#endif 1982 1983static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 1984{ 1985 struct pci_dev *pdev = slot->chip->pdev; 1986 struct sdhci_host *host = slot->host; 1987 u32 value; 1988 1989 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 1990 MMC_CAP_1_8V_DDR | 1991 MMC_CAP_NONREMOVABLE; 1992 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 1993 MMC_CAP2_HS400_1_8V | 1994 MMC_CAP2_HS400_ES | 1995 MMC_CAP2_NO_SDIO | 1996 MMC_CAP2_NO_SD; 1997 1998 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 1999 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 2000 if (value & GLI_9763E_MB_ERP_ON) 2001 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2002 2003 gli_pcie_enable_msi(slot); 2004 host->mmc_host_ops.hs400_enhanced_strobe = 2005 gl9763e_hs400_enhanced_strobe; 2006 gl9763e_hw_setting(slot); 2007 sdhci_enable_v4_mode(host); 2008 2009 return 0; 2010} 2011 2012#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 2013 2014static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 2015{ 2016 u32 val = readl(host->ioaddr + (reg & ~3)); 2017 u16 word; 2018 2019 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 2020 return word; 2021} 2022 2023static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 2024{ 2025 u32 val = readl(host->ioaddr + (reg & ~3)); 2026 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 2027 2028 return byte; 2029} 2030 2031static const struct sdhci_ops sdhci_gl9755_ops = { 2032 .read_w = sdhci_gli_readw, 2033 .read_b = sdhci_gli_readb, 2034 .set_clock = sdhci_gl9755_set_clock, 2035 .set_power = gl9755_set_power, 2036 .enable_dma = sdhci_pci_enable_dma, 2037 .set_bus_width = sdhci_set_bus_width, 2038 .reset = sdhci_gl9755_reset, 2039 .set_uhs_signaling = sdhci_set_uhs_signaling, 2040 .voltage_switch = sdhci_gli_voltage_switch, 2041 .dump_uhs2_regs = sdhci_uhs2_dump_regs, 2042 .set_timeout = sdhci_uhs2_set_timeout, 2043 .irq = sdhci_uhs2_irq, 2044 .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, 2045}; 2046 2047const struct sdhci_pci_fixes sdhci_gl9755 = { 2048 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2049 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 2050 .probe_slot = gli_probe_slot_gl9755, 2051 .add_host = sdhci_pci_uhs2_add_host, 2052 .remove_host = sdhci_pci_uhs2_remove_host, 2053 .ops = &sdhci_gl9755_ops, 2054#ifdef CONFIG_PM_SLEEP 2055 .resume = sdhci_pci_gli_resume, 2056#endif 2057}; 2058 2059static const struct sdhci_ops sdhci_gl9750_ops = { 2060 .read_w = sdhci_gli_readw, 2061 .read_b = sdhci_gli_readb, 2062 .read_l = sdhci_gl9750_readl, 2063 .set_clock = sdhci_gl9750_set_clock, 2064 .enable_dma = sdhci_pci_enable_dma, 2065 .set_bus_width = sdhci_set_bus_width, 2066 .reset = sdhci_gl9750_reset, 2067 .set_uhs_signaling = sdhci_set_uhs_signaling, 2068 .voltage_switch = sdhci_gli_voltage_switch, 2069 .platform_execute_tuning = gl9750_execute_tuning, 2070}; 2071 2072const struct sdhci_pci_fixes sdhci_gl9750 = { 2073 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2074 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 2075 .probe_slot = gli_probe_slot_gl9750, 2076 .ops = &sdhci_gl9750_ops, 2077#ifdef CONFIG_PM_SLEEP 2078 .resume = sdhci_pci_gli_resume, 2079#endif 2080}; 2081 2082static const struct sdhci_ops sdhci_gl9763e_ops = { 2083 .set_clock = sdhci_set_clock, 2084 .enable_dma = sdhci_pci_enable_dma, 2085 .set_bus_width = sdhci_set_bus_width, 2086 .reset = sdhci_and_cqhci_reset, 2087 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 2088 .voltage_switch = sdhci_gli_voltage_switch, 2089 .irq = sdhci_gl9763e_cqhci_irq, 2090}; 2091 2092const struct sdhci_pci_fixes sdhci_gl9763e = { 2093 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2094 .probe_slot = gli_probe_slot_gl9763e, 2095 .ops = &sdhci_gl9763e_ops, 2096#ifdef CONFIG_PM_SLEEP 2097 .resume = gl9763e_resume, 2098 .suspend = gl9763e_suspend, 2099#endif 2100#ifdef CONFIG_PM 2101 .runtime_suspend = gl9763e_runtime_suspend, 2102 .runtime_resume = gl9763e_runtime_resume, 2103 .allow_runtime_pm = true, 2104#endif 2105 .add_host = gl9763e_add_host, 2106}; 2107 2108static const struct sdhci_ops sdhci_gl9767_ops = { 2109 .set_clock = sdhci_gl9767_set_clock, 2110 .enable_dma = sdhci_pci_enable_dma, 2111 .set_bus_width = sdhci_set_bus_width, 2112 .reset = sdhci_gl9767_reset, 2113 .set_uhs_signaling = sdhci_set_uhs_signaling, 2114 .voltage_switch = sdhci_gl9767_voltage_switch, 2115 .dump_uhs2_regs = sdhci_uhs2_dump_regs, 2116 .set_timeout = sdhci_uhs2_set_timeout, 2117 .irq = sdhci_uhs2_irq, 2118 .set_power = sdhci_gl9767_set_power, 2119 .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, 2120 .card_event = sdhci_gl9767_card_event, 2121}; 2122 2123const struct sdhci_pci_fixes sdhci_gl9767 = { 2124 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2125 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 2126 .probe_slot = gli_probe_slot_gl9767, 2127 .add_host = sdhci_pci_uhs2_add_host, 2128 .remove_host = sdhci_pci_uhs2_remove_host, 2129 .ops = &sdhci_gl9767_ops, 2130#ifdef CONFIG_PM_SLEEP 2131 .resume = sdhci_pci_gli_resume, 2132#endif 2133};
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