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sdhci-pci-core.c
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linux-6.19.14/drivers/mmc/host/sdhci-pci-core.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11#include <linux/bitfield.h> 12#include <linux/string.h> 13#include <linux/delay.h> 14#include <linux/highmem.h> 15#include <linux/module.h> 16#include <linux/pci.h> 17#include <linux/dma-mapping.h> 18#include <linux/slab.h> 19#include <linux/device.h> 20#include <linux/scatterlist.h> 21#include <linux/io.h> 22#include <linux/iopoll.h> 23#include <linux/gpio.h> 24#include <linux/gpio/machine.h> 25#include <linux/pm_runtime.h> 26#include <linux/pm_qos.h> 27#include <linux/debugfs.h> 28#include <linux/acpi.h> 29#include <linux/dmi.h> 30 31#include <linux/mmc/host.h> 32#include <linux/mmc/mmc.h> 33#include <linux/mmc/slot-gpio.h> 34 35#ifdef CONFIG_X86 36#include <asm/iosf_mbi.h> 37#endif 38 39#include "cqhci.h" 40 41#include "sdhci.h" 42#include "sdhci-cqhci.h" 43#include "sdhci-pci.h" 44#include "sdhci-uhs2.h" 45 46static void sdhci_pci_hw_reset(struct sdhci_host *host); 47 48#ifdef CONFIG_PM_SLEEP 49static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 50{ 51 mmc_pm_flag_t pm_flags = 0; 52 bool cap_cd_wake = false; 53 int i; 54 55 for (i = 0; i < chip->num_slots; i++) { 56 struct sdhci_pci_slot *slot = chip->slots[i]; 57 58 if (slot) { 59 pm_flags |= slot->host->mmc->pm_flags; 60 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 61 cap_cd_wake = true; 62 } 63 } 64 65 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 66 return device_wakeup_enable(&chip->pdev->dev); 67 else if (!cap_cd_wake) 68 device_wakeup_disable(&chip->pdev->dev); 69 70 return 0; 71} 72 73static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 74{ 75 int i, ret; 76 77 sdhci_pci_init_wakeup(chip); 78 79 for (i = 0; i < chip->num_slots; i++) { 80 struct sdhci_pci_slot *slot = chip->slots[i]; 81 struct sdhci_host *host; 82 83 if (!slot) 84 continue; 85 86 host = slot->host; 87 88 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 89 mmc_retune_needed(host->mmc); 90 91 ret = sdhci_suspend_host(host); 92 if (ret) 93 goto err_pci_suspend; 94 95 if (device_may_wakeup(&chip->pdev->dev)) 96 mmc_gpio_set_cd_wake(host->mmc, true); 97 } 98 99 return 0; 100 101err_pci_suspend: 102 while (--i >= 0) 103 sdhci_resume_host(chip->slots[i]->host); 104 return ret; 105} 106 107int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 108{ 109 struct sdhci_pci_slot *slot; 110 int i, ret; 111 112 for (i = 0; i < chip->num_slots; i++) { 113 slot = chip->slots[i]; 114 if (!slot) 115 continue; 116 117 ret = sdhci_resume_host(slot->host); 118 if (ret) 119 return ret; 120 121 mmc_gpio_set_cd_wake(slot->host->mmc, false); 122 } 123 124 return 0; 125} 126 127static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 128{ 129 int ret; 130 131 ret = cqhci_suspend(chip->slots[0]->host->mmc); 132 if (ret) 133 return ret; 134 135 return sdhci_pci_suspend_host(chip); 136} 137 138static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 139{ 140 int ret; 141 142 ret = sdhci_pci_resume_host(chip); 143 if (ret) 144 return ret; 145 146 return cqhci_resume(chip->slots[0]->host->mmc); 147} 148#endif 149 150#ifdef CONFIG_PM 151static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 152{ 153 struct sdhci_pci_slot *slot; 154 struct sdhci_host *host; 155 156 for (int i = 0; i < chip->num_slots; i++) { 157 slot = chip->slots[i]; 158 if (!slot) 159 continue; 160 161 host = slot->host; 162 163 sdhci_runtime_suspend_host(host); 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171} 172 173static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 174{ 175 struct sdhci_pci_slot *slot; 176 177 for (int i = 0; i < chip->num_slots; i++) { 178 slot = chip->slots[i]; 179 if (!slot) 180 continue; 181 182 sdhci_runtime_resume_host(slot->host, 0); 183 } 184 185 return 0; 186} 187 188static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 189{ 190 int ret; 191 192 ret = cqhci_suspend(chip->slots[0]->host->mmc); 193 if (ret) 194 return ret; 195 196 return sdhci_pci_runtime_suspend_host(chip); 197} 198 199static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 200{ 201 int ret; 202 203 ret = sdhci_pci_runtime_resume_host(chip); 204 if (ret) 205 return ret; 206 207 return cqhci_resume(chip->slots[0]->host->mmc); 208} 209#endif 210 211static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 212{ 213 int cmd_error = 0; 214 int data_error = 0; 215 216 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 217 return intmask; 218 219 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 220 221 return 0; 222} 223 224static void sdhci_pci_dumpregs(struct mmc_host *mmc) 225{ 226 sdhci_dumpregs(mmc_priv(mmc)); 227} 228 229/*****************************************************************************\ 230 * * 231 * Hardware specific quirk handling * 232 * * 233\*****************************************************************************/ 234 235static int ricoh_probe(struct sdhci_pci_chip *chip) 236{ 237 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 238 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 239 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 240 return 0; 241} 242 243static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 244{ 245 u32 caps = 246 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 247 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 248 SDHCI_TIMEOUT_CLK_UNIT | 249 SDHCI_CAN_VDD_330 | 250 SDHCI_CAN_DO_HISPD | 251 SDHCI_CAN_DO_SDMA; 252 u32 caps1 = 0; 253 254 __sdhci_read_caps(slot->host, NULL, &caps, &caps1); 255 return 0; 256} 257 258#ifdef CONFIG_PM_SLEEP 259static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 260{ 261 /* Apply a delay to allow controller to settle */ 262 /* Otherwise it becomes confused if card state changed 263 during suspend */ 264 msleep(500); 265 return sdhci_pci_resume_host(chip); 266} 267#endif 268 269static const struct sdhci_pci_fixes sdhci_ricoh = { 270 .probe = ricoh_probe, 271 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 272 SDHCI_QUIRK_FORCE_DMA | 273 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 274}; 275 276static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 277 .probe_slot = ricoh_mmc_probe_slot, 278#ifdef CONFIG_PM_SLEEP 279 .resume = ricoh_mmc_resume, 280#endif 281 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 282 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 283 SDHCI_QUIRK_NO_CARD_NO_RESET, 284}; 285 286static void ene_714_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 287{ 288 struct sdhci_host *host = mmc_priv(mmc); 289 290 sdhci_set_ios(mmc, ios); 291 292 /* 293 * Some (ENE) controllers misbehave on some ios operations, 294 * signalling timeout and CRC errors even on CMD0. Resetting 295 * it on each ios seems to solve the problem. 296 */ 297 if (!(host->flags & SDHCI_DEVICE_DEAD)) 298 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 299} 300 301static int ene_714_probe_slot(struct sdhci_pci_slot *slot) 302{ 303 slot->host->mmc_host_ops.set_ios = ene_714_set_ios; 304 return 0; 305} 306 307static const struct sdhci_pci_fixes sdhci_ene_712 = { 308 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 309 SDHCI_QUIRK_BROKEN_DMA, 310}; 311 312static const struct sdhci_pci_fixes sdhci_ene_714 = { 313 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 314 SDHCI_QUIRK_BROKEN_DMA, 315 .probe_slot = ene_714_probe_slot, 316}; 317 318static const struct sdhci_pci_fixes sdhci_cafe = { 319 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 320 SDHCI_QUIRK_NO_BUSY_IRQ | 321 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 322 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 323}; 324 325static const struct sdhci_pci_fixes sdhci_intel_qrk = { 326 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 327}; 328 329static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 330{ 331 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 332 return 0; 333} 334 335/* 336 * ADMA operation is disabled for Moorestown platform due to 337 * hardware bugs. 338 */ 339static int mrst_hc_probe(struct sdhci_pci_chip *chip) 340{ 341 /* 342 * slots number is fixed here for MRST as SDIO3/5 are never used and 343 * have hardware bugs. 344 */ 345 chip->num_slots = 1; 346 return 0; 347} 348 349static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 350{ 351 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 352 return 0; 353} 354 355static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 356{ 357 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 358 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 359 return 0; 360} 361 362static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 363{ 364 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 365 return 0; 366} 367 368static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 369 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 370 .probe_slot = mrst_hc_probe_slot, 371}; 372 373static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 374 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 375 .probe = mrst_hc_probe, 376}; 377 378static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 379 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 380 .allow_runtime_pm = true, 381 .own_cd_for_runtime_pm = true, 382}; 383 384static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 385 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 386 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 387 .allow_runtime_pm = true, 388 .probe_slot = mfd_sdio_probe_slot, 389}; 390 391static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 392 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 393 .allow_runtime_pm = true, 394 .probe_slot = mfd_emmc_probe_slot, 395}; 396 397static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 398 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 399 .probe_slot = pch_hc_probe_slot, 400}; 401 402#ifdef CONFIG_X86 403 404#define BYT_IOSF_SCCEP 0x63 405#define BYT_IOSF_OCP_NETCTRL0 0x1078 406#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 407 408static void byt_ocp_setting(struct pci_dev *pdev) 409{ 410 u32 val = 0; 411 412 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 413 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 414 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 415 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 416 return; 417 418 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 419 &val)) { 420 dev_err(&pdev->dev, "%s read error\n", __func__); 421 return; 422 } 423 424 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 425 return; 426 427 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 428 429 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 430 val)) { 431 dev_err(&pdev->dev, "%s write error\n", __func__); 432 return; 433 } 434 435 dev_dbg(&pdev->dev, "%s completed\n", __func__); 436} 437 438#else 439 440static inline void byt_ocp_setting(struct pci_dev *pdev) 441{ 442} 443 444#endif 445 446enum { 447 INTEL_DSM_FNS = 0, 448 INTEL_DSM_V18_SWITCH = 3, 449 INTEL_DSM_V33_SWITCH = 4, 450 INTEL_DSM_DRV_STRENGTH = 9, 451 INTEL_DSM_D3_RETUNE = 10, 452}; 453 454struct intel_host { 455 u32 dsm_fns; 456 int drv_strength; 457 bool d3_retune; 458 bool rpm_retune_ok; 459 bool needs_pwr_off; 460 u32 glk_rx_ctrl1; 461 u32 glk_tun_val; 462 u32 active_ltr; 463 u32 idle_ltr; 464}; 465 466static const guid_t intel_dsm_guid = 467 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 468 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 469 470static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 471 unsigned int fn, u32 *result) 472{ 473 union acpi_object *obj; 474 int err = 0; 475 size_t len; 476 477 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL, 478 ACPI_TYPE_BUFFER); 479 if (!obj) 480 return -EOPNOTSUPP; 481 482 if (obj->buffer.length < 1) { 483 err = -EINVAL; 484 goto out; 485 } 486 487 len = min_t(size_t, obj->buffer.length, 4); 488 489 *result = 0; 490 memcpy(result, obj->buffer.pointer, len); 491out: 492 ACPI_FREE(obj); 493 494 return err; 495} 496 497static int intel_dsm(struct intel_host *intel_host, struct device *dev, 498 unsigned int fn, u32 *result) 499{ 500 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 501 return -EOPNOTSUPP; 502 503 return __intel_dsm(intel_host, dev, fn, result); 504} 505 506static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 507 struct mmc_host *mmc) 508{ 509 int err; 510 u32 val; 511 512 intel_host->d3_retune = true; 513 514 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 515 if (err) { 516 pr_debug("%s: DSM not supported, error %d\n", 517 mmc_hostname(mmc), err); 518 return; 519 } 520 521 pr_debug("%s: DSM function mask %#x\n", 522 mmc_hostname(mmc), intel_host->dsm_fns); 523 524 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 525 intel_host->drv_strength = err ? 0 : val; 526 527 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 528 intel_host->d3_retune = err ? true : !!val; 529} 530 531static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 532{ 533 u8 reg; 534 535 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 536 reg |= 0x10; 537 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 538 /* For eMMC, minimum is 1us but give it 9us for good measure */ 539 udelay(9); 540 reg &= ~0x10; 541 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 542 /* For eMMC, minimum is 200us but give it 300us for good measure */ 543 usleep_range(300, 1000); 544} 545 546static int intel_select_drive_strength(struct mmc_card *card, 547 unsigned int max_dtr, int host_drv, 548 int card_drv, int *drv_type) 549{ 550 struct sdhci_host *host = mmc_priv(card->host); 551 struct sdhci_pci_slot *slot = sdhci_priv(host); 552 struct intel_host *intel_host = sdhci_pci_priv(slot); 553 554 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 555 return 0; 556 557 return intel_host->drv_strength; 558} 559 560static int bxt_get_cd(struct mmc_host *mmc) 561{ 562 int gpio_cd = mmc_gpio_get_cd(mmc); 563 564 if (!gpio_cd) 565 return 0; 566 567 return sdhci_get_cd_nogpio(mmc); 568} 569 570static int mrfld_get_cd(struct mmc_host *mmc) 571{ 572 return sdhci_get_cd_nogpio(mmc); 573} 574 575#define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 576#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 577 578static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 579 unsigned short vdd) 580{ 581 struct sdhci_pci_slot *slot = sdhci_priv(host); 582 struct intel_host *intel_host = sdhci_pci_priv(slot); 583 int cntr; 584 u8 reg; 585 586 /* 587 * Bus power may control card power, but a full reset still may not 588 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. 589 * That might be needed to initialize correctly, if the card was left 590 * powered on previously. 591 */ 592 if (intel_host->needs_pwr_off) { 593 intel_host->needs_pwr_off = false; 594 if (mode != MMC_POWER_OFF) { 595 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 596 usleep_range(10000, 12500); 597 } 598 } 599 600 sdhci_set_power(host, mode, vdd); 601 602 if (mode == MMC_POWER_OFF) { 603 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 604 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BYT_SD) 605 usleep_range(15000, 17500); 606 return; 607 } 608 609 /* 610 * Bus power might not enable after D3 -> D0 transition due to the 611 * present state not yet having propagated. Retry for up to 2ms. 612 */ 613 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 614 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 615 if (reg & SDHCI_POWER_ON) 616 break; 617 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 618 reg |= SDHCI_POWER_ON; 619 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 620 } 621} 622 623static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 624 unsigned int timing) 625{ 626 /* Set UHS timing to SDR25 for High Speed mode */ 627 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 628 timing = MMC_TIMING_UHS_SDR25; 629 sdhci_set_uhs_signaling(host, timing); 630} 631 632#define INTEL_HS400_ES_REG 0x78 633#define INTEL_HS400_ES_BIT BIT(0) 634 635static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 636 struct mmc_ios *ios) 637{ 638 struct sdhci_host *host = mmc_priv(mmc); 639 u32 val; 640 641 val = sdhci_readl(host, INTEL_HS400_ES_REG); 642 if (ios->enhanced_strobe) 643 val |= INTEL_HS400_ES_BIT; 644 else 645 val &= ~INTEL_HS400_ES_BIT; 646 sdhci_writel(host, val, INTEL_HS400_ES_REG); 647} 648 649static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 650 struct mmc_ios *ios) 651{ 652 struct device *dev = mmc_dev(mmc); 653 struct sdhci_host *host = mmc_priv(mmc); 654 struct sdhci_pci_slot *slot = sdhci_priv(host); 655 struct intel_host *intel_host = sdhci_pci_priv(slot); 656 unsigned int fn; 657 u32 result = 0; 658 int err; 659 660 err = sdhci_start_signal_voltage_switch(mmc, ios); 661 if (err) 662 return err; 663 664 switch (ios->signal_voltage) { 665 case MMC_SIGNAL_VOLTAGE_330: 666 fn = INTEL_DSM_V33_SWITCH; 667 break; 668 case MMC_SIGNAL_VOLTAGE_180: 669 fn = INTEL_DSM_V18_SWITCH; 670 break; 671 default: 672 return 0; 673 } 674 675 err = intel_dsm(intel_host, dev, fn, &result); 676 pr_debug("%s: %s DSM fn %u error %d result %u\n", 677 mmc_hostname(mmc), __func__, fn, err, result); 678 679 return 0; 680} 681 682static void sdhci_intel_set_clock(struct sdhci_host *host, unsigned int clock) 683{ 684 u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 685 686 /* Stop card clock separately to avoid glitches on clock line */ 687 if (clk & SDHCI_CLOCK_CARD_EN) 688 sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, SDHCI_CLOCK_CONTROL); 689 690 sdhci_set_clock(host, clock); 691} 692 693static const struct sdhci_ops sdhci_intel_byt_ops = { 694 .set_clock = sdhci_intel_set_clock, 695 .set_power = sdhci_intel_set_power, 696 .enable_dma = sdhci_pci_enable_dma, 697 .set_bus_width = sdhci_set_bus_width, 698 .reset = sdhci_reset, 699 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 700 .hw_reset = sdhci_pci_hw_reset, 701}; 702 703static const struct sdhci_ops sdhci_intel_glk_ops = { 704 .set_clock = sdhci_intel_set_clock, 705 .set_power = sdhci_intel_set_power, 706 .enable_dma = sdhci_pci_enable_dma, 707 .set_bus_width = sdhci_set_bus_width, 708 .reset = sdhci_and_cqhci_reset, 709 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 710 .hw_reset = sdhci_pci_hw_reset, 711 .irq = sdhci_cqhci_irq, 712}; 713 714static void byt_read_dsm(struct sdhci_pci_slot *slot) 715{ 716 struct intel_host *intel_host = sdhci_pci_priv(slot); 717 struct device *dev = &slot->chip->pdev->dev; 718 struct mmc_host *mmc = slot->host->mmc; 719 720 intel_dsm_init(intel_host, dev, mmc); 721 slot->chip->rpm_retune = intel_host->d3_retune; 722} 723 724static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 725{ 726 int err = sdhci_execute_tuning(mmc, opcode); 727 struct sdhci_host *host = mmc_priv(mmc); 728 729 if (err) 730 return err; 731 732 /* 733 * Tuning can leave the IP in an active state (Buffer Read Enable bit 734 * set) which prevents the entry to low power states (i.e. S0i3). Data 735 * reset will clear it. 736 */ 737 sdhci_reset(host, SDHCI_RESET_DATA); 738 739 return 0; 740} 741 742#define INTEL_ACTIVELTR 0x804 743#define INTEL_IDLELTR 0x808 744 745#define INTEL_LTR_REQ BIT(15) 746#define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 747#define INTEL_LTR_SCALE_1US (2 << 10) 748#define INTEL_LTR_SCALE_32US (3 << 10) 749#define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 750 751static void intel_cache_ltr(struct sdhci_pci_slot *slot) 752{ 753 struct intel_host *intel_host = sdhci_pci_priv(slot); 754 struct sdhci_host *host = slot->host; 755 756 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 757 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 758} 759 760static void intel_ltr_set(struct device *dev, s32 val) 761{ 762 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 763 struct sdhci_pci_slot *slot = chip->slots[0]; 764 struct intel_host *intel_host = sdhci_pci_priv(slot); 765 struct sdhci_host *host = slot->host; 766 u32 ltr; 767 768 pm_runtime_get_sync(dev); 769 770 /* 771 * Program latency tolerance (LTR) accordingly what has been asked 772 * by the PM QoS layer or disable it in case we were passed 773 * negative value or PM_QOS_LATENCY_ANY. 774 */ 775 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 776 777 if (val == PM_QOS_LATENCY_ANY || val < 0) { 778 ltr &= ~INTEL_LTR_REQ; 779 } else { 780 ltr |= INTEL_LTR_REQ; 781 ltr &= ~INTEL_LTR_SCALE_MASK; 782 ltr &= ~INTEL_LTR_VALUE_MASK; 783 784 if (val > INTEL_LTR_VALUE_MASK) { 785 val >>= 5; 786 if (val > INTEL_LTR_VALUE_MASK) 787 val = INTEL_LTR_VALUE_MASK; 788 ltr |= INTEL_LTR_SCALE_32US | val; 789 } else { 790 ltr |= INTEL_LTR_SCALE_1US | val; 791 } 792 } 793 794 if (ltr == intel_host->active_ltr) 795 goto out; 796 797 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 798 writel(ltr, host->ioaddr + INTEL_IDLELTR); 799 800 /* Cache the values into lpss structure */ 801 intel_cache_ltr(slot); 802out: 803 pm_runtime_put_autosuspend(dev); 804} 805 806static bool intel_use_ltr(struct sdhci_pci_chip *chip) 807{ 808 switch (chip->pdev->device) { 809 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 810 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 811 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 812 case PCI_DEVICE_ID_INTEL_BYT_SD: 813 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 814 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 815 case PCI_DEVICE_ID_INTEL_BSW_SD: 816 return false; 817 default: 818 return true; 819 } 820} 821 822static void intel_ltr_expose(struct sdhci_pci_chip *chip) 823{ 824 struct device *dev = &chip->pdev->dev; 825 826 if (!intel_use_ltr(chip)) 827 return; 828 829 dev->power.set_latency_tolerance = intel_ltr_set; 830 dev_pm_qos_expose_latency_tolerance(dev); 831} 832 833static void intel_ltr_hide(struct sdhci_pci_chip *chip) 834{ 835 struct device *dev = &chip->pdev->dev; 836 837 if (!intel_use_ltr(chip)) 838 return; 839 840 dev_pm_qos_hide_latency_tolerance(dev); 841 dev->power.set_latency_tolerance = NULL; 842} 843 844static void byt_probe_slot(struct sdhci_pci_slot *slot) 845{ 846 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 847 struct device *dev = &slot->chip->pdev->dev; 848 struct mmc_host *mmc = slot->host->mmc; 849 850 byt_read_dsm(slot); 851 852 byt_ocp_setting(slot->chip->pdev); 853 854 ops->execute_tuning = intel_execute_tuning; 855 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 856 857 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 858 859 if (!mmc->slotno) { 860 slot->chip->slots[mmc->slotno] = slot; 861 intel_ltr_expose(slot->chip); 862 } 863} 864 865static void byt_add_debugfs(struct sdhci_pci_slot *slot) 866{ 867 struct intel_host *intel_host = sdhci_pci_priv(slot); 868 struct mmc_host *mmc = slot->host->mmc; 869 struct dentry *dir = mmc->debugfs_root; 870 871 if (!intel_use_ltr(slot->chip)) 872 return; 873 874 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 875 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 876 877 intel_cache_ltr(slot); 878} 879 880static int byt_add_host(struct sdhci_pci_slot *slot) 881{ 882 int ret = sdhci_add_host(slot->host); 883 884 if (!ret) 885 byt_add_debugfs(slot); 886 return ret; 887} 888 889static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 890{ 891 struct mmc_host *mmc = slot->host->mmc; 892 893 if (!mmc->slotno) 894 intel_ltr_hide(slot->chip); 895} 896 897static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 898{ 899 byt_probe_slot(slot); 900 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 901 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 902 MMC_CAP_CMD_DURING_TFR | 903 MMC_CAP_WAIT_WHILE_BUSY; 904 slot->hw_reset = sdhci_pci_int_hw_reset; 905 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 906 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 907 slot->host->mmc_host_ops.select_drive_strength = 908 intel_select_drive_strength; 909 return 0; 910} 911 912static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 913{ 914 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 915 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 916 dmi_match(DMI_SYS_VENDOR, "IRBIS") || 917 dmi_match(DMI_SYS_VENDOR, "Positivo Tecnologia SA")); 918} 919 920static bool jsl_broken_hs400es(struct sdhci_pci_slot *slot) 921{ 922 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_JSL_EMMC && 923 dmi_match(DMI_BIOS_VENDOR, "ASUSTeK COMPUTER INC."); 924} 925 926static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 927{ 928 int ret = byt_emmc_probe_slot(slot); 929 930 if (!glk_broken_cqhci(slot)) 931 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 932 933 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 934 if (!jsl_broken_hs400es(slot)) { 935 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES; 936 slot->host->mmc_host_ops.hs400_enhanced_strobe = 937 intel_hs400_enhanced_strobe; 938 } 939 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 940 } 941 942 return ret; 943} 944 945static const struct cqhci_host_ops glk_cqhci_ops = { 946 .enable = sdhci_cqe_enable, 947 .disable = sdhci_cqe_disable, 948 .dumpregs = sdhci_pci_dumpregs, 949}; 950 951static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 952{ 953 struct device *dev = &slot->chip->pdev->dev; 954 struct sdhci_host *host = slot->host; 955 struct cqhci_host *cq_host; 956 bool dma64; 957 int ret; 958 959 ret = sdhci_setup_host(host); 960 if (ret) 961 return ret; 962 963 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 964 if (!cq_host) { 965 ret = -ENOMEM; 966 goto cleanup; 967 } 968 969 cq_host->mmio = host->ioaddr + 0x200; 970 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 971 cq_host->ops = &glk_cqhci_ops; 972 973 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 974 if (dma64) 975 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 976 977 ret = cqhci_init(cq_host, host->mmc, dma64); 978 if (ret) 979 goto cleanup; 980 981 ret = __sdhci_add_host(host); 982 if (ret) 983 goto cleanup; 984 985 byt_add_debugfs(slot); 986 987 return 0; 988 989cleanup: 990 sdhci_cleanup_host(host); 991 return ret; 992} 993 994#ifdef CONFIG_PM 995#define GLK_RX_CTRL1 0x834 996#define GLK_TUN_VAL 0x840 997#define GLK_PATH_PLL GENMASK(13, 8) 998#define GLK_DLY GENMASK(6, 0) 999/* Workaround firmware failing to restore the tuning value */ 1000static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 1001{ 1002 struct sdhci_pci_slot *slot = chip->slots[0]; 1003 struct intel_host *intel_host = sdhci_pci_priv(slot); 1004 struct sdhci_host *host = slot->host; 1005 u32 glk_rx_ctrl1; 1006 u32 glk_tun_val; 1007 u32 dly; 1008 1009 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1010 return; 1011 1012 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1013 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1014 1015 if (susp) { 1016 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1017 intel_host->glk_tun_val = glk_tun_val; 1018 return; 1019 } 1020 1021 if (!intel_host->glk_tun_val) 1022 return; 1023 1024 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1025 intel_host->rpm_retune_ok = true; 1026 return; 1027 } 1028 1029 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1030 (intel_host->glk_tun_val << 1)); 1031 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1032 return; 1033 1034 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1035 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1036 1037 intel_host->rpm_retune_ok = true; 1038 chip->rpm_retune = true; 1039 mmc_retune_needed(host->mmc); 1040 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1041} 1042 1043static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1044{ 1045 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1046 !chip->rpm_retune) 1047 glk_rpm_retune_wa(chip, susp); 1048} 1049 1050static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1051{ 1052 glk_rpm_retune_chk(chip, true); 1053 1054 return sdhci_cqhci_runtime_suspend(chip); 1055} 1056 1057static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1058{ 1059 glk_rpm_retune_chk(chip, false); 1060 1061 return sdhci_cqhci_runtime_resume(chip); 1062} 1063#endif 1064 1065#ifdef CONFIG_ACPI 1066static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1067{ 1068 acpi_status status; 1069 unsigned long long max_freq; 1070 1071 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1072 "MXFQ", NULL, &max_freq); 1073 if (ACPI_FAILURE(status)) { 1074 dev_err(&slot->chip->pdev->dev, 1075 "MXFQ not found in acpi table\n"); 1076 return -EINVAL; 1077 } 1078 1079 slot->host->mmc->f_max = max_freq * 1000000; 1080 1081 return 0; 1082} 1083#else 1084static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1085{ 1086 return 0; 1087} 1088#endif 1089 1090static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1091{ 1092 int err; 1093 1094 byt_probe_slot(slot); 1095 1096 err = ni_set_max_freq(slot); 1097 if (err) 1098 return err; 1099 1100 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1101 MMC_CAP_WAIT_WHILE_BUSY; 1102 return 0; 1103} 1104 1105static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1106{ 1107 byt_probe_slot(slot); 1108 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1109 MMC_CAP_WAIT_WHILE_BUSY; 1110 return 0; 1111} 1112 1113static void byt_needs_pwr_off(struct sdhci_pci_slot *slot) 1114{ 1115 struct intel_host *intel_host = sdhci_pci_priv(slot); 1116 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL); 1117 1118 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON; 1119} 1120 1121static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1122{ 1123 byt_probe_slot(slot); 1124 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1125 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1126 slot->cd_idx = 0; 1127 slot->cd_override_level = true; 1128 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1129 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1130 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1131 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1132 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1133 1134 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1135 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1136 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1137 1138 byt_needs_pwr_off(slot); 1139 1140 return 0; 1141} 1142 1143#ifdef CONFIG_PM_SLEEP 1144 1145static int byt_resume(struct sdhci_pci_chip *chip) 1146{ 1147 byt_ocp_setting(chip->pdev); 1148 1149 return sdhci_pci_resume_host(chip); 1150} 1151 1152#endif 1153 1154#ifdef CONFIG_PM 1155 1156static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1157{ 1158 byt_ocp_setting(chip->pdev); 1159 1160 return sdhci_pci_runtime_resume_host(chip); 1161} 1162 1163#endif 1164 1165static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1166#ifdef CONFIG_PM_SLEEP 1167 .resume = byt_resume, 1168#endif 1169#ifdef CONFIG_PM 1170 .runtime_resume = byt_runtime_resume, 1171#endif 1172 .allow_runtime_pm = true, 1173 .probe_slot = byt_emmc_probe_slot, 1174 .add_host = byt_add_host, 1175 .remove_slot = byt_remove_slot, 1176 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1177 SDHCI_QUIRK_NO_LED, 1178 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1179 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1180 SDHCI_QUIRK2_STOP_WITH_TC, 1181 .ops = &sdhci_intel_byt_ops, 1182 .priv_size = sizeof(struct intel_host), 1183}; 1184 1185static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1186 .allow_runtime_pm = true, 1187 .probe_slot = glk_emmc_probe_slot, 1188 .add_host = glk_emmc_add_host, 1189 .remove_slot = byt_remove_slot, 1190#ifdef CONFIG_PM_SLEEP 1191 .suspend = sdhci_cqhci_suspend, 1192 .resume = sdhci_cqhci_resume, 1193#endif 1194#ifdef CONFIG_PM 1195 .runtime_suspend = glk_runtime_suspend, 1196 .runtime_resume = glk_runtime_resume, 1197#endif 1198 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1199 SDHCI_QUIRK_NO_LED, 1200 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1201 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1202 SDHCI_QUIRK2_STOP_WITH_TC, 1203 .ops = &sdhci_intel_glk_ops, 1204 .priv_size = sizeof(struct intel_host), 1205}; 1206 1207static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1208#ifdef CONFIG_PM_SLEEP 1209 .resume = byt_resume, 1210#endif 1211#ifdef CONFIG_PM 1212 .runtime_resume = byt_runtime_resume, 1213#endif 1214 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1215 SDHCI_QUIRK_NO_LED, 1216 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1217 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1218 .allow_runtime_pm = true, 1219 .probe_slot = ni_byt_sdio_probe_slot, 1220 .add_host = byt_add_host, 1221 .remove_slot = byt_remove_slot, 1222 .ops = &sdhci_intel_byt_ops, 1223 .priv_size = sizeof(struct intel_host), 1224}; 1225 1226static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1227#ifdef CONFIG_PM_SLEEP 1228 .resume = byt_resume, 1229#endif 1230#ifdef CONFIG_PM 1231 .runtime_resume = byt_runtime_resume, 1232#endif 1233 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1234 SDHCI_QUIRK_NO_LED, 1235 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1236 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1237 .allow_runtime_pm = true, 1238 .probe_slot = byt_sdio_probe_slot, 1239 .add_host = byt_add_host, 1240 .remove_slot = byt_remove_slot, 1241 .ops = &sdhci_intel_byt_ops, 1242 .priv_size = sizeof(struct intel_host), 1243}; 1244 1245/* DMI quirks for devices with missing or broken CD GPIO info */ 1246static const struct gpiod_lookup_table vexia_edu_atla10_cd_gpios = { 1247 .dev_id = "0000:00:12.0", 1248 .table = { 1249 GPIO_LOOKUP("INT33FC:00", 38, "cd", GPIO_ACTIVE_HIGH), 1250 { } 1251 }, 1252}; 1253 1254static const struct dmi_system_id sdhci_intel_byt_cd_gpio_override[] = { 1255 { 1256 /* Vexia Edu Atla 10 tablet 9V version */ 1257 .matches = { 1258 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 1259 DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"), 1260 /* Above strings are too generic, also match on BIOS date */ 1261 DMI_MATCH(DMI_BIOS_DATE, "08/25/2014"), 1262 }, 1263 .driver_data = (void *)&vexia_edu_atla10_cd_gpios, 1264 }, 1265 { } 1266}; 1267 1268static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1269#ifdef CONFIG_PM_SLEEP 1270 .resume = byt_resume, 1271#endif 1272#ifdef CONFIG_PM 1273 .runtime_resume = byt_runtime_resume, 1274#endif 1275 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1276 SDHCI_QUIRK_NO_LED, 1277 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1278 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1279 SDHCI_QUIRK2_STOP_WITH_TC, 1280 .allow_runtime_pm = true, 1281 .own_cd_for_runtime_pm = true, 1282 .probe_slot = byt_sd_probe_slot, 1283 .add_host = byt_add_host, 1284 .remove_slot = byt_remove_slot, 1285 .ops = &sdhci_intel_byt_ops, 1286 .cd_gpio_override = sdhci_intel_byt_cd_gpio_override, 1287 .priv_size = sizeof(struct intel_host), 1288}; 1289 1290/* Define Host controllers for Intel Merrifield platform */ 1291#define INTEL_MRFLD_EMMC_0 0 1292#define INTEL_MRFLD_EMMC_1 1 1293#define INTEL_MRFLD_SD 2 1294#define INTEL_MRFLD_SDIO 3 1295 1296#ifdef CONFIG_ACPI 1297static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1298{ 1299 struct acpi_device *device; 1300 1301 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1302 if (device) 1303 acpi_device_fix_up_power_extended(device); 1304} 1305#else 1306static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1307#endif 1308 1309static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1310{ 1311 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1312 1313 switch (func) { 1314 case INTEL_MRFLD_EMMC_0: 1315 case INTEL_MRFLD_EMMC_1: 1316 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1317 MMC_CAP_8_BIT_DATA | 1318 MMC_CAP_1_8V_DDR; 1319 break; 1320 case INTEL_MRFLD_SD: 1321 slot->cd_idx = 0; 1322 slot->cd_override_level = true; 1323 /* 1324 * There are two PCB designs of SD card slot with the opposite 1325 * card detection sense. Quirk this out by ignoring GPIO state 1326 * completely in the custom ->get_cd() callback. 1327 */ 1328 slot->host->mmc_host_ops.get_cd = mrfld_get_cd; 1329 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1330 break; 1331 case INTEL_MRFLD_SDIO: 1332 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1333 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1334 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1335 MMC_CAP_POWER_OFF_CARD; 1336 break; 1337 default: 1338 return -ENODEV; 1339 } 1340 1341 intel_mrfld_mmc_fix_up_power_slot(slot); 1342 return 0; 1343} 1344 1345static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1346 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1347 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1348 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1349 .allow_runtime_pm = true, 1350 .probe_slot = intel_mrfld_mmc_probe_slot, 1351}; 1352 1353#define JMB388_SAMPLE_COUNT 5 1354 1355static int jmicron_jmb388_get_ro(struct mmc_host *mmc) 1356{ 1357 int i, ro_count; 1358 1359 ro_count = 0; 1360 for (i = 0; i < JMB388_SAMPLE_COUNT; i++) { 1361 if (sdhci_get_ro(mmc) > 0) { 1362 if (++ro_count > JMB388_SAMPLE_COUNT / 2) 1363 return 1; 1364 } 1365 msleep(30); 1366 } 1367 return 0; 1368} 1369 1370static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1371{ 1372 u8 scratch; 1373 int ret; 1374 1375 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1376 if (ret) 1377 goto fail; 1378 1379 /* 1380 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1381 * [bit 1:2] and enable over current debouncing [bit 6]. 1382 */ 1383 if (on) 1384 scratch |= 0x47; 1385 else 1386 scratch &= ~0x47; 1387 1388 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); 1389 1390fail: 1391 return pcibios_err_to_errno(ret); 1392} 1393 1394static int jmicron_probe(struct sdhci_pci_chip *chip) 1395{ 1396 int ret; 1397 u16 mmcdev = 0; 1398 1399 if (chip->pdev->revision == 0) { 1400 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1401 SDHCI_QUIRK_32BIT_DMA_SIZE | 1402 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1403 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1404 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1405 } 1406 1407 /* 1408 * JMicron chips can have two interfaces to the same hardware 1409 * in order to work around limitations in Microsoft's driver. 1410 * We need to make sure we only bind to one of them. 1411 * 1412 * This code assumes two things: 1413 * 1414 * 1. The PCI code adds subfunctions in order. 1415 * 1416 * 2. The MMC interface has a lower subfunction number 1417 * than the SD interface. 1418 */ 1419 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1420 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1421 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1422 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1423 1424 if (mmcdev) { 1425 struct pci_dev *sd_dev; 1426 1427 sd_dev = NULL; 1428 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1429 mmcdev, sd_dev)) != NULL) { 1430 if ((PCI_SLOT(chip->pdev->devfn) == 1431 PCI_SLOT(sd_dev->devfn)) && 1432 (chip->pdev->bus == sd_dev->bus)) 1433 break; 1434 } 1435 1436 if (sd_dev) { 1437 pci_dev_put(sd_dev); 1438 dev_info(&chip->pdev->dev, "Refusing to bind to " 1439 "secondary interface.\n"); 1440 return -ENODEV; 1441 } 1442 } 1443 1444 /* 1445 * JMicron chips need a bit of a nudge to enable the power 1446 * output pins. 1447 */ 1448 ret = jmicron_pmos(chip, 1); 1449 if (ret) { 1450 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1451 return ret; 1452 } 1453 1454 return 0; 1455} 1456 1457static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1458{ 1459 u8 scratch; 1460 1461 scratch = readb(host->ioaddr + 0xC0); 1462 1463 if (on) 1464 scratch |= 0x01; 1465 else 1466 scratch &= ~0x01; 1467 1468 writeb(scratch, host->ioaddr + 0xC0); 1469} 1470 1471static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1472{ 1473 if (slot->chip->pdev->revision == 0) { 1474 u16 version; 1475 1476 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1477 version = (version & SDHCI_VENDOR_VER_MASK) >> 1478 SDHCI_VENDOR_VER_SHIFT; 1479 1480 /* 1481 * Older versions of the chip have lots of nasty glitches 1482 * in the ADMA engine. It's best just to avoid it 1483 * completely. 1484 */ 1485 if (version < 0xAC) 1486 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1487 } 1488 1489 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1490 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1491 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1492 MMC_VDD_29_30 | MMC_VDD_30_31 | 1493 MMC_VDD_165_195; /* allow 1.8V */ 1494 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1495 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1496 } 1497 1498 /* 1499 * The secondary interface requires a bit set to get the 1500 * interrupts. 1501 */ 1502 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1503 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1504 jmicron_enable_mmc(slot->host, 1); 1505 1506 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1507 1508 /* Handle unstable RO-detection on JM388 chips */ 1509 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1510 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1511 slot->host->mmc_host_ops.get_ro = jmicron_jmb388_get_ro; 1512 1513 return 0; 1514} 1515 1516static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1517{ 1518 if (dead) 1519 return; 1520 1521 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1522 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1523 jmicron_enable_mmc(slot->host, 0); 1524} 1525 1526#ifdef CONFIG_PM_SLEEP 1527static int jmicron_suspend(struct sdhci_pci_chip *chip) 1528{ 1529 int i, ret; 1530 1531 ret = sdhci_pci_suspend_host(chip); 1532 if (ret) 1533 return ret; 1534 1535 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1536 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1537 for (i = 0; i < chip->num_slots; i++) 1538 jmicron_enable_mmc(chip->slots[i]->host, 0); 1539 } 1540 1541 return 0; 1542} 1543 1544static int jmicron_resume(struct sdhci_pci_chip *chip) 1545{ 1546 int ret, i; 1547 1548 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1549 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1550 for (i = 0; i < chip->num_slots; i++) 1551 jmicron_enable_mmc(chip->slots[i]->host, 1); 1552 } 1553 1554 ret = jmicron_pmos(chip, 1); 1555 if (ret) { 1556 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1557 return ret; 1558 } 1559 1560 return sdhci_pci_resume_host(chip); 1561} 1562#endif 1563 1564static const struct sdhci_pci_fixes sdhci_jmicron = { 1565 .probe = jmicron_probe, 1566 1567 .probe_slot = jmicron_probe_slot, 1568 .remove_slot = jmicron_remove_slot, 1569 1570#ifdef CONFIG_PM_SLEEP 1571 .suspend = jmicron_suspend, 1572 .resume = jmicron_resume, 1573#endif 1574}; 1575 1576/* SysKonnect CardBus2SDIO extra registers */ 1577#define SYSKT_CTRL 0x200 1578#define SYSKT_RDFIFO_STAT 0x204 1579#define SYSKT_WRFIFO_STAT 0x208 1580#define SYSKT_POWER_DATA 0x20c 1581#define SYSKT_POWER_330 0xef 1582#define SYSKT_POWER_300 0xf8 1583#define SYSKT_POWER_184 0xcc 1584#define SYSKT_POWER_CMD 0x20d 1585#define SYSKT_POWER_START (1 << 7) 1586#define SYSKT_POWER_STATUS 0x20e 1587#define SYSKT_POWER_STATUS_OK (1 << 0) 1588#define SYSKT_BOARD_REV 0x210 1589#define SYSKT_CHIP_REV 0x211 1590#define SYSKT_CONF_DATA 0x212 1591#define SYSKT_CONF_DATA_1V8 (1 << 2) 1592#define SYSKT_CONF_DATA_2V5 (1 << 1) 1593#define SYSKT_CONF_DATA_3V3 (1 << 0) 1594 1595static int syskt_probe(struct sdhci_pci_chip *chip) 1596{ 1597 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1598 chip->pdev->class &= ~0x0000FF; 1599 chip->pdev->class |= PCI_SDHCI_IFDMA; 1600 } 1601 return 0; 1602} 1603 1604static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1605{ 1606 int tm, ps; 1607 1608 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1609 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1610 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1611 "board rev %d.%d, chip rev %d.%d\n", 1612 board_rev >> 4, board_rev & 0xf, 1613 chip_rev >> 4, chip_rev & 0xf); 1614 if (chip_rev >= 0x20) 1615 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1616 1617 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1618 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1619 udelay(50); 1620 tm = 10; /* Wait max 1 ms */ 1621 do { 1622 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1623 if (ps & SYSKT_POWER_STATUS_OK) 1624 break; 1625 udelay(100); 1626 } while (--tm); 1627 if (!tm) { 1628 dev_err(&slot->chip->pdev->dev, 1629 "power regulator never stabilized"); 1630 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1631 return -ENODEV; 1632 } 1633 1634 return 0; 1635} 1636 1637static const struct sdhci_pci_fixes sdhci_syskt = { 1638 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1639 .probe = syskt_probe, 1640 .probe_slot = syskt_probe_slot, 1641}; 1642 1643static int via_probe(struct sdhci_pci_chip *chip) 1644{ 1645 if (chip->pdev->revision == 0x10) 1646 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1647 1648 return 0; 1649} 1650 1651static const struct sdhci_pci_fixes sdhci_via = { 1652 .probe = via_probe, 1653}; 1654 1655static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1656{ 1657 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1658 return 0; 1659} 1660 1661static const struct sdhci_pci_fixes sdhci_rtsx = { 1662 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1663 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1664 SDHCI_QUIRK2_BROKEN_DDR50, 1665 .probe_slot = rtsx_probe_slot, 1666}; 1667 1668/*AMD chipset generation*/ 1669enum amd_chipset_gen { 1670 AMD_CHIPSET_BEFORE_ML, 1671 AMD_CHIPSET_CZ, 1672 AMD_CHIPSET_NL, 1673 AMD_CHIPSET_UNKNOWN, 1674}; 1675 1676/* AMD registers */ 1677#define AMD_SD_AUTO_PATTERN 0xB8 1678#define AMD_MSLEEP_DURATION 4 1679#define AMD_SD_MISC_CONTROL 0xD0 1680#define AMD_MAX_TUNE_VALUE 0x0B 1681#define AMD_AUTO_TUNE_SEL 0x10800 1682#define AMD_FIFO_PTR 0x30 1683#define AMD_BIT_MASK 0x1F 1684 1685static void amd_tuning_reset(struct sdhci_host *host) 1686{ 1687 unsigned int val; 1688 1689 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1690 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1691 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1692 1693 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1694 val &= ~SDHCI_CTRL_EXEC_TUNING; 1695 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1696} 1697 1698static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1699{ 1700 unsigned int val; 1701 1702 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1703 val &= ~AMD_BIT_MASK; 1704 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1705 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1706} 1707 1708static void amd_enable_manual_tuning(struct pci_dev *pdev) 1709{ 1710 unsigned int val; 1711 1712 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1713 val |= AMD_FIFO_PTR; 1714 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1715} 1716 1717static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1718{ 1719 struct sdhci_pci_slot *slot = sdhci_priv(host); 1720 struct pci_dev *pdev = slot->chip->pdev; 1721 u8 valid_win = 0; 1722 u8 valid_win_max = 0; 1723 u8 valid_win_end = 0; 1724 u8 ctrl, tune_around; 1725 1726 amd_tuning_reset(host); 1727 1728 for (tune_around = 0; tune_around < 12; tune_around++) { 1729 amd_config_tuning_phase(pdev, tune_around); 1730 1731 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1732 valid_win = 0; 1733 msleep(AMD_MSLEEP_DURATION); 1734 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1735 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1736 } else if (++valid_win > valid_win_max) { 1737 valid_win_max = valid_win; 1738 valid_win_end = tune_around; 1739 } 1740 } 1741 1742 if (!valid_win_max) { 1743 dev_err(&pdev->dev, "no tuning point found\n"); 1744 return -EIO; 1745 } 1746 1747 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1748 1749 amd_enable_manual_tuning(pdev); 1750 1751 host->mmc->retune_period = 0; 1752 1753 return 0; 1754} 1755 1756static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1757{ 1758 struct sdhci_host *host = mmc_priv(mmc); 1759 1760 /* AMD requires custom HS200 tuning */ 1761 if (host->timing == MMC_TIMING_MMC_HS200) 1762 return amd_execute_tuning_hs200(host, opcode); 1763 1764 /* Otherwise perform standard SDHCI tuning */ 1765 return sdhci_execute_tuning(mmc, opcode); 1766} 1767 1768static int amd_probe_slot(struct sdhci_pci_slot *slot) 1769{ 1770 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1771 1772 ops->execute_tuning = amd_execute_tuning; 1773 1774 return 0; 1775} 1776 1777static int amd_probe(struct sdhci_pci_chip *chip) 1778{ 1779 struct pci_dev *smbus_dev; 1780 enum amd_chipset_gen gen; 1781 1782 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1783 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1784 if (smbus_dev) { 1785 gen = AMD_CHIPSET_BEFORE_ML; 1786 } else { 1787 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1788 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1789 if (smbus_dev) { 1790 if (smbus_dev->revision < 0x51) 1791 gen = AMD_CHIPSET_CZ; 1792 else 1793 gen = AMD_CHIPSET_NL; 1794 } else { 1795 gen = AMD_CHIPSET_UNKNOWN; 1796 } 1797 } 1798 1799 pci_dev_put(smbus_dev); 1800 1801 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1802 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1803 1804 return 0; 1805} 1806 1807static u32 sdhci_read_present_state(struct sdhci_host *host) 1808{ 1809 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1810} 1811 1812static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1813{ 1814 struct sdhci_pci_slot *slot = sdhci_priv(host); 1815 struct pci_dev *pdev = slot->chip->pdev; 1816 u32 present_state; 1817 1818 /* 1819 * SDHC 0x7906 requires a hard reset to clear all internal state. 1820 * Otherwise it can get into a bad state where the DATA lines are always 1821 * read as zeros. 1822 */ 1823 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1824 pci_clear_master(pdev); 1825 1826 pci_save_state(pdev); 1827 1828 pci_set_power_state(pdev, PCI_D3cold); 1829 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1830 pdev->current_state); 1831 pci_set_power_state(pdev, PCI_D0); 1832 1833 pci_restore_state(pdev); 1834 1835 /* 1836 * SDHCI_RESET_ALL says the card detect logic should not be 1837 * reset, but since we need to reset the entire controller 1838 * we should wait until the card detect logic has stabilized. 1839 * 1840 * This normally takes about 40ms. 1841 */ 1842 readx_poll_timeout( 1843 sdhci_read_present_state, 1844 host, 1845 present_state, 1846 present_state & SDHCI_CD_STABLE, 1847 10000, 1848 100000 1849 ); 1850 } 1851 1852 return sdhci_reset(host, mask); 1853} 1854 1855static const struct sdhci_ops amd_sdhci_pci_ops = { 1856 .set_clock = sdhci_set_clock, 1857 .enable_dma = sdhci_pci_enable_dma, 1858 .set_bus_width = sdhci_set_bus_width, 1859 .reset = amd_sdhci_reset, 1860 .set_uhs_signaling = sdhci_set_uhs_signaling, 1861}; 1862 1863static const struct sdhci_pci_fixes sdhci_amd = { 1864 .probe = amd_probe, 1865 .ops = &amd_sdhci_pci_ops, 1866 .probe_slot = amd_probe_slot, 1867}; 1868 1869static const struct pci_device_id pci_ids[] = { 1870 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1871 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1872 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1873 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1874 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1875 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1876 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1877 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1878 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1879 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1880 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1881 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1882 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1883 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1884 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1885 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1886 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1887 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1888 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1889 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1890 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1891 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1892 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1893 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1894 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1895 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1896 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1897 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1898 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1899 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1900 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1901 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1902 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1903 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1904 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1905 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1906 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1907 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1908 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1909 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1910 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1911 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1912 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1913 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1914 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1915 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1916 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1917 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1918 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1919 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1920 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1921 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1922 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1923 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1924 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1925 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1926 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1927 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1928 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1929 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1930 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1931 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1932 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1933 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1934 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1935 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1936 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1937 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1938 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1939 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1940 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc), 1941 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd), 1942 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc), 1943 SDHCI_PCI_DEVICE(O2, 8120, o2), 1944 SDHCI_PCI_DEVICE(O2, 8220, o2), 1945 SDHCI_PCI_DEVICE(O2, 8221, o2), 1946 SDHCI_PCI_DEVICE(O2, 8320, o2), 1947 SDHCI_PCI_DEVICE(O2, 8321, o2), 1948 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1949 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1950 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1951 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1952 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1953 SDHCI_PCI_DEVICE(O2, GG8_9860, o2), 1954 SDHCI_PCI_DEVICE(O2, GG8_9861, o2), 1955 SDHCI_PCI_DEVICE(O2, GG8_9862, o2), 1956 SDHCI_PCI_DEVICE(O2, GG8_9863, o2), 1957 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1958 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1959 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1960 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1961 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1962 SDHCI_PCI_DEVICE(GLI, 9767, gl9767), 1963 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1964 /* Generic SD host controller */ 1965 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1966 { /* end: all zeroes */ }, 1967}; 1968 1969MODULE_DEVICE_TABLE(pci, pci_ids); 1970 1971/*****************************************************************************\ 1972 * * 1973 * SDHCI core callbacks * 1974 * * 1975\*****************************************************************************/ 1976 1977int sdhci_pci_enable_dma(struct sdhci_host *host) 1978{ 1979 struct sdhci_pci_slot *slot; 1980 struct pci_dev *pdev; 1981 1982 slot = sdhci_priv(host); 1983 pdev = slot->chip->pdev; 1984 1985 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1986 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1987 (host->flags & SDHCI_USE_SDMA)) { 1988 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1989 "doesn't fully claim to support it.\n"); 1990 } 1991 1992 pci_set_master(pdev); 1993 1994 return 0; 1995} 1996 1997static void sdhci_pci_hw_reset(struct sdhci_host *host) 1998{ 1999 struct sdhci_pci_slot *slot = sdhci_priv(host); 2000 2001 if (slot->hw_reset) 2002 slot->hw_reset(host); 2003} 2004 2005static const struct sdhci_ops sdhci_pci_ops = { 2006 .set_clock = sdhci_set_clock, 2007 .enable_dma = sdhci_pci_enable_dma, 2008 .set_bus_width = sdhci_set_bus_width, 2009 .reset = sdhci_reset, 2010 .set_uhs_signaling = sdhci_set_uhs_signaling, 2011 .hw_reset = sdhci_pci_hw_reset, 2012}; 2013 2014/*****************************************************************************\ 2015 * * 2016 * Suspend/resume * 2017 * * 2018\*****************************************************************************/ 2019 2020#ifdef CONFIG_PM_SLEEP 2021static int sdhci_pci_suspend(struct device *dev) 2022{ 2023 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2024 2025 if (!chip) 2026 return 0; 2027 2028 if (chip->fixes && chip->fixes->suspend) 2029 return chip->fixes->suspend(chip); 2030 2031 return sdhci_pci_suspend_host(chip); 2032} 2033 2034static int sdhci_pci_resume(struct device *dev) 2035{ 2036 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2037 2038 if (!chip) 2039 return 0; 2040 2041 if (chip->fixes && chip->fixes->resume) 2042 return chip->fixes->resume(chip); 2043 2044 return sdhci_pci_resume_host(chip); 2045} 2046#endif 2047 2048#ifdef CONFIG_PM 2049static int sdhci_pci_runtime_suspend(struct device *dev) 2050{ 2051 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2052 2053 if (!chip) 2054 return 0; 2055 2056 if (chip->fixes && chip->fixes->runtime_suspend) 2057 return chip->fixes->runtime_suspend(chip); 2058 2059 return sdhci_pci_runtime_suspend_host(chip); 2060} 2061 2062static int sdhci_pci_runtime_resume(struct device *dev) 2063{ 2064 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2065 2066 if (!chip) 2067 return 0; 2068 2069 if (chip->fixes && chip->fixes->runtime_resume) 2070 return chip->fixes->runtime_resume(chip); 2071 2072 return sdhci_pci_runtime_resume_host(chip); 2073} 2074#endif 2075 2076static const struct dev_pm_ops sdhci_pci_pm_ops = { 2077 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2078 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2079 sdhci_pci_runtime_resume, NULL) 2080}; 2081 2082/*****************************************************************************\ 2083 * * 2084 * Device probing/removal * 2085 * * 2086\*****************************************************************************/ 2087 2088static struct gpiod_lookup_table *sdhci_pci_add_gpio_lookup_table( 2089 struct sdhci_pci_chip *chip) 2090{ 2091 struct gpiod_lookup_table *cd_gpio_lookup_table; 2092 const struct dmi_system_id *dmi_id = NULL; 2093 size_t count; 2094 2095 if (chip->fixes && chip->fixes->cd_gpio_override) 2096 dmi_id = dmi_first_match(chip->fixes->cd_gpio_override); 2097 2098 if (!dmi_id) 2099 return NULL; 2100 2101 cd_gpio_lookup_table = dmi_id->driver_data; 2102 for (count = 0; cd_gpio_lookup_table->table[count].key; count++) 2103 ; 2104 2105 cd_gpio_lookup_table = kmemdup(dmi_id->driver_data, 2106 /* count + 1 terminating entry */ 2107 struct_size(cd_gpio_lookup_table, table, count + 1), 2108 GFP_KERNEL); 2109 if (!cd_gpio_lookup_table) 2110 return ERR_PTR(-ENOMEM); 2111 2112 gpiod_add_lookup_table(cd_gpio_lookup_table); 2113 return cd_gpio_lookup_table; 2114} 2115 2116static void sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table *lookup_table) 2117{ 2118 if (lookup_table) { 2119 gpiod_remove_lookup_table(lookup_table); 2120 kfree(lookup_table); 2121 } 2122} 2123 2124static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2125 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2126 int slotno) 2127{ 2128 struct sdhci_pci_slot *slot; 2129 struct sdhci_host *host; 2130 int ret, bar = first_bar + slotno; 2131 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2132 2133 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2134 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2135 return ERR_PTR(-ENODEV); 2136 } 2137 2138 if (pci_resource_len(pdev, bar) < 0x100) { 2139 dev_err(&pdev->dev, "Invalid iomem size. You may " 2140 "experience problems.\n"); 2141 } 2142 2143 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2144 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2145 return ERR_PTR(-ENODEV); 2146 } 2147 2148 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2149 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2150 return ERR_PTR(-ENODEV); 2151 } 2152 2153 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2154 if (IS_ERR(host)) { 2155 dev_err(&pdev->dev, "cannot allocate host\n"); 2156 return ERR_CAST(host); 2157 } 2158 2159 slot = sdhci_priv(host); 2160 2161 slot->chip = chip; 2162 slot->host = host; 2163 slot->cd_idx = -1; 2164 2165 host->hw_name = "PCI"; 2166 host->ops = chip->fixes && chip->fixes->ops ? 2167 chip->fixes->ops : 2168 &sdhci_pci_ops; 2169 host->quirks = chip->quirks; 2170 host->quirks2 = chip->quirks2; 2171 2172 host->irq = pdev->irq; 2173 2174 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2175 if (ret) { 2176 dev_err(&pdev->dev, "cannot request region\n"); 2177 return ERR_PTR(ret); 2178 } 2179 2180 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2181 2182 if (chip->fixes && chip->fixes->probe_slot) { 2183 ret = chip->fixes->probe_slot(slot); 2184 if (ret) 2185 return ERR_PTR(ret); 2186 } 2187 2188 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2189 host->mmc->slotno = slotno; 2190 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2191 2192 if (device_can_wakeup(&pdev->dev)) 2193 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2194 2195 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2196 device_init_wakeup(&pdev->dev, true); 2197 2198 if (slot->cd_idx >= 0) { 2199 struct gpiod_lookup_table *cd_gpio_lookup_table; 2200 2201 cd_gpio_lookup_table = sdhci_pci_add_gpio_lookup_table(chip); 2202 if (IS_ERR(cd_gpio_lookup_table)) { 2203 ret = PTR_ERR(cd_gpio_lookup_table); 2204 goto remove; 2205 } 2206 2207 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2208 slot->cd_override_level, 0); 2209 2210 sdhci_pci_remove_gpio_lookup_table(cd_gpio_lookup_table); 2211 2212 if (ret && ret != -EPROBE_DEFER) 2213 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2214 slot->cd_idx, 2215 slot->cd_override_level, 2216 0); 2217 if (ret == -EPROBE_DEFER) 2218 goto remove; 2219 2220 if (ret) { 2221 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2222 slot->cd_idx = -1; 2223 } 2224 } 2225 2226 if (chip->fixes && chip->fixes->add_host) 2227 ret = chip->fixes->add_host(slot); 2228 else 2229 ret = sdhci_add_host(host); 2230 if (ret) 2231 goto remove; 2232 2233 /* 2234 * Check if the chip needs a separate GPIO for card detect to wake up 2235 * from runtime suspend. If it is not there, don't allow runtime PM. 2236 */ 2237 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && slot->cd_idx < 0) 2238 chip->allow_runtime_pm = false; 2239 2240 return slot; 2241 2242remove: 2243 if (chip->fixes && chip->fixes->remove_slot) 2244 chip->fixes->remove_slot(slot, 0); 2245 2246 return ERR_PTR(ret); 2247} 2248 2249static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2250{ 2251 int dead; 2252 u32 scratch; 2253 2254 dead = 0; 2255 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2256 if (scratch == (u32)-1) 2257 dead = 1; 2258 2259 if (slot->chip->fixes && slot->chip->fixes->remove_host) 2260 slot->chip->fixes->remove_host(slot, dead); 2261 else 2262 sdhci_remove_host(slot->host, dead); 2263 2264 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2265 slot->chip->fixes->remove_slot(slot, dead); 2266} 2267 2268int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot) 2269{ 2270 return sdhci_uhs2_add_host(slot->host); 2271} 2272 2273void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead) 2274{ 2275 sdhci_uhs2_remove_host(slot->host, dead); 2276} 2277 2278static void sdhci_pci_runtime_pm_allow(struct device *dev) 2279{ 2280 pm_suspend_ignore_children(dev, 1); 2281 pm_runtime_set_autosuspend_delay(dev, 50); 2282 pm_runtime_use_autosuspend(dev); 2283 pm_runtime_allow(dev); 2284 /* Stay active until mmc core scans for a card */ 2285 pm_runtime_put_noidle(dev); 2286} 2287 2288static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2289{ 2290 pm_runtime_forbid(dev); 2291 pm_runtime_get_noresume(dev); 2292} 2293 2294static int sdhci_pci_probe(struct pci_dev *pdev, 2295 const struct pci_device_id *ent) 2296{ 2297 struct sdhci_pci_chip *chip; 2298 struct sdhci_pci_slot *slot; 2299 2300 u8 slots, first_bar; 2301 int ret, i; 2302 2303 BUG_ON(pdev == NULL); 2304 BUG_ON(ent == NULL); 2305 2306 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2307 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2308 2309 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2310 if (ret) 2311 return pcibios_err_to_errno(ret); 2312 2313 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2314 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2315 2316 BUG_ON(slots > MAX_SLOTS); 2317 2318 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2319 if (ret) 2320 return pcibios_err_to_errno(ret); 2321 2322 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2323 2324 if (first_bar > 5) { 2325 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2326 return -ENODEV; 2327 } 2328 2329 ret = pcim_enable_device(pdev); 2330 if (ret) 2331 return ret; 2332 2333 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2334 if (!chip) 2335 return -ENOMEM; 2336 2337 chip->pdev = pdev; 2338 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2339 if (chip->fixes) { 2340 chip->quirks = chip->fixes->quirks; 2341 chip->quirks2 = chip->fixes->quirks2; 2342 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2343 } 2344 chip->num_slots = slots; 2345 chip->pm_retune = true; 2346 chip->rpm_retune = true; 2347 2348 pci_set_drvdata(pdev, chip); 2349 2350 if (chip->fixes && chip->fixes->probe) { 2351 ret = chip->fixes->probe(chip); 2352 if (ret) 2353 return ret; 2354 } 2355 2356 slots = chip->num_slots; /* Quirk may have changed this */ 2357 2358 for (i = 0; i < slots; i++) { 2359 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2360 if (IS_ERR(slot)) { 2361 for (i--; i >= 0; i--) 2362 sdhci_pci_remove_slot(chip->slots[i]); 2363 return PTR_ERR(slot); 2364 } 2365 2366 chip->slots[i] = slot; 2367 } 2368 2369 if (chip->allow_runtime_pm) 2370 sdhci_pci_runtime_pm_allow(&pdev->dev); 2371 2372 return 0; 2373} 2374 2375static void sdhci_pci_remove(struct pci_dev *pdev) 2376{ 2377 int i; 2378 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2379 2380 if (chip->allow_runtime_pm) 2381 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2382 2383 for (i = 0; i < chip->num_slots; i++) 2384 sdhci_pci_remove_slot(chip->slots[i]); 2385} 2386 2387static struct pci_driver sdhci_driver = { 2388 .name = "sdhci-pci", 2389 .id_table = pci_ids, 2390 .probe = sdhci_pci_probe, 2391 .remove = sdhci_pci_remove, 2392 .driver = { 2393 .pm = &sdhci_pci_pm_ops, 2394 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2395 }, 2396}; 2397 2398module_pci_driver(sdhci_driver); 2399 2400MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2401MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2402MODULE_LICENSE("GPL");
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