sdhci-of-arasan.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Arasan Secure Digital Host Controller Interface.
   4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
   5 * Copyright (c) 2012 Wind River Systems, Inc.
   6 * Copyright (C) 2013 Pengutronix e.K.
   7 * Copyright (C) 2013 Xilinx Inc.
   8 *
   9 * Based on sdhci-of-esdhc.c
  10 *
  11 * Copyright (c) 2007 Freescale Semiconductor, Inc.
  12 * Copyright (c) 2009 MontaVista Software, Inc.
  13 *
  14 * Authors: Xiaobo Xie <X.Xie@freescale.com>
  15 *	    Anton Vorontsov <avorontsov@ru.mvista.com>
  16 */
  17
  18#include <linux/clk-provider.h>
  19#include <linux/mfd/syscon.h>
  20#include <linux/module.h>
  21#include <linux/of.h>
  22#include <linux/platform_device.h>
  23#include <linux/phy/phy.h>
  24#include <linux/regmap.h>
  25#include <linux/reset.h>
  26#include <linux/firmware/xlnx-zynqmp.h>
  27
  28#include "cqhci.h"
  29#include "sdhci-cqhci.h"
  30#include "sdhci-pltfm.h"
  31
  32#define SDHCI_ARASAN_VENDOR_REGISTER	0x78
  33
  34#define SDHCI_ARASAN_ITAPDLY_REGISTER	0xF0F8
  35#define SDHCI_ARASAN_ITAPDLY_SEL_MASK	0xFF
  36
  37#define SDHCI_ARASAN_OTAPDLY_REGISTER	0xF0FC
  38#define SDHCI_ARASAN_OTAPDLY_SEL_MASK	0x3F
  39
  40#define SDHCI_ARASAN_CQE_BASE_ADDR	0x200
  41#define VENDOR_ENHANCED_STROBE		BIT(0)
  42
  43#define PHY_CLK_TOO_SLOW_HZ		400000
  44#define MIN_PHY_CLK_HZ			50000000
  45
  46#define SDHCI_ITAPDLY_CHGWIN		0x200
  47#define SDHCI_ITAPDLY_ENABLE		0x100
  48#define SDHCI_OTAPDLY_ENABLE		0x40
  49
  50#define PHY_CTRL_REG1			0x270
  51#define PHY_CTRL_ITAPDLY_ENA_MASK	BIT(0)
  52#define PHY_CTRL_ITAPDLY_SEL_MASK	GENMASK(5, 1)
  53#define PHY_CTRL_ITAPDLY_SEL_SHIFT	1
  54#define PHY_CTRL_ITAP_CHG_WIN_MASK	BIT(6)
  55#define PHY_CTRL_OTAPDLY_ENA_MASK	BIT(8)
  56#define PHY_CTRL_OTAPDLY_SEL_MASK	GENMASK(15, 12)
  57#define PHY_CTRL_OTAPDLY_SEL_SHIFT	12
  58#define PHY_CTRL_STRB_SEL_MASK		GENMASK(23, 16)
  59#define PHY_CTRL_STRB_SEL_SHIFT		16
  60#define PHY_CTRL_TEST_CTRL_MASK		GENMASK(31, 24)
  61
  62#define PHY_CTRL_REG2			0x274
  63#define PHY_CTRL_EN_DLL_MASK		BIT(0)
  64#define PHY_CTRL_DLL_RDY_MASK		BIT(1)
  65#define PHY_CTRL_FREQ_SEL_MASK		GENMASK(6, 4)
  66#define PHY_CTRL_FREQ_SEL_SHIFT		4
  67#define PHY_CTRL_SEL_DLY_TX_MASK	BIT(16)
  68#define PHY_CTRL_SEL_DLY_RX_MASK	BIT(17)
  69#define FREQSEL_200M_170M		0x0
  70#define FREQSEL_170M_140M	        0x1
  71#define FREQSEL_140M_110M	        0x2
  72#define FREQSEL_110M_80M	        0x3
  73#define FREQSEL_80M_50M			0x4
  74#define FREQSEL_275M_250M		0x5
  75#define FREQSEL_250M_225M		0x6
  76#define FREQSEL_225M_200M		0x7
  77#define PHY_DLL_TIMEOUT_MS		100
  78
  79#define SDHCI_HW_RST_EN		BIT(4)
  80
  81/* Default settings for ZynqMP Clock Phases */
  82#define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63,  0,   0, 183, 54,  0, 0}
  83#define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
  84
  85#define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
  86#define VERSAL_OCLK_PHASE {0,  60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
  87
  88#define VERSAL_NET_EMMC_ICLK_PHASE {0, 0, 0, 0, 0, 0, 0, 0, 39, 0, 0}
  89#define VERSAL_NET_EMMC_OCLK_PHASE {0, 113, 0, 0, 0, 0, 0, 0, 113, 79, 45}
  90
  91#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL		0X77
  92
  93/*
  94 * On some SoCs the syscon area has a feature where the upper 16-bits of
  95 * each 32-bit register act as a write mask for the lower 16-bits.  This allows
  96 * atomic updates of the register without locking.  This macro is used on SoCs
  97 * that have that feature.
  98 */
  99#define HIWORD_UPDATE(val, mask, shift) \
 100		((val) << (shift) | (mask) << ((shift) + 16))
 101
 102#define CD_STABLE_TIMEOUT_US		2000000
 103#define CD_STABLE_MAX_SLEEP_US		10
 104
 105/**
 106 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
 107 *
 108 * @reg:	Offset within the syscon of the register containing this field
 109 * @width:	Number of bits for this field
 110 * @shift:	Bit offset within @reg of this field (or -1 if not avail)
 111 */
 112struct sdhci_arasan_soc_ctl_field {
 113	u32 reg;
 114	u16 width;
 115	s16 shift;
 116};
 117
 118/**
 119 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
 120 *
 121 * @baseclkfreq:	Where to find corecfg_baseclkfreq
 122 * @clockmultiplier:	Where to find corecfg_clockmultiplier
 123 * @support64b:		Where to find SUPPORT64B bit
 124 * @hiword_update:	If true, use HIWORD_UPDATE to access the syscon
 125 *
 126 * It's up to the licensee of the Arsan IP block to make these available
 127 * somewhere if needed.  Presumably these will be scattered somewhere that's
 128 * accessible via the syscon API.
 129 */
 130struct sdhci_arasan_soc_ctl_map {
 131	struct sdhci_arasan_soc_ctl_field	baseclkfreq;
 132	struct sdhci_arasan_soc_ctl_field	clockmultiplier;
 133	struct sdhci_arasan_soc_ctl_field	support64b;
 134	bool					hiword_update;
 135};
 136
 137/**
 138 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
 139 *
 140 * @sdcardclk_ops:	The output clock related operations
 141 * @sampleclk_ops:	The sample clock related operations
 142 */
 143struct sdhci_arasan_clk_ops {
 144	const struct clk_ops *sdcardclk_ops;
 145	const struct clk_ops *sampleclk_ops;
 146};
 147
 148/**
 149 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
 150 *
 151 * @sdcardclk_hw:	Struct for the clock we might provide to a PHY.
 152 * @sdcardclk:		Pointer to normal 'struct clock' for sdcardclk_hw.
 153 * @sampleclk_hw:	Struct for the clock we might provide to a PHY.
 154 * @sampleclk:		Pointer to normal 'struct clock' for sampleclk_hw.
 155 * @clk_phase_in:	Array of Input Clock Phase Delays for all speed modes
 156 * @clk_phase_out:	Array of Output Clock Phase Delays for all speed modes
 157 * @set_clk_delays:	Function pointer for setting Clock Delays
 158 * @clk_of_data:	Platform specific runtime clock data storage pointer
 159 */
 160struct sdhci_arasan_clk_data {
 161	struct clk_hw	sdcardclk_hw;
 162	struct clk      *sdcardclk;
 163	struct clk_hw	sampleclk_hw;
 164	struct clk      *sampleclk;
 165	int		clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
 166	int		clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
 167	void		(*set_clk_delays)(struct sdhci_host *host);
 168	void		*clk_of_data;
 169};
 170
 171/**
 172 * struct sdhci_arasan_data - Arasan Controller Data
 173 *
 174 * @host:		Pointer to the main SDHCI host structure.
 175 * @clk_ahb:		Pointer to the AHB clock
 176 * @phy:		Pointer to the generic phy
 177 * @is_phy_on:		True if the PHY is on; false if not.
 178 * @internal_phy_reg:	True if the PHY is within the Host controller.
 179 * @has_cqe:		True if controller has command queuing engine.
 180 * @clk_data:		Struct for the Arasan Controller Clock Data.
 181 * @clk_ops:		Struct for the Arasan Controller Clock Operations.
 182 * @soc_ctl_base:	Pointer to regmap for syscon for soc_ctl registers.
 183 * @soc_ctl_map:	Map to get offsets into soc_ctl registers.
 184 * @quirks:		Arasan deviations from spec.
 185 */
 186struct sdhci_arasan_data {
 187	struct sdhci_host *host;
 188	struct clk	*clk_ahb;
 189	struct phy	*phy;
 190	bool		is_phy_on;
 191	bool		internal_phy_reg;
 192
 193	bool		has_cqe;
 194	struct sdhci_arasan_clk_data clk_data;
 195	const struct sdhci_arasan_clk_ops *clk_ops;
 196
 197	struct regmap	*soc_ctl_base;
 198	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
 199	unsigned int	quirks;
 200
 201/* Controller does not have CD wired and will not function normally without */
 202#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST	BIT(0)
 203/* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
 204 * internal clock even when the clock isn't stable */
 205#define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
 206/*
 207 * Some of the Arasan variations might not have timing requirements
 208 * met at 25MHz for Default Speed mode, those controllers work at
 209 * 19MHz instead
 210 */
 211#define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
 212/* Enable CD stable check before power-up */
 213#define SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE	BIT(3)
 214};
 215
 216struct sdhci_arasan_of_data {
 217	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
 218	const struct sdhci_pltfm_data *pdata;
 219	const struct sdhci_arasan_clk_ops *clk_ops;
 220	u32 quirks;
 221};
 222
 223static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
 224	.baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
 225	.clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
 226	.hiword_update = true,
 227};
 228
 229static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
 230	.baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
 231	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
 232	.hiword_update = false,
 233};
 234
 235static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
 236	.baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
 237	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
 238	.hiword_update = false,
 239};
 240
 241static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
 242	.baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
 243	.clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
 244	.support64b = { .reg = 0x4, .width = 1, .shift = 24 },
 245	.hiword_update = false,
 246};
 247
 248static void sdhci_arasan_phy_set_delaychain(struct sdhci_host *host, bool enable)
 249{
 250	u32 reg;
 251
 252	reg = readl(host->ioaddr + PHY_CTRL_REG2);
 253	if (enable)
 254		reg |= (PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
 255	else
 256		reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
 257
 258	writel(reg, host->ioaddr + PHY_CTRL_REG2);
 259}
 260
 261static int sdhci_arasan_phy_set_dll(struct sdhci_host *host, bool enable)
 262{
 263	u32 reg;
 264
 265	reg = readl(host->ioaddr + PHY_CTRL_REG2);
 266	if (enable)
 267		reg |= PHY_CTRL_EN_DLL_MASK;
 268	else
 269		reg &= ~PHY_CTRL_EN_DLL_MASK;
 270
 271	writel(reg, host->ioaddr + PHY_CTRL_REG2);
 272
 273	if (!enable)
 274		return 0;
 275
 276	return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg,
 277					  (reg & PHY_CTRL_DLL_RDY_MASK), 10,
 278					  1000 * PHY_DLL_TIMEOUT_MS);
 279}
 280
 281static void sdhci_arasan_phy_dll_set_freq(struct sdhci_host *host, int clock)
 282{
 283	u32 reg, freq_sel, freq;
 284
 285	freq = DIV_ROUND_CLOSEST(clock, 1000000);
 286	if (freq <= 200 && freq > 170)
 287		freq_sel = FREQSEL_200M_170M;
 288	else if (freq <= 170 && freq > 140)
 289		freq_sel = FREQSEL_170M_140M;
 290	else if (freq <= 140 && freq > 110)
 291		freq_sel = FREQSEL_140M_110M;
 292	else if (freq <= 110 && freq > 80)
 293		freq_sel = FREQSEL_110M_80M;
 294	else
 295		freq_sel = FREQSEL_80M_50M;
 296
 297	reg = readl(host->ioaddr + PHY_CTRL_REG2);
 298	reg &= ~PHY_CTRL_FREQ_SEL_MASK;
 299	reg |= (freq_sel << PHY_CTRL_FREQ_SEL_SHIFT);
 300	writel(reg, host->ioaddr + PHY_CTRL_REG2);
 301}
 302
 303/**
 304 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
 305 *
 306 * @host:	The sdhci_host
 307 * @fld:	The field to write to
 308 * @val:	The value to write
 309 *
 310 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
 311 * Note that if a field is specified as not available (shift < 0) then
 312 * this function will silently return an error code.  It will be noisy
 313 * and print errors for any other (unexpected) errors.
 314 *
 315 * Return: 0 on success and error value on error
 316 */
 317static int sdhci_arasan_syscon_write(struct sdhci_host *host,
 318				   const struct sdhci_arasan_soc_ctl_field *fld,
 319				   u32 val)
 320{
 321	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 322	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 323	struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
 324	u32 reg = fld->reg;
 325	u16 width = fld->width;
 326	s16 shift = fld->shift;
 327	int ret;
 328
 329	/*
 330	 * Silently return errors for shift < 0 so caller doesn't have
 331	 * to check for fields which are optional.  For fields that
 332	 * are required then caller needs to do something special
 333	 * anyway.
 334	 */
 335	if (shift < 0)
 336		return -EINVAL;
 337
 338	if (sdhci_arasan->soc_ctl_map->hiword_update)
 339		ret = regmap_write(soc_ctl_base, reg,
 340				   HIWORD_UPDATE(val, GENMASK(width, 0),
 341						 shift));
 342	else
 343		ret = regmap_update_bits(soc_ctl_base, reg,
 344					 GENMASK(shift + width, shift),
 345					 val << shift);
 346
 347	/* Yell about (unexpected) regmap errors */
 348	if (ret)
 349		pr_warn("%s: Regmap write fail: %d\n",
 350			 mmc_hostname(host->mmc), ret);
 351
 352	return ret;
 353}
 354
 355static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
 356{
 357	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 358	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 359	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
 360	bool ctrl_phy = false;
 361
 362	if (!IS_ERR(sdhci_arasan->phy)) {
 363		if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
 364			/*
 365			 * If PHY off, set clock to max speed and power PHY on.
 366			 *
 367			 * Although PHY docs apparently suggest power cycling
 368			 * when changing the clock the PHY doesn't like to be
 369			 * powered on while at low speeds like those used in ID
 370			 * mode.  Even worse is powering the PHY on while the
 371			 * clock is off.
 372			 *
 373			 * To workaround the PHY limitations, the best we can
 374			 * do is to power it on at a faster speed and then slam
 375			 * through low speeds without power cycling.
 376			 */
 377			sdhci_set_clock(host, host->max_clk);
 378			if (phy_power_on(sdhci_arasan->phy)) {
 379				pr_err("%s: Cannot power on phy.\n",
 380				       mmc_hostname(host->mmc));
 381				return;
 382			}
 383
 384			sdhci_arasan->is_phy_on = true;
 385
 386			/*
 387			 * We'll now fall through to the below case with
 388			 * ctrl_phy = false (so we won't turn off/on).  The
 389			 * sdhci_set_clock() will set the real clock.
 390			 */
 391		} else if (clock > PHY_CLK_TOO_SLOW_HZ) {
 392			/*
 393			 * At higher clock speeds the PHY is fine being power
 394			 * cycled and docs say you _should_ power cycle when
 395			 * changing clock speeds.
 396			 */
 397			ctrl_phy = true;
 398		}
 399	}
 400
 401	if (ctrl_phy && sdhci_arasan->is_phy_on) {
 402		phy_power_off(sdhci_arasan->phy);
 403		sdhci_arasan->is_phy_on = false;
 404	}
 405
 406	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {
 407		/*
 408		 * Some of the Arasan variations might not have timing
 409		 * requirements met at 25MHz for Default Speed mode,
 410		 * those controllers work at 19MHz instead.
 411		 */
 412		if (clock == DEFAULT_SPEED_MAX_DTR)
 413			clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
 414	}
 415
 416	/* Set the Input and Output Clock Phase Delays */
 417	if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ)
 418		clk_data->set_clk_delays(host);
 419
 420	if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {
 421		sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 422		sdhci_arasan_phy_set_dll(host, 0);
 423		sdhci_arasan_phy_set_delaychain(host, 0);
 424		sdhci_arasan_phy_dll_set_freq(host, clock);
 425	} else if (sdhci_arasan->internal_phy_reg) {
 426		sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 427		sdhci_arasan_phy_set_delaychain(host, 1);
 428	}
 429
 430	sdhci_set_clock(host, clock);
 431
 432	if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ)
 433		sdhci_arasan_phy_set_dll(host, 1);
 434
 435	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
 436		/*
 437		 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
 438		 * after enabling the clock even though the clock is not
 439		 * stable. Trying to use a clock without waiting here results
 440		 * in EILSEQ while detecting some older/slower cards. The
 441		 * chosen delay is the maximum delay from sdhci_set_clock.
 442		 */
 443		msleep(20);
 444
 445	if (ctrl_phy) {
 446		if (phy_power_on(sdhci_arasan->phy)) {
 447			pr_err("%s: Cannot power on phy.\n",
 448			       mmc_hostname(host->mmc));
 449			return;
 450		}
 451
 452		sdhci_arasan->is_phy_on = true;
 453	}
 454}
 455
 456static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
 457					struct mmc_ios *ios)
 458{
 459	u32 vendor;
 460	struct sdhci_host *host = mmc_priv(mmc);
 461
 462	vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
 463	if (ios->enhanced_strobe)
 464		vendor |= VENDOR_ENHANCED_STROBE;
 465	else
 466		vendor &= ~VENDOR_ENHANCED_STROBE;
 467
 468	sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
 469}
 470
 471static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
 472{
 473	u8 ctrl;
 474	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 475	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 476
 477	sdhci_and_cqhci_reset(host, mask);
 478
 479	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
 480		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 481		ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
 482		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 483	}
 484}
 485
 486static void sdhci_arasan_hw_reset(struct sdhci_host *host)
 487{
 488	u8 reg;
 489
 490	reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
 491	reg |= SDHCI_HW_RST_EN;
 492	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 493	/* As per eMMC spec, minimum 1us is required but give it 2us for good measure */
 494	usleep_range(2, 5);
 495	reg &= ~SDHCI_HW_RST_EN;
 496	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 497	/* As per eMMC spec, minimum 200us is required but give it 300us for good measure */
 498	usleep_range(300, 500);
 499}
 500
 501static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
 502				       struct mmc_ios *ios)
 503{
 504	switch (ios->signal_voltage) {
 505	case MMC_SIGNAL_VOLTAGE_180:
 506		/*
 507		 * Plese don't switch to 1V8 as arasan,5.1 doesn't
 508		 * actually refer to this setting to indicate the
 509		 * signal voltage and the state machine will be broken
 510		 * actually if we force to enable 1V8. That's something
 511		 * like broken quirk but we could work around here.
 512		 */
 513		return 0;
 514	case MMC_SIGNAL_VOLTAGE_330:
 515	case MMC_SIGNAL_VOLTAGE_120:
 516		/* We don't support 3V3 and 1V2 */
 517		break;
 518	}
 519
 520	return -EINVAL;
 521}
 522
 523static void sdhci_arasan_set_power_and_bus_voltage(struct sdhci_host *host, unsigned char mode,
 524						   unsigned short vdd)
 525{
 526	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 527	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 528	u32 reg;
 529
 530	/*
 531	 * Ensure that the card detect logic has stabilized before powering up, this is
 532	 * necessary after a host controller reset.
 533	 */
 534	if (mode == MMC_POWER_UP && sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE)
 535		read_poll_timeout(sdhci_readl, reg, reg & SDHCI_CD_STABLE, CD_STABLE_MAX_SLEEP_US,
 536				  CD_STABLE_TIMEOUT_US, false, host, SDHCI_PRESENT_STATE);
 537
 538	sdhci_set_power_and_bus_voltage(host, mode, vdd);
 539}
 540
 541static const struct sdhci_ops sdhci_arasan_ops = {
 542	.set_clock = sdhci_arasan_set_clock,
 543	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
 544	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 545	.set_bus_width = sdhci_set_bus_width,
 546	.reset = sdhci_arasan_reset,
 547	.set_uhs_signaling = sdhci_set_uhs_signaling,
 548	.set_power = sdhci_arasan_set_power_and_bus_voltage,
 549	.hw_reset = sdhci_arasan_hw_reset,
 550};
 551
 552static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
 553{
 554	int cmd_error = 0;
 555	int data_error = 0;
 556
 557	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
 558		return intmask;
 559
 560	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
 561
 562	return 0;
 563}
 564
 565static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
 566{
 567	sdhci_dumpregs(mmc_priv(mmc));
 568}
 569
 570static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
 571{
 572	struct sdhci_host *host = mmc_priv(mmc);
 573	u32 reg;
 574
 575	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
 576	while (reg & SDHCI_DATA_AVAILABLE) {
 577		sdhci_readl(host, SDHCI_BUFFER);
 578		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
 579	}
 580
 581	sdhci_cqe_enable(mmc);
 582}
 583
 584static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
 585	.enable         = sdhci_arasan_cqe_enable,
 586	.disable        = sdhci_cqe_disable,
 587	.dumpregs       = sdhci_arasan_dumpregs,
 588};
 589
 590static const struct sdhci_ops sdhci_arasan_cqe_ops = {
 591	.set_clock = sdhci_arasan_set_clock,
 592	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
 593	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 594	.set_bus_width = sdhci_set_bus_width,
 595	.reset = sdhci_arasan_reset,
 596	.set_uhs_signaling = sdhci_set_uhs_signaling,
 597	.set_power = sdhci_arasan_set_power_and_bus_voltage,
 598	.irq = sdhci_arasan_cqhci_irq,
 599};
 600
 601static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
 602	.ops = &sdhci_arasan_cqe_ops,
 603	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 604	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 605			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
 606};
 607
 608/**
 609 * sdhci_arasan_suspend - Suspend method for the driver
 610 * @dev:	Address of the device structure
 611 *
 612 * Put the device in a low power state.
 613 *
 614 * Return: 0 on success and error value on error
 615 */
 616static int sdhci_arasan_suspend(struct device *dev)
 617{
 618	struct sdhci_host *host = dev_get_drvdata(dev);
 619	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 620	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 621	int ret;
 622
 623	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 624		mmc_retune_needed(host->mmc);
 625
 626	if (sdhci_arasan->has_cqe) {
 627		ret = cqhci_suspend(host->mmc);
 628		if (ret)
 629			return ret;
 630	}
 631
 632	ret = sdhci_suspend_host(host);
 633	if (ret)
 634		return ret;
 635
 636	if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
 637		ret = phy_power_off(sdhci_arasan->phy);
 638		if (ret) {
 639			dev_err(dev, "Cannot power off phy.\n");
 640			if (sdhci_resume_host(host))
 641				dev_err(dev, "Cannot resume host.\n");
 642
 643			return ret;
 644		}
 645		sdhci_arasan->is_phy_on = false;
 646	}
 647
 648	clk_disable(pltfm_host->clk);
 649	clk_disable(sdhci_arasan->clk_ahb);
 650
 651	return 0;
 652}
 653
 654/**
 655 * sdhci_arasan_resume - Resume method for the driver
 656 * @dev:	Address of the device structure
 657 *
 658 * Resume operation after suspend
 659 *
 660 * Return: 0 on success and error value on error
 661 */
 662static int sdhci_arasan_resume(struct device *dev)
 663{
 664	struct sdhci_host *host = dev_get_drvdata(dev);
 665	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 666	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 667	int ret;
 668
 669	ret = clk_enable(sdhci_arasan->clk_ahb);
 670	if (ret) {
 671		dev_err(dev, "Cannot enable AHB clock.\n");
 672		return ret;
 673	}
 674
 675	ret = clk_enable(pltfm_host->clk);
 676	if (ret) {
 677		dev_err(dev, "Cannot enable SD clock.\n");
 678		return ret;
 679	}
 680
 681	if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
 682		ret = phy_power_on(sdhci_arasan->phy);
 683		if (ret) {
 684			dev_err(dev, "Cannot power on phy.\n");
 685			return ret;
 686		}
 687		sdhci_arasan->is_phy_on = true;
 688	}
 689
 690	ret = sdhci_resume_host(host);
 691	if (ret) {
 692		dev_err(dev, "Cannot resume host.\n");
 693		return ret;
 694	}
 695
 696	if (sdhci_arasan->has_cqe)
 697		return cqhci_resume(host->mmc);
 698
 699	return 0;
 700}
 701
 702static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
 703				sdhci_arasan_resume);
 704
 705/**
 706 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
 707 *
 708 * @hw:			Pointer to the hardware clock structure.
 709 * @parent_rate:		The parent rate (should be rate of clk_xin).
 710 *
 711 * Return the current actual rate of the SD card clock.  This can be used
 712 * to communicate with out PHY.
 713 *
 714 * Return: The card clock rate.
 715 */
 716static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
 717						      unsigned long parent_rate)
 718{
 719	struct sdhci_arasan_clk_data *clk_data =
 720		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
 721	struct sdhci_arasan_data *sdhci_arasan =
 722		container_of(clk_data, struct sdhci_arasan_data, clk_data);
 723	struct sdhci_host *host = sdhci_arasan->host;
 724
 725	return host->mmc->actual_clock;
 726}
 727
 728static const struct clk_ops arasan_sdcardclk_ops = {
 729	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
 730};
 731
 732/**
 733 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
 734 *
 735 * @hw:			Pointer to the hardware clock structure.
 736 * @parent_rate:		The parent rate (should be rate of clk_xin).
 737 *
 738 * Return the current actual rate of the sampling clock.  This can be used
 739 * to communicate with out PHY.
 740 *
 741 * Return: The sample clock rate.
 742 */
 743static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
 744						      unsigned long parent_rate)
 745{
 746	struct sdhci_arasan_clk_data *clk_data =
 747		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
 748	struct sdhci_arasan_data *sdhci_arasan =
 749		container_of(clk_data, struct sdhci_arasan_data, clk_data);
 750	struct sdhci_host *host = sdhci_arasan->host;
 751
 752	return host->mmc->actual_clock;
 753}
 754
 755static const struct clk_ops arasan_sampleclk_ops = {
 756	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
 757};
 758
 759/**
 760 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 761 *
 762 * @hw:			Pointer to the hardware clock structure.
 763 * @degrees:		The clock phase shift between 0 - 359.
 764 *
 765 * Set the SD Output Clock Tap Delays for Output path
 766 *
 767 * Return: 0 on success and error value on error
 768 */
 769static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
 770{
 771	struct sdhci_arasan_clk_data *clk_data =
 772		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
 773	struct sdhci_arasan_data *sdhci_arasan =
 774		container_of(clk_data, struct sdhci_arasan_data, clk_data);
 775	struct sdhci_host *host = sdhci_arasan->host;
 776	const char *clk_name = clk_hw_get_name(hw);
 777	u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
 778	u8 tap_delay, tap_max = 0;
 779	int ret;
 780
 781	/* This is applicable for SDHCI_SPEC_300 and above */
 782	if (host->version < SDHCI_SPEC_300)
 783		return 0;
 784
 785	switch (host->timing) {
 786	case MMC_TIMING_MMC_HS:
 787	case MMC_TIMING_SD_HS:
 788	case MMC_TIMING_UHS_SDR25:
 789	case MMC_TIMING_UHS_DDR50:
 790	case MMC_TIMING_MMC_DDR52:
 791		/* For 50MHz clock, 30 Taps are available */
 792		tap_max = 30;
 793		break;
 794	case MMC_TIMING_UHS_SDR50:
 795		/* For 100MHz clock, 15 Taps are available */
 796		tap_max = 15;
 797		break;
 798	case MMC_TIMING_UHS_SDR104:
 799	case MMC_TIMING_MMC_HS200:
 800		/* For 200MHz clock, 8 Taps are available */
 801		tap_max = 8;
 802		break;
 803	default:
 804		break;
 805	}
 806
 807	tap_delay = (degrees * tap_max) / 360;
 808
 809	/* Set the Clock Phase */
 810	ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
 811	if (ret)
 812		pr_err("Error setting Output Tap Delay\n");
 813
 814	/* Release DLL Reset */
 815	zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
 816
 817	return ret;
 818}
 819
 820static const struct clk_ops zynqmp_sdcardclk_ops = {
 821	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
 822	.set_phase = sdhci_zynqmp_sdcardclk_set_phase,
 823};
 824
 825/**
 826 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 827 *
 828 * @hw:			Pointer to the hardware clock structure.
 829 * @degrees:		The clock phase shift between 0 - 359.
 830 *
 831 * Set the SD Input Clock Tap Delays for Input path
 832 *
 833 * Return: 0 on success and error value on error
 834 */
 835static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
 836{
 837	struct sdhci_arasan_clk_data *clk_data =
 838		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
 839	struct sdhci_arasan_data *sdhci_arasan =
 840		container_of(clk_data, struct sdhci_arasan_data, clk_data);
 841	struct sdhci_host *host = sdhci_arasan->host;
 842	const char *clk_name = clk_hw_get_name(hw);
 843	u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
 844	u8 tap_delay, tap_max = 0;
 845	int ret;
 846
 847	/* This is applicable for SDHCI_SPEC_300 and above */
 848	if (host->version < SDHCI_SPEC_300)
 849		return 0;
 850
 851	/* Assert DLL Reset */
 852	zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
 853
 854	switch (host->timing) {
 855	case MMC_TIMING_MMC_HS:
 856	case MMC_TIMING_SD_HS:
 857	case MMC_TIMING_UHS_SDR25:
 858	case MMC_TIMING_UHS_DDR50:
 859	case MMC_TIMING_MMC_DDR52:
 860		/* For 50MHz clock, 120 Taps are available */
 861		tap_max = 120;
 862		break;
 863	case MMC_TIMING_UHS_SDR50:
 864		/* For 100MHz clock, 60 Taps are available */
 865		tap_max = 60;
 866		break;
 867	case MMC_TIMING_UHS_SDR104:
 868	case MMC_TIMING_MMC_HS200:
 869		/* For 200MHz clock, 30 Taps are available */
 870		tap_max = 30;
 871		break;
 872	default:
 873		break;
 874	}
 875
 876	tap_delay = (degrees * tap_max) / 360;
 877
 878	/* Set the Clock Phase */
 879	ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
 880	if (ret)
 881		pr_err("Error setting Input Tap Delay\n");
 882
 883	return ret;
 884}
 885
 886static const struct clk_ops zynqmp_sampleclk_ops = {
 887	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
 888	.set_phase = sdhci_zynqmp_sampleclk_set_phase,
 889};
 890
 891/**
 892 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 893 *
 894 * @hw:			Pointer to the hardware clock structure.
 895 * @degrees:		The clock phase shift between 0 - 359.
 896 *
 897 * Set the SD Output Clock Tap Delays for Output path
 898 *
 899 * Return: 0 on success and error value on error
 900 */
 901static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
 902{
 903	struct sdhci_arasan_clk_data *clk_data =
 904		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
 905	struct sdhci_arasan_data *sdhci_arasan =
 906		container_of(clk_data, struct sdhci_arasan_data, clk_data);
 907	struct sdhci_host *host = sdhci_arasan->host;
 908	u8 tap_delay, tap_max = 0;
 909
 910	/* This is applicable for SDHCI_SPEC_300 and above */
 911	if (host->version < SDHCI_SPEC_300)
 912		return 0;
 913
 914	switch (host->timing) {
 915	case MMC_TIMING_MMC_HS:
 916	case MMC_TIMING_SD_HS:
 917	case MMC_TIMING_UHS_SDR25:
 918	case MMC_TIMING_UHS_DDR50:
 919	case MMC_TIMING_MMC_DDR52:
 920		/* For 50MHz clock, 30 Taps are available */
 921		tap_max = 30;
 922		break;
 923	case MMC_TIMING_UHS_SDR50:
 924		/* For 100MHz clock, 15 Taps are available */
 925		tap_max = 15;
 926		break;
 927	case MMC_TIMING_UHS_SDR104:
 928	case MMC_TIMING_MMC_HS200:
 929		/* For 200MHz clock, 8 Taps are available */
 930		tap_max = 8;
 931		break;
 932	default:
 933		break;
 934	}
 935
 936	tap_delay = (degrees * tap_max) / 360;
 937
 938	/* Set the Clock Phase */
 939	if (tap_delay) {
 940		u32 regval;
 941
 942		regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
 943		regval |= SDHCI_OTAPDLY_ENABLE;
 944		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 945		regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 946		regval |= tap_delay;
 947		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 948	}
 949
 950	return 0;
 951}
 952
 953static const struct clk_ops versal_sdcardclk_ops = {
 954	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
 955	.set_phase = sdhci_versal_sdcardclk_set_phase,
 956};
 957
 958/**
 959 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 960 *
 961 * @hw:			Pointer to the hardware clock structure.
 962 * @degrees:		The clock phase shift between 0 - 359.
 963 *
 964 * Set the SD Input Clock Tap Delays for Input path
 965 *
 966 * Return: 0 on success and error value on error
 967 */
 968static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
 969{
 970	struct sdhci_arasan_clk_data *clk_data =
 971		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
 972	struct sdhci_arasan_data *sdhci_arasan =
 973		container_of(clk_data, struct sdhci_arasan_data, clk_data);
 974	struct sdhci_host *host = sdhci_arasan->host;
 975	u8 tap_delay, tap_max = 0;
 976
 977	/* This is applicable for SDHCI_SPEC_300 and above */
 978	if (host->version < SDHCI_SPEC_300)
 979		return 0;
 980
 981	switch (host->timing) {
 982	case MMC_TIMING_MMC_HS:
 983	case MMC_TIMING_SD_HS:
 984	case MMC_TIMING_UHS_SDR25:
 985	case MMC_TIMING_UHS_DDR50:
 986	case MMC_TIMING_MMC_DDR52:
 987		/* For 50MHz clock, 120 Taps are available */
 988		tap_max = 120;
 989		break;
 990	case MMC_TIMING_UHS_SDR50:
 991		/* For 100MHz clock, 60 Taps are available */
 992		tap_max = 60;
 993		break;
 994	case MMC_TIMING_UHS_SDR104:
 995	case MMC_TIMING_MMC_HS200:
 996		/* For 200MHz clock, 30 Taps are available */
 997		tap_max = 30;
 998		break;
 999	default:
1000		break;
1001	}
1002
1003	tap_delay = (degrees * tap_max) / 360;
1004
1005	/* Set the Clock Phase */
1006	if (tap_delay) {
1007		u32 regval;
1008
1009		regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
1010		regval |= SDHCI_ITAPDLY_CHGWIN;
1011		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
1012		regval |= SDHCI_ITAPDLY_ENABLE;
1013		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
1014		regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
1015		regval |= tap_delay;
1016		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
1017		regval &= ~SDHCI_ITAPDLY_CHGWIN;
1018		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
1019	}
1020
1021	return 0;
1022}
1023
1024static const struct clk_ops versal_sampleclk_ops = {
1025	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
1026	.set_phase = sdhci_versal_sampleclk_set_phase,
1027};
1028
1029static int sdhci_versal_net_emmc_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
1030{
1031	struct sdhci_arasan_clk_data *clk_data =
1032		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
1033	struct sdhci_arasan_data *sdhci_arasan =
1034		container_of(clk_data, struct sdhci_arasan_data, clk_data);
1035	struct sdhci_host *host = sdhci_arasan->host;
1036	u8 tap_delay, tap_max = 0;
1037
1038	switch (host->timing) {
1039	case MMC_TIMING_MMC_HS:
1040	case MMC_TIMING_MMC_DDR52:
1041		tap_max = 16;
1042		break;
1043	case MMC_TIMING_MMC_HS200:
1044	case MMC_TIMING_MMC_HS400:
1045		 /* For 200MHz clock, 32 Taps are available */
1046		tap_max = 32;
1047		break;
1048	default:
1049		break;
1050	}
1051
1052	tap_delay = (degrees * tap_max) / 360;
1053
1054	/* Set the Clock Phase */
1055	if (tap_delay) {
1056		u32 regval;
1057
1058		regval = sdhci_readl(host, PHY_CTRL_REG1);
1059		regval |= PHY_CTRL_OTAPDLY_ENA_MASK;
1060		sdhci_writel(host, regval, PHY_CTRL_REG1);
1061		regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK;
1062		regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT;
1063		sdhci_writel(host, regval, PHY_CTRL_REG1);
1064	}
1065
1066	return 0;
1067}
1068
1069static const struct clk_ops versal_net_sdcardclk_ops = {
1070	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
1071	.set_phase = sdhci_versal_net_emmc_sdcardclk_set_phase,
1072};
1073
1074static int sdhci_versal_net_emmc_sampleclk_set_phase(struct clk_hw *hw, int degrees)
1075{
1076	struct sdhci_arasan_clk_data *clk_data =
1077		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
1078	struct sdhci_arasan_data *sdhci_arasan =
1079		container_of(clk_data, struct sdhci_arasan_data, clk_data);
1080	struct sdhci_host *host = sdhci_arasan->host;
1081	u8 tap_delay, tap_max = 0;
1082	u32 regval;
1083
1084	switch (host->timing) {
1085	case MMC_TIMING_MMC_HS:
1086	case MMC_TIMING_MMC_DDR52:
1087		tap_max = 32;
1088		break;
1089	case MMC_TIMING_MMC_HS400:
1090		/* Strobe select tap point for strb90 and strb180 */
1091		regval = sdhci_readl(host, PHY_CTRL_REG1);
1092		regval &= ~PHY_CTRL_STRB_SEL_MASK;
1093		regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT;
1094		sdhci_writel(host, regval, PHY_CTRL_REG1);
1095		break;
1096	default:
1097		break;
1098	}
1099
1100	tap_delay = (degrees * tap_max) / 360;
1101
1102	/* Set the Clock Phase */
1103	if (tap_delay) {
1104		regval = sdhci_readl(host, PHY_CTRL_REG1);
1105		regval |= PHY_CTRL_ITAP_CHG_WIN_MASK;
1106		sdhci_writel(host, regval, PHY_CTRL_REG1);
1107		regval |= PHY_CTRL_ITAPDLY_ENA_MASK;
1108		sdhci_writel(host, regval, PHY_CTRL_REG1);
1109		regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK;
1110		regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT;
1111		sdhci_writel(host, regval, PHY_CTRL_REG1);
1112		regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK;
1113		sdhci_writel(host, regval, PHY_CTRL_REG1);
1114	}
1115
1116	return 0;
1117}
1118
1119static const struct clk_ops versal_net_sampleclk_ops = {
1120	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
1121	.set_phase = sdhci_versal_net_emmc_sampleclk_set_phase,
1122};
1123
1124static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
1125{
1126	u16 clk;
1127
1128	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1129	clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
1130	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1131
1132	/* Issue DLL Reset */
1133	zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
1134
1135	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1136
1137	sdhci_enable_clk(host, clk);
1138}
1139
1140static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
1141{
1142	struct sdhci_host *host = mmc_priv(mmc);
1143	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1144	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1145	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
1146	const char *clk_name = clk_hw_get_name(hw);
1147	u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
1148							   NODE_SD_1;
1149	int err;
1150
1151	/* ZynqMP SD controller does not perform auto tuning in DDR50 mode */
1152	if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1153		return 0;
1154
1155	arasan_zynqmp_dll_reset(host, device_id);
1156
1157	err = sdhci_execute_tuning(mmc, opcode);
1158	if (err)
1159		return err;
1160
1161	arasan_zynqmp_dll_reset(host, device_id);
1162
1163	return 0;
1164}
1165
1166/**
1167 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
1168 *
1169 * @host:		The sdhci_host
1170 * @value:		The value to write
1171 *
1172 * The corecfg_clockmultiplier is supposed to contain clock multiplier
1173 * value of programmable clock generator.
1174 *
1175 * NOTES:
1176 * - Many existing devices don't seem to do this and work fine.  To keep
1177 *   compatibility for old hardware where the device tree doesn't provide a
1178 *   register map, this function is a noop if a soc_ctl_map hasn't been provided
1179 *   for this platform.
1180 * - The value of corecfg_clockmultiplier should sync with that of corresponding
1181 *   value reading from sdhci_capability_register. So this function is called
1182 *   once at probe time and never called again.
1183 */
1184static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
1185						u32 value)
1186{
1187	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1188	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1189	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1190		sdhci_arasan->soc_ctl_map;
1191
1192	/* Having a map is optional */
1193	if (!soc_ctl_map)
1194		return;
1195
1196	/* If we have a map, we expect to have a syscon */
1197	if (!sdhci_arasan->soc_ctl_base) {
1198		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1199			mmc_hostname(host->mmc));
1200		return;
1201	}
1202
1203	sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
1204}
1205
1206/**
1207 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
1208 *
1209 * @host:		The sdhci_host
1210 *
1211 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
1212 * function can be used to make that happen.
1213 *
1214 * NOTES:
1215 * - Many existing devices don't seem to do this and work fine.  To keep
1216 *   compatibility for old hardware where the device tree doesn't provide a
1217 *   register map, this function is a noop if a soc_ctl_map hasn't been provided
1218 *   for this platform.
1219 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
1220 *   to achieve lower clock rates.  That means that this function is called once
1221 *   at probe time and never called again.
1222 */
1223static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
1224{
1225	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1226	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1227	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1228		sdhci_arasan->soc_ctl_map;
1229	u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1230
1231	/* Having a map is optional */
1232	if (!soc_ctl_map)
1233		return;
1234
1235	/* If we have a map, we expect to have a syscon */
1236	if (!sdhci_arasan->soc_ctl_base) {
1237		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1238			mmc_hostname(host->mmc));
1239		return;
1240	}
1241
1242	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
1243}
1244
1245static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
1246{
1247	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1248	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1249	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1250
1251	clk_set_phase(clk_data->sampleclk,
1252		      clk_data->clk_phase_in[host->timing]);
1253	clk_set_phase(clk_data->sdcardclk,
1254		      clk_data->clk_phase_out[host->timing]);
1255}
1256
1257static void arasan_dt_read_clk_phase(struct device *dev,
1258				     struct sdhci_arasan_clk_data *clk_data,
1259				     unsigned int timing, const char *prop)
1260{
1261	struct device_node *np = dev->of_node;
1262
1263	u32 clk_phase[2] = {0};
1264	int ret;
1265
1266	/*
1267	 * Read Tap Delay values from DT, if the DT does not contain the
1268	 * Tap Values then use the pre-defined values.
1269	 */
1270	ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0],
1271						  2, 0);
1272	if (ret < 0) {
1273		dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1274			prop, clk_data->clk_phase_in[timing],
1275			clk_data->clk_phase_out[timing]);
1276		return;
1277	}
1278
1279	/* The values read are Input and Output Clock Delays in order */
1280	clk_data->clk_phase_in[timing] = clk_phase[0];
1281	clk_data->clk_phase_out[timing] = clk_phase[1];
1282}
1283
1284/**
1285 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1286 *
1287 * @dev:		Pointer to our struct device.
1288 * @clk_data:		Pointer to the Clock Data structure
1289 *
1290 * Called at initialization to parse the values of Clock Delays.
1291 */
1292static void arasan_dt_parse_clk_phases(struct device *dev,
1293				       struct sdhci_arasan_clk_data *clk_data)
1294{
1295	u32 mio_bank = 0;
1296	int i;
1297
1298	/*
1299	 * This has been kept as a pointer and is assigned a function here.
1300	 * So that different controller variants can assign their own handling
1301	 * function.
1302	 */
1303	clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1304
1305	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1306		u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1307			ZYNQMP_ICLK_PHASE;
1308		u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1309			ZYNQMP_OCLK_PHASE;
1310
1311		of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1312		if (mio_bank == 2) {
1313			zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1314			zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1315		}
1316
1317		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1318			clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1319			clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1320		}
1321	}
1322
1323	if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1324		u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1325			VERSAL_ICLK_PHASE;
1326		u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1327			VERSAL_OCLK_PHASE;
1328
1329		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1330			clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1331			clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1332		}
1333	}
1334	if (of_device_is_compatible(dev->of_node, "xlnx,versal-net-emmc")) {
1335		u32 versal_net_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1336			VERSAL_NET_EMMC_ICLK_PHASE;
1337		u32 versal_net_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1338			VERSAL_NET_EMMC_OCLK_PHASE;
1339
1340		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1341			clk_data->clk_phase_in[i] = versal_net_iclk_phase[i];
1342			clk_data->clk_phase_out[i] = versal_net_oclk_phase[i];
1343		}
1344	}
1345	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1346				 "clk-phase-legacy");
1347	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1348				 "clk-phase-mmc-hs");
1349	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1350				 "clk-phase-sd-hs");
1351	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1352				 "clk-phase-uhs-sdr12");
1353	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1354				 "clk-phase-uhs-sdr25");
1355	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1356				 "clk-phase-uhs-sdr50");
1357	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1358				 "clk-phase-uhs-sdr104");
1359	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1360				 "clk-phase-uhs-ddr50");
1361	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1362				 "clk-phase-mmc-ddr52");
1363	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1364				 "clk-phase-mmc-hs200");
1365	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1366				 "clk-phase-mmc-hs400");
1367}
1368
1369static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1370	.ops = &sdhci_arasan_ops,
1371	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1372	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1373			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1374			SDHCI_QUIRK2_STOP_WITH_TC,
1375};
1376
1377static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1378	.sdcardclk_ops = &arasan_sdcardclk_ops,
1379	.sampleclk_ops = &arasan_sampleclk_ops,
1380};
1381
1382static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1383	.pdata = &sdhci_arasan_pdata,
1384	.clk_ops = &arasan_clk_ops,
1385};
1386
1387static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1388	.ops = &sdhci_arasan_cqe_ops,
1389	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1390		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1391		SDHCI_QUIRK_NO_LED |
1392		SDHCI_QUIRK_32BIT_DMA_ADDR |
1393		SDHCI_QUIRK_32BIT_DMA_SIZE |
1394		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1395	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1396		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1397		SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1398		SDHCI_QUIRK2_STOP_WITH_TC |
1399		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1400};
1401
1402static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1403	.ops = &sdhci_arasan_ops,
1404	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1405		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1406		SDHCI_QUIRK_NO_LED |
1407		SDHCI_QUIRK_32BIT_DMA_ADDR |
1408		SDHCI_QUIRK_32BIT_DMA_SIZE |
1409		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1410	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1411		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1412		SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1413		SDHCI_QUIRK2_STOP_WITH_TC |
1414		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1415};
1416
1417static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1418	.ops = &sdhci_arasan_ops,
1419	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1420		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1421		SDHCI_QUIRK_NO_LED |
1422		SDHCI_QUIRK_32BIT_DMA_ADDR |
1423		SDHCI_QUIRK_32BIT_DMA_SIZE |
1424		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1425	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1426		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1427		SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1428		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1429};
1430
1431static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1432	.soc_ctl_map = &rk3399_soc_ctl_map,
1433	.pdata = &sdhci_arasan_cqe_pdata,
1434	.clk_ops = &arasan_clk_ops,
1435};
1436
1437static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1438	.soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1439	.pdata = &sdhci_arasan_cqe_pdata,
1440	.clk_ops = &arasan_clk_ops,
1441};
1442
1443static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1444	.soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1445	.pdata = &sdhci_arasan_cqe_pdata,
1446	.clk_ops = &arasan_clk_ops,
1447};
1448
1449static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1450	.ops = &sdhci_arasan_ops,
1451	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1452			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1453			SDHCI_QUIRK2_STOP_WITH_TC,
1454};
1455
1456static const struct sdhci_pltfm_data sdhci_arasan_versal_net_pdata = {
1457	.ops = &sdhci_arasan_ops,
1458	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1459			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1460			SDHCI_QUIRK2_STOP_WITH_TC |
1461			SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
1462};
1463
1464static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1465	.sdcardclk_ops = &zynqmp_sdcardclk_ops,
1466	.sampleclk_ops = &zynqmp_sampleclk_ops,
1467};
1468
1469static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1470	.pdata = &sdhci_arasan_zynqmp_pdata,
1471	.clk_ops = &zynqmp_clk_ops,
1472	.quirks = SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE,
1473};
1474
1475static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1476	.sdcardclk_ops = &versal_sdcardclk_ops,
1477	.sampleclk_ops = &versal_sampleclk_ops,
1478};
1479
1480static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1481	.pdata = &sdhci_arasan_zynqmp_pdata,
1482	.clk_ops = &versal_clk_ops,
1483	.quirks = SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE,
1484};
1485
1486static const struct sdhci_arasan_clk_ops versal_net_clk_ops = {
1487	.sdcardclk_ops = &versal_net_sdcardclk_ops,
1488	.sampleclk_ops = &versal_net_sampleclk_ops,
1489};
1490
1491static struct sdhci_arasan_of_data sdhci_arasan_versal_net_data = {
1492	.pdata = &sdhci_arasan_versal_net_pdata,
1493	.clk_ops = &versal_net_clk_ops,
1494	.quirks = SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE,
1495};
1496
1497static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1498	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1499	.pdata = &sdhci_keembay_emmc_pdata,
1500	.clk_ops = &arasan_clk_ops,
1501};
1502
1503static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1504	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1505	.pdata = &sdhci_keembay_sd_pdata,
1506	.clk_ops = &arasan_clk_ops,
1507};
1508
1509static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1510	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1511	.pdata = &sdhci_keembay_sdio_pdata,
1512	.clk_ops = &arasan_clk_ops,
1513};
1514
1515static const struct of_device_id sdhci_arasan_of_match[] = {
1516	/* SoC-specific compatible strings w/ soc_ctl_map */
1517	{
1518		.compatible = "rockchip,rk3399-sdhci-5.1",
1519		.data = &sdhci_arasan_rk3399_data,
1520	},
1521	{
1522		.compatible = "intel,lgm-sdhci-5.1-emmc",
1523		.data = &intel_lgm_emmc_data,
1524	},
1525	{
1526		.compatible = "intel,lgm-sdhci-5.1-sdxc",
1527		.data = &intel_lgm_sdxc_data,
1528	},
1529	{
1530		.compatible = "intel,keembay-sdhci-5.1-emmc",
1531		.data = &intel_keembay_emmc_data,
1532	},
1533	{
1534		.compatible = "intel,keembay-sdhci-5.1-sd",
1535		.data = &intel_keembay_sd_data,
1536	},
1537	{
1538		.compatible = "intel,keembay-sdhci-5.1-sdio",
1539		.data = &intel_keembay_sdio_data,
1540	},
1541	/* Generic compatible below here */
1542	{
1543		.compatible = "arasan,sdhci-8.9a",
1544		.data = &sdhci_arasan_generic_data,
1545	},
1546	{
1547		.compatible = "arasan,sdhci-5.1",
1548		.data = &sdhci_arasan_generic_data,
1549	},
1550	{
1551		.compatible = "arasan,sdhci-4.9a",
1552		.data = &sdhci_arasan_generic_data,
1553	},
1554	{
1555		.compatible = "xlnx,zynqmp-8.9a",
1556		.data = &sdhci_arasan_zynqmp_data,
1557	},
1558	{
1559		.compatible = "xlnx,versal-8.9a",
1560		.data = &sdhci_arasan_versal_data,
1561	},
1562	{
1563		.compatible = "xlnx,versal-net-emmc",
1564		.data = &sdhci_arasan_versal_net_data,
1565	},
1566	{ /* sentinel */ }
1567};
1568MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1569
1570/**
1571 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1572 *
1573 * @sdhci_arasan:	Our private data structure.
1574 * @clk_xin:		Pointer to the functional clock
1575 * @dev:		Pointer to our struct device.
1576 *
1577 * Some PHY devices need to know what the actual card clock is.  In order for
1578 * them to find out, we'll provide a clock through the common clock framework
1579 * for them to query.
1580 *
1581 * Return: 0 on success and error value on error
1582 */
1583static int
1584sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1585				struct clk *clk_xin,
1586				struct device *dev)
1587{
1588	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1589	struct device_node *np = dev->of_node;
1590	struct clk_init_data sdcardclk_init;
1591	const char *parent_clk_name;
1592	int ret;
1593
1594	ret = of_property_read_string_index(np, "clock-output-names", 0,
1595					    &sdcardclk_init.name);
1596	if (ret) {
1597		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1598		return ret;
1599	}
1600
1601	parent_clk_name = __clk_get_name(clk_xin);
1602	sdcardclk_init.parent_names = &parent_clk_name;
1603	sdcardclk_init.num_parents = 1;
1604	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1605	sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1606
1607	clk_data->sdcardclk_hw.init = &sdcardclk_init;
1608	clk_data->sdcardclk =
1609		devm_clk_register(dev, &clk_data->sdcardclk_hw);
1610	if (IS_ERR(clk_data->sdcardclk))
1611		return PTR_ERR(clk_data->sdcardclk);
1612	clk_data->sdcardclk_hw.init = NULL;
1613
1614	ret = of_clk_add_provider(np, of_clk_src_simple_get,
1615				  clk_data->sdcardclk);
1616	if (ret)
1617		dev_err(dev, "Failed to add sdcard clock provider\n");
1618
1619	return ret;
1620}
1621
1622/**
1623 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1624 *
1625 * @sdhci_arasan:	Our private data structure.
1626 * @clk_xin:		Pointer to the functional clock
1627 * @dev:		Pointer to our struct device.
1628 *
1629 * Some PHY devices need to know what the actual card clock is.  In order for
1630 * them to find out, we'll provide a clock through the common clock framework
1631 * for them to query.
1632 *
1633 * Return: 0 on success and error value on error
1634 */
1635static int
1636sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1637				struct clk *clk_xin,
1638				struct device *dev)
1639{
1640	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1641	struct device_node *np = dev->of_node;
1642	struct clk_init_data sampleclk_init;
1643	const char *parent_clk_name;
1644	int ret;
1645
1646	ret = of_property_read_string_index(np, "clock-output-names", 1,
1647					    &sampleclk_init.name);
1648	if (ret) {
1649		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1650		return ret;
1651	}
1652
1653	parent_clk_name = __clk_get_name(clk_xin);
1654	sampleclk_init.parent_names = &parent_clk_name;
1655	sampleclk_init.num_parents = 1;
1656	sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1657	sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1658
1659	clk_data->sampleclk_hw.init = &sampleclk_init;
1660	clk_data->sampleclk =
1661		devm_clk_register(dev, &clk_data->sampleclk_hw);
1662	if (IS_ERR(clk_data->sampleclk))
1663		return PTR_ERR(clk_data->sampleclk);
1664	clk_data->sampleclk_hw.init = NULL;
1665
1666	ret = of_clk_add_provider(np, of_clk_src_simple_get,
1667				  clk_data->sampleclk);
1668	if (ret)
1669		dev_err(dev, "Failed to add sample clock provider\n");
1670
1671	return ret;
1672}
1673
1674/**
1675 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1676 *
1677 * @dev:		Pointer to our struct device.
1678 *
1679 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1680 * returned success.
1681 */
1682static void sdhci_arasan_unregister_sdclk(struct device *dev)
1683{
1684	struct device_node *np = dev->of_node;
1685
1686	if (!of_property_present(np, "#clock-cells"))
1687		return;
1688
1689	of_clk_del_provider(dev->of_node);
1690}
1691
1692/**
1693 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1694 * @host:		The sdhci_host
1695 * @value:		The value to write
1696 *
1697 * This should be set based on the System Address Bus.
1698 * 0: the Core supports only 32-bit System Address Bus.
1699 * 1: the Core supports 64-bit System Address Bus.
1700 *
1701 * NOTE:
1702 * For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1703 * Keem Bay does not support 64-bit access.
1704 */
1705static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1706{
1707	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1708	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1709	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
1710
1711	/* Having a map is optional */
1712	soc_ctl_map = sdhci_arasan->soc_ctl_map;
1713	if (!soc_ctl_map)
1714		return;
1715
1716	/* If we have a map, we expect to have a syscon */
1717	if (!sdhci_arasan->soc_ctl_base) {
1718		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1719			mmc_hostname(host->mmc));
1720		return;
1721	}
1722
1723	sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1724}
1725
1726/**
1727 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1728 *
1729 * @sdhci_arasan:	Our private data structure.
1730 * @clk_xin:		Pointer to the functional clock
1731 * @dev:		Pointer to our struct device.
1732 *
1733 * Some PHY devices need to know what the actual card clock is.  In order for
1734 * them to find out, we'll provide a clock through the common clock framework
1735 * for them to query.
1736 *
1737 * Note: without seriously re-architecting SDHCI's clock code and testing on
1738 * all platforms, there's no way to create a totally beautiful clock here
1739 * with all clock ops implemented.  Instead, we'll just create a clock that can
1740 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1741 * framework that we're doing things behind its back.  This should be sufficient
1742 * to create nice clean device tree bindings and later (if needed) we can try
1743 * re-architecting SDHCI if we see some benefit to it.
1744 *
1745 * Return: 0 on success and error value on error
1746 */
1747static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1748				       struct clk *clk_xin,
1749				       struct device *dev)
1750{
1751	struct device_node *np = dev->of_node;
1752	u32 num_clks = 0;
1753	int ret;
1754
1755	/* Providing a clock to the PHY is optional; no error if missing */
1756	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1757		return 0;
1758
1759	ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1760	if (ret)
1761		return ret;
1762
1763	if (num_clks) {
1764		ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1765						      dev);
1766		if (ret) {
1767			sdhci_arasan_unregister_sdclk(dev);
1768			return ret;
1769		}
1770	}
1771
1772	return 0;
1773}
1774
1775static int sdhci_zynqmp_set_dynamic_config(struct device *dev,
1776					   struct sdhci_arasan_data *sdhci_arasan)
1777{
1778	struct sdhci_host *host = sdhci_arasan->host;
1779	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
1780	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1781	const char *clk_name = clk_hw_get_name(hw);
1782	u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
1783	struct reset_control *rstc;
1784	int ret;
1785
1786	/* Obtain SDHC reset control */
1787	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
1788	if (IS_ERR(rstc)) {
1789		dev_err(dev, "Cannot get SDHC reset.\n");
1790		return PTR_ERR(rstc);
1791	}
1792
1793	ret = reset_control_assert(rstc);
1794	if (ret)
1795		return ret;
1796
1797	ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_FIXED, 0);
1798	if (ret)
1799		return ret;
1800
1801	ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_EMMC_SEL,
1802				      !!(host->mmc->caps & MMC_CAP_NONREMOVABLE));
1803	if (ret)
1804		return ret;
1805
1806	mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1807	if (mhz > 100 && mhz <= 200)
1808		mhz = 200;
1809	else if (mhz > 50 && mhz <= 100)
1810		mhz = 100;
1811	else if (mhz > 25 && mhz <= 50)
1812		mhz = 50;
1813	else
1814		mhz = 25;
1815
1816	ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);
1817	if (ret)
1818		return ret;
1819
1820	ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_8BIT,
1821				      !!(host->mmc->caps & MMC_CAP_8_BIT_DATA));
1822	if (ret)
1823		return ret;
1824
1825	ret = reset_control_deassert(rstc);
1826	if (ret)
1827		return ret;
1828
1829	usleep_range(1000, 1500);
1830
1831	return 0;
1832}
1833
1834static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1835{
1836	struct sdhci_host *host = sdhci_arasan->host;
1837	struct cqhci_host *cq_host;
1838	bool dma64;
1839	int ret;
1840
1841	if (!sdhci_arasan->has_cqe)
1842		return sdhci_add_host(host);
1843
1844	ret = sdhci_setup_host(host);
1845	if (ret)
1846		return ret;
1847
1848	cq_host = devm_kzalloc(host->mmc->parent,
1849			       sizeof(*cq_host), GFP_KERNEL);
1850	if (!cq_host) {
1851		ret = -ENOMEM;
1852		goto cleanup;
1853	}
1854
1855	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1856	cq_host->ops = &sdhci_arasan_cqhci_ops;
1857
1858	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1859	if (dma64)
1860		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1861
1862	ret = cqhci_init(cq_host, host->mmc, dma64);
1863	if (ret)
1864		goto cleanup;
1865
1866	ret = __sdhci_add_host(host);
1867	if (ret)
1868		goto cleanup;
1869
1870	return 0;
1871
1872cleanup:
1873	sdhci_cleanup_host(host);
1874	return ret;
1875}
1876
1877static int sdhci_arasan_probe(struct platform_device *pdev)
1878{
1879	int ret;
1880	struct device_node *node;
1881	struct clk *clk_xin;
1882	struct clk *clk_dll;
1883	struct sdhci_host *host;
1884	struct sdhci_pltfm_host *pltfm_host;
1885	struct device *dev = &pdev->dev;
1886	struct device_node *np = dev->of_node;
1887	struct sdhci_arasan_data *sdhci_arasan;
1888	const struct sdhci_arasan_of_data *data;
1889
1890	data = of_device_get_match_data(dev);
1891	if (!data)
1892		return -EINVAL;
1893
1894	host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1895
1896	if (IS_ERR(host))
1897		return PTR_ERR(host);
1898
1899	pltfm_host = sdhci_priv(host);
1900	sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1901	sdhci_arasan->host = host;
1902
1903	sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1904	sdhci_arasan->clk_ops = data->clk_ops;
1905
1906	node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0);
1907	if (node) {
1908		sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1909		of_node_put(node);
1910
1911		if (IS_ERR(sdhci_arasan->soc_ctl_base))
1912			return dev_err_probe(dev,
1913					    PTR_ERR(sdhci_arasan->soc_ctl_base),
1914					    "Can't get syscon\n");
1915	}
1916
1917	sdhci_get_of_property(pdev);
1918
1919	sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
1920	if (IS_ERR(sdhci_arasan->clk_ahb))
1921		return dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
1922				    "clk_ahb clock not found.\n");
1923
1924	clk_xin = devm_clk_get(dev, "clk_xin");
1925	if (IS_ERR(clk_xin))
1926		return dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n");
1927
1928	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1929	if (ret)
1930		return dev_err_probe(dev, ret, "Unable to enable AHB clock.\n");
1931
1932	/* If clock-frequency property is set, use the provided value */
1933	if (pltfm_host->clock &&
1934	    pltfm_host->clock != clk_get_rate(clk_xin)) {
1935		ret = clk_set_rate(clk_xin, pltfm_host->clock);
1936		if (ret) {
1937			dev_err(&pdev->dev, "Failed to set SD clock rate\n");
1938			goto clk_dis_ahb;
1939		}
1940	}
1941
1942	ret = clk_prepare_enable(clk_xin);
1943	if (ret) {
1944		dev_err(dev, "Unable to enable SD clock.\n");
1945		goto clk_dis_ahb;
1946	}
1947
1948	clk_dll = devm_clk_get_optional_enabled(dev, "gate");
1949	if (IS_ERR(clk_dll)) {
1950		ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n");
1951		goto clk_disable_all;
1952	}
1953
1954	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1955		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1956
1957	if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1958		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1959
1960	pltfm_host->clk = clk_xin;
1961
1962	if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1"))
1963		sdhci_arasan_update_clockmultiplier(host, 0x0);
1964
1965	sdhci_arasan->quirks |= data->quirks;
1966
1967	if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1968	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1969	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
1970		sdhci_arasan_update_clockmultiplier(host, 0x0);
1971		sdhci_arasan_update_support64b(host, 0x0);
1972
1973		host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1974	}
1975
1976	sdhci_arasan_update_baseclkfreq(host);
1977
1978	ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev);
1979	if (ret)
1980		goto clk_disable_all;
1981
1982	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1983		host->mmc_host_ops.execute_tuning =
1984			arasan_zynqmp_execute_tuning;
1985
1986		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;
1987		host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
1988	}
1989
1990	arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data);
1991
1992	ret = mmc_of_parse(host->mmc);
1993	if (ret) {
1994		dev_err_probe(dev, ret, "parsing dt failed.\n");
1995		goto unreg_clk;
1996	}
1997
1998	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1999		ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG);
2000		if (!ret) {
2001			ret = sdhci_zynqmp_set_dynamic_config(dev, sdhci_arasan);
2002			if (ret)
2003				goto unreg_clk;
2004		}
2005	}
2006
2007	sdhci_arasan->phy = ERR_PTR(-ENODEV);
2008	if (of_device_is_compatible(np, "arasan,sdhci-5.1")) {
2009		sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan");
2010		if (IS_ERR(sdhci_arasan->phy)) {
2011			ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy),
2012					    "No phy for arasan,sdhci-5.1.\n");
2013			goto unreg_clk;
2014		}
2015
2016		ret = phy_init(sdhci_arasan->phy);
2017		if (ret < 0) {
2018			dev_err(dev, "phy_init err.\n");
2019			goto unreg_clk;
2020		}
2021
2022		host->mmc_host_ops.hs400_enhanced_strobe =
2023					sdhci_arasan_hs400_enhanced_strobe;
2024		host->mmc_host_ops.start_signal_voltage_switch =
2025					sdhci_arasan_voltage_switch;
2026		sdhci_arasan->has_cqe = true;
2027		host->mmc->caps2 |= MMC_CAP2_CQE;
2028
2029		if (!of_property_read_bool(np, "disable-cqe-dcmd"))
2030			host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
2031	}
2032
2033	if (of_device_is_compatible(np, "xlnx,versal-net-emmc"))
2034		sdhci_arasan->internal_phy_reg = true;
2035
2036	ret = sdhci_arasan_add_host(sdhci_arasan);
2037	if (ret)
2038		goto err_add_host;
2039
2040	return 0;
2041
2042err_add_host:
2043	if (!IS_ERR(sdhci_arasan->phy))
2044		phy_exit(sdhci_arasan->phy);
2045unreg_clk:
2046	sdhci_arasan_unregister_sdclk(dev);
2047clk_disable_all:
2048	clk_disable_unprepare(clk_xin);
2049clk_dis_ahb:
2050	clk_disable_unprepare(sdhci_arasan->clk_ahb);
2051	return ret;
2052}
2053
2054static void sdhci_arasan_remove(struct platform_device *pdev)
2055{
2056	struct sdhci_host *host = platform_get_drvdata(pdev);
2057	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2058	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
2059	struct clk *clk_ahb = sdhci_arasan->clk_ahb;
2060	struct clk *clk_xin = pltfm_host->clk;
2061
2062	if (!IS_ERR(sdhci_arasan->phy)) {
2063		if (sdhci_arasan->is_phy_on)
2064			phy_power_off(sdhci_arasan->phy);
2065		phy_exit(sdhci_arasan->phy);
2066	}
2067
2068	sdhci_arasan_unregister_sdclk(&pdev->dev);
2069
2070	sdhci_pltfm_remove(pdev);
2071
2072	clk_disable_unprepare(clk_xin);
2073	clk_disable_unprepare(clk_ahb);
2074}
2075
2076static struct platform_driver sdhci_arasan_driver = {
2077	.driver = {
2078		.name = "sdhci-arasan",
2079		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
2080		.of_match_table = sdhci_arasan_of_match,
2081		.pm = pm_sleep_ptr(&sdhci_arasan_dev_pm_ops),
2082	},
2083	.probe = sdhci_arasan_probe,
2084	.remove = sdhci_arasan_remove,
2085};
2086
2087module_platform_driver(sdhci_arasan_driver);
2088
2089MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
2090MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
2091MODULE_LICENSE("GPL");