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sdhci-esdhc-imx.c
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linux-6.19.14/drivers/mmc/host/sdhci-esdhc-imx.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Freescale eSDHC i.MX controller driver for the platform bus. 4 * 5 * derived from the OF-version. 6 * 7 * Copyright (c) 2010 Pengutronix e.K. 8 * Author: Wolfram Sang <kernel@pengutronix.de> 9 */ 10 11#include <linux/bitfield.h> 12#include <linux/io.h> 13#include <linux/iopoll.h> 14#include <linux/delay.h> 15#include <linux/err.h> 16#include <linux/clk.h> 17#include <linux/module.h> 18#include <linux/slab.h> 19#include <linux/pm_qos.h> 20#include <linux/mmc/host.h> 21#include <linux/mmc/mmc.h> 22#include <linux/mmc/sdio.h> 23#include <linux/mmc/slot-gpio.h> 24#include <linux/of.h> 25#include <linux/platform_device.h> 26#include <linux/pinctrl/consumer.h> 27#include <linux/pm_runtime.h> 28#include "sdhci-cqhci.h" 29#include "sdhci-pltfm.h" 30#include "sdhci-esdhc.h" 31#include "cqhci.h" 32 33#define ESDHC_SYS_CTRL_DTOCV_MASK GENMASK(19, 16) 34#define ESDHC_SYS_CTRL_RST_FIFO BIT(22) 35#define ESDHC_SYS_CTRL_IPP_RST_N BIT(23) 36#define ESDHC_SYS_CTRL_RESET_TUNING BIT(28) 37#define ESDHC_CTRL_D3CD 0x08 38#define ESDHC_BURST_LEN_EN_INCR (1 << 27) 39/* VENDOR SPEC register */ 40#define ESDHC_VENDOR_SPEC 0xc0 41#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 42#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 43#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 44#define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2 45#define ESDHC_DEBUG_SEL_REG 0xc3 46#define ESDHC_DEBUG_SEL_MASK 0xf 47#define ESDHC_DEBUG_SEL_CMD_STATE 1 48#define ESDHC_DEBUG_SEL_DATA_STATE 2 49#define ESDHC_DEBUG_SEL_TRANS_STATE 3 50#define ESDHC_DEBUG_SEL_DMA_STATE 4 51#define ESDHC_DEBUG_SEL_ADMA_STATE 5 52#define ESDHC_DEBUG_SEL_FIFO_STATE 6 53#define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7 54#define ESDHC_WTMK_LVL 0x44 55#define ESDHC_WTMK_DEFAULT_VAL 0x10401040 56#define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 57#define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 58#define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 59#define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 60#define ESDHC_WTMK_LVL_WML_VAL_DEF 64 61#define ESDHC_WTMK_LVL_WML_VAL_MAX 128 62#define ESDHC_MIX_CTRL 0x48 63#define ESDHC_MIX_CTRL_DDREN (1 << 3) 64#define ESDHC_MIX_CTRL_AC23EN (1 << 7) 65#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 66#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 67#define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 68#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 69#define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 70#define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 71/* Bits 3 and 6 are not SDHCI standard definitions */ 72#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 73/* Tuning bits */ 74#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 75 76/* dll control register */ 77#define ESDHC_DLL_CTRL 0x60 78#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 79#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 80 81/* tune control register */ 82#define ESDHC_TUNE_CTRL_STATUS 0x68 83#define ESDHC_TUNE_CTRL_STEP 1 84#define ESDHC_TUNE_CTRL_MIN 0 85#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 86#define ESDHC_TUNE_CTRL_STATUS_TAP_SEL_MASK GENMASK(30, 16) 87#define ESDHC_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK GENMASK(30, 24) 88#define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK GENMASK(14, 8) 89#define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK GENMASK(7, 4) 90#define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK GENMASK(3, 0) 91/* strobe dll register */ 92#define ESDHC_STROBE_DLL_CTRL 0x70 93#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 94#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 95#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 96#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 97#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 98 99#define ESDHC_STROBE_DLL_STATUS 0x74 100#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 101#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 102 103#define ESDHC_VEND_SPEC2 0xc8 104#define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 105#define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN (1 << 4) 106#define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN (0 << 4) 107#define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN (2 << 4) 108#define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN (1 << 6) 109#define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK (7 << 4) 110 111#define ESDHC_TUNING_CTRL 0xcc 112#define ESDHC_STD_TUNING_EN (1 << 24) 113#define ESDHC_TUNING_WINDOW_MASK GENMASK(22, 20) 114/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 115#define ESDHC_TUNING_START_TAP_DEFAULT 0x1 116#define ESDHC_TUNING_START_TAP_MASK 0x7f 117#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) 118#define ESDHC_TUNING_STEP_DEFAULT 0x1 119#define ESDHC_TUNING_STEP_MASK 0x00070000 120#define ESDHC_TUNING_STEP_SHIFT 16 121 122/* pinctrl state */ 123#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 124#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 125 126/* 127 * Our interpretation of the SDHCI_HOST_CONTROL register 128 */ 129#define ESDHC_CTRL_4BITBUS (0x1 << 1) 130#define ESDHC_CTRL_8BITBUS (0x2 << 1) 131#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 132#define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK) 133 134/* 135 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 136 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 137 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 138 * Define this macro DMA error INT for fsl eSDHC 139 */ 140#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 141 142/* the address offset of CQHCI */ 143#define ESDHC_CQHCI_ADDR_OFFSET 0x100 144 145/* 146 * The CMDTYPE of the CMD register (offset 0xE) should be set to 147 * "11" when the STOP CMD12 is issued on imx53 to abort one 148 * open ended multi-blk IO. Otherwise the TC INT wouldn't 149 * be generated. 150 * In exact block transfer, the controller doesn't complete the 151 * operations automatically as required at the end of the 152 * transfer and remains on hold if the abort command is not sent. 153 * As a result, the TC flag is not asserted and SW received timeout 154 * exception. Bit1 of Vendor Spec register is used to fix it. 155 */ 156#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 157/* 158 * The flag tells that the ESDHC controller is an USDHC block that is 159 * integrated on the i.MX6 series. 160 */ 161#define ESDHC_FLAG_USDHC BIT(3) 162/* The IP supports manual tuning process */ 163#define ESDHC_FLAG_MAN_TUNING BIT(4) 164/* The IP supports standard tuning process */ 165#define ESDHC_FLAG_STD_TUNING BIT(5) 166/* The IP has SDHCI_CAPABILITIES_1 register */ 167#define ESDHC_FLAG_HAVE_CAP1 BIT(6) 168/* 169 * The IP has erratum ERR004536 170 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 171 * when reading data from the card 172 * This flag is also set for i.MX25 and i.MX35 in order to get 173 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 174 */ 175#define ESDHC_FLAG_ERR004536 BIT(7) 176/* The IP supports HS200 mode */ 177#define ESDHC_FLAG_HS200 BIT(8) 178/* The IP supports HS400 mode */ 179#define ESDHC_FLAG_HS400 BIT(9) 180/* 181 * The IP has errata ERR010450 182 * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card 183 * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 184 */ 185#define ESDHC_FLAG_ERR010450 BIT(10) 186/* The IP supports HS400ES mode */ 187#define ESDHC_FLAG_HS400_ES BIT(11) 188/* The IP has Host Controller Interface for Command Queuing */ 189#define ESDHC_FLAG_CQHCI BIT(12) 190/* need request pmqos during low power */ 191#define ESDHC_FLAG_PMQOS BIT(13) 192/* The IP state got lost in low power mode */ 193#define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) 194/* The IP lost clock rate in PM_RUNTIME */ 195#define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) 196/* 197 * The IP do not support the ACMD23 feature completely when use ADMA mode. 198 * In ADMA mode, it only use the 16 bit block count of the register 0x4 199 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will 200 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable 201 * write operation in RPMB, because RPMB reliable write need to set the bit31 202 * of the CMD23's argument. 203 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA 204 * do not has this limitation. so when these SoC use ADMA mode, it need to 205 * disable the ACMD23 feature. 206 */ 207#define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16) 208 209/* ERR004536 is not applicable for the IP */ 210#define ESDHC_FLAG_SKIP_ERR004536 BIT(17) 211 212/* The IP does not have GPIO CD wake capabilities */ 213#define ESDHC_FLAG_SKIP_CD_WAKE BIT(18) 214 215/* the controller has dummy pad for clock loopback */ 216#define ESDHC_FLAG_DUMMY_PAD BIT(19) 217 218#define ESDHC_AUTO_TUNING_WINDOW 3 219 220enum wp_types { 221 ESDHC_WP_NONE, /* no WP, neither controller nor gpio */ 222 ESDHC_WP_CONTROLLER, /* mmc controller internal WP */ 223 ESDHC_WP_GPIO, /* external gpio pin for WP */ 224}; 225 226enum cd_types { 227 ESDHC_CD_NONE, /* no CD, neither controller nor gpio */ 228 ESDHC_CD_CONTROLLER, /* mmc controller internal CD */ 229 ESDHC_CD_GPIO, /* external gpio pin for CD */ 230 ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */ 231}; 232 233/* 234 * struct esdhc_platform_data - platform data for esdhc on i.MX 235 * 236 * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35. 237 * 238 * @wp_type: type of write_protect method (see wp_types enum above) 239 * @cd_type: type of card_detect method (see cd_types enum above) 240 */ 241 242struct esdhc_platform_data { 243 enum wp_types wp_type; 244 enum cd_types cd_type; 245 int max_bus_width; 246 unsigned int delay_line; 247 unsigned int tuning_step; /* The delay cell steps in tuning procedure */ 248 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */ 249 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ 250 unsigned int saved_tuning_delay_cell; /* save the value of tuning delay cell */ 251 unsigned int saved_auto_tuning_window; /* save the auto tuning window width */ 252}; 253 254struct esdhc_soc_data { 255 u32 flags; 256 u32 quirks; 257}; 258 259static const struct esdhc_soc_data esdhc_imx25_data = { 260 .flags = ESDHC_FLAG_ERR004536, 261}; 262 263static const struct esdhc_soc_data esdhc_imx35_data = { 264 .flags = ESDHC_FLAG_ERR004536, 265}; 266 267static const struct esdhc_soc_data esdhc_imx51_data = { 268 .flags = 0, 269}; 270 271static const struct esdhc_soc_data esdhc_imx53_data = { 272 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 273}; 274 275static const struct esdhc_soc_data usdhc_imx6q_data = { 276 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 277 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 278}; 279 280static const struct esdhc_soc_data usdhc_imx6sl_data = { 281 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 282 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 283 | ESDHC_FLAG_HS200 284 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 285}; 286 287static const struct esdhc_soc_data usdhc_imx6sll_data = { 288 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 289 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 290 | ESDHC_FLAG_HS400 291 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 292}; 293 294static const struct esdhc_soc_data usdhc_imx6sx_data = { 295 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 296 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 297 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 298 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 299}; 300 301static const struct esdhc_soc_data usdhc_imx6ull_data = { 302 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 303 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 304 | ESDHC_FLAG_ERR010450 305 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 306}; 307 308static const struct esdhc_soc_data usdhc_imx7d_data = { 309 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 310 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 311 | ESDHC_FLAG_HS400 312 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 313 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 314}; 315 316static struct esdhc_soc_data usdhc_s32g2_data = { 317 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 318 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 319 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 320 | ESDHC_FLAG_SKIP_ERR004536 | ESDHC_FLAG_SKIP_CD_WAKE, 321 .quirks = SDHCI_QUIRK_NO_LED, 322}; 323 324static struct esdhc_soc_data usdhc_imx7ulp_data = { 325 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 326 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 327 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400 328 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 329 .quirks = SDHCI_QUIRK_NO_LED, 330}; 331static struct esdhc_soc_data usdhc_imxrt1050_data = { 332 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 333 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 334 .quirks = SDHCI_QUIRK_NO_LED, 335}; 336 337static struct esdhc_soc_data usdhc_imx8qxp_data = { 338 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 339 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 340 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 341 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 342 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME, 343 .quirks = SDHCI_QUIRK_NO_LED, 344}; 345 346static struct esdhc_soc_data usdhc_imx8mm_data = { 347 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 348 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 349 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 350 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 351 .quirks = SDHCI_QUIRK_NO_LED, 352}; 353 354static struct esdhc_soc_data usdhc_imx95_data = { 355 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 356 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 357 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 358 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 359 | ESDHC_FLAG_DUMMY_PAD, 360 .quirks = SDHCI_QUIRK_NO_LED, 361}; 362 363struct pltfm_imx_data { 364 u32 scratchpad; 365 struct pinctrl *pinctrl; 366 struct pinctrl_state *pins_100mhz; 367 struct pinctrl_state *pins_200mhz; 368 const struct esdhc_soc_data *socdata; 369 struct esdhc_platform_data boarddata; 370 struct clk *clk_ipg; 371 struct clk *clk_ahb; 372 struct clk *clk_per; 373 unsigned int actual_clock; 374 375 /* 376 * USDHC has one limition, require the SDIO device a different 377 * register setting. Driver has to recognize card type during 378 * the card init, but at this stage, mmc_host->card is not 379 * available. So involve this field to save the card type 380 * during card init through usdhc_init_card(). 381 */ 382 unsigned int init_card_type; 383 384 enum { 385 NO_CMD_PENDING, /* no multiblock command pending */ 386 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 387 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 388 } multiblock_status; 389 u32 is_ddr; 390 struct pm_qos_request pm_qos_req; 391}; 392 393static const struct of_device_id imx_esdhc_dt_ids[] = { 394 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 395 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 396 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 397 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 398 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 399 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 400 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, }, 401 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 402 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 403 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 404 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 405 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 406 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, }, 407 { .compatible = "fsl,imx94-usdhc", .data = &usdhc_imx95_data, }, 408 { .compatible = "fsl,imx95-usdhc", .data = &usdhc_imx95_data, }, 409 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, }, 410 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, }, 411 { /* sentinel */ } 412}; 413MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 414 415static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 416{ 417 return data->socdata == &esdhc_imx25_data; 418} 419 420static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 421{ 422 return data->socdata == &esdhc_imx53_data; 423} 424 425static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 426{ 427 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 428} 429 430static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 431{ 432 void __iomem *base = host->ioaddr + (reg & ~0x3); 433 u32 shift = (reg & 0x3) * 8; 434 435 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 436} 437 438#define DRIVER_NAME "sdhci-esdhc-imx" 439#define ESDHC_IMX_DUMP(f, x...) \ 440 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 441static void esdhc_dump_debug_regs(struct sdhci_host *host) 442{ 443 int i; 444 char *debug_status[7] = { 445 "cmd debug status", 446 "data debug status", 447 "trans debug status", 448 "dma debug status", 449 "adma debug status", 450 "fifo debug status", 451 "async fifo debug status" 452 }; 453 454 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n"); 455 for (i = 0; i < 7; i++) { 456 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 457 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG); 458 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i], 459 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); 460 } 461 462 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG); 463 464} 465 466static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host) 467{ 468 u32 present_state; 469 int ret; 470 471 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, 472 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100); 473 if (ret == -ETIMEDOUT) 474 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); 475} 476 477/* Enable the auto tuning circuit to check the CMD line and BUS line */ 478static inline void usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host *host) 479{ 480 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 481 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 482 u32 buswidth, auto_tune_buswidth; 483 u32 reg; 484 485 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL)); 486 487 switch (buswidth) { 488 case ESDHC_CTRL_8BITBUS: 489 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN; 490 break; 491 case ESDHC_CTRL_4BITBUS: 492 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN; 493 break; 494 default: /* 1BITBUS */ 495 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN; 496 break; 497 } 498 499 /* 500 * For USDHC, auto tuning circuit can not handle the async sdio 501 * device interrupt correctly. When sdio device use 4 data lines, 502 * async sdio interrupt will use the shared DAT[1], if enable auto 503 * tuning circuit check these 4 data lines, include the DAT[1], 504 * this circuit will detect this interrupt, take this as a data on 505 * DAT[1], and adjust the delay cell wrongly. 506 * This is the hardware design limitation, to avoid this, for sdio 507 * device, config the auto tuning circuit only check DAT[0] and CMD 508 * line. 509 */ 510 if (imx_data->init_card_type == MMC_TYPE_SDIO) 511 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN; 512 513 esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK, 514 auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN, 515 ESDHC_VEND_SPEC2); 516 517 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 518 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 519 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 520} 521 522static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 523{ 524 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 525 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 526 u32 val = readl(host->ioaddr + reg); 527 528 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 529 u32 fsl_prss = val; 530 /* save the least 20 bits */ 531 val = fsl_prss & 0x000FFFFF; 532 /* move dat[0-3] bits */ 533 val |= (fsl_prss & 0x0F000000) >> 4; 534 /* move cmd line bit */ 535 val |= (fsl_prss & 0x00800000) << 1; 536 } 537 538 if (unlikely(reg == SDHCI_CAPABILITIES)) { 539 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 540 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 541 val &= 0xffff0000; 542 543 /* In FSL esdhc IC module, only bit20 is used to indicate the 544 * ADMA2 capability of esdhc, but this bit is messed up on 545 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 546 * don't actually support ADMA2). So set the BROKEN_ADMA 547 * quirk on MX25/35 platforms. 548 */ 549 550 if (val & SDHCI_CAN_DO_ADMA1) { 551 val &= ~SDHCI_CAN_DO_ADMA1; 552 val |= SDHCI_CAN_DO_ADMA2; 553 } 554 } 555 556 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 557 if (esdhc_is_usdhc(imx_data)) { 558 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 559 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 560 else 561 /* imx6q/dl does not have cap_1 register, fake one */ 562 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 563 | SDHCI_SUPPORT_SDR50 564 | SDHCI_USE_SDR50_TUNING 565 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK, 566 SDHCI_TUNING_MODE_3); 567 568 /* 569 * Do not advertise faster UHS modes if there are no 570 * pinctrl states for 100MHz/200MHz. 571 */ 572 if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) 573 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); 574 if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) 575 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 576 } 577 } 578 579 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 580 val = 0; 581 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF); 582 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF); 583 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF); 584 } 585 586 if (unlikely(reg == SDHCI_INT_STATUS)) { 587 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 588 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 589 val |= SDHCI_INT_ADMA_ERROR; 590 } 591 592 /* 593 * mask off the interrupt we get in response to the manually 594 * sent CMD12 595 */ 596 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 597 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 598 val &= ~SDHCI_INT_RESPONSE; 599 writel(SDHCI_INT_RESPONSE, host->ioaddr + 600 SDHCI_INT_STATUS); 601 imx_data->multiblock_status = NO_CMD_PENDING; 602 } 603 } 604 605 return val; 606} 607 608static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 609{ 610 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 611 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 612 u32 data; 613 614 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 615 reg == SDHCI_INT_STATUS)) { 616 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 617 /* 618 * Clear and then set D3CD bit to avoid missing the 619 * card interrupt. This is an eSDHC controller problem 620 * so we need to apply the following workaround: clear 621 * and set D3CD bit will make eSDHC re-sample the card 622 * interrupt. In case a card interrupt was lost, 623 * re-sample it by the following steps. 624 */ 625 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 626 data &= ~ESDHC_CTRL_D3CD; 627 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 628 data |= ESDHC_CTRL_D3CD; 629 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 630 } 631 632 if (val & SDHCI_INT_ADMA_ERROR) { 633 val &= ~SDHCI_INT_ADMA_ERROR; 634 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 635 } 636 } 637 638 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 639 && (reg == SDHCI_INT_STATUS) 640 && (val & SDHCI_INT_DATA_END))) { 641 u32 v; 642 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 643 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 644 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 645 646 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 647 { 648 /* send a manual CMD12 with RESPTYP=none */ 649 data = MMC_STOP_TRANSMISSION << 24 | 650 SDHCI_CMD_ABORTCMD << 16; 651 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 652 imx_data->multiblock_status = WAIT_FOR_INT; 653 } 654 } 655 656 writel(val, host->ioaddr + reg); 657} 658 659static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 660{ 661 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 662 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 663 u16 ret = 0; 664 u32 val; 665 666 if (unlikely(reg == SDHCI_HOST_VERSION)) { 667 reg ^= 2; 668 if (esdhc_is_usdhc(imx_data)) { 669 /* 670 * The usdhc register returns a wrong host version. 671 * Correct it here. 672 */ 673 return SDHCI_SPEC_300; 674 } 675 } 676 677 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 678 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 679 if (val & ESDHC_VENDOR_SPEC_VSELECT) 680 ret |= SDHCI_CTRL_VDD_180; 681 682 if (esdhc_is_usdhc(imx_data)) { 683 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 684 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 685 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 686 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 687 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 688 } 689 690 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 691 ret |= SDHCI_CTRL_EXEC_TUNING; 692 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 693 ret |= SDHCI_CTRL_TUNED_CLK; 694 695 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 696 697 return ret; 698 } 699 700 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 701 if (esdhc_is_usdhc(imx_data)) { 702 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 703 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 704 /* Swap AC23 bit */ 705 if (m & ESDHC_MIX_CTRL_AC23EN) { 706 ret &= ~ESDHC_MIX_CTRL_AC23EN; 707 ret |= SDHCI_TRNS_AUTO_CMD23; 708 } 709 } else { 710 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 711 } 712 713 return ret; 714 } 715 716 return readw(host->ioaddr + reg); 717} 718 719static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 720{ 721 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 722 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 723 u32 new_val = 0; 724 725 switch (reg) { 726 case SDHCI_CLOCK_CONTROL: 727 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 728 if (val & SDHCI_CLOCK_CARD_EN) 729 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 730 else 731 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 732 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 733 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON)) 734 esdhc_wait_for_card_clock_gate_off(host); 735 return; 736 case SDHCI_HOST_CONTROL2: 737 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 738 if (val & SDHCI_CTRL_VDD_180) 739 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 740 else 741 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 742 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 743 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 744 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 745 if (val & SDHCI_CTRL_TUNED_CLK) 746 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 747 else 748 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 749 750 if (val & SDHCI_CTRL_EXEC_TUNING) 751 v |= ESDHC_MIX_CTRL_EXE_TUNE; 752 else 753 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 754 755 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 756 } 757 return; 758 case SDHCI_TRANSFER_MODE: 759 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 760 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 761 && (host->cmd->data->blocks > 1) 762 && (host->cmd->data->flags & MMC_DATA_READ)) { 763 u32 v; 764 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 765 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 766 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 767 } 768 769 if (esdhc_is_usdhc(imx_data)) { 770 u32 wml; 771 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 772 /* Swap AC23 bit */ 773 if (val & SDHCI_TRNS_AUTO_CMD23) { 774 val &= ~SDHCI_TRNS_AUTO_CMD23; 775 val |= ESDHC_MIX_CTRL_AC23EN; 776 } 777 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 778 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 779 780 /* Set watermark levels for PIO access to maximum value 781 * (128 words) to accommodate full 512 bytes buffer. 782 * For DMA access restore the levels to default value. 783 */ 784 m = readl(host->ioaddr + ESDHC_WTMK_LVL); 785 if (val & SDHCI_TRNS_DMA) { 786 wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 787 } else { 788 u8 ctrl; 789 wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 790 791 /* 792 * Since already disable DMA mode, so also need 793 * to clear the DMASEL. Otherwise, for standard 794 * tuning, when send tuning command, usdhc will 795 * still prefetch the ADMA script from wrong 796 * DMA address, then we will see IOMMU report 797 * some error which show lack of TLB mapping. 798 */ 799 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 800 ctrl &= ~SDHCI_CTRL_DMA_MASK; 801 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 802 } 803 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 804 ESDHC_WTMK_LVL_WR_WML_MASK); 805 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 806 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 807 writel(m, host->ioaddr + ESDHC_WTMK_LVL); 808 } else { 809 /* 810 * Postpone this write, we must do it together with a 811 * command write that is down below. 812 */ 813 imx_data->scratchpad = val; 814 } 815 return; 816 case SDHCI_COMMAND: 817 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 818 val |= SDHCI_CMD_ABORTCMD; 819 820 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 821 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 822 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 823 824 if (esdhc_is_usdhc(imx_data)) 825 writel(val << 16, 826 host->ioaddr + SDHCI_TRANSFER_MODE); 827 else 828 writel(val << 16 | imx_data->scratchpad, 829 host->ioaddr + SDHCI_TRANSFER_MODE); 830 return; 831 case SDHCI_BLOCK_SIZE: 832 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 833 break; 834 } 835 esdhc_clrset_le(host, 0xffff, val, reg); 836} 837 838static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 839{ 840 u8 ret; 841 u32 val; 842 843 switch (reg) { 844 case SDHCI_HOST_CONTROL: 845 val = readl(host->ioaddr + reg); 846 847 ret = val & SDHCI_CTRL_LED; 848 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 849 ret |= (val & ESDHC_CTRL_4BITBUS); 850 ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 851 return ret; 852 } 853 854 return readb(host->ioaddr + reg); 855} 856 857static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 858{ 859 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 860 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 861 u32 new_val = 0; 862 u32 mask; 863 864 switch (reg) { 865 case SDHCI_POWER_CONTROL: 866 /* 867 * FSL put some DMA bits here 868 * If your board has a regulator, code should be here 869 */ 870 return; 871 case SDHCI_HOST_CONTROL: 872 /* FSL messed up here, so we need to manually compose it. */ 873 new_val = val & SDHCI_CTRL_LED; 874 /* ensure the endianness */ 875 new_val |= ESDHC_HOST_CONTROL_LE; 876 /* bits 8&9 are reserved on mx25 */ 877 if (!is_imx25_esdhc(imx_data)) { 878 /* DMA mode bits are shifted */ 879 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 880 } 881 882 /* 883 * Do not touch buswidth bits here. This is done in 884 * esdhc_pltfm_bus_width. 885 * Do not touch the D3CD bit either which is used for the 886 * SDIO interrupt erratum workaround. 887 */ 888 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 889 890 esdhc_clrset_le(host, mask, new_val, reg); 891 return; 892 case SDHCI_TIMEOUT_CONTROL: 893 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 894 FIELD_PREP(ESDHC_SYS_CTRL_DTOCV_MASK, val), 895 ESDHC_SYSTEM_CONTROL); 896 return; 897 case SDHCI_SOFTWARE_RESET: 898 if (val & SDHCI_RESET_DATA) 899 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 900 break; 901 } 902 esdhc_clrset_le(host, 0xff, val, reg); 903 904 if (reg == SDHCI_SOFTWARE_RESET) { 905 if (val & SDHCI_RESET_ALL) { 906 /* 907 * The esdhc has a design violation to SDHC spec which 908 * tells that software reset should not affect card 909 * detection circuit. But esdhc clears its SYSCTL 910 * register bits [0..2] during the software reset. This 911 * will stop those clocks that card detection circuit 912 * relies on. To work around it, we turn the clocks on 913 * back to keep card detection circuit functional. 914 */ 915 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 916 /* 917 * The reset on usdhc fails to clear MIX_CTRL register. 918 * Do it manually here. 919 */ 920 if (esdhc_is_usdhc(imx_data)) { 921 /* 922 * the tuning bits should be kept during reset 923 */ 924 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 925 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 926 host->ioaddr + ESDHC_MIX_CTRL); 927 imx_data->is_ddr = 0; 928 } 929 } else if (val & SDHCI_RESET_DATA) { 930 /* 931 * The eSDHC DAT line software reset clears at least the 932 * data transfer width on i.MX25, so make sure that the 933 * Host Control register is unaffected. 934 */ 935 esdhc_clrset_le(host, 0xff, new_val, 936 SDHCI_HOST_CONTROL); 937 } 938 } 939} 940 941static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 942{ 943 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 944 945 return pltfm_host->clock; 946} 947 948static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 949{ 950 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 951 952 return pltfm_host->clock / 256 / 16; 953} 954 955static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 956 unsigned int clock) 957{ 958 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 959 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 960 unsigned int host_clock = pltfm_host->clock; 961 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 962 int pre_div = 1; 963 int div = 1; 964 int ret; 965 u32 temp, val; 966 967 if (esdhc_is_usdhc(imx_data)) { 968 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 969 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 970 host->ioaddr + ESDHC_VENDOR_SPEC); 971 esdhc_wait_for_card_clock_gate_off(host); 972 } 973 974 if (clock == 0) { 975 host->mmc->actual_clock = 0; 976 return; 977 } 978 979 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 980 if (is_imx53_esdhc(imx_data)) { 981 /* 982 * According to the i.MX53 reference manual, if DLLCTRL[10] can 983 * be set, then the controller is eSDHCv3, else it is eSDHCv2. 984 */ 985 val = readl(host->ioaddr + ESDHC_DLL_CTRL); 986 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 987 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 988 writel(val, host->ioaddr + ESDHC_DLL_CTRL); 989 if (temp & BIT(10)) 990 pre_div = 2; 991 } 992 993 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 994 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 995 | ESDHC_CLOCK_MASK); 996 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 997 998 if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) && 999 (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) { 1000 unsigned int max_clock; 1001 1002 max_clock = imx_data->is_ddr ? 45000000 : 150000000; 1003 1004 clock = min(clock, max_clock); 1005 } 1006 1007 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 1008 pre_div < 256) 1009 pre_div *= 2; 1010 1011 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 1012 div++; 1013 1014 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 1015 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 1016 clock, host->mmc->actual_clock); 1017 1018 pre_div >>= 1; 1019 div--; 1020 1021 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 1022 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 1023 | (div << ESDHC_DIVIDER_SHIFT) 1024 | (pre_div << ESDHC_PREDIV_SHIFT)); 1025 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 1026 1027 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */ 1028 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, 1029 (temp & ESDHC_CLOCK_STABLE), 2, 100); 1030 if (ret == -ETIMEDOUT) 1031 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); 1032 1033 if (esdhc_is_usdhc(imx_data)) { 1034 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 1035 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 1036 host->ioaddr + ESDHC_VENDOR_SPEC); 1037 } 1038 1039} 1040 1041static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 1042{ 1043 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1044 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1045 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1046 1047 switch (boarddata->wp_type) { 1048 case ESDHC_WP_GPIO: 1049 return mmc_gpio_get_ro(host->mmc); 1050 case ESDHC_WP_CONTROLLER: 1051 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 1052 SDHCI_WRITE_PROTECT); 1053 case ESDHC_WP_NONE: 1054 break; 1055 } 1056 1057 return -ENOSYS; 1058} 1059 1060static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 1061{ 1062 u32 ctrl; 1063 1064 switch (width) { 1065 case MMC_BUS_WIDTH_8: 1066 ctrl = ESDHC_CTRL_8BITBUS; 1067 break; 1068 case MMC_BUS_WIDTH_4: 1069 ctrl = ESDHC_CTRL_4BITBUS; 1070 break; 1071 default: 1072 ctrl = 0; 1073 break; 1074 } 1075 1076 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 1077 SDHCI_HOST_CONTROL); 1078} 1079 1080static void esdhc_reset_tuning(struct sdhci_host *host) 1081{ 1082 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1083 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1084 u32 ctrl, tuning_ctrl, sys_ctrl; 1085 int ret; 1086 1087 /* Reset the tuning circuit */ 1088 if (esdhc_is_usdhc(imx_data)) { 1089 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1090 ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 1091 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1092 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1093 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1094 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1095 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1096 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1097 /* 1098 * enable the std tuning just in case it cleared in 1099 * sdhc_esdhc_tuning_restore. 1100 */ 1101 tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1102 if (!(tuning_ctrl & ESDHC_STD_TUNING_EN)) { 1103 tuning_ctrl |= ESDHC_STD_TUNING_EN; 1104 writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL); 1105 } 1106 1107 /* set the reset tuning bit */ 1108 sys_ctrl = readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); 1109 sys_ctrl |= ESDHC_SYS_CTRL_RESET_TUNING; 1110 writel(sys_ctrl, host->ioaddr + ESDHC_SYSTEM_CONTROL); 1111 1112 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1113 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1114 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1115 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1116 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ 1117 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, 1118 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); 1119 if (ret == -ETIMEDOUT) 1120 dev_warn(mmc_dev(host->mmc), 1121 "Warning! clear execute tuning bit failed\n"); 1122 /* 1123 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the 1124 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which 1125 * will finally make sure the normal data transfer logic correct. 1126 */ 1127 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); 1128 ctrl |= SDHCI_INT_DATA_AVAIL; 1129 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); 1130 } 1131 } 1132} 1133 1134static void usdhc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1135{ 1136 struct sdhci_host *host = mmc_priv(mmc); 1137 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1138 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1139 1140 imx_data->init_card_type = card->type; 1141} 1142 1143static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1144{ 1145 struct sdhci_host *host = mmc_priv(mmc); 1146 int err; 1147 1148 /* 1149 * i.MX uSDHC internally already uses a fixed optimized timing for 1150 * DDR50, normally does not require tuning for DDR50 mode. 1151 */ 1152 if (host->timing == MMC_TIMING_UHS_DDR50) 1153 return 0; 1154 1155 /* 1156 * Reset tuning circuit logic. If not, the previous tuning result 1157 * will impact current tuning, make current tuning can't set the 1158 * correct delay cell. 1159 */ 1160 esdhc_reset_tuning(host); 1161 err = sdhci_execute_tuning(mmc, opcode); 1162 /* If tuning done, enable auto tuning */ 1163 if (!err && !host->tuning_err) 1164 usdhc_auto_tuning_mode_sel_and_en(host); 1165 1166 return err; 1167} 1168 1169static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 1170{ 1171 u32 reg, sys_ctrl; 1172 u8 sw_rst; 1173 int ret; 1174 1175 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 1176 mdelay(1); 1177 1178 /* IC suggest to reset USDHC before every tuning command */ 1179 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET); 1180 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, 1181 !(sw_rst & SDHCI_RESET_ALL), 10, 100); 1182 if (ret == -ETIMEDOUT) 1183 dev_warn(mmc_dev(host->mmc), 1184 "warning! RESET_ALL never complete before sending tuning command\n"); 1185 1186 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1187 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL; 1188 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1189 writel(FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK, val), 1190 host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1191 dev_dbg(mmc_dev(host->mmc), 1192 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 1193 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 1194 1195 /* set RST_FIFO to reset the async FIFO, and wat it to self-clear */ 1196 sys_ctrl = readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); 1197 sys_ctrl |= ESDHC_SYS_CTRL_RST_FIFO; 1198 writel(sys_ctrl, host->ioaddr + ESDHC_SYSTEM_CONTROL); 1199 ret = readl_poll_timeout(host->ioaddr + ESDHC_SYSTEM_CONTROL, sys_ctrl, 1200 !(sys_ctrl & ESDHC_SYS_CTRL_RST_FIFO), 10, 100); 1201 if (ret == -ETIMEDOUT) 1202 dev_warn(mmc_dev(host->mmc), 1203 "warning! RST_FIFO not clear in 100us\n"); 1204} 1205 1206static void esdhc_post_tuning(struct sdhci_host *host) 1207{ 1208 u32 reg; 1209 1210 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1211 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1212 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1213} 1214 1215/* 1216 * find the largest pass window, and use the average delay of this 1217 * largest window to get the best timing. 1218 */ 1219static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 1220{ 1221 int min, max, avg, ret; 1222 int win_length, target_min, target_max, target_win_length; 1223 u32 clk_tune_ctrl_status, temp; 1224 1225 min = target_min = ESDHC_TUNE_CTRL_MIN; 1226 max = target_max = ESDHC_TUNE_CTRL_MIN; 1227 target_win_length = 0; 1228 while (max < ESDHC_TUNE_CTRL_MAX) { 1229 /* find the mininum delay first which can pass tuning */ 1230 while (min < ESDHC_TUNE_CTRL_MAX) { 1231 esdhc_prepare_tuning(host, min); 1232 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1233 break; 1234 min += ESDHC_TUNE_CTRL_STEP; 1235 } 1236 1237 /* find the maxinum delay which can not pass tuning */ 1238 max = min + ESDHC_TUNE_CTRL_STEP; 1239 while (max < ESDHC_TUNE_CTRL_MAX) { 1240 esdhc_prepare_tuning(host, max); 1241 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1242 max -= ESDHC_TUNE_CTRL_STEP; 1243 break; 1244 } 1245 max += ESDHC_TUNE_CTRL_STEP; 1246 } 1247 1248 win_length = max - min + 1; 1249 /* get the largest pass window */ 1250 if (win_length > target_win_length) { 1251 target_win_length = win_length; 1252 target_min = min; 1253 target_max = max; 1254 } 1255 1256 /* continue to find the next pass window */ 1257 min = max + ESDHC_TUNE_CTRL_STEP; 1258 } 1259 1260 /* use average delay to get the best timing */ 1261 avg = (target_min + target_max) / 2; 1262 esdhc_prepare_tuning(host, avg); 1263 1264 /* 1265 * adjust the delay according to tuning window, make preparation 1266 * for the auto-tuning logic. According to hardware suggest, need 1267 * to config the auto tuning window width to 3, to make the auto 1268 * tuning logic have enough space to handle the sample point shift 1269 * caused by temperature change. 1270 */ 1271 clk_tune_ctrl_status = FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK, 1272 avg - ESDHC_AUTO_TUNING_WINDOW) | 1273 FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK, 1274 ESDHC_AUTO_TUNING_WINDOW) | 1275 FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK, 1276 ESDHC_AUTO_TUNING_WINDOW); 1277 1278 writel(clk_tune_ctrl_status, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1279 ret = readl_poll_timeout(host->ioaddr + ESDHC_TUNE_CTRL_STATUS, temp, 1280 clk_tune_ctrl_status == 1281 FIELD_GET(ESDHC_TUNE_CTRL_STATUS_TAP_SEL_MASK, temp), 1282 1, 10); 1283 if (ret == -ETIMEDOUT) 1284 dev_warn(mmc_dev(host->mmc), 1285 "clock tuning control status not set in 10us\n"); 1286 1287 ret = mmc_send_tuning(host->mmc, opcode, NULL); 1288 esdhc_post_tuning(host); 1289 1290 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 1291 ret ? "failed" : "passed", avg, ret); 1292 1293 return ret; 1294} 1295 1296static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 1297{ 1298 struct sdhci_host *host = mmc_priv(mmc); 1299 u32 m; 1300 1301 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1302 if (ios->enhanced_strobe) 1303 m |= ESDHC_MIX_CTRL_HS400_ES_EN; 1304 else 1305 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 1306 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1307} 1308 1309static int esdhc_change_pinstate(struct sdhci_host *host, 1310 unsigned int uhs) 1311{ 1312 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1313 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1314 struct pinctrl_state *pinctrl; 1315 1316 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 1317 1318 if (IS_ERR(imx_data->pinctrl) || 1319 IS_ERR(imx_data->pins_100mhz) || 1320 IS_ERR(imx_data->pins_200mhz)) 1321 return -EINVAL; 1322 1323 switch (uhs) { 1324 case MMC_TIMING_UHS_SDR50: 1325 case MMC_TIMING_UHS_DDR50: 1326 pinctrl = imx_data->pins_100mhz; 1327 break; 1328 case MMC_TIMING_UHS_SDR104: 1329 case MMC_TIMING_MMC_HS200: 1330 case MMC_TIMING_MMC_HS400: 1331 pinctrl = imx_data->pins_200mhz; 1332 break; 1333 default: 1334 /* back to default state for other legacy timing */ 1335 return pinctrl_select_default_state(mmc_dev(host->mmc)); 1336 } 1337 1338 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 1339} 1340 1341/* 1342 * For HS400 eMMC, there is a data_strobe line. This signal is generated 1343 * by the device and used for data output and CRC status response output 1344 * in HS400 mode. The frequency of this signal follows the frequency of 1345 * CLK generated by host. The host receives the data which is aligned to the 1346 * edge of data_strobe line. Due to the time delay between CLK line and 1347 * data_strobe line, if the delay time is larger than one clock cycle, 1348 * then CLK and data_strobe line will be misaligned, read error shows up. 1349 */ 1350static void esdhc_set_strobe_dll(struct sdhci_host *host) 1351{ 1352 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1353 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1354 u32 strobe_delay; 1355 u32 v; 1356 int ret; 1357 1358 /* disable clock before enabling strobe dll */ 1359 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 1360 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 1361 host->ioaddr + ESDHC_VENDOR_SPEC); 1362 esdhc_wait_for_card_clock_gate_off(host); 1363 1364 /* force a reset on strobe dll */ 1365 writel(ESDHC_STROBE_DLL_CTRL_RESET, 1366 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1367 /* clear the reset bit on strobe dll before any setting */ 1368 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1369 1370 /* 1371 * enable strobe dll ctrl and adjust the delay target 1372 * for the uSDHC loopback read clock 1373 */ 1374 if (imx_data->boarddata.strobe_dll_delay_target) 1375 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; 1376 else 1377 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT; 1378 v = ESDHC_STROBE_DLL_CTRL_ENABLE | 1379 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 1380 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 1381 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1382 1383 /* wait max 50us to get the REF/SLV lock */ 1384 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, 1385 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50); 1386 if (ret == -ETIMEDOUT) 1387 dev_warn(mmc_dev(host->mmc), 1388 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); 1389} 1390 1391static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1392{ 1393 u32 m; 1394 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1395 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1396 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1397 1398 /* disable ddr mode and disable HS400 mode */ 1399 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1400 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 1401 imx_data->is_ddr = 0; 1402 1403 switch (timing) { 1404 case MMC_TIMING_UHS_SDR12: 1405 case MMC_TIMING_UHS_SDR25: 1406 case MMC_TIMING_UHS_SDR50: 1407 case MMC_TIMING_UHS_SDR104: 1408 case MMC_TIMING_MMC_HS: 1409 case MMC_TIMING_MMC_HS200: 1410 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1411 break; 1412 case MMC_TIMING_UHS_DDR50: 1413 case MMC_TIMING_MMC_DDR52: 1414 m |= ESDHC_MIX_CTRL_DDREN; 1415 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1416 imx_data->is_ddr = 1; 1417 if (boarddata->delay_line) { 1418 u32 v; 1419 v = boarddata->delay_line << 1420 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1421 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1422 if (is_imx53_esdhc(imx_data)) 1423 v <<= 1; 1424 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1425 } 1426 break; 1427 case MMC_TIMING_MMC_HS400: 1428 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 1429 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1430 imx_data->is_ddr = 1; 1431 /* update clock after enable DDR for strobe DLL lock */ 1432 host->ops->set_clock(host, host->clock); 1433 esdhc_set_strobe_dll(host); 1434 break; 1435 case MMC_TIMING_LEGACY: 1436 default: 1437 esdhc_reset_tuning(host); 1438 break; 1439 } 1440 1441 if (!(imx_data->socdata->flags & ESDHC_FLAG_DUMMY_PAD) && 1442 (timing == MMC_TIMING_UHS_SDR104 || 1443 timing == MMC_TIMING_MMC_HS200 || 1444 timing == MMC_TIMING_MMC_HS400)) 1445 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 1446 else 1447 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1448 1449 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1450 1451 esdhc_change_pinstate(host, timing); 1452} 1453 1454static void esdhc_reset(struct sdhci_host *host, u8 mask) 1455{ 1456 sdhci_and_cqhci_reset(host, mask); 1457 1458 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1459 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1460} 1461 1462static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 1463{ 1464 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1465 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1466 1467 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 1468 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 1469} 1470 1471static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1472{ 1473 int cmd_error = 0; 1474 int data_error = 0; 1475 1476 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1477 return intmask; 1478 1479 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1480 1481 return 0; 1482} 1483 1484static void esdhc_hw_reset(struct sdhci_host *host) 1485{ 1486 esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 0, ESDHC_SYSTEM_CONTROL); 1487 /* eMMC spec requires minimum 1us, here delay between 1-10us */ 1488 usleep_range(1, 10); 1489 esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 1490 ESDHC_SYS_CTRL_IPP_RST_N, ESDHC_SYSTEM_CONTROL); 1491 /* eMMC spec requires minimum 200us, here delay between 200-300us */ 1492 usleep_range(200, 300); 1493} 1494 1495static struct sdhci_ops sdhci_esdhc_ops = { 1496 .read_l = esdhc_readl_le, 1497 .read_w = esdhc_readw_le, 1498 .read_b = esdhc_readb_le, 1499 .write_l = esdhc_writel_le, 1500 .write_w = esdhc_writew_le, 1501 .write_b = esdhc_writeb_le, 1502 .set_clock = esdhc_pltfm_set_clock, 1503 .get_max_clock = esdhc_pltfm_get_max_clock, 1504 .get_min_clock = esdhc_pltfm_get_min_clock, 1505 .get_max_timeout_count = esdhc_get_max_timeout_count, 1506 .get_ro = esdhc_pltfm_get_ro, 1507 .set_bus_width = esdhc_pltfm_set_bus_width, 1508 .set_uhs_signaling = esdhc_set_uhs_signaling, 1509 .reset = esdhc_reset, 1510 .irq = esdhc_cqhci_irq, 1511 .dump_vendor_regs = esdhc_dump_debug_regs, 1512 .hw_reset = esdhc_hw_reset, 1513}; 1514 1515static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 1516 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 1517 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 1518 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 1519 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 1520 .ops = &sdhci_esdhc_ops, 1521}; 1522 1523static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1524{ 1525 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1526 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1527 struct cqhci_host *cq_host = host->mmc->cqe_private; 1528 u32 tmp; 1529 1530 if (esdhc_is_usdhc(imx_data)) { 1531 /* 1532 * The imx6q ROM code will change the default watermark 1533 * level setting to something insane. Change it back here. 1534 */ 1535 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1536 1537 /* 1538 * ROM code will change the bit burst_length_enable setting 1539 * to zero if this usdhc is chosen to boot system. Change 1540 * it back here, otherwise it will impact the performance a 1541 * lot. This bit is used to enable/disable the burst length 1542 * for the external AHB2AXI bridge. It's useful especially 1543 * for INCR transfer because without burst length indicator, 1544 * the AHB2AXI bridge does not know the burst length in 1545 * advance. And without burst length indicator, AHB INCR 1546 * transfer can only be converted to singles on the AXI side. 1547 */ 1548 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1549 | ESDHC_BURST_LEN_EN_INCR, 1550 host->ioaddr + SDHCI_HOST_CONTROL); 1551 1552 /* 1553 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1554 * TO1.1, it's harmless for MX6SL 1555 */ 1556 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) { 1557 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1558 host->ioaddr + 0x6c); 1559 } 1560 1561 /* disable DLL_CTRL delay line settings */ 1562 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 1563 1564 /* 1565 * For the case of command with busy, if set the bit 1566 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1567 * transfer complete interrupt when busy is deasserted. 1568 * When CQHCI use DCMD to send a CMD need R1b respons, 1569 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1570 * otherwise DCMD will always meet timeout waiting for 1571 * hardware interrupt issue. 1572 */ 1573 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1574 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1575 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1576 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1577 1578 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1579 } 1580 1581 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1582 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1583 tmp |= ESDHC_STD_TUNING_EN; 1584 1585 /* 1586 * ROM code or bootloader may config the start tap 1587 * and step, unmask them first. 1588 */ 1589 tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK); 1590 if (imx_data->boarddata.tuning_start_tap) 1591 tmp |= imx_data->boarddata.tuning_start_tap; 1592 else 1593 tmp |= ESDHC_TUNING_START_TAP_DEFAULT; 1594 1595 if (imx_data->boarddata.tuning_step) { 1596 tmp |= imx_data->boarddata.tuning_step 1597 << ESDHC_TUNING_STEP_SHIFT; 1598 } else { 1599 tmp |= ESDHC_TUNING_STEP_DEFAULT 1600 << ESDHC_TUNING_STEP_SHIFT; 1601 } 1602 1603 /* 1604 * Config the tuning window to the hardware suggested value 3. 1605 * This tuning window is used for auto tuning logic. The default 1606 * tuning window is 2, here change to 3 make the window a bit 1607 * wider, give auto tuning enough space to handle the sample 1608 * point shift cause by temperature change. 1609 */ 1610 tmp &= ~ESDHC_TUNING_WINDOW_MASK; 1611 tmp |= FIELD_PREP(ESDHC_TUNING_WINDOW_MASK, ESDHC_AUTO_TUNING_WINDOW); 1612 1613 /* Disable the CMD CRC check for tuning, if not, need to 1614 * add some delay after every tuning command, because 1615 * hardware standard tuning logic will directly go to next 1616 * step once it detect the CMD CRC error, will not wait for 1617 * the card side to finally send out the tuning data, trigger 1618 * the buffer read ready interrupt immediately. If usdhc send 1619 * the next tuning command some eMMC card will stuck, can't 1620 * response, block the tuning procedure or the first command 1621 * after the whole tuning procedure always can't get any response. 1622 */ 1623 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; 1624 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1625 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1626 /* 1627 * ESDHC_STD_TUNING_EN may be configured in bootloader 1628 * or ROM code, so clear this bit here to make sure 1629 * the manual tuning can work. 1630 */ 1631 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1632 tmp &= ~ESDHC_STD_TUNING_EN; 1633 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1634 } 1635 1636 /* 1637 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card 1638 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let 1639 * the 1st linux configure power/clock for the 2nd Linux. 1640 * 1641 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux 1642 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump. 1643 * After we clear the pending interrupt and halt CQCTL, issue gone. 1644 */ 1645 if (cq_host) { 1646 tmp = cqhci_readl(cq_host, CQHCI_IS); 1647 cqhci_writel(cq_host, tmp, CQHCI_IS); 1648 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); 1649 } 1650 } 1651} 1652 1653static void sdhc_esdhc_tuning_save(struct sdhci_host *host) 1654{ 1655 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1656 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1657 u32 reg; 1658 1659 /* 1660 * SD/eMMC do not need this tuning save because it will re-init 1661 * after system resume back. 1662 * Here save the tuning delay value for SDIO device since it may 1663 * keep power during system PM. And for usdhc, only SDR50 and 1664 * SDR104 mode for SDIO device need to do tuning, and need to 1665 * save/restore. 1666 */ 1667 if (host->timing == MMC_TIMING_UHS_SDR50 || 1668 host->timing == MMC_TIMING_UHS_SDR104) { 1669 reg = readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1670 reg = FIELD_GET(ESDHC_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK, reg); 1671 imx_data->boarddata.saved_tuning_delay_cell = reg; 1672 } 1673} 1674 1675static void sdhc_esdhc_tuning_restore(struct sdhci_host *host) 1676{ 1677 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1678 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1679 u32 reg; 1680 1681 if (host->timing == MMC_TIMING_UHS_SDR50 || 1682 host->timing == MMC_TIMING_UHS_SDR104) { 1683 /* 1684 * restore the tuning delay value actually is a 1685 * manual tuning method, so clear the standard 1686 * tuning enable bit here. Will set back this 1687 * ESDHC_STD_TUNING_EN in esdhc_reset_tuning() 1688 * when trigger re-tuning. 1689 */ 1690 reg = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1691 reg &= ~ESDHC_STD_TUNING_EN; 1692 writel(reg, host->ioaddr + ESDHC_TUNING_CTRL); 1693 1694 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1695 reg |= ESDHC_MIX_CTRL_SMPCLK_SEL; 1696 if (!(imx_data->socdata->flags & ESDHC_FLAG_DUMMY_PAD)) 1697 reg |= ESDHC_MIX_CTRL_FBCLK_SEL; 1698 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1699 1700 writel(FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK, 1701 imx_data->boarddata.saved_tuning_delay_cell) | 1702 FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK, 1703 ESDHC_AUTO_TUNING_WINDOW) | 1704 FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK, 1705 ESDHC_AUTO_TUNING_WINDOW), 1706 host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1707 } 1708} 1709 1710static void esdhc_cqe_enable(struct mmc_host *mmc) 1711{ 1712 struct sdhci_host *host = mmc_priv(mmc); 1713 struct cqhci_host *cq_host = mmc->cqe_private; 1714 u32 reg; 1715 u16 mode; 1716 int count = 10; 1717 1718 /* 1719 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1720 * the case after tuning, so ensure the buffer is drained. 1721 */ 1722 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1723 while (reg & SDHCI_DATA_AVAILABLE) { 1724 sdhci_readl(host, SDHCI_BUFFER); 1725 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1726 if (count-- == 0) { 1727 dev_warn(mmc_dev(host->mmc), 1728 "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1729 break; 1730 } 1731 mdelay(1); 1732 } 1733 1734 /* 1735 * Runtime resume will reset the entire host controller, which 1736 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1737 * Here set DMAEN and BCEN when enable CMDQ. 1738 */ 1739 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1740 if (host->flags & SDHCI_REQ_USE_DMA) 1741 mode |= SDHCI_TRNS_DMA; 1742 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1743 mode |= SDHCI_TRNS_BLK_CNT_EN; 1744 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1745 1746 /* 1747 * Though Runtime resume reset the entire host controller, 1748 * but do not impact the CQHCI side, need to clear the 1749 * HALT bit, avoid CQHCI stuck in the first request when 1750 * system resume back. 1751 */ 1752 cqhci_writel(cq_host, 0, CQHCI_CTL); 1753 if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) 1754 dev_err(mmc_dev(host->mmc), 1755 "failed to exit halt state when enable CQE\n"); 1756 1757 1758 sdhci_cqe_enable(mmc); 1759} 1760 1761static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1762{ 1763 sdhci_dumpregs(mmc_priv(mmc)); 1764} 1765 1766static const struct cqhci_host_ops esdhc_cqhci_ops = { 1767 .enable = esdhc_cqe_enable, 1768 .disable = sdhci_cqe_disable, 1769 .dumpregs = esdhc_sdhci_dumpregs, 1770}; 1771 1772static int 1773sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1774 struct sdhci_host *host, 1775 struct pltfm_imx_data *imx_data) 1776{ 1777 struct device_node *np = pdev->dev.of_node; 1778 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1779 int ret; 1780 1781 if (of_property_read_bool(np, "fsl,wp-controller")) 1782 boarddata->wp_type = ESDHC_WP_CONTROLLER; 1783 1784 /* 1785 * If we have this property, then activate WP check. 1786 * Retrieving and requesting the actual WP GPIO will happen 1787 * in the call to mmc_of_parse(). 1788 */ 1789 if (of_property_present(np, "wp-gpios")) 1790 boarddata->wp_type = ESDHC_WP_GPIO; 1791 1792 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1793 of_property_read_u32(np, "fsl,tuning-start-tap", 1794 &boarddata->tuning_start_tap); 1795 1796 of_property_read_u32(np, "fsl,strobe-dll-delay-target", 1797 &boarddata->strobe_dll_delay_target); 1798 if (of_property_read_bool(np, "no-1-8-v")) 1799 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1800 1801 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1802 boarddata->delay_line = 0; 1803 1804 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); 1805 1806 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { 1807 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1808 ESDHC_PINCTRL_STATE_100MHZ); 1809 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1810 ESDHC_PINCTRL_STATE_200MHZ); 1811 } 1812 1813 /* call to generic mmc_of_parse to support additional capabilities */ 1814 ret = mmc_of_parse(host->mmc); 1815 if (ret) 1816 return ret; 1817 1818 /* HS400/HS400ES require 8 bit bus */ 1819 if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA)) 1820 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1821 1822 if (mmc_gpio_get_cd(host->mmc) >= 0) 1823 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1824 1825 return 0; 1826} 1827 1828static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 1829{ 1830 struct sdhci_pltfm_host *pltfm_host; 1831 struct sdhci_host *host; 1832 struct cqhci_host *cq_host; 1833 int err; 1834 struct pltfm_imx_data *imx_data; 1835 1836 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1837 sizeof(*imx_data)); 1838 if (IS_ERR(host)) 1839 return PTR_ERR(host); 1840 1841 pltfm_host = sdhci_priv(host); 1842 1843 imx_data = sdhci_pltfm_priv(pltfm_host); 1844 1845 imx_data->socdata = device_get_match_data(&pdev->dev); 1846 1847 host->quirks |= imx_data->socdata->quirks; 1848 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1849 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1850 1851 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1852 if (IS_ERR(imx_data->clk_ipg)) { 1853 err = PTR_ERR(imx_data->clk_ipg); 1854 goto free_sdhci; 1855 } 1856 1857 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1858 if (IS_ERR(imx_data->clk_ahb)) { 1859 err = PTR_ERR(imx_data->clk_ahb); 1860 goto free_sdhci; 1861 } 1862 1863 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 1864 if (IS_ERR(imx_data->clk_per)) { 1865 err = PTR_ERR(imx_data->clk_per); 1866 goto free_sdhci; 1867 } 1868 1869 pltfm_host->clk = imx_data->clk_per; 1870 err = clk_prepare_enable(imx_data->clk_per); 1871 if (err) 1872 goto free_sdhci; 1873 err = clk_prepare_enable(imx_data->clk_ipg); 1874 if (err) 1875 goto disable_per_clk; 1876 err = clk_prepare_enable(imx_data->clk_ahb); 1877 if (err) 1878 goto disable_ipg_clk; 1879 1880 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 1881 if (!pltfm_host->clock) { 1882 dev_err(mmc_dev(host->mmc), "could not get clk rate\n"); 1883 err = -EINVAL; 1884 goto disable_ahb_clk; 1885 } 1886 1887 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1888 if (IS_ERR(imx_data->pinctrl)) 1889 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); 1890 1891 if (esdhc_is_usdhc(imx_data)) { 1892 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1893 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1894 1895 /* GPIO CD can be set as a wakeup source */ 1896 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_CD_WAKE)) 1897 host->mmc->caps |= MMC_CAP_CD_WAKE; 1898 1899 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1900 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1901 1902 /* clear tuning bits in case ROM has set it already */ 1903 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1904 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1905 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1906 1907 /* 1908 * Link usdhc specific mmc_host_ops execute_tuning function, 1909 * to replace the standard one in sdhci_ops. 1910 */ 1911 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 1912 1913 /* 1914 * Link usdhc specific mmc_host_ops init card function, 1915 * to distinguish the card type. 1916 */ 1917 host->mmc_host_ops.init_card = usdhc_init_card; 1918 1919 host->max_timeout_count = 0xF; 1920 } 1921 1922 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1923 sdhci_esdhc_ops.platform_execute_tuning = 1924 esdhc_executing_tuning; 1925 1926 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1927 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1928 1929 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 1930 host->mmc->caps2 |= MMC_CAP2_HS400; 1931 1932 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) 1933 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; 1934 1935 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1936 host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1937 host->mmc_host_ops.hs400_enhanced_strobe = 1938 esdhc_hs400_enhanced_strobe; 1939 } 1940 1941 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1942 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1943 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 1944 if (!cq_host) { 1945 err = -ENOMEM; 1946 goto disable_ahb_clk; 1947 } 1948 1949 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1950 cq_host->ops = &esdhc_cqhci_ops; 1951 1952 err = cqhci_init(cq_host, host->mmc, false); 1953 if (err) 1954 goto disable_ahb_clk; 1955 } 1956 1957 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 1958 if (err) 1959 goto disable_ahb_clk; 1960 1961 sdhci_esdhc_imx_hwinit(host); 1962 1963 err = sdhci_add_host(host); 1964 if (err) 1965 goto disable_ahb_clk; 1966 1967 /* 1968 * Setup the wakeup capability here, let user to decide 1969 * whether need to enable this wakeup through sysfs interface. 1970 */ 1971 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) && 1972 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)) 1973 device_set_wakeup_capable(&pdev->dev, true); 1974 1975 pm_runtime_set_active(&pdev->dev); 1976 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1977 pm_runtime_use_autosuspend(&pdev->dev); 1978 pm_suspend_ignore_children(&pdev->dev, 1); 1979 pm_runtime_enable(&pdev->dev); 1980 1981 return 0; 1982 1983disable_ahb_clk: 1984 clk_disable_unprepare(imx_data->clk_ahb); 1985disable_ipg_clk: 1986 clk_disable_unprepare(imx_data->clk_ipg); 1987disable_per_clk: 1988 clk_disable_unprepare(imx_data->clk_per); 1989free_sdhci: 1990 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1991 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1992 return err; 1993} 1994 1995static void sdhci_esdhc_imx_remove(struct platform_device *pdev) 1996{ 1997 struct sdhci_host *host = platform_get_drvdata(pdev); 1998 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1999 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 2000 int dead; 2001 2002 pm_runtime_get_sync(&pdev->dev); 2003 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 2004 pm_runtime_disable(&pdev->dev); 2005 pm_runtime_put_noidle(&pdev->dev); 2006 2007 sdhci_remove_host(host, dead); 2008 2009 clk_disable_unprepare(imx_data->clk_per); 2010 clk_disable_unprepare(imx_data->clk_ipg); 2011 clk_disable_unprepare(imx_data->clk_ahb); 2012 2013 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 2014 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 2015} 2016 2017static int sdhci_esdhc_suspend(struct device *dev) 2018{ 2019 struct sdhci_host *host = dev_get_drvdata(dev); 2020 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2021 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 2022 int ret; 2023 2024 /* 2025 * Switch to runtime resume for two reasons: 2026 * 1, there is register access (e.g., wakeup control register), so 2027 * need to make sure gate on ipg clock. 2028 * 2, make sure the pm_runtime_force_resume() in sdhci_esdhc_resume() really 2029 * invoke its ->runtime_resume callback (needs_force_resume = 1). 2030 */ 2031 pm_runtime_get_sync(dev); 2032 2033 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && 2034 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { 2035 mmc_retune_timer_stop(host->mmc); 2036 mmc_retune_needed(host->mmc); 2037 } 2038 2039 /* 2040 * For the device need to keep power during system PM, need 2041 * to save the tuning delay value just in case the usdhc 2042 * lost power during system PM. 2043 */ 2044 if (mmc_card_keep_power(host->mmc) && mmc_card_wake_sdio_irq(host->mmc) && 2045 esdhc_is_usdhc(imx_data)) 2046 sdhc_esdhc_tuning_save(host); 2047 2048 if (device_may_wakeup(dev)) { 2049 /* The irqs of imx are not shared. It is safe to disable */ 2050 disable_irq(host->irq); 2051 ret = sdhci_enable_irq_wakeups(host); 2052 if (!ret) 2053 dev_warn(dev, "Failed to enable irq wakeup\n"); 2054 } else { 2055 /* 2056 * For the device which works as wakeup source, no need 2057 * to change the pinctrl to sleep state. 2058 * e.g. For SDIO device, the interrupt share with data pin, 2059 * but the pinctrl sleep state may config the data pin to 2060 * other function like GPIO function to save power in PM, 2061 * which finally block the SDIO wakeup function. 2062 */ 2063 ret = pinctrl_pm_select_sleep_state(dev); 2064 if (ret) 2065 return ret; 2066 } 2067 2068 ret = mmc_gpio_set_cd_wake(host->mmc, true); 2069 2070 /* 2071 * Make sure invoke runtime_suspend to gate off clock. 2072 * uSDHC IP supports in-band SDIO wakeup even without clock. 2073 */ 2074 pm_runtime_force_suspend(dev); 2075 2076 return ret; 2077} 2078 2079static int sdhci_esdhc_resume(struct device *dev) 2080{ 2081 struct sdhci_host *host = dev_get_drvdata(dev); 2082 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2083 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 2084 int ret; 2085 2086 pm_runtime_force_resume(dev); 2087 2088 ret = mmc_gpio_set_cd_wake(host->mmc, false); 2089 if (ret) 2090 return ret; 2091 2092 /* re-initialize hw state in case it's lost in low power mode */ 2093 sdhci_esdhc_imx_hwinit(host); 2094 2095 if (host->irq_wake_enabled) { 2096 sdhci_disable_irq_wakeups(host); 2097 enable_irq(host->irq); 2098 } 2099 2100 /* 2101 * restore the saved tuning delay value for the device which keep 2102 * power during system PM. 2103 */ 2104 if (mmc_card_keep_power(host->mmc) && mmc_card_wake_sdio_irq(host->mmc) && 2105 esdhc_is_usdhc(imx_data)) 2106 sdhc_esdhc_tuning_restore(host); 2107 2108 pm_runtime_put_autosuspend(dev); 2109 2110 return ret; 2111} 2112 2113static int sdhci_esdhc_runtime_suspend(struct device *dev) 2114{ 2115 struct sdhci_host *host = dev_get_drvdata(dev); 2116 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2117 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 2118 int ret; 2119 2120 if (host->mmc->caps2 & MMC_CAP2_CQE) { 2121 ret = cqhci_suspend(host->mmc); 2122 if (ret) 2123 return ret; 2124 } 2125 2126 sdhci_runtime_suspend_host(host); 2127 2128 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2129 mmc_retune_needed(host->mmc); 2130 2131 imx_data->actual_clock = host->mmc->actual_clock; 2132 esdhc_pltfm_set_clock(host, 0); 2133 clk_disable_unprepare(imx_data->clk_per); 2134 clk_disable_unprepare(imx_data->clk_ipg); 2135 clk_disable_unprepare(imx_data->clk_ahb); 2136 2137 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 2138 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 2139 2140 return 0; 2141} 2142 2143static int sdhci_esdhc_runtime_resume(struct device *dev) 2144{ 2145 struct sdhci_host *host = dev_get_drvdata(dev); 2146 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2147 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 2148 int err; 2149 2150 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 2151 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 2152 2153 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) 2154 clk_set_rate(imx_data->clk_per, pltfm_host->clock); 2155 2156 err = clk_prepare_enable(imx_data->clk_ahb); 2157 if (err) 2158 goto remove_pm_qos_request; 2159 2160 err = clk_prepare_enable(imx_data->clk_per); 2161 if (err) 2162 goto disable_ahb_clk; 2163 2164 err = clk_prepare_enable(imx_data->clk_ipg); 2165 if (err) 2166 goto disable_per_clk; 2167 2168 esdhc_pltfm_set_clock(host, imx_data->actual_clock); 2169 2170 sdhci_runtime_resume_host(host, 0); 2171 2172 if (host->mmc->caps2 & MMC_CAP2_CQE) 2173 err = cqhci_resume(host->mmc); 2174 2175 return err; 2176 2177disable_per_clk: 2178 clk_disable_unprepare(imx_data->clk_per); 2179disable_ahb_clk: 2180 clk_disable_unprepare(imx_data->clk_ahb); 2181remove_pm_qos_request: 2182 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 2183 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 2184 return err; 2185} 2186 2187static const struct dev_pm_ops sdhci_esdhc_pmops = { 2188 SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 2189 RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, sdhci_esdhc_runtime_resume, NULL) 2190}; 2191 2192static struct platform_driver sdhci_esdhc_imx_driver = { 2193 .driver = { 2194 .name = "sdhci-esdhc-imx", 2195 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2196 .of_match_table = imx_esdhc_dt_ids, 2197 .pm = pm_ptr(&sdhci_esdhc_pmops), 2198 }, 2199 .probe = sdhci_esdhc_imx_probe, 2200 .remove = sdhci_esdhc_imx_remove, 2201}; 2202 2203module_platform_driver(sdhci_esdhc_imx_driver); 2204 2205MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 2206MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 2207MODULE_LICENSE("GPL v2");
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