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renesas_sdhi_internal_dmac.c

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linux-6.19.14/drivers/mmc/host/renesas_sdhi_internal_dmac.c C 
  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * DMA support for Internal DMAC with SDHI SD/SDIO controller
  4 *
  5 * Copyright (C) 2016-19 Renesas Electronics Corporation
  6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
  7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
  8 */
  9
 10#include <linux/bitops.h>
 11#include <linux/device.h>
 12#include <linux/dma-mapping.h>
 13#include <linux/io-64-nonatomic-hi-lo.h>
 14#include <linux/mmc/host.h>
 15#include <linux/mod_devicetable.h>
 16#include <linux/module.h>
 17#include <linux/of.h>
 18#include <linux/pagemap.h>
 19#include <linux/platform_data/tmio.h>
 20#include <linux/platform_device.h>
 21#include <linux/scatterlist.h>
 22#include <linux/sys_soc.h>
 23
 24#include "renesas_sdhi.h"
 25#include "tmio_mmc.h"
 26
 27#define DM_CM_DTRAN_MODE	0x820
 28#define DM_CM_DTRAN_CTRL	0x828
 29#define DM_CM_RST		0x830
 30#define DM_CM_INFO1		0x840
 31#define DM_CM_INFO1_MASK	0x848
 32#define DM_CM_INFO2		0x850
 33#define DM_CM_INFO2_MASK	0x858
 34#define DM_DTRAN_ADDR		0x880
 35
 36/* DM_CM_DTRAN_MODE */
 37#define DTRAN_MODE_CH_NUM_CH0	0	/* "downstream" = for write commands */
 38#define DTRAN_MODE_CH_NUM_CH1	BIT(16)	/* "upstream" = for read commands */
 39#define DTRAN_MODE_BUS_WIDTH	(BIT(5) | BIT(4))
 40#define DTRAN_MODE_ADDR_MODE	BIT(0)	/* 1 = Increment address, 0 = Fixed */
 41
 42/* DM_CM_DTRAN_CTRL */
 43#define DTRAN_CTRL_DM_START	BIT(0)
 44
 45/* DM_CM_RST */
 46#define RST_DTRANRST1		BIT(9)
 47#define RST_DTRANRST0		BIT(8)
 48#define RST_RESERVED_BITS	GENMASK_ULL(31, 0)
 49
 50/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
 51#define INFO1_MASK_CLEAR	GENMASK_ULL(31, 0)
 52#define INFO1_DTRANEND1		BIT(20)
 53#define INFO1_DTRANEND1_OLD	BIT(17)
 54#define INFO1_DTRANEND0		BIT(16)
 55
 56/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
 57#define INFO2_MASK_CLEAR	GENMASK_ULL(31, 0)
 58#define INFO2_DTRANERR1		BIT(17)
 59#define INFO2_DTRANERR0		BIT(16)
 60
 61enum renesas_sdhi_dma_cookie {
 62	COOKIE_UNMAPPED,
 63	COOKIE_PRE_MAPPED,
 64	COOKIE_MAPPED,
 65};
 66
 67/*
 68 * Specification of this driver:
 69 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
 70 * - Since this SDHI DMAC register set has 16 but 32-bit width, we
 71 *   need a custom accessor.
 72 */
 73
 74static unsigned long global_flags;
 75/*
 76 * Workaround for avoiding to use RX DMAC by multiple channels. On R-Car M3-W
 77 * ES1.0, when multiple SDHI channels use RX DMAC simultaneously, sometimes
 78 * hundreds of data bytes are not stored into the system memory even if the
 79 * DMAC interrupt happened. So, this driver then uses one RX DMAC channel only.
 80 */
 81#define SDHI_INTERNAL_DMAC_RX_IN_USE	0
 82
 83/* Definitions for sampling clocks */
 84static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
 85	{
 86		.clk_rate = 0,
 87		.tap = 0x00000300,
 88		.tap_hs400_4tap = 0x00000100,
 89	},
 90};
 91
 92static const struct renesas_sdhi_of_data of_data_rza2 = {
 93	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
 94			  TMIO_MMC_HAVE_CBSY,
 95	.tmio_ocr_mask	= MMC_VDD_32_33,
 96	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 97			  MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
 98	.bus_shift	= 2,
 99	.scc_offset	= 0 - 0x1000,
100	.taps		= rcar_gen3_scc_taps,
101	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
102	/* DMAC can handle 32bit blk count but only 1 segment */
103	.max_blk_count	= UINT_MAX / TMIO_MAX_BLK_SIZE,
104	.max_segs	= 1,
105};
106
107static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
108	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
109			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
110			  TMIO_MMC_64BIT_DATA_PORT,
111	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
112			  MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
113	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
114	.bus_shift	= 2,
115	.scc_offset	= 0x1000,
116	.taps		= rcar_gen3_scc_taps,
117	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
118	/* DMAC can handle 32bit blk count but only 1 segment */
119	.max_blk_count	= UINT_MAX / TMIO_MAX_BLK_SIZE,
120	.max_segs	= 1,
121	.sdhi_flags	= SDHI_FLAG_NEED_CLKH_FALLBACK,
122};
123
124static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = {
125	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
126			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
127			  TMIO_MMC_64BIT_DATA_PORT,
128	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
129			  MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
130	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
131	.bus_shift	= 2,
132	.scc_offset	= 0x1000,
133	.taps		= rcar_gen3_scc_taps,
134	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
135	/* DMAC can handle 32bit blk count but only 1 segment */
136	.max_blk_count	= UINT_MAX / TMIO_MAX_BLK_SIZE,
137	.max_segs	= 1,
138};
139
140static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
141	{ 3,  3,  3,  3,  3,  3,  3,  4,  4,  5,  6,  7,  8,  9, 10, 15,
142	 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
143	{ 5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  6,  7,  8, 11,
144	 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
145};
146
147static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
148	{ 1,  2,  6,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
149	 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
150	{ 2,  3,  4,  4,  5,  6,  7,  9, 10, 11, 12, 13, 14, 15, 16, 17,
151	 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
152};
153
154static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
155	{ 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
156	  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },
157	{ 0,  0,  0,  1,  2,  3,  3,  4,  4,  4,  5,  5,  6,  8,  9, 10,
158	 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
159};
160
161static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
162	.hs400_disabled = true,
163	.hs400_4taps = true,
164};
165
166static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = {
167	.hs400_disabled = true,
168	.hs400_4taps = true,
169	.dma_one_rx_only = true,
170	.old_info1_layout = true,
171};
172
173static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
174	.hs400_4taps = true,
175	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
176	.manual_tap_correction = true,
177};
178
179static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
180	.hs400_disabled = true,
181};
182
183static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = {
184	.fixed_addr_mode = true,
185};
186
187static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
188	.hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
189	.manual_tap_correction = true,
190};
191
192static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
193	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
194	.manual_tap_correction = true,
195};
196
197static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
198	.hs400_4taps = true,
199	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
200	.hs400_calib_table = r8a7796_es13_calib_table,
201	.manual_tap_correction = true,
202};
203
204static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
205	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
206	.hs400_calib_table = r8a77965_calib_table,
207	.manual_tap_correction = true,
208};
209
210static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
211	.hs400_calib_table = r8a77990_calib_table,
212	.manual_tap_correction = true,
213};
214
215static const struct renesas_sdhi_quirks sdhi_quirks_rzg2l = {
216	.fixed_addr_mode = true,
217	.hs400_disabled = true,
218};
219
220/*
221 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
222 * So, we want to treat them equally and only have a match for ES1.2 to enforce
223 * this if there ever will be a way to distinguish ES1.2.
224 */
225static const struct soc_device_attribute sdhi_quirks_match[]  = {
226	{ .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
227	{ .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
228	{ .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx },
229	{ .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 },
230	{ .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
231	{ .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 },
232	{ /* Sentinel. */ }
233};
234
235static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = {
236	.of_data = &of_data_rcar_gen3,
237	.quirks = &sdhi_quirks_bad_taps2367,
238};
239
240static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = {
241	.of_data = &of_data_rcar_gen3,
242	.quirks = &sdhi_quirks_bad_taps1357,
243};
244
245static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = {
246	.of_data = &of_data_rcar_gen3,
247	.quirks = &sdhi_quirks_r8a77965,
248};
249
250static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = {
251	.of_data = &of_data_rcar_gen3_no_sdh_fallback,
252	.quirks = &sdhi_quirks_nohs400,
253};
254
255static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = {
256	.of_data = &of_data_rcar_gen3,
257	.quirks = &sdhi_quirks_r8a77990,
258};
259
260static const struct renesas_sdhi_of_data_with_quirks of_rzg2l_compatible = {
261	.of_data = &of_data_rcar_gen3,
262	.quirks = &sdhi_quirks_rzg2l,
263};
264
265static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = {
266	.of_data = &of_data_rcar_gen3,
267};
268
269static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = {
270	.of_data = &of_data_rcar_gen3,
271	.quirks = &sdhi_quirks_nohs400,
272};
273
274static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = {
275	.of_data	= &of_data_rza2,
276	.quirks		= &sdhi_quirks_fixed_addr,
277};
278
279static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
280	{ .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
281	{ .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
282	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, },
283	{ .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, },
284	{ .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, },
285	{ .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, },
286	{ .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, },
287	{ .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, },
288	{ .compatible = "renesas,sdhi-r9a09g011", .data = &of_rzg2l_compatible, },
289	{ .compatible = "renesas,sdhi-r9a09g057", .data = &of_rzg2l_compatible, },
290	{ .compatible = "renesas,rzg2l-sdhi", .data = &of_rzg2l_compatible, },
291	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
292	{ .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, },
293	{},
294};
295MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
296
297static void
298renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
299{
300	struct renesas_sdhi *priv = host_to_priv(host);
301	u32 dma_irqs = INFO1_DTRANEND0 |
302			(sdhi_has_quirk(priv, old_info1_layout) ?
303			INFO1_DTRANEND1_OLD : INFO1_DTRANEND1);
304
305	if (!host->chan_tx || !host->chan_rx)
306		return;
307
308	writel(enable ? ~dma_irqs : INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK);
309
310	if (priv->dma_priv.enable)
311		priv->dma_priv.enable(host, enable);
312}
313
314static void
315renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host)
316{
317	u64 val = RST_DTRANRST1 | RST_DTRANRST0;
318
319	renesas_sdhi_internal_dmac_enable_dma(host, false);
320
321	writel(RST_RESERVED_BITS & ~val, host->ctl + DM_CM_RST);
322	writel(RST_RESERVED_BITS | val, host->ctl + DM_CM_RST);
323
324	clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
325
326	renesas_sdhi_internal_dmac_enable_dma(host, true);
327}
328
329static bool renesas_sdhi_internal_dmac_dma_irq(struct tmio_mmc_host *host)
330{
331	struct renesas_sdhi *priv = host_to_priv(host);
332	struct renesas_sdhi_dma *dma_priv = &priv->dma_priv;
333
334	u32 dma_irqs = INFO1_DTRANEND0 |
335			(sdhi_has_quirk(priv, old_info1_layout) ?
336			INFO1_DTRANEND1_OLD : INFO1_DTRANEND1);
337	u32 status = readl(host->ctl + DM_CM_INFO1);
338
339	if (status & dma_irqs) {
340		writel(status ^ dma_irqs, host->ctl + DM_CM_INFO1);
341		set_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags);
342		if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags))
343			queue_work(system_bh_wq, &dma_priv->dma_complete);
344	}
345
346	return status & dma_irqs;
347}
348
349static void
350renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host)
351{
352	struct renesas_sdhi *priv = host_to_priv(host);
353	struct renesas_sdhi_dma *dma_priv = &priv->dma_priv;
354
355	set_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags);
356	if (test_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags) ||
357	    host->data->error)
358		queue_work(system_bh_wq, &dma_priv->dma_complete);
359}
360
361/*
362 * renesas_sdhi_internal_dmac_map() will be called with two different
363 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single
364 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg
365 * pointer in a mmc_data instead of host->sg_ptr.
366 */
367static void
368renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host,
369				 struct mmc_data *data,
370				 enum renesas_sdhi_dma_cookie cookie)
371{
372	bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) :
373						 (data->host_cookie == cookie);
374
375	if (unmap) {
376		dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
377			     mmc_get_dma_dir(data));
378		data->host_cookie = COOKIE_UNMAPPED;
379	}
380}
381
382static bool
383renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host,
384			       struct mmc_data *data,
385			       enum renesas_sdhi_dma_cookie cookie)
386{
387	if (data->host_cookie == COOKIE_PRE_MAPPED)
388		return true;
389
390	if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
391			    mmc_get_dma_dir(data)))
392		return false;
393
394	data->host_cookie = cookie;
395
396	/* This DMAC needs buffers to be 128-byte aligned */
397	if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) {
398		renesas_sdhi_internal_dmac_unmap(host, data, cookie);
399		return false;
400	}
401
402	return true;
403}
404
405static void
406renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
407				     struct mmc_data *data)
408{
409	struct renesas_sdhi *priv = host_to_priv(host);
410	struct scatterlist *sg = host->sg_ptr;
411	u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
412
413	if (!sdhi_has_quirk(priv, fixed_addr_mode))
414		dtran_mode |= DTRAN_MODE_ADDR_MODE;
415
416	if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED))
417		goto force_pio;
418
419	if (data->flags & MMC_DATA_READ) {
420		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
421		if (sdhi_has_quirk(priv, dma_one_rx_only) &&
422		    test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
423			goto force_pio_with_unmap;
424	} else {
425		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
426	}
427
428	priv->dma_priv.end_flags = 0;
429	renesas_sdhi_internal_dmac_enable_dma(host, true);
430
431	/* set dma parameters */
432	writel(dtran_mode, host->ctl + DM_CM_DTRAN_MODE);
433	writel(sg_dma_address(sg), host->ctl + DM_DTRAN_ADDR);
434
435	host->dma_on = true;
436
437	return;
438
439force_pio_with_unmap:
440	renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
441
442force_pio:
443	renesas_sdhi_internal_dmac_enable_dma(host, false);
444}
445
446static void renesas_sdhi_internal_dmac_issue_work_fn(struct work_struct *work)
447{
448	struct tmio_mmc_host *host = from_work(host, work, dma_issue);
449	struct renesas_sdhi *priv = host_to_priv(host);
450
451	tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
452
453	if (!host->cmd->error) {
454		/* start the DMAC */
455		writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL);
456	} else {
457		/* on CMD errors, simulate DMA end immediately */
458		set_bit(SDHI_DMA_END_FLAG_DMA, &priv->dma_priv.end_flags);
459		if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &priv->dma_priv.end_flags))
460			queue_work(system_bh_wq, &priv->dma_priv.dma_complete);
461	}
462}
463
464static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host)
465{
466	enum dma_data_direction dir;
467
468	if (!host->dma_on)
469		return false;
470
471	if (!host->data)
472		return false;
473
474	if (host->data->flags & MMC_DATA_READ)
475		dir = DMA_FROM_DEVICE;
476	else
477		dir = DMA_TO_DEVICE;
478
479	renesas_sdhi_internal_dmac_enable_dma(host, false);
480	renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED);
481
482	if (dir == DMA_FROM_DEVICE)
483		clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
484
485	host->dma_on = false;
486
487	return true;
488}
489
490static void renesas_sdhi_internal_dmac_complete_work_fn(struct work_struct *work)
491{
492	struct renesas_sdhi_dma *dma_priv = from_work(dma_priv, work, dma_complete);
493	struct renesas_sdhi *priv = container_of(dma_priv, typeof(*priv), dma_priv);
494	struct tmio_mmc_host *host = priv->host;
495
496	spin_lock_irq(&host->lock);
497	if (!renesas_sdhi_internal_dmac_complete(host))
498		goto out;
499
500	tmio_mmc_do_data_irq(host);
501out:
502	spin_unlock_irq(&host->lock);
503}
504
505static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host)
506{
507	if (host->data)
508		renesas_sdhi_internal_dmac_complete(host);
509}
510
511static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc,
512						struct mmc_request *mrq,
513						int err)
514{
515	struct tmio_mmc_host *host = mmc_priv(mmc);
516	struct mmc_data *data = mrq->data;
517
518	if (!data)
519		return;
520
521	renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
522}
523
524static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc,
525					       struct mmc_request *mrq)
526{
527	struct tmio_mmc_host *host = mmc_priv(mmc);
528	struct mmc_data *data = mrq->data;
529
530	if (!data)
531		return;
532
533	data->host_cookie = COOKIE_UNMAPPED;
534	renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED);
535}
536
537static void
538renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
539				       struct tmio_mmc_data *pdata)
540{
541	struct renesas_sdhi *priv = host_to_priv(host);
542
543	/* Disable DMAC interrupts initially */
544	writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK);
545	writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK);
546	writel(0, host->ctl + DM_CM_INFO1);
547	writel(0, host->ctl + DM_CM_INFO2);
548
549	/* Each value is set to non-zero to assume "enabling" each DMA */
550	host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
551
552	INIT_WORK(&priv->dma_priv.dma_complete,
553		  renesas_sdhi_internal_dmac_complete_work_fn);
554	INIT_WORK(&host->dma_issue,
555		  renesas_sdhi_internal_dmac_issue_work_fn);
556
557	/* Add pre_req and post_req */
558	host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req;
559	host->ops.post_req = renesas_sdhi_internal_dmac_post_req;
560}
561
562static void
563renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
564{
565	/* Each value is set to zero to assume "disabling" each DMA */
566	host->chan_rx = host->chan_tx = NULL;
567}
568
569static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
570	.start = renesas_sdhi_internal_dmac_start_dma,
571	.enable = renesas_sdhi_internal_dmac_enable_dma,
572	.request = renesas_sdhi_internal_dmac_request_dma,
573	.release = renesas_sdhi_internal_dmac_release_dma,
574	.abort = renesas_sdhi_internal_dmac_abort_dma,
575	.dataend = renesas_sdhi_internal_dmac_dataend_dma,
576	.end = renesas_sdhi_internal_dmac_end_dma,
577	.dma_irq = renesas_sdhi_internal_dmac_dma_irq,
578};
579
580static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
581{
582	const struct soc_device_attribute *attr;
583	const struct renesas_sdhi_of_data_with_quirks *of_data_quirks;
584	const struct renesas_sdhi_quirks *quirks;
585	struct device *dev = &pdev->dev;
586
587	of_data_quirks = of_device_get_match_data(&pdev->dev);
588	quirks = of_data_quirks->quirks;
589
590	attr = soc_device_match(sdhi_quirks_match);
591	if (attr)
592		quirks = attr->data;
593
594	/* value is max of SD_SECCNT. Confirmed by HW engineers */
595	dma_set_max_seg_size(dev, 0xffffffff);
596
597	return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops,
598				  of_data_quirks->of_data, quirks);
599}
600
601static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
602	SYSTEM_SLEEP_PM_OPS(renesas_sdhi_suspend, renesas_sdhi_resume)
603	RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
604		       tmio_mmc_host_runtime_resume,
605		       NULL)
606};
607
608static struct platform_driver renesas_internal_dmac_sdhi_driver = {
609	.driver		= {
610		.name	= "renesas_sdhi_internal_dmac",
611		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
612		.pm	= pm_ptr(&renesas_sdhi_internal_dmac_dev_pm_ops),
613		.of_match_table = renesas_sdhi_internal_dmac_of_match,
614	},
615	.probe		= renesas_sdhi_internal_dmac_probe,
616	.remove		= renesas_sdhi_remove,
617};
618
619module_platform_driver(renesas_internal_dmac_sdhi_driver);
620
621MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
622MODULE_AUTHOR("Yoshihiro Shimoda");
623MODULE_LICENSE("GPL v2");
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