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renesas_sdhi_core.c
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linux-6.19.14/drivers/mmc/host/renesas_sdhi_core.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21#include <linux/clk.h> 22#include <linux/delay.h> 23#include <linux/iopoll.h> 24#include <linux/kernel.h> 25#include <linux/mmc/host.h> 26#include <linux/mmc/mmc.h> 27#include <linux/mmc/slot-gpio.h> 28#include <linux/module.h> 29#include <linux/pinctrl/consumer.h> 30#include <linux/pinctrl/pinctrl-state.h> 31#include <linux/platform_data/tmio.h> 32#include <linux/platform_device.h> 33#include <linux/pm_domain.h> 34#include <linux/pm_runtime.h> 35#include <linux/regulator/consumer.h> 36#include <linux/regulator/driver.h> 37#include <linux/regulator/of_regulator.h> 38#include <linux/reset.h> 39#include <linux/sh_dma.h> 40#include <linux/slab.h> 41 42#include "renesas_sdhi.h" 43#include "tmio_mmc.h" 44 45#define CTL_HOST_MODE 0xe4 46#define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 47#define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 48#define HOST_MODE_GEN3_WMODE BIT(0) 49#define HOST_MODE_GEN3_BUSWIDTH BIT(8) 50 51#define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 52#define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 53#define HOST_MODE_GEN3_64BIT 0 54 55#define SDHI_VER_GEN2_SDR50 0x490c 56#define SDHI_VER_RZ_A1 0x820b 57/* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 58#define SDHI_VER_GEN2_SDR104 0xcb0d 59#define SDHI_VER_GEN3_SD 0xcc10 60#define SDHI_VER_GEN3_SDMMC 0xcd10 61 62#define SDHI_GEN3_MMC0_ADDR 0xee140000 63 64static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 65{ 66 u32 val; 67 68 /* 69 * see also 70 * renesas_sdhi_of_data :: dma_buswidth 71 */ 72 switch (sd_ctrl_read16(host, CTL_VERSION)) { 73 case SDHI_VER_GEN2_SDR50: 74 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 75 break; 76 case SDHI_VER_GEN2_SDR104: 77 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 78 break; 79 case SDHI_VER_GEN3_SD: 80 case SDHI_VER_GEN3_SDMMC: 81 if (width == 64) 82 val = HOST_MODE_GEN3_64BIT; 83 else if (width == 32) 84 val = HOST_MODE_GEN3_32BIT; 85 else 86 val = HOST_MODE_GEN3_16BIT; 87 break; 88 default: 89 /* nothing to do */ 90 return; 91 } 92 93 sd_ctrl_write16(host, CTL_HOST_MODE, val); 94} 95 96static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 97{ 98 struct mmc_host *mmc = host->mmc; 99 struct renesas_sdhi *priv = host_to_priv(host); 100 int ret; 101 102 ret = clk_prepare_enable(priv->clk_cd); 103 if (ret < 0) 104 return ret; 105 106 /* 107 * The clock driver may not know what maximum frequency 108 * actually works, so it should be set with the max-frequency 109 * property which will already have been read to f_max. If it 110 * was missing, assume the current frequency is the maximum. 111 */ 112 if (!mmc->f_max) 113 mmc->f_max = clk_get_rate(priv->clk); 114 115 /* 116 * Minimum frequency is the minimum input clock frequency 117 * divided by our maximum divider. 118 */ 119 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 120 121 /* enable 16bit data access on SDBUF as default */ 122 renesas_sdhi_sdbuf_width(host, 16); 123 124 return 0; 125} 126 127static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 128 unsigned int wanted_clock) 129{ 130 struct renesas_sdhi *priv = host_to_priv(host); 131 struct clk *ref_clk = priv->clk; 132 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 133 unsigned int new_clock, clkh_shift = 0; 134 unsigned int new_upper_limit; 135 int i; 136 137 /* 138 * We simply return the current rate if a) we are not on a R-Car Gen2+ 139 * SoC (may work for others, but untested) or b) if the SCC needs its 140 * clock during tuning, so we don't change the external clock setup. 141 */ 142 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 143 return clk_get_rate(priv->clk); 144 145 if (priv->clkh) { 146 /* HS400 with 4TAP needs different clock settings */ 147 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 148 bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 149 clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 150 ref_clk = priv->clkh; 151 } 152 153 new_clock = wanted_clock << clkh_shift; 154 155 /* 156 * We want the bus clock to be as close as possible to, but no 157 * greater than, new_clock. As we can divide by 1 << i for 158 * any i in [0, 9] we want the input clock to be as close as 159 * possible, but no greater than, new_clock << i. 160 * 161 * Add an upper limit of 1/1024 rate higher to the clock rate to fix 162 * clk rate jumping to lower rate due to rounding error (eg: RZ/G2L has 163 * 3 clk sources 533.333333 MHz, 400 MHz and 266.666666 MHz. The request 164 * for 533.333333 MHz will selects a slower 400 MHz due to rounding 165 * error (533333333 Hz / 4 * 4 = 533333332 Hz < 533333333 Hz)). 166 */ 167 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 168 freq = clk_round_rate(ref_clk, new_clock << i); 169 new_upper_limit = (new_clock << i) + ((new_clock << i) >> 10); 170 if (freq > new_upper_limit) { 171 /* Too fast; look for a slightly slower option */ 172 freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 173 if (freq > new_upper_limit) 174 continue; 175 } 176 177 diff = new_clock - (freq >> i); 178 if (diff <= diff_min) { 179 best_freq = freq; 180 diff_min = diff; 181 } 182 } 183 184 clk_set_rate(ref_clk, best_freq); 185 186 if (priv->clkh) 187 clk_set_rate(priv->clk, best_freq >> clkh_shift); 188 189 return clk_get_rate(priv->clk); 190} 191 192static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 193 unsigned int new_clock) 194{ 195 unsigned int clk_margin; 196 u32 clk = 0, clock; 197 198 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 199 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 200 201 if (new_clock == 0) { 202 host->mmc->actual_clock = 0; 203 goto out; 204 } 205 206 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 207 clock = host->mmc->actual_clock / 512; 208 209 /* 210 * Add a margin of 1/1024 rate higher to the clock rate in order 211 * to avoid clk variable setting a value of 0 due to the margin 212 * provided for actual_clock in renesas_sdhi_clk_update(). 213 */ 214 clk_margin = new_clock >> 10; 215 for (clk = 0x80000080; new_clock + clk_margin >= (clock << 1); clk >>= 1) 216 clock <<= 1; 217 218 /* 1/1 clock is option */ 219 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 220 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 221 clk |= 0xff; 222 else 223 clk &= ~0xff; 224 } 225 226 clock = clk & CLK_CTL_DIV_MASK; 227 if (clock != CLK_CTL_DIV_MASK) 228 host->mmc->actual_clock /= (1 << (ffs(clock) + 1)); 229 230 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock); 231 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 232 usleep_range(10000, 11000); 233 234 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 235 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 236 237out: 238 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 239 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 240 usleep_range(10000, 11000); 241} 242 243static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 244{ 245 struct renesas_sdhi *priv = host_to_priv(host); 246 247 clk_disable_unprepare(priv->clk_cd); 248} 249 250static int renesas_sdhi_card_busy(struct mmc_host *mmc) 251{ 252 struct tmio_mmc_host *host = mmc_priv(mmc); 253 254 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 255 TMIO_STAT_DAT0); 256} 257 258static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 259 struct mmc_ios *ios) 260{ 261 struct tmio_mmc_host *host = mmc_priv(mmc); 262 struct renesas_sdhi *priv = host_to_priv(host); 263 struct pinctrl_state *pin_state; 264 int ret; 265 266 switch (ios->signal_voltage) { 267 case MMC_SIGNAL_VOLTAGE_330: 268 pin_state = priv->pins_default; 269 break; 270 case MMC_SIGNAL_VOLTAGE_180: 271 pin_state = priv->pins_uhs; 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 /* 278 * If anything is missing, assume signal voltage is fixed at 279 * 3.3V and succeed/fail accordingly. 280 */ 281 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 282 return ios->signal_voltage == 283 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 284 285 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 286 if (ret < 0) 287 return ret; 288 289 return pinctrl_select_state(priv->pinctrl, pin_state); 290} 291 292/* SCC registers */ 293#define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 294#define SH_MOBILE_SDHI_SCC_TAPSET 0x002 295#define SH_MOBILE_SDHI_SCC_DT2FF 0x004 296#define SH_MOBILE_SDHI_SCC_CKSEL 0x006 297#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 298#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 299#define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 300#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 301#define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 302#define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 303#define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 304#define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 305#define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 306 307#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 308#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 309#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 310 311#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 312 313#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 314 315#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 316#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 317#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 318 319#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 320#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 321#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 322 323#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 324#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 325 326/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 327#define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 328 329/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 330#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 331#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 332#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 333 334/* Definitions for values the SH_MOBILE_SDHI_SCC register */ 335#define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 336#define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 337#define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 338 339static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 340 struct renesas_sdhi *priv, int addr) 341{ 342 return readl(priv->scc_ctl + (addr << host->bus_shift)); 343} 344 345static inline void sd_scc_write32(struct tmio_mmc_host *host, 346 struct renesas_sdhi *priv, 347 int addr, u32 val) 348{ 349 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 350} 351 352static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 353{ 354 struct renesas_sdhi *priv; 355 356 priv = host_to_priv(host); 357 358 /* Initialize SCC */ 359 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 360 361 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 362 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 363 364 /* set sampling clock selection range */ 365 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 366 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 367 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 368 369 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 370 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 371 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 372 373 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 374 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 375 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 376 377 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 378 379 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 380 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 381 382 /* Read TAPNUM */ 383 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 384 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 385 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 386} 387 388static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 389{ 390 struct tmio_mmc_host *host = mmc_priv(mmc); 391 struct renesas_sdhi *priv = host_to_priv(host); 392 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 393 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 394 395 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 396 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 397 398 /* Set HS400 mode */ 399 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 400 sd_ctrl_read16(host, CTL_SDIF_MODE)); 401 402 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 403 priv->scc_tappos_hs400); 404 405 if (sdhi_has_quirk(priv, manual_tap_correction)) 406 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 407 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 408 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 409 410 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 411 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 412 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 413 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 414 415 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 416 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 417 sd_scc_read32(host, priv, 418 SH_MOBILE_SDHI_SCC_DTCNTL)); 419 420 /* Avoid bad TAP */ 421 if (bad_taps & BIT(priv->tap_set)) { 422 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 423 424 if (bad_taps & BIT(new_tap)) 425 new_tap = (priv->tap_set - 1) % priv->tap_num; 426 427 if (bad_taps & BIT(new_tap)) { 428 new_tap = priv->tap_set; 429 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 430 } 431 432 priv->tap_set = new_tap; 433 } 434 435 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 436 priv->tap_set / (use_4tap ? 2 : 1)); 437 438 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 439 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 440 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 441 442 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 443 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 444 445 if (priv->adjust_hs400_calib_table) 446 priv->needs_adjust_hs400 = true; 447} 448 449static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 450{ 451 struct tmio_mmc_host *host = mmc_priv(mmc); 452 struct renesas_sdhi *priv = host_to_priv(host); 453 454 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 455 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 456 457 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 458 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 459 sd_scc_read32(host, priv, 460 SH_MOBILE_SDHI_SCC_CKSEL)); 461 462 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 463 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 464 sd_scc_read32(host, priv, 465 SH_MOBILE_SDHI_SCC_DTCNTL)); 466 467 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 468 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 469} 470 471static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 472 struct renesas_sdhi *priv, u32 addr) 473{ 474 /* read mode */ 475 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 476 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 477 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 478 479 /* access start and stop */ 480 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 481 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 482 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 483 484 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 485} 486 487static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 488 struct renesas_sdhi *priv, u32 addr, u32 val) 489{ 490 /* write mode */ 491 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 492 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 493 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 494 495 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 496 497 /* access start and stop */ 498 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 499 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 500 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 501} 502 503static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 504{ 505 struct renesas_sdhi *priv = host_to_priv(host); 506 u32 calib_code; 507 508 /* disable write protect */ 509 sd_scc_tmpport_write32(host, priv, 0x00, 510 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 511 /* read calibration code and adjust */ 512 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 513 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 514 515 sd_scc_tmpport_write32(host, priv, 0x22, 516 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 517 priv->adjust_hs400_calib_table[calib_code]); 518 519 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 520 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 521 522 /* adjustment done, clear flag */ 523 priv->needs_adjust_hs400 = false; 524} 525 526static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 527{ 528 struct renesas_sdhi *priv = host_to_priv(host); 529 530 /* disable write protect */ 531 sd_scc_tmpport_write32(host, priv, 0x00, 532 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 533 /* disable manual calibration */ 534 sd_scc_tmpport_write32(host, priv, 0x22, 0); 535 /* clear offset value of TMPPORT3 */ 536 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 537} 538 539static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 540 struct renesas_sdhi *priv) 541{ 542 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 543 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 544 545 /* Reset HS400 mode */ 546 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 547 sd_ctrl_read16(host, CTL_SDIF_MODE)); 548 549 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 550 551 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 552 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 553 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 554 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 555 556 if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400_bad_taps)) 557 renesas_sdhi_adjust_hs400_mode_disable(host); 558 559 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 560 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 561} 562 563static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 564{ 565 struct tmio_mmc_host *host = mmc_priv(mmc); 566 567 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 568 return 0; 569} 570 571static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 572{ 573 renesas_sdhi_disable_scc(host->mmc); 574 renesas_sdhi_reset_hs400_mode(host, priv); 575 priv->needs_adjust_hs400 = false; 576 577 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 578 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 579 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 580} 581 582/* only populated for TMIO_MMC_MIN_RCAR2 */ 583static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) 584{ 585 struct renesas_sdhi *priv = host_to_priv(host); 586 int ret; 587 u16 val; 588 589 if (!preserve) { 590 if (priv->rstc) { 591 u32 sd_status; 592 /* 593 * HW reset might have toggled the regulator state in 594 * HW which regulator core might be unaware of so save 595 * and restore the regulator state during HW reset. 596 */ 597 if (priv->rdev) 598 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 599 600 reset_control_reset(priv->rstc); 601 /* Unknown why but without polling reset status, it will hang */ 602 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 603 false, priv->rstc); 604 /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 605 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 606 if (priv->rdev) 607 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 608 609 priv->needs_adjust_hs400 = false; 610 renesas_sdhi_set_clock(host, host->clk_cache); 611 612 /* Ensure default value for this driver. */ 613 renesas_sdhi_sdbuf_width(host, 16); 614 } else if (priv->scc_ctl) { 615 renesas_sdhi_scc_reset(host, priv); 616 } 617 } 618 619 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 620 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 621 val |= CARD_OPT_EXTOP; 622 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 623 } 624} 625 626static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 627{ 628 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 629 630 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 631 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 632 633} 634 635#define SH_MOBILE_SDHI_MIN_TAP_ROW 3 636 637static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 638{ 639 struct renesas_sdhi *priv = host_to_priv(host); 640 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 641 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 642 unsigned long *bitmap; 643 644 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 645 646 /* 647 * When tuning CMD19 is issued twice for each tap, merge the 648 * result requiring the tap to be good in both runs before 649 * considering it for tuning selection. 650 */ 651 for (i = 0; i < taps_size; i++) { 652 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 653 654 if (!test_bit(i, priv->taps)) 655 clear_bit(i + offset, priv->taps); 656 657 if (!test_bit(i, priv->smpcmp)) 658 clear_bit(i + offset, priv->smpcmp); 659 } 660 661 /* 662 * If all TAP are OK, the sampling clock position is selected by 663 * identifying the change point of data. 664 */ 665 if (bitmap_full(priv->taps, taps_size)) { 666 bitmap = priv->smpcmp; 667 min_tap_row = 1; 668 } else { 669 bitmap = priv->taps; 670 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 671 } 672 673 /* 674 * Find the longest consecutive run of successful probes. If that 675 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 676 * center index as the tap, otherwise bail out. 677 */ 678 for_each_set_bitrange(rs, re, bitmap, taps_size) { 679 if (re - rs > tap_cnt) { 680 tap_end = re; 681 tap_start = rs; 682 tap_cnt = tap_end - tap_start; 683 } 684 } 685 686 if (tap_cnt >= min_tap_row) 687 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 688 else 689 return -EIO; 690 691 /* Set SCC */ 692 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 693 694 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 695 (priv->card_is_sdio ? 0 : SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) | 696 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 697 698 return 0; 699} 700 701static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 702{ 703 struct tmio_mmc_host *host = mmc_priv(mmc); 704 struct renesas_sdhi *priv = host_to_priv(host); 705 int i, ret; 706 707 priv->tap_num = renesas_sdhi_init_tuning(host); 708 if (!priv->tap_num) 709 return 0; /* Tuning is not supported */ 710 711 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 712 dev_err(&host->pdev->dev, 713 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 714 return -EINVAL; 715 } 716 717 bitmap_zero(priv->taps, priv->tap_num * 2); 718 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 719 720 /* Issue CMD19 twice for each tap */ 721 for (i = 0; i < 2 * priv->tap_num; i++) { 722 int cmd_error = 0; 723 724 /* Set sampling clock position */ 725 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 726 727 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 728 set_bit(i, priv->taps); 729 730 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 731 set_bit(i, priv->smpcmp); 732 733 if (cmd_error) 734 mmc_send_abort_tuning(mmc, opcode); 735 } 736 737 ret = renesas_sdhi_select_tuning(host); 738 if (ret < 0) 739 renesas_sdhi_scc_reset(host, priv); 740 return ret; 741} 742 743static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 744{ 745 struct renesas_sdhi *priv = host_to_priv(host); 746 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 747 u32 val; 748 749 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 750 if (!val) 751 return false; 752 753 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 754 755 /* Change TAP position according to correction status */ 756 if (sdhi_has_quirk(priv, manual_tap_correction) && 757 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 758 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 759 /* 760 * With HS400, the DAT signal is based on DS, not CLK. 761 * Therefore, use only CMD status. 762 */ 763 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 764 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 765 if (!smpcmp) { 766 return false; /* no error in CMD signal */ 767 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 768 new_tap++; 769 error_tap--; 770 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 771 new_tap--; 772 error_tap++; 773 } else { 774 return true; /* need retune */ 775 } 776 777 /* 778 * When new_tap is a bad tap, we cannot change. Then, we compare 779 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 780 * we can at least retune. 781 */ 782 if (bad_taps & BIT(new_tap % priv->tap_num)) 783 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 784 } else { 785 if (!priv->card_is_sdio && 786 !(val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)) { 787 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP); 788 789 /* DAT1 is unmatched because of an SDIO irq */ 790 if (smpcmp & (BIT(17) | BIT(1))) 791 return false; 792 } 793 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 794 return true; /* need retune */ 795 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 796 new_tap++; 797 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 798 new_tap--; 799 else 800 return false; 801 } 802 803 priv->tap_set = (new_tap % priv->tap_num); 804 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 805 priv->tap_set / (use_4tap ? 2 : 1)); 806 807 return false; 808} 809 810static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 811{ 812 struct renesas_sdhi *priv = host_to_priv(host); 813 814 /* Check SCC error */ 815 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 816 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 817 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 818 return true; 819 } 820 821 return false; 822} 823 824static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 825 struct mmc_request *mrq) 826{ 827 struct renesas_sdhi *priv = host_to_priv(host); 828 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 829 bool ret = false; 830 831 /* 832 * Skip checking SCC errors when running on 4 taps in HS400 mode as 833 * any retuning would still result in the same 4 taps being used. 834 */ 835 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 836 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 837 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 838 return false; 839 840 if (mmc_doing_tune(host->mmc)) 841 return false; 842 843 /* mrq can be NULL to check SCC error on SDIO irq without any request */ 844 if (mrq) { 845 if (((mrq->cmd->error == -ETIMEDOUT) || 846 (mrq->data && mrq->data->error == -ETIMEDOUT)) && 847 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 848 (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 849 ret |= true; 850 } 851 852 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 853 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 854 ret |= renesas_sdhi_auto_correction(host); 855 else 856 ret |= renesas_sdhi_manual_correction(host, use_4tap); 857 858 return ret; 859} 860 861static void renesas_sdhi_init_card(struct mmc_host *mmc, struct mmc_card *card) 862{ 863 struct tmio_mmc_host *host = mmc_priv(mmc); 864 struct renesas_sdhi *priv = host_to_priv(host); 865 866 /* 867 * This controller cannot do auto-retune with SDIO irqs, so we 868 * then need to enforce manual correction. However, when tuning, 869 * mmc->card is not populated yet, so we don't know if the card 870 * is SDIO. init_card provides this information earlier, so we 871 * keep a copy of it. 872 */ 873 priv->card_is_sdio = mmc_card_sdio(card); 874} 875 876static void renesas_sdhi_sdio_irq(struct tmio_mmc_host *host) 877{ 878 /* This controller requires retune when an SDIO irq occurs */ 879 if (renesas_sdhi_check_scc_error(host, NULL)) 880 mmc_retune_needed(host->mmc); 881} 882 883static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 884{ 885 int timeout = 1000; 886 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 887 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 888 889 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 890 & bit) == wait_state) 891 udelay(1); 892 893 if (!timeout) { 894 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 895 return -EBUSY; 896 } 897 898 return 0; 899} 900 901static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 902{ 903 u32 bit = TMIO_STAT_SCLKDIVEN; 904 905 switch (addr) { 906 case CTL_SD_CMD: 907 case CTL_STOP_INTERNAL_ACTION: 908 case CTL_XFER_BLK_COUNT: 909 case CTL_SD_XFER_LEN: 910 case CTL_SD_MEM_CARD_OPT: 911 case CTL_TRANSACTION_CTL: 912 case CTL_DMA_ENABLE: 913 case CTL_HOST_MODE: 914 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 915 bit = TMIO_STAT_CMD_BUSY; 916 fallthrough; 917 case CTL_SD_CARD_CLK_CTL: 918 return renesas_sdhi_wait_idle(host, bit); 919 } 920 921 return 0; 922} 923 924static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 925 unsigned int direction, int blk_size) 926{ 927 /* 928 * In Renesas controllers, when performing a 929 * multiple block read of one or two blocks, 930 * depending on the timing with which the 931 * response register is read, the response 932 * value may not be read properly. 933 * Use single block read for this HW bug 934 */ 935 if ((direction == MMC_DATA_READ) && 936 blk_size == 2) 937 return 1; 938 939 return blk_size; 940} 941 942static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 943{ 944 struct renesas_sdhi *priv = host_to_priv(host); 945 946 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 947 renesas_sdhi_adjust_hs400_mode_enable(host); 948} 949static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 950{ 951 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 952 int width = (host->bus_shift == 2) ? 64 : 32; 953 954 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 955 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 956} 957 958static const unsigned int renesas_sdhi_vqmmc_voltages[] = { 959 3300000, 1800000 960}; 961 962static int renesas_sdhi_regulator_disable(struct regulator_dev *rdev) 963{ 964 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 965 u32 sd_status; 966 967 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 968 sd_status &= ~SD_STATUS_PWEN; 969 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 970 971 return 0; 972} 973 974static int renesas_sdhi_regulator_enable(struct regulator_dev *rdev) 975{ 976 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 977 u32 sd_status; 978 979 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 980 sd_status |= SD_STATUS_PWEN; 981 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 982 983 return 0; 984} 985 986static int renesas_sdhi_regulator_is_enabled(struct regulator_dev *rdev) 987{ 988 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 989 u32 sd_status; 990 991 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 992 993 return (sd_status & SD_STATUS_PWEN) ? 1 : 0; 994} 995 996static int renesas_sdhi_regulator_get_voltage(struct regulator_dev *rdev) 997{ 998 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 999 u32 sd_status; 1000 1001 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 1002 1003 return (sd_status & SD_STATUS_IOVS) ? 1800000 : 3300000; 1004} 1005 1006static int renesas_sdhi_regulator_set_voltage(struct regulator_dev *rdev, 1007 int min_uV, int max_uV, 1008 unsigned int *selector) 1009{ 1010 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 1011 u32 sd_status; 1012 1013 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 1014 if (min_uV >= 1700000 && max_uV <= 1950000) { 1015 sd_status |= SD_STATUS_IOVS; 1016 *selector = 1; 1017 } else { 1018 sd_status &= ~SD_STATUS_IOVS; 1019 *selector = 0; 1020 } 1021 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 1022 1023 return 0; 1024} 1025 1026static int renesas_sdhi_regulator_list_voltage(struct regulator_dev *rdev, 1027 unsigned int selector) 1028{ 1029 if (selector >= ARRAY_SIZE(renesas_sdhi_vqmmc_voltages)) 1030 return -EINVAL; 1031 1032 return renesas_sdhi_vqmmc_voltages[selector]; 1033} 1034 1035static const struct regulator_ops renesas_sdhi_regulator_voltage_ops = { 1036 .enable = renesas_sdhi_regulator_enable, 1037 .disable = renesas_sdhi_regulator_disable, 1038 .is_enabled = renesas_sdhi_regulator_is_enabled, 1039 .list_voltage = renesas_sdhi_regulator_list_voltage, 1040 .get_voltage = renesas_sdhi_regulator_get_voltage, 1041 .set_voltage = renesas_sdhi_regulator_set_voltage, 1042}; 1043 1044static const struct regulator_desc renesas_sdhi_vqmmc_regulator = { 1045 .name = "sdhi-vqmmc-regulator", 1046 .of_match = of_match_ptr("vqmmc-regulator"), 1047 .type = REGULATOR_VOLTAGE, 1048 .owner = THIS_MODULE, 1049 .ops = &renesas_sdhi_regulator_voltage_ops, 1050 .volt_table = renesas_sdhi_vqmmc_voltages, 1051 .n_voltages = ARRAY_SIZE(renesas_sdhi_vqmmc_voltages), 1052}; 1053 1054int renesas_sdhi_probe(struct platform_device *pdev, 1055 const struct tmio_mmc_dma_ops *dma_ops, 1056 const struct renesas_sdhi_of_data *of_data, 1057 const struct renesas_sdhi_quirks *quirks) 1058{ 1059 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 1060 struct tmio_mmc_data *mmc_data; 1061 struct regulator_config rcfg = { .dev = &pdev->dev, }; 1062 struct regulator_dev *rdev; 1063 struct renesas_sdhi_dma *dma_priv; 1064 struct device *dev = &pdev->dev; 1065 struct tmio_mmc_host *host; 1066 struct renesas_sdhi *priv; 1067 int num_irqs, irq, ret, i; 1068 struct resource *res; 1069 u16 ver; 1070 1071 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1072 if (!res) 1073 return -EINVAL; 1074 1075 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 1076 GFP_KERNEL); 1077 if (!priv) 1078 return -ENOMEM; 1079 1080 priv->quirks = quirks; 1081 mmc_data = &priv->mmc_data; 1082 dma_priv = &priv->dma_priv; 1083 1084 priv->clk = devm_clk_get(&pdev->dev, NULL); 1085 if (IS_ERR(priv->clk)) 1086 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); 1087 1088 priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); 1089 if (IS_ERR(priv->clkh)) 1090 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); 1091 1092 /* 1093 * Some controllers provide a 2nd clock just to run the internal card 1094 * detection logic. Unfortunately, the existing driver architecture does 1095 * not support a separation of clocks for runtime PM usage. When 1096 * native hotplug is used, the tmio driver assumes that the core 1097 * must continue to run for card detect to stay active, so we cannot 1098 * disable it. 1099 * Additionally, it is prohibited to supply a clock to the core but not 1100 * to the card detect circuit. That leaves us with if separate clocks 1101 * are presented, we must treat them both as virtually 1 clock. 1102 */ 1103 priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd"); 1104 if (IS_ERR(priv->clk_cd)) 1105 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 1106 1107 priv->rstc = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL); 1108 if (IS_ERR(priv->rstc)) 1109 return PTR_ERR(priv->rstc); 1110 1111 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1112 if (!IS_ERR(priv->pinctrl)) { 1113 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 1114 PINCTRL_STATE_DEFAULT); 1115 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 1116 "state_uhs"); 1117 } 1118 1119 host = tmio_mmc_host_alloc(pdev, mmc_data); 1120 if (IS_ERR(host)) 1121 return PTR_ERR(host); 1122 1123 priv->host = host; 1124 1125 if (of_data) { 1126 mmc_data->flags |= of_data->tmio_flags; 1127 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 1128 mmc_data->capabilities |= of_data->capabilities; 1129 mmc_data->capabilities2 |= of_data->capabilities2; 1130 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 1131 mmc_data->max_blk_count = of_data->max_blk_count; 1132 mmc_data->max_segs = of_data->max_segs; 1133 dma_priv->dma_buswidth = of_data->dma_buswidth; 1134 host->bus_shift = of_data->bus_shift; 1135 /* Fallback for old DTs */ 1136 if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 1137 priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 1138 1139 } 1140 1141 host->write16_hook = renesas_sdhi_write16_hook; 1142 host->clk_enable = renesas_sdhi_clk_enable; 1143 host->clk_disable = renesas_sdhi_clk_disable; 1144 host->set_clock = renesas_sdhi_set_clock; 1145 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 1146 host->dma_ops = dma_ops; 1147 1148 if (sdhi_has_quirk(priv, hs400_disabled)) 1149 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1150 1151 /* For some SoC, we disable internal WP. GPIO may override this */ 1152 if (mmc_host_can_gpio_ro(host->mmc)) 1153 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 1154 1155 /* SDR speeds are only available on Gen2+ */ 1156 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 1157 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 1158 host->ops.card_busy = renesas_sdhi_card_busy; 1159 host->ops.start_signal_voltage_switch = 1160 renesas_sdhi_start_signal_voltage_switch; 1161 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 1162 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 1163 host->reset = renesas_sdhi_reset; 1164 } else { 1165 host->sdcard_irq_mask_all = TMIO_MASK_ALL; 1166 } 1167 1168 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1169 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1170 host->bus_shift = 1; 1171 1172 if (mmd) 1173 *mmc_data = *mmd; 1174 1175 dma_priv->filter = shdma_chan_filter; 1176 dma_priv->enable = renesas_sdhi_enable_dma; 1177 1178 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1179 1180 /* 1181 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1182 * bus width mode. 1183 */ 1184 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1185 1186 /* 1187 * All SDHI blocks support SDIO IRQ signalling. 1188 */ 1189 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1190 1191 /* All SDHI have CMD12 control bit */ 1192 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1193 1194 /* All SDHI have SDIO status bits which must be 1 */ 1195 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1196 1197 /* All SDHI support HW busy detection */ 1198 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1199 1200 dev_pm_domain_start(&pdev->dev); 1201 1202 ret = renesas_sdhi_clk_enable(host); 1203 if (ret) 1204 return ret; 1205 1206 rcfg.of_node = of_get_available_child_by_name(dev->of_node, "vqmmc-regulator"); 1207 if (rcfg.of_node) { 1208 rcfg.driver_data = priv->host; 1209 rdev = devm_regulator_register(dev, &renesas_sdhi_vqmmc_regulator, &rcfg); 1210 of_node_put(rcfg.of_node); 1211 if (IS_ERR(rdev)) { 1212 dev_err(dev, "regulator register failed err=%ld", PTR_ERR(rdev)); 1213 ret = PTR_ERR(rdev); 1214 goto edisclk; 1215 } 1216 priv->rdev = rdev; 1217 } 1218 1219 ver = sd_ctrl_read16(host, CTL_VERSION); 1220 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1221 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1222 mmc_data->max_blk_count = U16_MAX; 1223 1224 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1225 if (ver == SDHI_VER_GEN2_SDR50) 1226 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1227 1228 if (ver == SDHI_VER_GEN3_SDMMC && sdhi_has_quirk(priv, hs400_calib_table)) { 1229 host->fixup_request = renesas_sdhi_fixup_request; 1230 priv->adjust_hs400_calib_table = *( 1231 res->start == SDHI_GEN3_MMC0_ADDR ? 1232 quirks->hs400_calib_table : 1233 quirks->hs400_calib_table + 1); 1234 } 1235 1236 /* these have an EXTOP bit */ 1237 if (ver >= SDHI_VER_GEN3_SD) 1238 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1239 1240 /* Check for SCC so we can reset it if needed */ 1241 if (of_data && of_data->scc_offset && ver >= SDHI_VER_GEN2_SDR104) 1242 priv->scc_ctl = host->ctl + of_data->scc_offset; 1243 1244 /* Enable tuning iff we have an SCC and a supported mode */ 1245 if (priv->scc_ctl && (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1246 host->mmc->caps2 & MMC_CAP2_HSX00_1_8V)) { 1247 const struct renesas_sdhi_scc *taps = of_data->taps; 1248 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 1249 bool hit = false; 1250 1251 for (i = 0; i < of_data->taps_num; i++) { 1252 if (taps[i].clk_rate == 0 || 1253 taps[i].clk_rate == host->mmc->f_max) { 1254 priv->scc_tappos = taps->tap; 1255 priv->scc_tappos_hs400 = use_4tap ? 1256 taps->tap_hs400_4tap : 1257 taps->tap; 1258 hit = true; 1259 break; 1260 } 1261 } 1262 1263 if (!hit) 1264 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1265 1266 host->check_retune = renesas_sdhi_check_scc_error; 1267 host->sdio_irq = renesas_sdhi_sdio_irq; 1268 host->ops.init_card = renesas_sdhi_init_card; 1269 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1270 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1271 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1272 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1273 } 1274 1275 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all); 1276 1277 /* There must be at least one IRQ source */ 1278 num_irqs = platform_irq_count(pdev); 1279 if (num_irqs <= 0) { 1280 ret = num_irqs ?: -ENOENT; 1281 goto edisclk; 1282 } 1283 1284 for (i = 0; i < num_irqs; i++) { 1285 irq = platform_get_irq(pdev, i); 1286 if (irq < 0) { 1287 ret = irq; 1288 goto edisclk; 1289 } 1290 1291 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1292 dev_name(&pdev->dev), host); 1293 if (ret) 1294 goto edisclk; 1295 } 1296 1297 ret = tmio_mmc_host_probe(host); 1298 if (ret < 0) 1299 goto edisclk; 1300 1301 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1302 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1303 1304 return ret; 1305 1306edisclk: 1307 renesas_sdhi_clk_disable(host); 1308 return ret; 1309} 1310EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1311 1312void renesas_sdhi_remove(struct platform_device *pdev) 1313{ 1314 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1315 1316 tmio_mmc_host_remove(host); 1317 renesas_sdhi_clk_disable(host); 1318} 1319EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1320 1321int renesas_sdhi_suspend(struct device *dev) 1322{ 1323 struct tmio_mmc_host *host = dev_get_drvdata(dev); 1324 struct renesas_sdhi *priv = host_to_priv(host); 1325 int ret; 1326 1327 ret = pm_runtime_force_suspend(dev); 1328 if (ret) 1329 return ret; 1330 1331 ret = reset_control_assert(priv->rstc); 1332 if (ret) 1333 pm_runtime_force_resume(dev); 1334 1335 return ret; 1336} 1337EXPORT_SYMBOL_GPL(renesas_sdhi_suspend); 1338 1339int renesas_sdhi_resume(struct device *dev) 1340{ 1341 struct tmio_mmc_host *host = dev_get_drvdata(dev); 1342 struct renesas_sdhi *priv = host_to_priv(host); 1343 int ret; 1344 1345 ret = reset_control_deassert(priv->rstc); 1346 if (ret) 1347 return ret; 1348 1349 ret = pm_runtime_force_resume(dev); 1350 if (ret) 1351 reset_control_assert(priv->rstc); 1352 1353 return ret; 1354} 1355EXPORT_SYMBOL_GPL(renesas_sdhi_resume); 1356 1357MODULE_DESCRIPTION("Renesas SDHI core driver"); 1358MODULE_LICENSE("GPL v2");
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