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omap_hsmmc.c
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linux-6.19.14/drivers/mmc/host/omap_hsmmc.c
1/* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18#include <linux/module.h> 19#include <linux/init.h> 20#include <linux/kernel.h> 21#include <linux/debugfs.h> 22#include <linux/dmaengine.h> 23#include <linux/seq_file.h> 24#include <linux/sizes.h> 25#include <linux/interrupt.h> 26#include <linux/delay.h> 27#include <linux/dma-mapping.h> 28#include <linux/platform_device.h> 29#include <linux/timer.h> 30#include <linux/clk.h> 31#include <linux/of.h> 32#include <linux/of_irq.h> 33#include <linux/of_device.h> 34#include <linux/mmc/host.h> 35#include <linux/mmc/core.h> 36#include <linux/mmc/mmc.h> 37#include <linux/mmc/slot-gpio.h> 38#include <linux/io.h> 39#include <linux/irq.h> 40#include <linux/regulator/consumer.h> 41#include <linux/pinctrl/consumer.h> 42#include <linux/pm_runtime.h> 43#include <linux/pm_wakeirq.h> 44#include <linux/platform_data/hsmmc-omap.h> 45 46/* OMAP HSMMC Host Controller Registers */ 47#define OMAP_HSMMC_SYSSTATUS 0x0014 48#define OMAP_HSMMC_CON 0x002C 49#define OMAP_HSMMC_SDMASA 0x0100 50#define OMAP_HSMMC_BLK 0x0104 51#define OMAP_HSMMC_ARG 0x0108 52#define OMAP_HSMMC_CMD 0x010C 53#define OMAP_HSMMC_RSP10 0x0110 54#define OMAP_HSMMC_RSP32 0x0114 55#define OMAP_HSMMC_RSP54 0x0118 56#define OMAP_HSMMC_RSP76 0x011C 57#define OMAP_HSMMC_DATA 0x0120 58#define OMAP_HSMMC_PSTATE 0x0124 59#define OMAP_HSMMC_HCTL 0x0128 60#define OMAP_HSMMC_SYSCTL 0x012C 61#define OMAP_HSMMC_STAT 0x0130 62#define OMAP_HSMMC_IE 0x0134 63#define OMAP_HSMMC_ISE 0x0138 64#define OMAP_HSMMC_AC12 0x013C 65#define OMAP_HSMMC_CAPA 0x0140 66 67#define VS18 (1 << 26) 68#define VS30 (1 << 25) 69#define HSS (1 << 21) 70#define SDVS18 (0x5 << 9) 71#define SDVS30 (0x6 << 9) 72#define SDVS33 (0x7 << 9) 73#define SDVS_MASK 0x00000E00 74#define SDVSCLR 0xFFFFF1FF 75#define SDVSDET 0x00000400 76#define AUTOIDLE 0x1 77#define SDBP (1 << 8) 78#define DTO 0xe 79#define ICE 0x1 80#define ICS 0x2 81#define CEN (1 << 2) 82#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 83#define CLKD_MASK 0x0000FFC0 84#define CLKD_SHIFT 6 85#define DTO_MASK 0x000F0000 86#define DTO_SHIFT 16 87#define INIT_STREAM (1 << 1) 88#define ACEN_ACMD23 (2 << 2) 89#define DP_SELECT (1 << 21) 90#define DDIR (1 << 4) 91#define DMAE 0x1 92#define MSBS (1 << 5) 93#define BCE (1 << 1) 94#define FOUR_BIT (1 << 1) 95#define HSPE (1 << 2) 96#define IWE (1 << 24) 97#define DDR (1 << 19) 98#define CLKEXTFREE (1 << 16) 99#define CTPL (1 << 11) 100#define DW8 (1 << 5) 101#define OD 0x1 102#define STAT_CLEAR 0xFFFFFFFF 103#define INIT_STREAM_CMD 0x00000000 104#define DUAL_VOLT_OCR_BIT 7 105#define SRC (1 << 25) 106#define SRD (1 << 26) 107#define SOFTRESET (1 << 1) 108 109/* PSTATE */ 110#define DLEV_DAT(x) (1 << (20 + (x))) 111 112/* Interrupt masks for IE and ISE register */ 113#define CC_EN (1 << 0) 114#define TC_EN (1 << 1) 115#define BWR_EN (1 << 4) 116#define BRR_EN (1 << 5) 117#define CIRQ_EN (1 << 8) 118#define ERR_EN (1 << 15) 119#define CTO_EN (1 << 16) 120#define CCRC_EN (1 << 17) 121#define CEB_EN (1 << 18) 122#define CIE_EN (1 << 19) 123#define DTO_EN (1 << 20) 124#define DCRC_EN (1 << 21) 125#define DEB_EN (1 << 22) 126#define ACE_EN (1 << 24) 127#define CERR_EN (1 << 28) 128#define BADA_EN (1 << 29) 129 130#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 131 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 132 BRR_EN | BWR_EN | TC_EN | CC_EN) 133 134#define CNI (1 << 7) 135#define ACIE (1 << 4) 136#define ACEB (1 << 3) 137#define ACCE (1 << 2) 138#define ACTO (1 << 1) 139#define ACNE (1 << 0) 140 141#define MMC_AUTOSUSPEND_DELAY 100 142#define MMC_TIMEOUT_MS 20 /* 20 mSec */ 143#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 144#define OMAP_MMC_MIN_CLOCK 400000 145#define OMAP_MMC_MAX_CLOCK 52000000 146#define DRIVER_NAME "omap_hsmmc" 147 148/* 149 * One controller can have multiple slots, like on some omap boards using 150 * omap.c controller driver. Luckily this is not currently done on any known 151 * omap_hsmmc.c device. 152 */ 153#define mmc_pdata(host) host->pdata 154 155/* 156 * MMC Host controller read/write API's 157 */ 158#define OMAP_HSMMC_READ(base, reg) \ 159 __raw_readl((base) + OMAP_HSMMC_##reg) 160 161#define OMAP_HSMMC_WRITE(base, reg, val) \ 162 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 163 164struct omap_hsmmc_next { 165 unsigned int dma_len; 166 s32 cookie; 167}; 168 169struct omap_hsmmc_host { 170 struct device *dev; 171 struct mmc_host *mmc; 172 struct mmc_request *mrq; 173 struct mmc_command *cmd; 174 struct mmc_data *data; 175 struct clk *fclk; 176 struct clk *dbclk; 177 struct regulator *pbias; 178 bool pbias_enabled; 179 void __iomem *base; 180 bool vqmmc_enabled; 181 resource_size_t mapbase; 182 spinlock_t irq_lock; /* Prevent races with irq handler */ 183 unsigned int dma_len; 184 unsigned int dma_sg_idx; 185 unsigned char bus_mode; 186 unsigned char power_mode; 187 int suspended; 188 u32 con; 189 u32 hctl; 190 u32 sysctl; 191 u32 capa; 192 int irq; 193 int wake_irq; 194 int use_dma, dma_ch; 195 struct dma_chan *tx_chan; 196 struct dma_chan *rx_chan; 197 int response_busy; 198 int context_loss; 199 int reqs_blocked; 200 int req_in_progress; 201 unsigned long clk_rate; 202 unsigned int flags; 203#define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 204#define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 205 struct omap_hsmmc_next next_data; 206 struct omap_hsmmc_platform_data *pdata; 207}; 208 209struct omap_mmc_of_data { 210 u32 reg_offset; 211 u8 controller_flags; 212}; 213 214static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 215 216static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 217{ 218 int ret; 219 struct omap_hsmmc_host *host = mmc_priv(mmc); 220 struct mmc_ios *ios = &mmc->ios; 221 222 if (!IS_ERR(mmc->supply.vmmc)) { 223 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 224 if (ret) 225 return ret; 226 } 227 228 /* Enable interface voltage rail, if needed */ 229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 230 ret = regulator_enable(mmc->supply.vqmmc); 231 if (ret) { 232 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 233 goto err_vqmmc; 234 } 235 host->vqmmc_enabled = true; 236 } 237 238 return 0; 239 240err_vqmmc: 241 if (!IS_ERR(mmc->supply.vmmc)) 242 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 243 244 return ret; 245} 246 247static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 248{ 249 int ret; 250 int status; 251 struct omap_hsmmc_host *host = mmc_priv(mmc); 252 253 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 254 ret = regulator_disable(mmc->supply.vqmmc); 255 if (ret) { 256 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 257 return ret; 258 } 259 host->vqmmc_enabled = false; 260 } 261 262 if (!IS_ERR(mmc->supply.vmmc)) { 263 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 264 if (ret) 265 goto err_set_ocr; 266 } 267 268 return 0; 269 270err_set_ocr: 271 if (!IS_ERR(mmc->supply.vqmmc)) { 272 status = regulator_enable(mmc->supply.vqmmc); 273 if (status) 274 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 275 } 276 277 return ret; 278} 279 280static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on) 281{ 282 int ret; 283 284 if (IS_ERR(host->pbias)) 285 return 0; 286 287 if (power_on) { 288 if (!host->pbias_enabled) { 289 ret = regulator_enable(host->pbias); 290 if (ret) { 291 dev_err(host->dev, "pbias reg enable fail\n"); 292 return ret; 293 } 294 host->pbias_enabled = true; 295 } 296 } else { 297 if (host->pbias_enabled) { 298 ret = regulator_disable(host->pbias); 299 if (ret) { 300 dev_err(host->dev, "pbias reg disable fail\n"); 301 return ret; 302 } 303 host->pbias_enabled = false; 304 } 305 } 306 307 return 0; 308} 309 310static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on) 311{ 312 struct mmc_host *mmc = host->mmc; 313 int ret = 0; 314 315 /* 316 * If we don't see a Vcc regulator, assume it's a fixed 317 * voltage always-on regulator. 318 */ 319 if (IS_ERR(mmc->supply.vmmc)) 320 return 0; 321 322 ret = omap_hsmmc_set_pbias(host, false); 323 if (ret) 324 return ret; 325 326 /* 327 * Assume Vcc regulator is used only to power the card ... OMAP 328 * VDDS is used to power the pins, optionally with a transceiver to 329 * support cards using voltages other than VDDS (1.8V nominal). When a 330 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 331 * 332 * In some cases this regulator won't support enable/disable; 333 * e.g. it's a fixed rail for a WLAN chip. 334 * 335 * In other cases vcc_aux switches interface power. Example, for 336 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 337 * chips/cards need an interface voltage rail too. 338 */ 339 if (power_on) { 340 ret = omap_hsmmc_enable_supply(mmc); 341 if (ret) 342 return ret; 343 344 ret = omap_hsmmc_set_pbias(host, true); 345 if (ret) 346 goto err_set_voltage; 347 } else { 348 ret = omap_hsmmc_disable_supply(mmc); 349 if (ret) 350 return ret; 351 } 352 353 return 0; 354 355err_set_voltage: 356 omap_hsmmc_disable_supply(mmc); 357 358 return ret; 359} 360 361static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 362{ 363 int ret; 364 365 if (IS_ERR(reg)) 366 return 0; 367 368 if (regulator_is_enabled(reg)) { 369 ret = regulator_enable(reg); 370 if (ret) 371 return ret; 372 373 ret = regulator_disable(reg); 374 if (ret) 375 return ret; 376 } 377 378 return 0; 379} 380 381static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 382{ 383 struct mmc_host *mmc = host->mmc; 384 int ret; 385 386 /* 387 * disable regulators enabled during boot and get the usecount 388 * right so that regulators can be enabled/disabled by checking 389 * the return value of regulator_is_enabled 390 */ 391 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 392 if (ret) { 393 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 394 return ret; 395 } 396 397 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 398 if (ret) { 399 dev_err(host->dev, 400 "fail to disable boot enabled vmmc_aux reg\n"); 401 return ret; 402 } 403 404 ret = omap_hsmmc_disable_boot_regulator(host->pbias); 405 if (ret) { 406 dev_err(host->dev, 407 "failed to disable boot enabled pbias reg\n"); 408 return ret; 409 } 410 411 return 0; 412} 413 414static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 415{ 416 int ret; 417 struct mmc_host *mmc = host->mmc; 418 419 420 ret = mmc_regulator_get_supply(mmc); 421 if (ret) 422 return ret; 423 424 /* Allow an aux regulator */ 425 if (IS_ERR(mmc->supply.vqmmc)) { 426 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, 427 "vmmc_aux"); 428 if (IS_ERR(mmc->supply.vqmmc)) { 429 ret = PTR_ERR(mmc->supply.vqmmc); 430 if ((ret != -ENODEV) && host->dev->of_node) 431 return ret; 432 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 433 PTR_ERR(mmc->supply.vqmmc)); 434 } 435 } 436 437 host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 438 if (IS_ERR(host->pbias)) { 439 ret = PTR_ERR(host->pbias); 440 if ((ret != -ENODEV) && host->dev->of_node) { 441 dev_err(host->dev, 442 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); 443 return ret; 444 } 445 dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 446 PTR_ERR(host->pbias)); 447 } 448 449 /* For eMMC do not power off when not in sleep state */ 450 if (mmc_pdata(host)->no_regulator_off_init) 451 return 0; 452 453 ret = omap_hsmmc_disable_boot_regulators(host); 454 if (ret) 455 return ret; 456 457 return 0; 458} 459 460/* 461 * Start clock to the card 462 */ 463static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 464{ 465 OMAP_HSMMC_WRITE(host->base, SYSCTL, 466 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 467} 468 469/* 470 * Stop clock to the card 471 */ 472static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 473{ 474 OMAP_HSMMC_WRITE(host->base, SYSCTL, 475 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 476 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 477 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 478} 479 480static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 481 struct mmc_command *cmd) 482{ 483 u32 irq_mask = INT_EN_MASK; 484 unsigned long flags; 485 486 if (host->use_dma) 487 irq_mask &= ~(BRR_EN | BWR_EN); 488 489 /* Disable timeout for erases */ 490 if (cmd->opcode == MMC_ERASE) 491 irq_mask &= ~DTO_EN; 492 493 spin_lock_irqsave(&host->irq_lock, flags); 494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 495 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 496 497 /* latch pending CIRQ, but don't signal MMC core */ 498 if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 499 irq_mask |= CIRQ_EN; 500 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 501 spin_unlock_irqrestore(&host->irq_lock, flags); 502} 503 504static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 505{ 506 u32 irq_mask = 0; 507 unsigned long flags; 508 509 spin_lock_irqsave(&host->irq_lock, flags); 510 /* no transfer running but need to keep cirq if enabled */ 511 if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 512 irq_mask |= CIRQ_EN; 513 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 514 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 515 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 516 spin_unlock_irqrestore(&host->irq_lock, flags); 517} 518 519/* Calculate divisor for the given clock frequency */ 520static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 521{ 522 u16 dsor = 0; 523 524 if (ios->clock) { 525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 526 if (dsor > CLKD_MAX) 527 dsor = CLKD_MAX; 528 } 529 530 return dsor; 531} 532 533static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 534{ 535 struct mmc_ios *ios = &host->mmc->ios; 536 unsigned long regval; 537 unsigned long timeout; 538 unsigned long clkdiv; 539 540 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 541 542 omap_hsmmc_stop_clock(host); 543 544 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 545 regval = regval & ~(CLKD_MASK | DTO_MASK); 546 clkdiv = calc_divisor(host, ios); 547 regval = regval | (clkdiv << 6) | (DTO << 16); 548 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 549 OMAP_HSMMC_WRITE(host->base, SYSCTL, 550 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 551 552 /* Wait till the ICS bit is set */ 553 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 554 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 555 && time_before(jiffies, timeout)) 556 cpu_relax(); 557 558 /* 559 * Enable High-Speed Support 560 * Pre-Requisites 561 * - Controller should support High-Speed-Enable Bit 562 * - Controller should not be using DDR Mode 563 * - Controller should advertise that it supports High Speed 564 * in capabilities register 565 * - MMC/SD clock coming out of controller > 25MHz 566 */ 567 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 568 (ios->timing != MMC_TIMING_MMC_DDR52) && 569 (ios->timing != MMC_TIMING_UHS_DDR50) && 570 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 571 regval = OMAP_HSMMC_READ(host->base, HCTL); 572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 573 regval |= HSPE; 574 else 575 regval &= ~HSPE; 576 577 OMAP_HSMMC_WRITE(host->base, HCTL, regval); 578 } 579 580 omap_hsmmc_start_clock(host); 581} 582 583static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 584{ 585 struct mmc_ios *ios = &host->mmc->ios; 586 u32 con; 587 588 con = OMAP_HSMMC_READ(host->base, CON); 589 if (ios->timing == MMC_TIMING_MMC_DDR52 || 590 ios->timing == MMC_TIMING_UHS_DDR50) 591 con |= DDR; /* configure in DDR mode */ 592 else 593 con &= ~DDR; 594 switch (ios->bus_width) { 595 case MMC_BUS_WIDTH_8: 596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 597 break; 598 case MMC_BUS_WIDTH_4: 599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 600 OMAP_HSMMC_WRITE(host->base, HCTL, 601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 602 break; 603 case MMC_BUS_WIDTH_1: 604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 605 OMAP_HSMMC_WRITE(host->base, HCTL, 606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 607 break; 608 } 609} 610 611static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 612{ 613 struct mmc_ios *ios = &host->mmc->ios; 614 u32 con; 615 616 con = OMAP_HSMMC_READ(host->base, CON); 617 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 618 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 619 else 620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 621} 622 623/* 624 * Restore the MMC host context, if it was lost as result of a 625 * power state change. 626 */ 627static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 628{ 629 struct mmc_ios *ios = &host->mmc->ios; 630 u32 hctl, capa; 631 unsigned long timeout; 632 633 if (host->con == OMAP_HSMMC_READ(host->base, CON) && 634 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 635 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 636 host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 637 return 0; 638 639 host->context_loss++; 640 641 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 642 if (host->power_mode != MMC_POWER_OFF && 643 (1 << ios->vdd) <= MMC_VDD_23_24) 644 hctl = SDVS18; 645 else 646 hctl = SDVS30; 647 capa = VS30 | VS18; 648 } else { 649 hctl = SDVS18; 650 capa = VS18; 651 } 652 653 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 654 hctl |= IWE; 655 656 OMAP_HSMMC_WRITE(host->base, HCTL, 657 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 658 659 OMAP_HSMMC_WRITE(host->base, CAPA, 660 OMAP_HSMMC_READ(host->base, CAPA) | capa); 661 662 OMAP_HSMMC_WRITE(host->base, HCTL, 663 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 664 665 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 666 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 667 && time_before(jiffies, timeout)) 668 ; 669 670 OMAP_HSMMC_WRITE(host->base, ISE, 0); 671 OMAP_HSMMC_WRITE(host->base, IE, 0); 672 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 673 674 /* Do not initialize card-specific things if the power is off */ 675 if (host->power_mode == MMC_POWER_OFF) 676 goto out; 677 678 omap_hsmmc_set_bus_width(host); 679 680 omap_hsmmc_set_clock(host); 681 682 omap_hsmmc_set_bus_mode(host); 683 684out: 685 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 686 host->context_loss); 687 return 0; 688} 689 690#ifdef CONFIG_PM 691/* 692 * Save the MMC host context (store the number of power state changes so far). 693 */ 694static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 695{ 696 host->con = OMAP_HSMMC_READ(host->base, CON); 697 host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 698 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 699 host->capa = OMAP_HSMMC_READ(host->base, CAPA); 700} 701 702#else 703 704static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 705{ 706} 707 708#endif 709 710/* 711 * Send init stream sequence to card 712 * before sending IDLE command 713 */ 714static void send_init_stream(struct omap_hsmmc_host *host) 715{ 716 int reg = 0; 717 unsigned long timeout; 718 719 disable_irq(host->irq); 720 721 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 722 OMAP_HSMMC_WRITE(host->base, CON, 723 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 724 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 725 726 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 727 while ((reg != CC_EN) && time_before(jiffies, timeout)) 728 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 729 730 OMAP_HSMMC_WRITE(host->base, CON, 731 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 732 733 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 734 OMAP_HSMMC_READ(host->base, STAT); 735 736 enable_irq(host->irq); 737} 738 739static ssize_t 740omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 741 char *buf) 742{ 743 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 744 struct omap_hsmmc_host *host = mmc_priv(mmc); 745 746 return sprintf(buf, "%s\n", mmc_pdata(host)->name); 747} 748 749static DEVICE_ATTR(slot_name, 0444, omap_hsmmc_show_slot_name, NULL); 750 751/* 752 * Configure the response type and send the cmd. 753 */ 754static void 755omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 756 struct mmc_data *data) 757{ 758 int cmdreg = 0, resptype = 0, cmdtype = 0; 759 760 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 761 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 762 host->cmd = cmd; 763 764 omap_hsmmc_enable_irq(host, cmd); 765 766 host->response_busy = 0; 767 if (cmd->flags & MMC_RSP_PRESENT) { 768 if (cmd->flags & MMC_RSP_136) 769 resptype = 1; 770 else if (cmd->flags & MMC_RSP_BUSY) { 771 resptype = 3; 772 host->response_busy = 1; 773 } else 774 resptype = 2; 775 } 776 777 /* 778 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 779 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 780 * a val of 0x3, rest 0x0. 781 */ 782 if (cmd == host->mrq->stop) 783 cmdtype = 0x3; 784 785 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 786 787 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 788 host->mrq->sbc) { 789 cmdreg |= ACEN_ACMD23; 790 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 791 } 792 if (data) { 793 cmdreg |= DP_SELECT | MSBS | BCE; 794 if (data->flags & MMC_DATA_READ) 795 cmdreg |= DDIR; 796 else 797 cmdreg &= ~(DDIR); 798 } 799 800 if (host->use_dma) 801 cmdreg |= DMAE; 802 803 host->req_in_progress = 1; 804 805 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 806 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 807} 808 809static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 810 struct mmc_data *data) 811{ 812 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 813} 814 815static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 816{ 817 int dma_ch; 818 unsigned long flags; 819 820 spin_lock_irqsave(&host->irq_lock, flags); 821 host->req_in_progress = 0; 822 dma_ch = host->dma_ch; 823 spin_unlock_irqrestore(&host->irq_lock, flags); 824 825 omap_hsmmc_disable_irq(host); 826 /* Do not complete the request if DMA is still in progress */ 827 if (mrq->data && host->use_dma && dma_ch != -1) 828 return; 829 host->mrq = NULL; 830 mmc_request_done(host->mmc, mrq); 831} 832 833/* 834 * Notify the transfer complete to MMC core 835 */ 836static void 837omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 838{ 839 if (!data) { 840 struct mmc_request *mrq = host->mrq; 841 842 /* TC before CC from CMD6 - don't know why, but it happens */ 843 if (host->cmd && host->cmd->opcode == 6 && 844 host->response_busy) { 845 host->response_busy = 0; 846 return; 847 } 848 849 omap_hsmmc_request_done(host, mrq); 850 return; 851 } 852 853 host->data = NULL; 854 855 if (!data->error) 856 data->bytes_xfered += data->blocks * (data->blksz); 857 else 858 data->bytes_xfered = 0; 859 860 if (data->stop && (data->error || !host->mrq->sbc)) 861 omap_hsmmc_start_command(host, data->stop, NULL); 862 else 863 omap_hsmmc_request_done(host, data->mrq); 864} 865 866/* 867 * Notify the core about command completion 868 */ 869static void 870omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 871{ 872 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 873 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 874 host->cmd = NULL; 875 omap_hsmmc_start_dma_transfer(host); 876 omap_hsmmc_start_command(host, host->mrq->cmd, 877 host->mrq->data); 878 return; 879 } 880 881 host->cmd = NULL; 882 883 if (cmd->flags & MMC_RSP_PRESENT) { 884 if (cmd->flags & MMC_RSP_136) { 885 /* response type 2 */ 886 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 887 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 888 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 889 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 890 } else { 891 /* response types 1, 1b, 3, 4, 5, 6 */ 892 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 893 } 894 } 895 if ((host->data == NULL && !host->response_busy) || cmd->error) 896 omap_hsmmc_request_done(host, host->mrq); 897} 898 899/* 900 * DMA clean up for command errors 901 */ 902static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 903{ 904 int dma_ch; 905 unsigned long flags; 906 907 host->data->error = errno; 908 909 spin_lock_irqsave(&host->irq_lock, flags); 910 dma_ch = host->dma_ch; 911 host->dma_ch = -1; 912 spin_unlock_irqrestore(&host->irq_lock, flags); 913 914 if (host->use_dma && dma_ch != -1) { 915 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 916 917 dmaengine_terminate_all(chan); 918 dma_unmap_sg(chan->device->dev, 919 host->data->sg, host->data->sg_len, 920 mmc_get_dma_dir(host->data)); 921 922 host->data->host_cookie = 0; 923 } 924 host->data = NULL; 925} 926 927/* 928 * Readable error output 929 */ 930#ifdef CONFIG_MMC_DEBUG 931static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 932{ 933 /* --- means reserved bit without definition at documentation */ 934 static const char *omap_hsmmc_status_bits[] = { 935 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 936 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 937 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 938 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 939 }; 940 char res[256]; 941 char *buf = res; 942 int len, i; 943 944 len = sprintf(buf, "MMC IRQ 0x%x :", status); 945 buf += len; 946 947 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 948 if (status & (1 << i)) { 949 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 950 buf += len; 951 } 952 953 dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 954} 955#else 956static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 957 u32 status) 958{ 959} 960#endif /* CONFIG_MMC_DEBUG */ 961 962/* 963 * MMC controller internal state machines reset 964 * 965 * Used to reset command or data internal state machines, using respectively 966 * SRC or SRD bit of SYSCTL register 967 * Can be called from interrupt context 968 */ 969static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 970 unsigned long bit) 971{ 972 unsigned long i = 0; 973 unsigned long limit = MMC_TIMEOUT_US; 974 975 OMAP_HSMMC_WRITE(host->base, SYSCTL, 976 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 977 978 /* 979 * OMAP4 ES2 and greater has an updated reset logic. 980 * Monitor a 0->1 transition first 981 */ 982 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 983 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 984 && (i++ < limit)) 985 udelay(1); 986 } 987 i = 0; 988 989 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 990 (i++ < limit)) 991 udelay(1); 992 993 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 994 dev_err(mmc_dev(host->mmc), 995 "Timeout waiting on controller reset in %s\n", 996 __func__); 997} 998 999static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 1000 int err, int end_cmd) 1001{ 1002 if (end_cmd) { 1003 omap_hsmmc_reset_controller_fsm(host, SRC); 1004 if (host->cmd) 1005 host->cmd->error = err; 1006 } 1007 1008 if (host->data) { 1009 omap_hsmmc_reset_controller_fsm(host, SRD); 1010 omap_hsmmc_dma_cleanup(host, err); 1011 } else if (host->mrq && host->mrq->cmd) 1012 host->mrq->cmd->error = err; 1013} 1014 1015static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1016{ 1017 struct mmc_data *data; 1018 int end_cmd = 0, end_trans = 0; 1019 int error = 0; 1020 1021 data = host->data; 1022 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1023 1024 if (status & ERR_EN) { 1025 omap_hsmmc_dbg_report_irq(host, status); 1026 1027 if (status & (CTO_EN | CCRC_EN | CEB_EN)) 1028 end_cmd = 1; 1029 if (host->data || host->response_busy) { 1030 end_trans = !end_cmd; 1031 host->response_busy = 0; 1032 } 1033 if (status & (CTO_EN | DTO_EN)) 1034 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1035 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 1036 BADA_EN)) 1037 hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 1038 1039 if (status & ACE_EN) { 1040 u32 ac12; 1041 ac12 = OMAP_HSMMC_READ(host->base, AC12); 1042 if (!(ac12 & ACNE) && host->mrq->sbc) { 1043 end_cmd = 1; 1044 if (ac12 & ACTO) 1045 error = -ETIMEDOUT; 1046 else if (ac12 & (ACCE | ACEB | ACIE)) 1047 error = -EILSEQ; 1048 host->mrq->sbc->error = error; 1049 hsmmc_command_incomplete(host, error, end_cmd); 1050 } 1051 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1052 } 1053 } 1054 1055 OMAP_HSMMC_WRITE(host->base, STAT, status); 1056 if (end_cmd || ((status & CC_EN) && host->cmd)) 1057 omap_hsmmc_cmd_done(host, host->cmd); 1058 if ((end_trans || (status & TC_EN)) && host->mrq) 1059 omap_hsmmc_xfer_done(host, data); 1060} 1061 1062/* 1063 * MMC controller IRQ handler 1064 */ 1065static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1066{ 1067 struct omap_hsmmc_host *host = dev_id; 1068 int status; 1069 1070 status = OMAP_HSMMC_READ(host->base, STAT); 1071 while (status & (INT_EN_MASK | CIRQ_EN)) { 1072 if (host->req_in_progress) 1073 omap_hsmmc_do_irq(host, status); 1074 1075 if (status & CIRQ_EN) 1076 mmc_signal_sdio_irq(host->mmc); 1077 1078 /* Flush posted write */ 1079 status = OMAP_HSMMC_READ(host->base, STAT); 1080 } 1081 1082 return IRQ_HANDLED; 1083} 1084 1085static void set_sd_bus_power(struct omap_hsmmc_host *host) 1086{ 1087 unsigned long i; 1088 1089 OMAP_HSMMC_WRITE(host->base, HCTL, 1090 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1091 for (i = 0; i < loops_per_jiffy; i++) { 1092 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1093 break; 1094 cpu_relax(); 1095 } 1096} 1097 1098/* 1099 * Switch MMC interface voltage ... only relevant for MMC1. 1100 * 1101 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1102 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1103 * Some chips, like eMMC ones, use internal transceivers. 1104 */ 1105static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1106{ 1107 u32 reg_val = 0; 1108 int ret; 1109 1110 /* Disable the clocks */ 1111 clk_disable_unprepare(host->dbclk); 1112 1113 /* Turn the power off */ 1114 ret = omap_hsmmc_set_power(host, 0); 1115 1116 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1117 if (!ret) 1118 ret = omap_hsmmc_set_power(host, 1); 1119 clk_prepare_enable(host->dbclk); 1120 1121 if (ret != 0) 1122 goto err; 1123 1124 OMAP_HSMMC_WRITE(host->base, HCTL, 1125 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1126 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1127 1128 /* 1129 * If a MMC dual voltage card is detected, the set_ios fn calls 1130 * this fn with VDD bit set for 1.8V. Upon card removal from the 1131 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1132 * 1133 * Cope with a bit of slop in the range ... per data sheets: 1134 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1135 * but recommended values are 1.71V to 1.89V 1136 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1137 * but recommended values are 2.7V to 3.3V 1138 * 1139 * Board setup code shouldn't permit anything very out-of-range. 1140 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1141 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1142 */ 1143 if ((1 << vdd) <= MMC_VDD_23_24) 1144 reg_val |= SDVS18; 1145 else 1146 reg_val |= SDVS30; 1147 1148 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1149 set_sd_bus_power(host); 1150 1151 return 0; 1152err: 1153 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1154 return ret; 1155} 1156 1157static void omap_hsmmc_dma_callback(void *param) 1158{ 1159 struct omap_hsmmc_host *host = param; 1160 struct dma_chan *chan; 1161 struct mmc_data *data; 1162 int req_in_progress; 1163 1164 spin_lock_irq(&host->irq_lock); 1165 if (host->dma_ch < 0) { 1166 spin_unlock_irq(&host->irq_lock); 1167 return; 1168 } 1169 1170 data = host->mrq->data; 1171 chan = omap_hsmmc_get_dma_chan(host, data); 1172 if (!data->host_cookie) 1173 dma_unmap_sg(chan->device->dev, 1174 data->sg, data->sg_len, 1175 mmc_get_dma_dir(data)); 1176 1177 req_in_progress = host->req_in_progress; 1178 host->dma_ch = -1; 1179 spin_unlock_irq(&host->irq_lock); 1180 1181 /* If DMA has finished after TC, complete the request */ 1182 if (!req_in_progress) { 1183 struct mmc_request *mrq = host->mrq; 1184 1185 host->mrq = NULL; 1186 mmc_request_done(host->mmc, mrq); 1187 } 1188} 1189 1190static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 1191 struct mmc_data *data, 1192 struct omap_hsmmc_next *next, 1193 struct dma_chan *chan) 1194{ 1195 int dma_len; 1196 1197 if (!next && data->host_cookie && 1198 data->host_cookie != host->next_data.cookie) { 1199 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 1200 " host->next_data.cookie %d\n", 1201 __func__, data->host_cookie, host->next_data.cookie); 1202 data->host_cookie = 0; 1203 } 1204 1205 /* Check if next job is already prepared */ 1206 if (next || data->host_cookie != host->next_data.cookie) { 1207 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1208 mmc_get_dma_dir(data)); 1209 1210 } else { 1211 dma_len = host->next_data.dma_len; 1212 host->next_data.dma_len = 0; 1213 } 1214 1215 1216 if (dma_len == 0) 1217 return -EINVAL; 1218 1219 if (next) { 1220 next->dma_len = dma_len; 1221 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 1222 } else 1223 host->dma_len = dma_len; 1224 1225 return 0; 1226} 1227 1228/* 1229 * Routine to configure and start DMA for the MMC card 1230 */ 1231static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 1232 struct mmc_request *req) 1233{ 1234 struct dma_async_tx_descriptor *tx; 1235 int ret = 0, i; 1236 struct mmc_data *data = req->data; 1237 struct dma_chan *chan; 1238 struct dma_slave_config cfg = { 1239 .src_addr = host->mapbase + OMAP_HSMMC_DATA, 1240 .dst_addr = host->mapbase + OMAP_HSMMC_DATA, 1241 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1242 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1243 .src_maxburst = data->blksz / 4, 1244 .dst_maxburst = data->blksz / 4, 1245 }; 1246 1247 /* Sanity check: all the SG entries must be aligned by block size. */ 1248 for (i = 0; i < data->sg_len; i++) { 1249 struct scatterlist *sgl; 1250 1251 sgl = data->sg + i; 1252 if (sgl->length % data->blksz) 1253 return -EINVAL; 1254 } 1255 if ((data->blksz % 4) != 0) 1256 /* REVISIT: The MMC buffer increments only when MSB is written. 1257 * Return error for blksz which is non multiple of four. 1258 */ 1259 return -EINVAL; 1260 1261 BUG_ON(host->dma_ch != -1); 1262 1263 chan = omap_hsmmc_get_dma_chan(host, data); 1264 1265 ret = dmaengine_slave_config(chan, &cfg); 1266 if (ret) 1267 return ret; 1268 1269 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1270 if (ret) 1271 return ret; 1272 1273 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1274 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1275 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1276 if (!tx) { 1277 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1278 /* FIXME: cleanup */ 1279 return -1; 1280 } 1281 1282 tx->callback = omap_hsmmc_dma_callback; 1283 tx->callback_param = host; 1284 1285 /* Does not fail */ 1286 dmaengine_submit(tx); 1287 1288 host->dma_ch = 1; 1289 1290 return 0; 1291} 1292 1293static void set_data_timeout(struct omap_hsmmc_host *host, 1294 unsigned long long timeout_ns, 1295 unsigned int timeout_clks) 1296{ 1297 unsigned long long timeout = timeout_ns; 1298 unsigned int cycle_ns; 1299 uint32_t reg, clkd, dto = 0; 1300 1301 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1302 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1303 if (clkd == 0) 1304 clkd = 1; 1305 1306 cycle_ns = 1000000000 / (host->clk_rate / clkd); 1307 do_div(timeout, cycle_ns); 1308 timeout += timeout_clks; 1309 if (timeout) { 1310 while ((timeout & 0x80000000) == 0) { 1311 dto += 1; 1312 timeout <<= 1; 1313 } 1314 dto = 31 - dto; 1315 timeout <<= 1; 1316 if (timeout && dto) 1317 dto += 1; 1318 if (dto >= 13) 1319 dto -= 13; 1320 else 1321 dto = 0; 1322 if (dto > 14) 1323 dto = 14; 1324 } 1325 1326 reg &= ~DTO_MASK; 1327 reg |= dto << DTO_SHIFT; 1328 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1329} 1330 1331static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 1332{ 1333 struct mmc_request *req = host->mrq; 1334 struct dma_chan *chan; 1335 1336 if (!req->data) 1337 return; 1338 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1339 | (req->data->blocks << 16)); 1340 set_data_timeout(host, req->data->timeout_ns, 1341 req->data->timeout_clks); 1342 chan = omap_hsmmc_get_dma_chan(host, req->data); 1343 dma_async_issue_pending(chan); 1344} 1345 1346/* 1347 * Configure block length for MMC/SD cards and initiate the transfer. 1348 */ 1349static int 1350omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1351{ 1352 int ret; 1353 unsigned long long timeout; 1354 1355 host->data = req->data; 1356 1357 if (req->data == NULL) { 1358 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1359 if (req->cmd->flags & MMC_RSP_BUSY) { 1360 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; 1361 1362 /* 1363 * Set an arbitrary 100ms data timeout for commands with 1364 * busy signal and no indication of busy_timeout. 1365 */ 1366 if (!timeout) 1367 timeout = 100000000U; 1368 1369 set_data_timeout(host, timeout, 0); 1370 } 1371 return 0; 1372 } 1373 1374 if (host->use_dma) { 1375 ret = omap_hsmmc_setup_dma_transfer(host, req); 1376 if (ret != 0) { 1377 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1378 return ret; 1379 } 1380 } 1381 return 0; 1382} 1383 1384static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1385 int err) 1386{ 1387 struct omap_hsmmc_host *host = mmc_priv(mmc); 1388 struct mmc_data *data = mrq->data; 1389 1390 if (host->use_dma && data->host_cookie) { 1391 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1392 1393 dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1394 mmc_get_dma_dir(data)); 1395 data->host_cookie = 0; 1396 } 1397} 1398 1399static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1400{ 1401 struct omap_hsmmc_host *host = mmc_priv(mmc); 1402 1403 if (mrq->data->host_cookie) { 1404 mrq->data->host_cookie = 0; 1405 return ; 1406 } 1407 1408 if (host->use_dma) { 1409 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1410 1411 if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 1412 &host->next_data, c)) 1413 mrq->data->host_cookie = 0; 1414 } 1415} 1416 1417/* 1418 * Request function. for read/write operation 1419 */ 1420static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1421{ 1422 struct omap_hsmmc_host *host = mmc_priv(mmc); 1423 int err; 1424 1425 BUG_ON(host->req_in_progress); 1426 BUG_ON(host->dma_ch != -1); 1427 if (host->reqs_blocked) 1428 host->reqs_blocked = 0; 1429 WARN_ON(host->mrq != NULL); 1430 host->mrq = req; 1431 host->clk_rate = clk_get_rate(host->fclk); 1432 err = omap_hsmmc_prepare_data(host, req); 1433 if (err) { 1434 req->cmd->error = err; 1435 if (req->data) 1436 req->data->error = err; 1437 host->mrq = NULL; 1438 mmc_request_done(mmc, req); 1439 return; 1440 } 1441 if (req->sbc && !(host->flags & AUTO_CMD23)) { 1442 omap_hsmmc_start_command(host, req->sbc, NULL); 1443 return; 1444 } 1445 1446 omap_hsmmc_start_dma_transfer(host); 1447 omap_hsmmc_start_command(host, req->cmd, req->data); 1448} 1449 1450/* Routine to configure clock values. Exposed API to core */ 1451static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1452{ 1453 struct omap_hsmmc_host *host = mmc_priv(mmc); 1454 int do_send_init_stream = 0; 1455 1456 if (ios->power_mode != host->power_mode) { 1457 switch (ios->power_mode) { 1458 case MMC_POWER_OFF: 1459 omap_hsmmc_set_power(host, 0); 1460 break; 1461 case MMC_POWER_UP: 1462 omap_hsmmc_set_power(host, 1); 1463 break; 1464 case MMC_POWER_ON: 1465 do_send_init_stream = 1; 1466 break; 1467 } 1468 host->power_mode = ios->power_mode; 1469 } 1470 1471 /* FIXME: set registers based only on changes to ios */ 1472 1473 omap_hsmmc_set_bus_width(host); 1474 1475 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1476 /* Only MMC1 can interface at 3V without some flavor 1477 * of external transceiver; but they all handle 1.8V. 1478 */ 1479 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1480 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1481 /* 1482 * The mmc_select_voltage fn of the core does 1483 * not seem to set the power_mode to 1484 * MMC_POWER_UP upon recalculating the voltage. 1485 * vdd 1.8v. 1486 */ 1487 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1488 dev_dbg(mmc_dev(host->mmc), 1489 "Switch operation failed\n"); 1490 } 1491 } 1492 1493 omap_hsmmc_set_clock(host); 1494 1495 if (do_send_init_stream) 1496 send_init_stream(host); 1497 1498 omap_hsmmc_set_bus_mode(host); 1499} 1500 1501static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 1502{ 1503 struct omap_hsmmc_host *host = mmc_priv(mmc); 1504 u32 irq_mask, con; 1505 unsigned long flags; 1506 1507 spin_lock_irqsave(&host->irq_lock, flags); 1508 1509 con = OMAP_HSMMC_READ(host->base, CON); 1510 irq_mask = OMAP_HSMMC_READ(host->base, ISE); 1511 if (enable) { 1512 host->flags |= HSMMC_SDIO_IRQ_ENABLED; 1513 irq_mask |= CIRQ_EN; 1514 con |= CTPL | CLKEXTFREE; 1515 } else { 1516 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 1517 irq_mask &= ~CIRQ_EN; 1518 con &= ~(CTPL | CLKEXTFREE); 1519 } 1520 OMAP_HSMMC_WRITE(host->base, CON, con); 1521 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 1522 1523 /* 1524 * if enable, piggy back detection on current request 1525 * but always disable immediately 1526 */ 1527 if (!host->req_in_progress || !enable) 1528 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 1529 1530 /* flush posted write */ 1531 OMAP_HSMMC_READ(host->base, IE); 1532 1533 spin_unlock_irqrestore(&host->irq_lock, flags); 1534} 1535 1536static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 1537{ 1538 int ret; 1539 1540 /* 1541 * For omaps with wake-up path, wakeirq will be irq from pinctrl and 1542 * for other omaps, wakeirq will be from GPIO (dat line remuxed to 1543 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 1544 * with functional clock disabled. 1545 */ 1546 if (!host->dev->of_node || !host->wake_irq) 1547 return -ENODEV; 1548 1549 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 1550 if (ret) { 1551 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 1552 goto err; 1553 } 1554 1555 /* 1556 * Some omaps don't have wake-up path from deeper idle states 1557 * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 1558 */ 1559 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1560 struct pinctrl *p = devm_pinctrl_get(host->dev); 1561 if (IS_ERR(p)) { 1562 ret = PTR_ERR(p); 1563 goto err_free_irq; 1564 } 1565 1566 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1567 dev_info(host->dev, "missing idle pinctrl state\n"); 1568 devm_pinctrl_put(p); 1569 ret = -EINVAL; 1570 goto err_free_irq; 1571 } 1572 devm_pinctrl_put(p); 1573 } 1574 1575 OMAP_HSMMC_WRITE(host->base, HCTL, 1576 OMAP_HSMMC_READ(host->base, HCTL) | IWE); 1577 return 0; 1578 1579err_free_irq: 1580 dev_pm_clear_wake_irq(host->dev); 1581err: 1582 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 1583 host->wake_irq = 0; 1584 return ret; 1585} 1586 1587static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1588{ 1589 u32 hctl, capa, value; 1590 1591 /* Only MMC1 supports 3.0V */ 1592 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1593 hctl = SDVS30; 1594 capa = VS30 | VS18; 1595 } else { 1596 hctl = SDVS18; 1597 capa = VS18; 1598 } 1599 1600 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1601 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1602 1603 value = OMAP_HSMMC_READ(host->base, CAPA); 1604 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1605 1606 /* Set SD bus power bit */ 1607 set_sd_bus_power(host); 1608} 1609 1610static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1611 unsigned int direction, int blk_size) 1612{ 1613 /* This controller can't do multiblock reads due to hw bugs */ 1614 if (direction == MMC_DATA_READ) 1615 return 1; 1616 1617 return blk_size; 1618} 1619 1620static struct mmc_host_ops omap_hsmmc_ops = { 1621 .post_req = omap_hsmmc_post_req, 1622 .pre_req = omap_hsmmc_pre_req, 1623 .request = omap_hsmmc_request, 1624 .set_ios = omap_hsmmc_set_ios, 1625 .get_cd = mmc_gpio_get_cd, 1626 .get_ro = mmc_gpio_get_ro, 1627 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1628}; 1629 1630#ifdef CONFIG_DEBUG_FS 1631 1632static int mmc_regs_show(struct seq_file *s, void *data) 1633{ 1634 struct mmc_host *mmc = s->private; 1635 struct omap_hsmmc_host *host = mmc_priv(mmc); 1636 1637 seq_printf(s, "mmc%d:\n", mmc->index); 1638 seq_printf(s, "sdio irq mode\t%s\n", 1639 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1640 1641 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1642 seq_printf(s, "sdio irq \t%s\n", 1643 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1644 : "disabled"); 1645 } 1646 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 1647 1648 pm_runtime_get_sync(host->dev); 1649 seq_puts(s, "\nregs:\n"); 1650 seq_printf(s, "CON:\t\t0x%08x\n", 1651 OMAP_HSMMC_READ(host->base, CON)); 1652 seq_printf(s, "PSTATE:\t\t0x%08x\n", 1653 OMAP_HSMMC_READ(host->base, PSTATE)); 1654 seq_printf(s, "HCTL:\t\t0x%08x\n", 1655 OMAP_HSMMC_READ(host->base, HCTL)); 1656 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1657 OMAP_HSMMC_READ(host->base, SYSCTL)); 1658 seq_printf(s, "IE:\t\t0x%08x\n", 1659 OMAP_HSMMC_READ(host->base, IE)); 1660 seq_printf(s, "ISE:\t\t0x%08x\n", 1661 OMAP_HSMMC_READ(host->base, ISE)); 1662 seq_printf(s, "CAPA:\t\t0x%08x\n", 1663 OMAP_HSMMC_READ(host->base, CAPA)); 1664 1665 pm_runtime_put_autosuspend(host->dev); 1666 1667 return 0; 1668} 1669 1670DEFINE_SHOW_ATTRIBUTE(mmc_regs); 1671 1672static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1673{ 1674 if (mmc->debugfs_root) 1675 debugfs_create_file("regs", 0400, mmc->debugfs_root, 1676 mmc, &mmc_regs_fops); 1677} 1678 1679#else 1680 1681static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1682{ 1683} 1684 1685#endif 1686 1687#ifdef CONFIG_OF 1688static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 1689 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1690 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1691}; 1692 1693static const struct omap_mmc_of_data omap4_mmc_of_data = { 1694 .reg_offset = 0x100, 1695}; 1696static const struct omap_mmc_of_data am33xx_mmc_of_data = { 1697 .reg_offset = 0x100, 1698 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 1699}; 1700 1701static const struct of_device_id omap_mmc_of_match[] = { 1702 { 1703 .compatible = "ti,omap2-hsmmc", 1704 }, 1705 { 1706 .compatible = "ti,omap3-pre-es3-hsmmc", 1707 .data = &omap3_pre_es3_mmc_of_data, 1708 }, 1709 { 1710 .compatible = "ti,omap3-hsmmc", 1711 }, 1712 { 1713 .compatible = "ti,omap4-hsmmc", 1714 .data = &omap4_mmc_of_data, 1715 }, 1716 { 1717 .compatible = "ti,am33xx-hsmmc", 1718 .data = &am33xx_mmc_of_data, 1719 }, 1720 {}, 1721}; 1722MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 1723 1724static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 1725{ 1726 struct omap_hsmmc_platform_data *pdata, *legacy; 1727 struct device_node *np = dev->of_node; 1728 1729 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1730 if (!pdata) 1731 return ERR_PTR(-ENOMEM); /* out of memory */ 1732 1733 legacy = dev_get_platdata(dev); 1734 if (legacy && legacy->name) 1735 pdata->name = legacy->name; 1736 1737 if (of_property_read_bool(np, "ti,dual-volt")) 1738 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1739 1740 if (of_property_read_bool(np, "ti,non-removable")) { 1741 pdata->nonremovable = true; 1742 pdata->no_regulator_off_init = true; 1743 } 1744 1745 if (of_property_read_bool(np, "ti,needs-special-reset")) 1746 pdata->features |= HSMMC_HAS_UPDATED_RESET; 1747 1748 if (of_property_read_bool(np, "ti,needs-special-hs-handling")) 1749 pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1750 1751 return pdata; 1752} 1753#else 1754static inline struct omap_hsmmc_platform_data 1755 *of_get_hsmmc_pdata(struct device *dev) 1756{ 1757 return ERR_PTR(-EINVAL); 1758} 1759#endif 1760 1761static int omap_hsmmc_probe(struct platform_device *pdev) 1762{ 1763 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1764 struct mmc_host *mmc; 1765 struct omap_hsmmc_host *host = NULL; 1766 struct resource *res; 1767 int ret, irq; 1768 const struct of_device_id *match; 1769 const struct omap_mmc_of_data *data; 1770 void __iomem *base; 1771 1772 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 1773 if (match) { 1774 pdata = of_get_hsmmc_pdata(&pdev->dev); 1775 1776 if (IS_ERR(pdata)) 1777 return PTR_ERR(pdata); 1778 1779 if (match->data) { 1780 data = match->data; 1781 pdata->reg_offset = data->reg_offset; 1782 pdata->controller_flags |= data->controller_flags; 1783 } 1784 } 1785 1786 if (pdata == NULL) { 1787 dev_err(&pdev->dev, "Platform Data is missing\n"); 1788 return -ENXIO; 1789 } 1790 1791 irq = platform_get_irq(pdev, 0); 1792 if (irq < 0) 1793 return irq; 1794 1795 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1796 if (IS_ERR(base)) 1797 return PTR_ERR(base); 1798 1799 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1800 if (!mmc) 1801 return -ENOMEM; 1802 1803 ret = mmc_of_parse(mmc); 1804 if (ret) 1805 return ret; 1806 1807 host = mmc_priv(mmc); 1808 host->mmc = mmc; 1809 host->pdata = pdata; 1810 host->dev = &pdev->dev; 1811 host->use_dma = 1; 1812 host->dma_ch = -1; 1813 host->irq = irq; 1814 host->mapbase = res->start + pdata->reg_offset; 1815 host->base = base + pdata->reg_offset; 1816 host->power_mode = MMC_POWER_OFF; 1817 host->next_data.cookie = 1; 1818 host->pbias_enabled = false; 1819 host->vqmmc_enabled = false; 1820 1821 platform_set_drvdata(pdev, host); 1822 1823 if (pdev->dev.of_node) 1824 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1825 1826 mmc->ops = &omap_hsmmc_ops; 1827 1828 mmc->f_min = OMAP_MMC_MIN_CLOCK; 1829 1830 if (pdata->max_freq > 0) 1831 mmc->f_max = pdata->max_freq; 1832 else if (mmc->f_max == 0) 1833 mmc->f_max = OMAP_MMC_MAX_CLOCK; 1834 1835 spin_lock_init(&host->irq_lock); 1836 1837 host->fclk = devm_clk_get(&pdev->dev, "fck"); 1838 if (IS_ERR(host->fclk)) { 1839 ret = PTR_ERR(host->fclk); 1840 host->fclk = NULL; 1841 return ret; 1842 } 1843 1844 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 1845 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 1846 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 1847 } 1848 1849 device_init_wakeup(&pdev->dev, true); 1850 pm_runtime_enable(host->dev); 1851 pm_runtime_get_sync(host->dev); 1852 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1853 pm_runtime_use_autosuspend(host->dev); 1854 1855 omap_hsmmc_context_save(host); 1856 1857 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 1858 /* 1859 * MMC can still work without debounce clock. 1860 */ 1861 if (IS_ERR(host->dbclk)) { 1862 host->dbclk = NULL; 1863 } else if (clk_prepare_enable(host->dbclk) != 0) { 1864 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1865 host->dbclk = NULL; 1866 } 1867 1868 /* Set this to a value that allows allocating an entire descriptor 1869 * list within a page (zero order allocation). */ 1870 mmc->max_segs = 64; 1871 1872 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1873 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1874 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1875 1876 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1877 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23; 1878 1879 mmc->caps |= mmc_pdata(host)->caps; 1880 if (mmc->caps & MMC_CAP_8_BIT_DATA) 1881 mmc->caps |= MMC_CAP_4_BIT_DATA; 1882 1883 if (mmc_pdata(host)->nonremovable) 1884 mmc->caps |= MMC_CAP_NONREMOVABLE; 1885 1886 mmc->pm_caps |= mmc_pdata(host)->pm_caps; 1887 1888 omap_hsmmc_conf_bus_power(host); 1889 1890 host->rx_chan = dma_request_chan(&pdev->dev, "rx"); 1891 if (IS_ERR(host->rx_chan)) { 1892 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); 1893 ret = PTR_ERR(host->rx_chan); 1894 goto err_irq; 1895 } 1896 1897 host->tx_chan = dma_request_chan(&pdev->dev, "tx"); 1898 if (IS_ERR(host->tx_chan)) { 1899 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); 1900 ret = PTR_ERR(host->tx_chan); 1901 goto err_irq; 1902 } 1903 1904 /* 1905 * Limit the maximum segment size to the lower of the request size 1906 * and the DMA engine device segment size limits. In reality, with 1907 * 32-bit transfers, the DMA engine can do longer segments than this 1908 * but there is no way to represent that in the DMA model - if we 1909 * increase this figure here, we get warnings from the DMA API debug. 1910 */ 1911 mmc->max_seg_size = min3(mmc->max_req_size, 1912 dma_get_max_seg_size(host->rx_chan->device->dev), 1913 dma_get_max_seg_size(host->tx_chan->device->dev)); 1914 1915 /* Request IRQ for MMC operations */ 1916 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 1917 mmc_hostname(mmc), host); 1918 if (ret) { 1919 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1920 goto err_irq; 1921 } 1922 1923 ret = omap_hsmmc_reg_get(host); 1924 if (ret) 1925 goto err_irq; 1926 1927 if (!mmc->ocr_avail) 1928 mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 1929 1930 omap_hsmmc_disable_irq(host); 1931 1932 /* 1933 * For now, only support SDIO interrupt if we have a separate 1934 * wake-up interrupt configured from device tree. This is because 1935 * the wake-up interrupt is needed for idle state and some 1936 * platforms need special quirks. And we don't want to add new 1937 * legacy mux platform init code callbacks any longer as we 1938 * are moving to DT based booting anyways. 1939 */ 1940 ret = omap_hsmmc_configure_wake_irq(host); 1941 if (!ret) 1942 mmc->caps |= MMC_CAP_SDIO_IRQ; 1943 1944 ret = mmc_add_host(mmc); 1945 if (ret) 1946 goto err_irq; 1947 1948 if (mmc_pdata(host)->name != NULL) { 1949 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1950 if (ret < 0) 1951 goto err_slot_name; 1952 } 1953 1954 omap_hsmmc_debugfs(mmc); 1955 pm_runtime_put_autosuspend(host->dev); 1956 1957 return 0; 1958 1959err_slot_name: 1960 mmc_remove_host(mmc); 1961err_irq: 1962 device_init_wakeup(&pdev->dev, false); 1963 if (!IS_ERR_OR_NULL(host->tx_chan)) 1964 dma_release_channel(host->tx_chan); 1965 if (!IS_ERR_OR_NULL(host->rx_chan)) 1966 dma_release_channel(host->rx_chan); 1967 pm_runtime_dont_use_autosuspend(host->dev); 1968 pm_runtime_put_sync(host->dev); 1969 pm_runtime_disable(host->dev); 1970 clk_disable_unprepare(host->dbclk); 1971 return ret; 1972} 1973 1974static void omap_hsmmc_remove(struct platform_device *pdev) 1975{ 1976 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 1977 1978 pm_runtime_get_sync(host->dev); 1979 mmc_remove_host(host->mmc); 1980 1981 dma_release_channel(host->tx_chan); 1982 dma_release_channel(host->rx_chan); 1983 1984 dev_pm_clear_wake_irq(host->dev); 1985 pm_runtime_dont_use_autosuspend(host->dev); 1986 pm_runtime_put_sync(host->dev); 1987 pm_runtime_disable(host->dev); 1988 device_init_wakeup(&pdev->dev, false); 1989 clk_disable_unprepare(host->dbclk); 1990} 1991 1992static int omap_hsmmc_suspend(struct device *dev) 1993{ 1994 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 1995 1996 if (!host) 1997 return 0; 1998 1999 pm_runtime_get_sync(host->dev); 2000 2001 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 2002 OMAP_HSMMC_WRITE(host->base, ISE, 0); 2003 OMAP_HSMMC_WRITE(host->base, IE, 0); 2004 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2005 OMAP_HSMMC_WRITE(host->base, HCTL, 2006 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2007 } 2008 2009 clk_disable_unprepare(host->dbclk); 2010 2011 pm_runtime_put_sync(host->dev); 2012 return 0; 2013} 2014 2015/* Routine to resume the MMC device */ 2016static int omap_hsmmc_resume(struct device *dev) 2017{ 2018 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2019 2020 if (!host) 2021 return 0; 2022 2023 pm_runtime_get_sync(host->dev); 2024 2025 clk_prepare_enable(host->dbclk); 2026 2027 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 2028 omap_hsmmc_conf_bus_power(host); 2029 2030 pm_runtime_put_autosuspend(host->dev); 2031 return 0; 2032} 2033 2034static int omap_hsmmc_runtime_suspend(struct device *dev) 2035{ 2036 struct omap_hsmmc_host *host; 2037 unsigned long flags; 2038 int ret = 0; 2039 2040 host = dev_get_drvdata(dev); 2041 omap_hsmmc_context_save(host); 2042 dev_dbg(dev, "disabled\n"); 2043 2044 spin_lock_irqsave(&host->irq_lock, flags); 2045 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 2046 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 2047 /* disable sdio irq handling to prevent race */ 2048 OMAP_HSMMC_WRITE(host->base, ISE, 0); 2049 OMAP_HSMMC_WRITE(host->base, IE, 0); 2050 2051 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2052 /* 2053 * dat1 line low, pending sdio irq 2054 * race condition: possible irq handler running on 2055 * multi-core, abort 2056 */ 2057 dev_dbg(dev, "pending sdio irq, abort suspend\n"); 2058 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2059 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2060 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2061 pm_runtime_mark_last_busy(dev); 2062 ret = -EBUSY; 2063 goto abort; 2064 } 2065 2066 pinctrl_pm_select_idle_state(dev); 2067 } else { 2068 pinctrl_pm_select_idle_state(dev); 2069 } 2070 2071abort: 2072 spin_unlock_irqrestore(&host->irq_lock, flags); 2073 return ret; 2074} 2075 2076static int omap_hsmmc_runtime_resume(struct device *dev) 2077{ 2078 struct omap_hsmmc_host *host; 2079 unsigned long flags; 2080 2081 host = dev_get_drvdata(dev); 2082 omap_hsmmc_context_restore(host); 2083 dev_dbg(dev, "enabled\n"); 2084 2085 spin_lock_irqsave(&host->irq_lock, flags); 2086 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 2087 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 2088 2089 pinctrl_select_default_state(host->dev); 2090 2091 /* irq lost, if pinmux incorrect */ 2092 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2093 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2094 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2095 } else { 2096 pinctrl_select_default_state(host->dev); 2097 } 2098 spin_unlock_irqrestore(&host->irq_lock, flags); 2099 return 0; 2100} 2101 2102static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2103 SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2104 RUNTIME_PM_OPS(omap_hsmmc_runtime_suspend, omap_hsmmc_runtime_resume, NULL) 2105}; 2106 2107static struct platform_driver omap_hsmmc_driver = { 2108 .probe = omap_hsmmc_probe, 2109 .remove = omap_hsmmc_remove, 2110 .driver = { 2111 .name = DRIVER_NAME, 2112 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2113 .pm = pm_ptr(&omap_hsmmc_dev_pm_ops), 2114 .of_match_table = of_match_ptr(omap_mmc_of_match), 2115 }, 2116}; 2117 2118module_platform_driver(omap_hsmmc_driver); 2119MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2120MODULE_LICENSE("GPL"); 2121MODULE_ALIAS("platform:" DRIVER_NAME); 2122MODULE_AUTHOR("Texas Instruments Inc");
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