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omap.c
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linux-6.19.14/drivers/mmc/host/omap.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/drivers/mmc/host/omap.c 4 * 5 * Copyright (C) 2004 Nokia Corporation 6 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com> 7 * Misc hacks here and there by Tony Lindgren <tony@atomide.com> 8 * Other hacks (DMA, SD, etc) by David Brownell 9 */ 10 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/platform_device.h> 16#include <linux/interrupt.h> 17#include <linux/dmaengine.h> 18#include <linux/dma-mapping.h> 19#include <linux/delay.h> 20#include <linux/spinlock.h> 21#include <linux/timer.h> 22#include <linux/of.h> 23#include <linux/mmc/host.h> 24#include <linux/mmc/card.h> 25#include <linux/mmc/mmc.h> 26#include <linux/clk.h> 27#include <linux/scatterlist.h> 28#include <linux/slab.h> 29#include <linux/gpio/consumer.h> 30#include <linux/platform_data/mmc-omap.h> 31#include <linux/workqueue.h> 32 33 34#define OMAP_MMC_REG_CMD 0x00 35#define OMAP_MMC_REG_ARGL 0x01 36#define OMAP_MMC_REG_ARGH 0x02 37#define OMAP_MMC_REG_CON 0x03 38#define OMAP_MMC_REG_STAT 0x04 39#define OMAP_MMC_REG_IE 0x05 40#define OMAP_MMC_REG_CTO 0x06 41#define OMAP_MMC_REG_DTO 0x07 42#define OMAP_MMC_REG_DATA 0x08 43#define OMAP_MMC_REG_BLEN 0x09 44#define OMAP_MMC_REG_NBLK 0x0a 45#define OMAP_MMC_REG_BUF 0x0b 46#define OMAP_MMC_REG_SDIO 0x0d 47#define OMAP_MMC_REG_REV 0x0f 48#define OMAP_MMC_REG_RSP0 0x10 49#define OMAP_MMC_REG_RSP1 0x11 50#define OMAP_MMC_REG_RSP2 0x12 51#define OMAP_MMC_REG_RSP3 0x13 52#define OMAP_MMC_REG_RSP4 0x14 53#define OMAP_MMC_REG_RSP5 0x15 54#define OMAP_MMC_REG_RSP6 0x16 55#define OMAP_MMC_REG_RSP7 0x17 56#define OMAP_MMC_REG_IOSR 0x18 57#define OMAP_MMC_REG_SYSC 0x19 58#define OMAP_MMC_REG_SYSS 0x1a 59 60#define OMAP_MMC_STAT_CARD_ERR (1 << 14) 61#define OMAP_MMC_STAT_CARD_IRQ (1 << 13) 62#define OMAP_MMC_STAT_OCR_BUSY (1 << 12) 63#define OMAP_MMC_STAT_A_EMPTY (1 << 11) 64#define OMAP_MMC_STAT_A_FULL (1 << 10) 65#define OMAP_MMC_STAT_CMD_CRC (1 << 8) 66#define OMAP_MMC_STAT_CMD_TOUT (1 << 7) 67#define OMAP_MMC_STAT_DATA_CRC (1 << 6) 68#define OMAP_MMC_STAT_DATA_TOUT (1 << 5) 69#define OMAP_MMC_STAT_END_BUSY (1 << 4) 70#define OMAP_MMC_STAT_END_OF_DATA (1 << 3) 71#define OMAP_MMC_STAT_CARD_BUSY (1 << 2) 72#define OMAP_MMC_STAT_END_OF_CMD (1 << 0) 73 74#define mmc_omap7xx() (host->features & MMC_OMAP7XX) 75#define mmc_omap15xx() (host->features & MMC_OMAP15XX) 76#define mmc_omap16xx() (host->features & MMC_OMAP16XX) 77#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX) 78#define mmc_omap1() (host->features & MMC_OMAP1_MASK) 79#define mmc_omap2() (!mmc_omap1()) 80 81#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift) 82#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg)) 83#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) 84 85/* 86 * Command types 87 */ 88#define OMAP_MMC_CMDTYPE_BC 0 89#define OMAP_MMC_CMDTYPE_BCR 1 90#define OMAP_MMC_CMDTYPE_AC 2 91#define OMAP_MMC_CMDTYPE_ADTC 3 92 93#define DRIVER_NAME "mmci-omap" 94 95/* Specifies how often in millisecs to poll for card status changes 96 * when the cover switch is open */ 97#define OMAP_MMC_COVER_POLL_DELAY 500 98 99struct mmc_omap_host; 100 101struct mmc_omap_slot { 102 int id; 103 unsigned int vdd; 104 u16 saved_con; 105 u16 bus_mode; 106 u16 power_mode; 107 unsigned int fclk_freq; 108 109 struct work_struct cover_bh_work; 110 struct timer_list cover_timer; 111 unsigned cover_open; 112 113 struct mmc_request *mrq; 114 struct mmc_omap_host *host; 115 struct mmc_host *mmc; 116 struct gpio_desc *vsd; 117 struct gpio_desc *vio; 118 struct gpio_desc *cover; 119 struct omap_mmc_slot_data *pdata; 120}; 121 122struct mmc_omap_host { 123 int initialized; 124 struct mmc_request * mrq; 125 struct mmc_command * cmd; 126 struct mmc_data * data; 127 struct mmc_host * mmc; 128 struct device * dev; 129 unsigned char id; /* 16xx chips have 2 MMC blocks */ 130 struct clk * iclk; 131 struct clk * fclk; 132 struct dma_chan *dma_rx; 133 u32 dma_rx_burst; 134 struct dma_chan *dma_tx; 135 u32 dma_tx_burst; 136 void __iomem *virt_base; 137 unsigned int phys_base; 138 int irq; 139 unsigned char bus_mode; 140 unsigned int reg_shift; 141 struct gpio_desc *slot_switch; 142 143 struct work_struct cmd_abort_work; 144 unsigned abort:1; 145 struct timer_list cmd_abort_timer; 146 147 struct work_struct slot_release_work; 148 struct mmc_omap_slot *next_slot; 149 struct work_struct send_stop_work; 150 struct mmc_data *stop_data; 151 152 struct sg_mapping_iter sg_miter; 153 unsigned int sg_len; 154 u32 total_bytes_left; 155 156 unsigned features; 157 unsigned brs_received:1, dma_done:1; 158 unsigned dma_in_use:1; 159 spinlock_t dma_lock; 160 161 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS]; 162 struct mmc_omap_slot *current_slot; 163 spinlock_t slot_lock; 164 wait_queue_head_t slot_wq; 165 int nr_slots; 166 167 struct timer_list clk_timer; 168 spinlock_t clk_lock; /* for changing enabled state */ 169 unsigned int fclk_enabled:1; 170 struct workqueue_struct *mmc_omap_wq; 171 172 struct omap_mmc_platform_data *pdata; 173}; 174 175 176static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot) 177{ 178 unsigned long tick_ns; 179 180 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) { 181 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq); 182 ndelay(8 * tick_ns); 183 } 184} 185 186static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable) 187{ 188 unsigned long flags; 189 190 spin_lock_irqsave(&host->clk_lock, flags); 191 if (host->fclk_enabled != enable) { 192 host->fclk_enabled = enable; 193 if (enable) 194 clk_enable(host->fclk); 195 else 196 clk_disable(host->fclk); 197 } 198 spin_unlock_irqrestore(&host->clk_lock, flags); 199} 200 201static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed) 202{ 203 struct mmc_omap_host *host = slot->host; 204 unsigned long flags; 205 206 if (claimed) 207 goto no_claim; 208 spin_lock_irqsave(&host->slot_lock, flags); 209 while (host->mmc != NULL) { 210 spin_unlock_irqrestore(&host->slot_lock, flags); 211 wait_event(host->slot_wq, host->mmc == NULL); 212 spin_lock_irqsave(&host->slot_lock, flags); 213 } 214 host->mmc = slot->mmc; 215 spin_unlock_irqrestore(&host->slot_lock, flags); 216no_claim: 217 timer_delete(&host->clk_timer); 218 if (host->current_slot != slot || !claimed) 219 mmc_omap_fclk_offdelay(host->current_slot); 220 221 if (host->current_slot != slot) { 222 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00); 223 if (host->slot_switch) 224 /* 225 * With two slots and a simple GPIO switch, setting 226 * the GPIO to 0 selects slot ID 0, setting it to 1 227 * selects slot ID 1. 228 */ 229 gpiod_set_value(host->slot_switch, slot->id); 230 host->current_slot = slot; 231 } 232 233 if (claimed) { 234 mmc_omap_fclk_enable(host, 1); 235 236 /* Doing the dummy read here seems to work around some bug 237 * at least in OMAP24xx silicon where the command would not 238 * start after writing the CMD register. Sigh. */ 239 OMAP_MMC_READ(host, CON); 240 241 OMAP_MMC_WRITE(host, CON, slot->saved_con); 242 } else 243 mmc_omap_fclk_enable(host, 0); 244} 245 246static void mmc_omap_start_request(struct mmc_omap_host *host, 247 struct mmc_request *req); 248 249static void mmc_omap_slot_release_work(struct work_struct *work) 250{ 251 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 252 slot_release_work); 253 struct mmc_omap_slot *next_slot = host->next_slot; 254 struct mmc_request *rq; 255 256 host->next_slot = NULL; 257 mmc_omap_select_slot(next_slot, 1); 258 259 rq = next_slot->mrq; 260 next_slot->mrq = NULL; 261 mmc_omap_start_request(host, rq); 262} 263 264static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled) 265{ 266 struct mmc_omap_host *host = slot->host; 267 unsigned long flags; 268 int i; 269 270 BUG_ON(slot == NULL || host->mmc == NULL); 271 272 if (clk_enabled) 273 /* Keeps clock running for at least 8 cycles on valid freq */ 274 mod_timer(&host->clk_timer, jiffies + HZ/10); 275 else { 276 timer_delete(&host->clk_timer); 277 mmc_omap_fclk_offdelay(slot); 278 mmc_omap_fclk_enable(host, 0); 279 } 280 281 spin_lock_irqsave(&host->slot_lock, flags); 282 /* Check for any pending requests */ 283 for (i = 0; i < host->nr_slots; i++) { 284 struct mmc_omap_slot *new_slot; 285 286 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL) 287 continue; 288 289 BUG_ON(host->next_slot != NULL); 290 new_slot = host->slots[i]; 291 /* The current slot should not have a request in queue */ 292 BUG_ON(new_slot == host->current_slot); 293 294 host->next_slot = new_slot; 295 host->mmc = new_slot->mmc; 296 spin_unlock_irqrestore(&host->slot_lock, flags); 297 queue_work(host->mmc_omap_wq, &host->slot_release_work); 298 return; 299 } 300 301 host->mmc = NULL; 302 wake_up(&host->slot_wq); 303 spin_unlock_irqrestore(&host->slot_lock, flags); 304} 305 306static inline 307int mmc_omap_cover_is_open(struct mmc_omap_slot *slot) 308{ 309 /* If we have a GPIO then use that */ 310 if (slot->cover) 311 return gpiod_get_value(slot->cover); 312 if (slot->pdata->get_cover_state) 313 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), 314 slot->id); 315 return 0; 316} 317 318static ssize_t 319mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, 320 char *buf) 321{ 322 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 323 struct mmc_omap_slot *slot = mmc_priv(mmc); 324 325 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" : 326 "closed"); 327} 328 329static DEVICE_ATTR(cover_switch, 0444, mmc_omap_show_cover_switch, NULL); 330 331static ssize_t 332mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, 333 char *buf) 334{ 335 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 336 struct mmc_omap_slot *slot = mmc_priv(mmc); 337 338 return sprintf(buf, "%s\n", slot->pdata->name); 339} 340 341static DEVICE_ATTR(slot_name, 0444, mmc_omap_show_slot_name, NULL); 342 343static void 344mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) 345{ 346 u32 cmdreg; 347 u32 resptype; 348 u32 cmdtype; 349 u16 irq_mask; 350 351 host->cmd = cmd; 352 353 resptype = 0; 354 cmdtype = 0; 355 356 /* Our hardware needs to know exact type */ 357 switch (mmc_resp_type(cmd)) { 358 case MMC_RSP_NONE: 359 break; 360 case MMC_RSP_R1: 361 case MMC_RSP_R1B: 362 /* resp 1, 1b, 6, 7 */ 363 resptype = 1; 364 break; 365 case MMC_RSP_R2: 366 resptype = 2; 367 break; 368 case MMC_RSP_R3: 369 resptype = 3; 370 break; 371 default: 372 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd)); 373 break; 374 } 375 376 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) { 377 cmdtype = OMAP_MMC_CMDTYPE_ADTC; 378 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) { 379 cmdtype = OMAP_MMC_CMDTYPE_BC; 380 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) { 381 cmdtype = OMAP_MMC_CMDTYPE_BCR; 382 } else { 383 cmdtype = OMAP_MMC_CMDTYPE_AC; 384 } 385 386 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12); 387 388 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN) 389 cmdreg |= 1 << 6; 390 391 if (cmd->flags & MMC_RSP_BUSY) 392 cmdreg |= 1 << 11; 393 394 if (host->data && !(host->data->flags & MMC_DATA_WRITE)) 395 cmdreg |= 1 << 15; 396 397 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2); 398 399 OMAP_MMC_WRITE(host, CTO, 200); 400 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff); 401 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16); 402 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | 403 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | 404 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | 405 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | 406 OMAP_MMC_STAT_END_OF_DATA; 407 if (cmd->opcode == MMC_ERASE) 408 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT; 409 OMAP_MMC_WRITE(host, IE, irq_mask); 410 OMAP_MMC_WRITE(host, CMD, cmdreg); 411} 412 413static void 414mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data, 415 int abort) 416{ 417 enum dma_data_direction dma_data_dir; 418 struct device *dev = mmc_dev(host->mmc); 419 struct dma_chan *c; 420 421 if (data->flags & MMC_DATA_WRITE) { 422 dma_data_dir = DMA_TO_DEVICE; 423 c = host->dma_tx; 424 } else { 425 dma_data_dir = DMA_FROM_DEVICE; 426 c = host->dma_rx; 427 } 428 if (c) { 429 if (data->error) { 430 dmaengine_terminate_all(c); 431 /* Claim nothing transferred on error... */ 432 data->bytes_xfered = 0; 433 } 434 dev = c->device->dev; 435 } 436 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir); 437} 438 439static void mmc_omap_send_stop_work(struct work_struct *work) 440{ 441 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 442 send_stop_work); 443 struct mmc_omap_slot *slot = host->current_slot; 444 struct mmc_data *data = host->stop_data; 445 unsigned long tick_ns; 446 447 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq); 448 ndelay(8*tick_ns); 449 450 mmc_omap_start_command(host, data->stop); 451} 452 453static void 454mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) 455{ 456 if (host->dma_in_use) 457 mmc_omap_release_dma(host, data, data->error); 458 else 459 sg_miter_stop(&host->sg_miter); 460 461 host->data = NULL; 462 host->sg_len = 0; 463 464 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing 465 * dozens of requests until the card finishes writing data. 466 * It'd be cheaper to just wait till an EOFB interrupt arrives... 467 */ 468 469 if (!data->stop) { 470 struct mmc_host *mmc; 471 472 host->mrq = NULL; 473 mmc = host->mmc; 474 mmc_omap_release_slot(host->current_slot, 1); 475 mmc_request_done(mmc, data->mrq); 476 return; 477 } 478 479 host->stop_data = data; 480 queue_work(host->mmc_omap_wq, &host->send_stop_work); 481} 482 483static void 484mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops) 485{ 486 struct mmc_omap_slot *slot = host->current_slot; 487 unsigned int restarts, passes, timeout; 488 u16 stat = 0; 489 490 /* Sending abort takes 80 clocks. Have some extra and round up */ 491 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq); 492 restarts = 0; 493 while (restarts < maxloops) { 494 OMAP_MMC_WRITE(host, STAT, 0xFFFF); 495 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7)); 496 497 passes = 0; 498 while (passes < timeout) { 499 stat = OMAP_MMC_READ(host, STAT); 500 if (stat & OMAP_MMC_STAT_END_OF_CMD) 501 goto out; 502 udelay(1); 503 passes++; 504 } 505 506 restarts++; 507 } 508out: 509 OMAP_MMC_WRITE(host, STAT, stat); 510} 511 512static void 513mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data) 514{ 515 if (host->dma_in_use) 516 mmc_omap_release_dma(host, data, 1); 517 518 host->data = NULL; 519 host->sg_len = 0; 520 521 mmc_omap_send_abort(host, 10000); 522} 523 524static void 525mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data) 526{ 527 unsigned long flags; 528 int done; 529 530 if (!host->dma_in_use) { 531 mmc_omap_xfer_done(host, data); 532 return; 533 } 534 done = 0; 535 spin_lock_irqsave(&host->dma_lock, flags); 536 if (host->dma_done) 537 done = 1; 538 else 539 host->brs_received = 1; 540 spin_unlock_irqrestore(&host->dma_lock, flags); 541 if (done) 542 mmc_omap_xfer_done(host, data); 543} 544 545static void 546mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data) 547{ 548 unsigned long flags; 549 int done; 550 551 done = 0; 552 spin_lock_irqsave(&host->dma_lock, flags); 553 if (host->brs_received) 554 done = 1; 555 else 556 host->dma_done = 1; 557 spin_unlock_irqrestore(&host->dma_lock, flags); 558 if (done) 559 mmc_omap_xfer_done(host, data); 560} 561 562static void 563mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) 564{ 565 host->cmd = NULL; 566 567 timer_delete(&host->cmd_abort_timer); 568 569 if (cmd->flags & MMC_RSP_PRESENT) { 570 if (cmd->flags & MMC_RSP_136) { 571 /* response type 2 */ 572 cmd->resp[3] = 573 OMAP_MMC_READ(host, RSP0) | 574 (OMAP_MMC_READ(host, RSP1) << 16); 575 cmd->resp[2] = 576 OMAP_MMC_READ(host, RSP2) | 577 (OMAP_MMC_READ(host, RSP3) << 16); 578 cmd->resp[1] = 579 OMAP_MMC_READ(host, RSP4) | 580 (OMAP_MMC_READ(host, RSP5) << 16); 581 cmd->resp[0] = 582 OMAP_MMC_READ(host, RSP6) | 583 (OMAP_MMC_READ(host, RSP7) << 16); 584 } else { 585 /* response types 1, 1b, 3, 4, 5, 6 */ 586 cmd->resp[0] = 587 OMAP_MMC_READ(host, RSP6) | 588 (OMAP_MMC_READ(host, RSP7) << 16); 589 } 590 } 591 592 if (host->data == NULL || cmd->error) { 593 struct mmc_host *mmc; 594 595 if (host->data != NULL) 596 mmc_omap_abort_xfer(host, host->data); 597 host->mrq = NULL; 598 mmc = host->mmc; 599 mmc_omap_release_slot(host->current_slot, 1); 600 mmc_request_done(mmc, cmd->mrq); 601 } 602} 603 604/* 605 * Abort stuck command. Can occur when card is removed while it is being 606 * read. 607 */ 608static void mmc_omap_abort_command(struct work_struct *work) 609{ 610 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 611 cmd_abort_work); 612 BUG_ON(!host->cmd); 613 614 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n", 615 host->cmd->opcode); 616 617 if (host->cmd->error == 0) 618 host->cmd->error = -ETIMEDOUT; 619 620 if (host->data == NULL) { 621 struct mmc_command *cmd; 622 struct mmc_host *mmc; 623 624 cmd = host->cmd; 625 host->cmd = NULL; 626 mmc_omap_send_abort(host, 10000); 627 628 host->mrq = NULL; 629 mmc = host->mmc; 630 mmc_omap_release_slot(host->current_slot, 1); 631 mmc_request_done(mmc, cmd->mrq); 632 } else 633 mmc_omap_cmd_done(host, host->cmd); 634 635 host->abort = 0; 636 enable_irq(host->irq); 637} 638 639static void 640mmc_omap_cmd_timer(struct timer_list *t) 641{ 642 struct mmc_omap_host *host = timer_container_of(host, t, 643 cmd_abort_timer); 644 unsigned long flags; 645 646 spin_lock_irqsave(&host->slot_lock, flags); 647 if (host->cmd != NULL && !host->abort) { 648 OMAP_MMC_WRITE(host, IE, 0); 649 disable_irq(host->irq); 650 host->abort = 1; 651 queue_work(host->mmc_omap_wq, &host->cmd_abort_work); 652 } 653 spin_unlock_irqrestore(&host->slot_lock, flags); 654} 655 656static void 657mmc_omap_clk_timer(struct timer_list *t) 658{ 659 struct mmc_omap_host *host = timer_container_of(host, t, clk_timer); 660 661 mmc_omap_fclk_enable(host, 0); 662} 663 664/* PIO only */ 665static void 666mmc_omap_xfer_data(struct mmc_omap_host *host, int write) 667{ 668 struct sg_mapping_iter *sgm = &host->sg_miter; 669 int n, nwords; 670 u16 *buffer; 671 672 if (!sg_miter_next(sgm)) { 673 /* This should not happen */ 674 dev_err(mmc_dev(host->mmc), "ran out of scatterlist prematurely\n"); 675 return; 676 } 677 buffer = sgm->addr; 678 679 n = 64; 680 if (n > sgm->length) 681 n = sgm->length; 682 if (n > host->total_bytes_left) 683 n = host->total_bytes_left; 684 685 /* Round up to handle odd number of bytes to transfer */ 686 nwords = DIV_ROUND_UP(n, 2); 687 688 sgm->consumed = n; 689 host->total_bytes_left -= n; 690 host->data->bytes_xfered += n; 691 692 if (write) { 693 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), 694 buffer, nwords); 695 } else { 696 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), 697 buffer, nwords); 698 } 699} 700 701#ifdef CONFIG_MMC_DEBUG 702static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status) 703{ 704 static const char *mmc_omap_status_bits[] = { 705 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO", 706 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR" 707 }; 708 int i; 709 char res[64], *buf = res; 710 711 buf += sprintf(buf, "MMC IRQ 0x%x:", status); 712 713 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) 714 if (status & (1 << i)) 715 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]); 716 dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 717} 718#else 719static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status) 720{ 721} 722#endif 723 724 725static irqreturn_t mmc_omap_irq(int irq, void *dev_id) 726{ 727 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id; 728 u16 status; 729 int end_command; 730 int end_transfer; 731 int transfer_error, cmd_error; 732 733 if (host->cmd == NULL && host->data == NULL) { 734 status = OMAP_MMC_READ(host, STAT); 735 dev_info(mmc_dev(host->slots[0]->mmc), 736 "Spurious IRQ 0x%04x\n", status); 737 if (status != 0) { 738 OMAP_MMC_WRITE(host, STAT, status); 739 OMAP_MMC_WRITE(host, IE, 0); 740 } 741 return IRQ_HANDLED; 742 } 743 744 end_command = 0; 745 end_transfer = 0; 746 transfer_error = 0; 747 cmd_error = 0; 748 749 while ((status = OMAP_MMC_READ(host, STAT)) != 0) { 750 int cmd; 751 752 OMAP_MMC_WRITE(host, STAT, status); 753 if (host->cmd != NULL) 754 cmd = host->cmd->opcode; 755 else 756 cmd = -1; 757 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", 758 status, cmd); 759 mmc_omap_report_irq(host, status); 760 761 if (host->total_bytes_left) { 762 if ((status & OMAP_MMC_STAT_A_FULL) || 763 (status & OMAP_MMC_STAT_END_OF_DATA)) 764 mmc_omap_xfer_data(host, 0); 765 if (status & OMAP_MMC_STAT_A_EMPTY) 766 mmc_omap_xfer_data(host, 1); 767 } 768 769 if (status & OMAP_MMC_STAT_END_OF_DATA) 770 end_transfer = 1; 771 772 if (status & OMAP_MMC_STAT_DATA_TOUT) { 773 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n", 774 cmd); 775 if (host->data) { 776 host->data->error = -ETIMEDOUT; 777 transfer_error = 1; 778 } 779 } 780 781 if (status & OMAP_MMC_STAT_DATA_CRC) { 782 if (host->data) { 783 host->data->error = -EILSEQ; 784 dev_dbg(mmc_dev(host->mmc), 785 "data CRC error, bytes left %d\n", 786 host->total_bytes_left); 787 transfer_error = 1; 788 } else { 789 dev_dbg(mmc_dev(host->mmc), "data CRC error\n"); 790 } 791 } 792 793 if (status & OMAP_MMC_STAT_CMD_TOUT) { 794 /* Timeouts are routine with some commands */ 795 if (host->cmd) { 796 struct mmc_omap_slot *slot = 797 host->current_slot; 798 if (slot == NULL || 799 !mmc_omap_cover_is_open(slot)) 800 dev_err(mmc_dev(host->mmc), 801 "command timeout (CMD%d)\n", 802 cmd); 803 host->cmd->error = -ETIMEDOUT; 804 end_command = 1; 805 cmd_error = 1; 806 } 807 } 808 809 if (status & OMAP_MMC_STAT_CMD_CRC) { 810 if (host->cmd) { 811 dev_err(mmc_dev(host->mmc), 812 "command CRC error (CMD%d, arg 0x%08x)\n", 813 cmd, host->cmd->arg); 814 host->cmd->error = -EILSEQ; 815 end_command = 1; 816 cmd_error = 1; 817 } else 818 dev_err(mmc_dev(host->mmc), 819 "command CRC error without cmd?\n"); 820 } 821 822 if (status & OMAP_MMC_STAT_CARD_ERR) { 823 dev_dbg(mmc_dev(host->mmc), 824 "ignoring card status error (CMD%d)\n", 825 cmd); 826 end_command = 1; 827 } 828 829 /* 830 * NOTE: On 1610 the END_OF_CMD may come too early when 831 * starting a write 832 */ 833 if ((status & OMAP_MMC_STAT_END_OF_CMD) && 834 (!(status & OMAP_MMC_STAT_A_EMPTY))) { 835 end_command = 1; 836 } 837 } 838 839 if (cmd_error && host->data) { 840 timer_delete(&host->cmd_abort_timer); 841 host->abort = 1; 842 OMAP_MMC_WRITE(host, IE, 0); 843 disable_irq_nosync(host->irq); 844 queue_work(host->mmc_omap_wq, &host->cmd_abort_work); 845 return IRQ_HANDLED; 846 } 847 848 if (end_command && host->cmd) 849 mmc_omap_cmd_done(host, host->cmd); 850 if (host->data != NULL) { 851 if (transfer_error) 852 mmc_omap_xfer_done(host, host->data); 853 else if (end_transfer) 854 mmc_omap_end_of_data(host, host->data); 855 } 856 857 return IRQ_HANDLED; 858} 859 860void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed) 861{ 862 int cover_open; 863 struct mmc_omap_host *host = dev_get_drvdata(dev); 864 struct mmc_omap_slot *slot = host->slots[num]; 865 866 BUG_ON(num >= host->nr_slots); 867 868 /* Other subsystems can call in here before we're initialised. */ 869 if (host->nr_slots == 0 || !host->slots[num]) 870 return; 871 872 cover_open = mmc_omap_cover_is_open(slot); 873 if (cover_open != slot->cover_open) { 874 slot->cover_open = cover_open; 875 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch"); 876 } 877 878 queue_work(system_bh_highpri_wq, &slot->cover_bh_work); 879} 880 881static void mmc_omap_cover_timer(struct timer_list *t) 882{ 883 struct mmc_omap_slot *slot = timer_container_of(slot, t, cover_timer); 884 queue_work(system_bh_wq, &slot->cover_bh_work); 885} 886 887static void mmc_omap_cover_bh_handler(struct work_struct *t) 888{ 889 struct mmc_omap_slot *slot = from_work(slot, t, cover_bh_work); 890 int cover_open = mmc_omap_cover_is_open(slot); 891 892 mmc_detect_change(slot->mmc, 0); 893 if (!cover_open) 894 return; 895 896 /* 897 * If no card is inserted, we postpone polling until 898 * the cover has been closed. 899 */ 900 if (slot->mmc->card == NULL) 901 return; 902 903 mod_timer(&slot->cover_timer, 904 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY)); 905} 906 907static void mmc_omap_dma_callback(void *priv) 908{ 909 struct mmc_omap_host *host = priv; 910 struct mmc_data *data = host->data; 911 912 /* If we got to the end of DMA, assume everything went well */ 913 data->bytes_xfered += data->blocks * data->blksz; 914 915 mmc_omap_dma_done(host, data); 916} 917 918static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req) 919{ 920 u16 reg; 921 922 reg = OMAP_MMC_READ(host, SDIO); 923 reg &= ~(1 << 5); 924 OMAP_MMC_WRITE(host, SDIO, reg); 925 /* Set maximum timeout */ 926 OMAP_MMC_WRITE(host, CTO, 0xfd); 927} 928 929static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) 930{ 931 unsigned int timeout, cycle_ns; 932 u16 reg; 933 934 cycle_ns = 1000000000 / host->current_slot->fclk_freq; 935 timeout = req->data->timeout_ns / cycle_ns; 936 timeout += req->data->timeout_clks; 937 938 /* Check if we need to use timeout multiplier register */ 939 reg = OMAP_MMC_READ(host, SDIO); 940 if (timeout > 0xffff) { 941 reg |= (1 << 5); 942 timeout /= 1024; 943 } else 944 reg &= ~(1 << 5); 945 OMAP_MMC_WRITE(host, SDIO, reg); 946 OMAP_MMC_WRITE(host, DTO, timeout); 947} 948 949static void 950mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) 951{ 952 unsigned int miter_flags = SG_MITER_ATOMIC; /* Used from IRQ */ 953 struct mmc_data *data = req->data; 954 int i, use_dma = 1, block_size; 955 struct scatterlist *sg; 956 unsigned sg_len; 957 958 host->data = data; 959 if (data == NULL) { 960 OMAP_MMC_WRITE(host, BLEN, 0); 961 OMAP_MMC_WRITE(host, NBLK, 0); 962 OMAP_MMC_WRITE(host, BUF, 0); 963 host->dma_in_use = 0; 964 set_cmd_timeout(host, req); 965 return; 966 } 967 968 block_size = data->blksz; 969 970 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1); 971 OMAP_MMC_WRITE(host, BLEN, block_size - 1); 972 set_data_timeout(host, req); 973 974 /* cope with calling layer confusion; it issues "single 975 * block" writes using multi-block scatterlists. 976 */ 977 sg_len = (data->blocks == 1) ? 1 : data->sg_len; 978 979 /* Only do DMA for entire blocks */ 980 for_each_sg(data->sg, sg, sg_len, i) { 981 if ((sg->length % block_size) != 0) { 982 use_dma = 0; 983 break; 984 } 985 } 986 987 if (use_dma) { 988 enum dma_data_direction dma_data_dir; 989 struct dma_async_tx_descriptor *tx; 990 struct dma_chan *c; 991 u32 burst, *bp; 992 u16 buf; 993 994 /* 995 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx 996 * and 24xx. Use 16 or 32 word frames when the 997 * blocksize is at least that large. Blocksize is 998 * usually 512 bytes; but not for some SD reads. 999 */ 1000 burst = mmc_omap15xx() ? 32 : 64; 1001 if (burst > data->blksz) 1002 burst = data->blksz; 1003 1004 burst >>= 1; 1005 1006 if (data->flags & MMC_DATA_WRITE) { 1007 c = host->dma_tx; 1008 bp = &host->dma_tx_burst; 1009 buf = 0x0f80 | (burst - 1) << 0; 1010 dma_data_dir = DMA_TO_DEVICE; 1011 } else { 1012 c = host->dma_rx; 1013 bp = &host->dma_rx_burst; 1014 buf = 0x800f | (burst - 1) << 8; 1015 dma_data_dir = DMA_FROM_DEVICE; 1016 } 1017 1018 if (!c) 1019 goto use_pio; 1020 1021 /* Only reconfigure if we have a different burst size */ 1022 if (*bp != burst) { 1023 struct dma_slave_config cfg = { 1024 .src_addr = host->phys_base + 1025 OMAP_MMC_REG(host, DATA), 1026 .dst_addr = host->phys_base + 1027 OMAP_MMC_REG(host, DATA), 1028 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES, 1029 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES, 1030 .src_maxburst = burst, 1031 .dst_maxburst = burst, 1032 }; 1033 1034 if (dmaengine_slave_config(c, &cfg)) 1035 goto use_pio; 1036 1037 *bp = burst; 1038 } 1039 1040 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len, 1041 dma_data_dir); 1042 if (host->sg_len == 0) 1043 goto use_pio; 1044 1045 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len, 1046 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1047 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1048 if (!tx) 1049 goto use_pio; 1050 1051 OMAP_MMC_WRITE(host, BUF, buf); 1052 1053 tx->callback = mmc_omap_dma_callback; 1054 tx->callback_param = host; 1055 dmaengine_submit(tx); 1056 host->brs_received = 0; 1057 host->dma_done = 0; 1058 host->dma_in_use = 1; 1059 return; 1060 } 1061 use_pio: 1062 1063 /* Revert to PIO? */ 1064 OMAP_MMC_WRITE(host, BUF, 0x1f1f); 1065 host->total_bytes_left = data->blocks * block_size; 1066 host->sg_len = sg_len; 1067 if (data->flags & MMC_DATA_READ) 1068 miter_flags |= SG_MITER_TO_SG; 1069 else 1070 miter_flags |= SG_MITER_FROM_SG; 1071 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, miter_flags); 1072 host->dma_in_use = 0; 1073} 1074 1075static void mmc_omap_start_request(struct mmc_omap_host *host, 1076 struct mmc_request *req) 1077{ 1078 BUG_ON(host->mrq != NULL); 1079 1080 host->mrq = req; 1081 1082 /* only touch fifo AFTER the controller readies it */ 1083 mmc_omap_prepare_data(host, req); 1084 mmc_omap_start_command(host, req->cmd); 1085 if (host->dma_in_use) { 1086 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ? 1087 host->dma_tx : host->dma_rx; 1088 1089 dma_async_issue_pending(c); 1090 } 1091} 1092 1093static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req) 1094{ 1095 struct mmc_omap_slot *slot = mmc_priv(mmc); 1096 struct mmc_omap_host *host = slot->host; 1097 unsigned long flags; 1098 1099 spin_lock_irqsave(&host->slot_lock, flags); 1100 if (host->mmc != NULL) { 1101 BUG_ON(slot->mrq != NULL); 1102 slot->mrq = req; 1103 spin_unlock_irqrestore(&host->slot_lock, flags); 1104 return; 1105 } else 1106 host->mmc = mmc; 1107 spin_unlock_irqrestore(&host->slot_lock, flags); 1108 mmc_omap_select_slot(slot, 1); 1109 mmc_omap_start_request(host, req); 1110} 1111 1112static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on, 1113 int vdd) 1114{ 1115 struct mmc_omap_host *host; 1116 1117 host = slot->host; 1118 1119 if (power_on) { 1120 if (slot->vsd) { 1121 gpiod_set_value(slot->vsd, power_on); 1122 msleep(1); 1123 } 1124 if (slot->vio) { 1125 gpiod_set_value(slot->vio, power_on); 1126 msleep(1); 1127 } 1128 } else { 1129 if (slot->vio) { 1130 gpiod_set_value(slot->vio, power_on); 1131 msleep(50); 1132 } 1133 if (slot->vsd) { 1134 gpiod_set_value(slot->vsd, power_on); 1135 msleep(50); 1136 } 1137 } 1138 1139 if (slot->pdata->set_power != NULL) 1140 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on, 1141 vdd); 1142 if (mmc_omap2()) { 1143 u16 w; 1144 1145 if (power_on) { 1146 w = OMAP_MMC_READ(host, CON); 1147 OMAP_MMC_WRITE(host, CON, w | (1 << 11)); 1148 } else { 1149 w = OMAP_MMC_READ(host, CON); 1150 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11)); 1151 } 1152 } 1153} 1154 1155static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios) 1156{ 1157 struct mmc_omap_slot *slot = mmc_priv(mmc); 1158 struct mmc_omap_host *host = slot->host; 1159 int func_clk_rate = clk_get_rate(host->fclk); 1160 int dsor; 1161 1162 if (ios->clock == 0) 1163 return 0; 1164 1165 dsor = func_clk_rate / ios->clock; 1166 if (dsor < 1) 1167 dsor = 1; 1168 1169 if (func_clk_rate / dsor > ios->clock) 1170 dsor++; 1171 1172 if (dsor > 250) 1173 dsor = 250; 1174 1175 slot->fclk_freq = func_clk_rate / dsor; 1176 1177 if (ios->bus_width == MMC_BUS_WIDTH_4) 1178 dsor |= 1 << 15; 1179 1180 return dsor; 1181} 1182 1183static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1184{ 1185 struct mmc_omap_slot *slot = mmc_priv(mmc); 1186 struct mmc_omap_host *host = slot->host; 1187 int i, dsor; 1188 int clk_enabled, init_stream; 1189 1190 mmc_omap_select_slot(slot, 0); 1191 1192 dsor = mmc_omap_calc_divisor(mmc, ios); 1193 1194 if (ios->vdd != slot->vdd) 1195 slot->vdd = ios->vdd; 1196 1197 clk_enabled = 0; 1198 init_stream = 0; 1199 switch (ios->power_mode) { 1200 case MMC_POWER_OFF: 1201 mmc_omap_set_power(slot, 0, ios->vdd); 1202 break; 1203 case MMC_POWER_UP: 1204 /* Cannot touch dsor yet, just power up MMC */ 1205 mmc_omap_set_power(slot, 1, ios->vdd); 1206 slot->power_mode = ios->power_mode; 1207 goto exit; 1208 case MMC_POWER_ON: 1209 mmc_omap_fclk_enable(host, 1); 1210 clk_enabled = 1; 1211 dsor |= 1 << 11; 1212 if (slot->power_mode != MMC_POWER_ON) 1213 init_stream = 1; 1214 break; 1215 } 1216 slot->power_mode = ios->power_mode; 1217 1218 if (slot->bus_mode != ios->bus_mode) { 1219 if (slot->pdata->set_bus_mode != NULL) 1220 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id, 1221 ios->bus_mode); 1222 slot->bus_mode = ios->bus_mode; 1223 } 1224 1225 /* On insanely high arm_per frequencies something sometimes 1226 * goes somehow out of sync, and the POW bit is not being set, 1227 * which results in the while loop below getting stuck. 1228 * Writing to the CON register twice seems to do the trick. */ 1229 for (i = 0; i < 2; i++) 1230 OMAP_MMC_WRITE(host, CON, dsor); 1231 slot->saved_con = dsor; 1232 if (init_stream) { 1233 /* worst case at 400kHz, 80 cycles makes 200 microsecs */ 1234 int usecs = 250; 1235 1236 /* Send clock cycles, poll completion */ 1237 OMAP_MMC_WRITE(host, IE, 0); 1238 OMAP_MMC_WRITE(host, STAT, 0xffff); 1239 OMAP_MMC_WRITE(host, CMD, 1 << 7); 1240 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) { 1241 udelay(1); 1242 usecs--; 1243 } 1244 OMAP_MMC_WRITE(host, STAT, 1); 1245 } 1246 1247exit: 1248 mmc_omap_release_slot(slot, clk_enabled); 1249} 1250 1251static const struct mmc_host_ops mmc_omap_ops = { 1252 .request = mmc_omap_request, 1253 .set_ios = mmc_omap_set_ios, 1254}; 1255 1256static int mmc_omap_new_slot(struct mmc_omap_host *host, int id) 1257{ 1258 struct mmc_omap_slot *slot = NULL; 1259 struct mmc_host *mmc; 1260 int r; 1261 1262 mmc = devm_mmc_alloc_host(host->dev, sizeof(*slot)); 1263 if (mmc == NULL) 1264 return -ENOMEM; 1265 1266 slot = mmc_priv(mmc); 1267 slot->host = host; 1268 slot->mmc = mmc; 1269 slot->id = id; 1270 slot->power_mode = MMC_POWER_UNDEFINED; 1271 slot->pdata = &host->pdata->slots[id]; 1272 1273 /* Check for some optional GPIO controls */ 1274 slot->vsd = devm_gpiod_get_index_optional(host->dev, "vsd", 1275 id, GPIOD_OUT_LOW); 1276 if (IS_ERR(slot->vsd)) 1277 return dev_err_probe(host->dev, PTR_ERR(slot->vsd), 1278 "error looking up VSD GPIO\n"); 1279 1280 slot->vio = devm_gpiod_get_index_optional(host->dev, "vio", 1281 id, GPIOD_OUT_LOW); 1282 if (IS_ERR(slot->vio)) 1283 return dev_err_probe(host->dev, PTR_ERR(slot->vio), 1284 "error looking up VIO GPIO\n"); 1285 1286 slot->cover = devm_gpiod_get_index_optional(host->dev, "cover", 1287 id, GPIOD_IN); 1288 if (IS_ERR(slot->cover)) 1289 return dev_err_probe(host->dev, PTR_ERR(slot->cover), 1290 "error looking up cover switch GPIO\n"); 1291 1292 host->slots[id] = slot; 1293 1294 mmc->caps = 0; 1295 if (host->pdata->slots[id].wires >= 4) 1296 mmc->caps |= MMC_CAP_4_BIT_DATA; 1297 1298 mmc->ops = &mmc_omap_ops; 1299 mmc->f_min = 400000; 1300 1301 if (mmc_omap2()) 1302 mmc->f_max = 48000000; 1303 else 1304 mmc->f_max = 24000000; 1305 if (host->pdata->max_freq) 1306 mmc->f_max = min(host->pdata->max_freq, mmc->f_max); 1307 mmc->ocr_avail = slot->pdata->ocr_mask; 1308 1309 /* Use scatterlist DMA to reduce per-transfer costs. 1310 * NOTE max_seg_size assumption that small blocks aren't 1311 * normally used (except e.g. for reading SD registers). 1312 */ 1313 mmc->max_segs = 32; 1314 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */ 1315 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */ 1316 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1317 mmc->max_seg_size = mmc->max_req_size; 1318 1319 if (slot->pdata->get_cover_state != NULL) { 1320 timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0); 1321 INIT_WORK(&slot->cover_bh_work, mmc_omap_cover_bh_handler); 1322 } 1323 1324 r = mmc_add_host(mmc); 1325 if (r < 0) 1326 goto err_remove_host; 1327 1328 if (slot->pdata->name != NULL) { 1329 r = device_create_file(&mmc->class_dev, 1330 &dev_attr_slot_name); 1331 if (r < 0) 1332 goto err_remove_host; 1333 } 1334 1335 if (slot->pdata->get_cover_state != NULL) { 1336 r = device_create_file(&mmc->class_dev, 1337 &dev_attr_cover_switch); 1338 if (r < 0) 1339 goto err_remove_slot_name; 1340 queue_work(system_bh_wq, &slot->cover_bh_work); 1341 } 1342 1343 return 0; 1344 1345err_remove_slot_name: 1346 if (slot->pdata->name != NULL) 1347 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1348err_remove_host: 1349 mmc_remove_host(mmc); 1350 return r; 1351} 1352 1353static void mmc_omap_remove_slot(struct mmc_omap_slot *slot) 1354{ 1355 struct mmc_host *mmc = slot->mmc; 1356 1357 if (slot->pdata->name != NULL) 1358 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1359 if (slot->pdata->get_cover_state != NULL) 1360 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); 1361 1362 cancel_work_sync(&slot->cover_bh_work); 1363 timer_delete_sync(&slot->cover_timer); 1364 flush_workqueue(slot->host->mmc_omap_wq); 1365 1366 mmc_remove_host(mmc); 1367} 1368 1369static int mmc_omap_probe(struct platform_device *pdev) 1370{ 1371 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1372 struct mmc_omap_host *host = NULL; 1373 struct resource *res; 1374 int i, ret = 0; 1375 int irq; 1376 1377 if (pdata == NULL) { 1378 dev_err(&pdev->dev, "platform data missing\n"); 1379 return -ENXIO; 1380 } 1381 if (pdata->nr_slots == 0) { 1382 dev_err(&pdev->dev, "no slots\n"); 1383 return -EPROBE_DEFER; 1384 } 1385 1386 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host), 1387 GFP_KERNEL); 1388 if (host == NULL) 1389 return -ENOMEM; 1390 1391 irq = platform_get_irq(pdev, 0); 1392 if (irq < 0) 1393 return irq; 1394 1395 host->virt_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1396 if (IS_ERR(host->virt_base)) 1397 return PTR_ERR(host->virt_base); 1398 1399 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); 1400 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); 1401 1402 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); 1403 timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0); 1404 1405 spin_lock_init(&host->clk_lock); 1406 timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0); 1407 1408 spin_lock_init(&host->dma_lock); 1409 spin_lock_init(&host->slot_lock); 1410 init_waitqueue_head(&host->slot_wq); 1411 1412 host->pdata = pdata; 1413 host->features = host->pdata->slots[0].features; 1414 host->dev = &pdev->dev; 1415 platform_set_drvdata(pdev, host); 1416 1417 host->slot_switch = devm_gpiod_get_optional(host->dev, "switch", 1418 GPIOD_OUT_LOW); 1419 if (IS_ERR(host->slot_switch)) 1420 return dev_err_probe(host->dev, PTR_ERR(host->slot_switch), 1421 "error looking up slot switch GPIO\n"); 1422 1423 host->id = pdev->id; 1424 host->irq = irq; 1425 host->phys_base = res->start; 1426 host->iclk = clk_get(&pdev->dev, "ick"); 1427 if (IS_ERR(host->iclk)) 1428 return PTR_ERR(host->iclk); 1429 clk_prepare_enable(host->iclk); 1430 1431 host->fclk = clk_get(&pdev->dev, "fck"); 1432 if (IS_ERR(host->fclk)) { 1433 ret = PTR_ERR(host->fclk); 1434 goto err_free_iclk; 1435 } 1436 1437 ret = clk_prepare(host->fclk); 1438 if (ret) 1439 goto err_put_fclk; 1440 1441 host->dma_tx_burst = -1; 1442 host->dma_rx_burst = -1; 1443 1444 host->dma_tx = dma_request_chan(&pdev->dev, "tx"); 1445 if (IS_ERR(host->dma_tx)) { 1446 ret = PTR_ERR(host->dma_tx); 1447 if (ret == -EPROBE_DEFER) 1448 goto err_free_fclk; 1449 1450 host->dma_tx = NULL; 1451 dev_warn(host->dev, "TX DMA channel request failed\n"); 1452 } 1453 1454 host->dma_rx = dma_request_chan(&pdev->dev, "rx"); 1455 if (IS_ERR(host->dma_rx)) { 1456 ret = PTR_ERR(host->dma_rx); 1457 if (ret == -EPROBE_DEFER) { 1458 if (host->dma_tx) 1459 dma_release_channel(host->dma_tx); 1460 goto err_free_fclk; 1461 } 1462 1463 host->dma_rx = NULL; 1464 dev_warn(host->dev, "RX DMA channel request failed\n"); 1465 } 1466 1467 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); 1468 if (ret) 1469 goto err_free_dma; 1470 1471 if (pdata->init != NULL) { 1472 ret = pdata->init(&pdev->dev); 1473 if (ret < 0) 1474 goto err_free_irq; 1475 } 1476 1477 host->nr_slots = pdata->nr_slots; 1478 host->reg_shift = (mmc_omap7xx() ? 1 : 2); 1479 1480 host->mmc_omap_wq = alloc_workqueue("mmc_omap", WQ_PERCPU, 0); 1481 if (!host->mmc_omap_wq) { 1482 ret = -ENOMEM; 1483 goto err_plat_cleanup; 1484 } 1485 1486 for (i = 0; i < pdata->nr_slots; i++) { 1487 ret = mmc_omap_new_slot(host, i); 1488 if (ret < 0) { 1489 while (--i >= 0) 1490 mmc_omap_remove_slot(host->slots[i]); 1491 1492 goto err_destroy_wq; 1493 } 1494 } 1495 1496 return 0; 1497 1498err_destroy_wq: 1499 destroy_workqueue(host->mmc_omap_wq); 1500err_plat_cleanup: 1501 if (pdata->cleanup) 1502 pdata->cleanup(&pdev->dev); 1503err_free_irq: 1504 free_irq(host->irq, host); 1505err_free_dma: 1506 if (host->dma_tx) 1507 dma_release_channel(host->dma_tx); 1508 if (host->dma_rx) 1509 dma_release_channel(host->dma_rx); 1510err_free_fclk: 1511 clk_unprepare(host->fclk); 1512err_put_fclk: 1513 clk_put(host->fclk); 1514err_free_iclk: 1515 clk_disable_unprepare(host->iclk); 1516 clk_put(host->iclk); 1517 return ret; 1518} 1519 1520static void mmc_omap_remove(struct platform_device *pdev) 1521{ 1522 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1523 int i; 1524 1525 BUG_ON(host == NULL); 1526 1527 for (i = 0; i < host->nr_slots; i++) 1528 mmc_omap_remove_slot(host->slots[i]); 1529 1530 if (host->pdata->cleanup) 1531 host->pdata->cleanup(&pdev->dev); 1532 1533 mmc_omap_fclk_enable(host, 0); 1534 free_irq(host->irq, host); 1535 clk_unprepare(host->fclk); 1536 clk_put(host->fclk); 1537 clk_disable_unprepare(host->iclk); 1538 clk_put(host->iclk); 1539 1540 if (host->dma_tx) 1541 dma_release_channel(host->dma_tx); 1542 if (host->dma_rx) 1543 dma_release_channel(host->dma_rx); 1544 1545 destroy_workqueue(host->mmc_omap_wq); 1546} 1547 1548#if IS_BUILTIN(CONFIG_OF) 1549static const struct of_device_id mmc_omap_match[] = { 1550 { .compatible = "ti,omap2420-mmc", }, 1551 { }, 1552}; 1553MODULE_DEVICE_TABLE(of, mmc_omap_match); 1554#endif 1555 1556static struct platform_driver mmc_omap_driver = { 1557 .probe = mmc_omap_probe, 1558 .remove = mmc_omap_remove, 1559 .driver = { 1560 .name = DRIVER_NAME, 1561 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1562 .of_match_table = of_match_ptr(mmc_omap_match), 1563 }, 1564}; 1565 1566module_platform_driver(mmc_omap_driver); 1567MODULE_DESCRIPTION("OMAP Multimedia Card driver"); 1568MODULE_LICENSE("GPL"); 1569MODULE_ALIAS("platform:" DRIVER_NAME); 1570MODULE_AUTHOR("Juha Yrjölä");
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