mxcmmc.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
   4 *
   5 *  This is a driver for the SDHC controller found in Freescale MX2/MX3
   6 *  SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
   7 *  Unlike the hardware found on MX1, this hardware just works and does
   8 *  not need all the quirks found in imxmmc.c, hence the separate driver.
   9 *
  10 *  Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  11 *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
  12 *
  13 *  derived from pxamci.c by Russell King
  14 */
  15
  16#include <linux/module.h>
  17#include <linux/init.h>
  18#include <linux/ioport.h>
  19#include <linux/platform_device.h>
  20#include <linux/highmem.h>
  21#include <linux/interrupt.h>
  22#include <linux/irq.h>
  23#include <linux/blkdev.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/mmc/host.h>
  26#include <linux/mmc/card.h>
  27#include <linux/delay.h>
  28#include <linux/clk.h>
  29#include <linux/io.h>
  30#include <linux/regulator/consumer.h>
  31#include <linux/dmaengine.h>
  32#include <linux/types.h>
  33#include <linux/of.h>
  34#include <linux/of_dma.h>
  35#include <linux/mmc/slot-gpio.h>
  36
  37#include <asm/dma.h>
  38#include <asm/irq.h>
  39#include <linux/platform_data/mmc-mxcmmc.h>
  40
  41#include <linux/dma/imx-dma.h>
  42
  43#define DRIVER_NAME "mxc-mmc"
  44#define MXCMCI_TIMEOUT_MS 10000
  45
  46#define MMC_REG_STR_STP_CLK		0x00
  47#define MMC_REG_STATUS			0x04
  48#define MMC_REG_CLK_RATE		0x08
  49#define MMC_REG_CMD_DAT_CONT		0x0C
  50#define MMC_REG_RES_TO			0x10
  51#define MMC_REG_READ_TO			0x14
  52#define MMC_REG_BLK_LEN			0x18
  53#define MMC_REG_NOB			0x1C
  54#define MMC_REG_REV_NO			0x20
  55#define MMC_REG_INT_CNTR		0x24
  56#define MMC_REG_CMD			0x28
  57#define MMC_REG_ARG			0x2C
  58#define MMC_REG_RES_FIFO		0x34
  59#define MMC_REG_BUFFER_ACCESS		0x38
  60
  61#define STR_STP_CLK_RESET               (1 << 3)
  62#define STR_STP_CLK_START_CLK           (1 << 1)
  63#define STR_STP_CLK_STOP_CLK            (1 << 0)
  64
  65#define STATUS_CARD_INSERTION		(1 << 31)
  66#define STATUS_CARD_REMOVAL		(1 << 30)
  67#define STATUS_YBUF_EMPTY		(1 << 29)
  68#define STATUS_XBUF_EMPTY		(1 << 28)
  69#define STATUS_YBUF_FULL		(1 << 27)
  70#define STATUS_XBUF_FULL		(1 << 26)
  71#define STATUS_BUF_UND_RUN		(1 << 25)
  72#define STATUS_BUF_OVFL			(1 << 24)
  73#define STATUS_SDIO_INT_ACTIVE		(1 << 14)
  74#define STATUS_END_CMD_RESP		(1 << 13)
  75#define STATUS_WRITE_OP_DONE		(1 << 12)
  76#define STATUS_DATA_TRANS_DONE		(1 << 11)
  77#define STATUS_READ_OP_DONE		(1 << 11)
  78#define STATUS_WR_CRC_ERROR_CODE_MASK	(3 << 10)
  79#define STATUS_CARD_BUS_CLK_RUN		(1 << 8)
  80#define STATUS_BUF_READ_RDY		(1 << 7)
  81#define STATUS_BUF_WRITE_RDY		(1 << 6)
  82#define STATUS_RESP_CRC_ERR		(1 << 5)
  83#define STATUS_CRC_READ_ERR		(1 << 3)
  84#define STATUS_CRC_WRITE_ERR		(1 << 2)
  85#define STATUS_TIME_OUT_RESP		(1 << 1)
  86#define STATUS_TIME_OUT_READ		(1 << 0)
  87#define STATUS_ERR_MASK			0x2f
  88
  89#define CMD_DAT_CONT_CMD_RESP_LONG_OFF	(1 << 12)
  90#define CMD_DAT_CONT_STOP_READWAIT	(1 << 11)
  91#define CMD_DAT_CONT_START_READWAIT	(1 << 10)
  92#define CMD_DAT_CONT_BUS_WIDTH_4	(2 << 8)
  93#define CMD_DAT_CONT_INIT		(1 << 7)
  94#define CMD_DAT_CONT_WRITE		(1 << 4)
  95#define CMD_DAT_CONT_DATA_ENABLE	(1 << 3)
  96#define CMD_DAT_CONT_RESPONSE_48BIT_CRC	(1 << 0)
  97#define CMD_DAT_CONT_RESPONSE_136BIT	(2 << 0)
  98#define CMD_DAT_CONT_RESPONSE_48BIT	(3 << 0)
  99
 100#define INT_SDIO_INT_WKP_EN		(1 << 18)
 101#define INT_CARD_INSERTION_WKP_EN	(1 << 17)
 102#define INT_CARD_REMOVAL_WKP_EN		(1 << 16)
 103#define INT_CARD_INSERTION_EN		(1 << 15)
 104#define INT_CARD_REMOVAL_EN		(1 << 14)
 105#define INT_SDIO_IRQ_EN			(1 << 13)
 106#define INT_DAT0_EN			(1 << 12)
 107#define INT_BUF_READ_EN			(1 << 4)
 108#define INT_BUF_WRITE_EN		(1 << 3)
 109#define INT_END_CMD_RES_EN		(1 << 2)
 110#define INT_WRITE_OP_DONE_EN		(1 << 1)
 111#define INT_READ_OP_EN			(1 << 0)
 112
 113enum mxcmci_type {
 114	IMX21_MMC,
 115	IMX31_MMC,
 116	MPC512X_MMC,
 117};
 118
 119struct mxcmci_host {
 120	struct mmc_host		*mmc;
 121	void __iomem		*base;
 122	dma_addr_t		phys_base;
 123	int			detect_irq;
 124	struct dma_chan		*dma;
 125	struct dma_async_tx_descriptor *desc;
 126	int			do_dma;
 127	int			default_irq_mask;
 128	int			use_sdio;
 129	unsigned int		power_mode;
 130	struct imxmmc_platform_data *pdata;
 131
 132	struct mmc_request	*req;
 133	struct mmc_command	*cmd;
 134	struct mmc_data		*data;
 135
 136	unsigned int		datasize;
 137	unsigned int		dma_dir;
 138
 139	u16			rev_no;
 140	unsigned int		cmdat;
 141
 142	struct clk		*clk_ipg;
 143	struct clk		*clk_per;
 144
 145	int			clock;
 146
 147	struct work_struct	datawork;
 148	spinlock_t		lock;
 149
 150	int			burstlen;
 151	int			dmareq;
 152	struct dma_slave_config dma_slave_config;
 153	struct imx_dma_data	dma_data;
 154
 155	struct timer_list	watchdog;
 156	enum mxcmci_type	devtype;
 157};
 158
 159static const struct of_device_id mxcmci_of_match[] = {
 160	{
 161		.compatible = "fsl,imx21-mmc",
 162		.data = (void *) IMX21_MMC,
 163	}, {
 164		.compatible = "fsl,imx31-mmc",
 165		.data = (void *) IMX31_MMC,
 166	}, {
 167		.compatible = "fsl,mpc5121-sdhc",
 168		.data = (void *) MPC512X_MMC,
 169	}, {
 170		/* sentinel */
 171	}
 172};
 173MODULE_DEVICE_TABLE(of, mxcmci_of_match);
 174
 175static inline int is_imx31_mmc(struct mxcmci_host *host)
 176{
 177	return host->devtype == IMX31_MMC;
 178}
 179
 180static inline int is_mpc512x_mmc(struct mxcmci_host *host)
 181{
 182	return host->devtype == MPC512X_MMC;
 183}
 184
 185static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
 186{
 187	if (IS_ENABLED(CONFIG_PPC_MPC512x))
 188		return ioread32be(host->base + reg);
 189	else
 190		return readl(host->base + reg);
 191}
 192
 193static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
 194{
 195	if (IS_ENABLED(CONFIG_PPC_MPC512x))
 196		iowrite32be(val, host->base + reg);
 197	else
 198		writel(val, host->base + reg);
 199}
 200
 201static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
 202{
 203	if (IS_ENABLED(CONFIG_PPC_MPC512x))
 204		return ioread32be(host->base + reg);
 205	else
 206		return readw(host->base + reg);
 207}
 208
 209static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
 210{
 211	if (IS_ENABLED(CONFIG_PPC_MPC512x))
 212		iowrite32be(val, host->base + reg);
 213	else
 214		writew(val, host->base + reg);
 215}
 216
 217static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
 218
 219static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
 220{
 221	if (!IS_ERR(host->mmc->supply.vmmc)) {
 222		if (host->power_mode == MMC_POWER_UP)
 223			mmc_regulator_set_ocr(host->mmc,
 224					      host->mmc->supply.vmmc, vdd);
 225		else if (host->power_mode == MMC_POWER_OFF)
 226			mmc_regulator_set_ocr(host->mmc,
 227					      host->mmc->supply.vmmc, 0);
 228	}
 229
 230	if (host->pdata && host->pdata->setpower)
 231		host->pdata->setpower(mmc_dev(host->mmc), vdd);
 232}
 233
 234static inline int mxcmci_use_dma(struct mxcmci_host *host)
 235{
 236	return host->do_dma;
 237}
 238
 239static void mxcmci_softreset(struct mxcmci_host *host)
 240{
 241	int i;
 242
 243	dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
 244
 245	/* reset sequence */
 246	mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
 247	mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
 248			MMC_REG_STR_STP_CLK);
 249
 250	for (i = 0; i < 8; i++)
 251		mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
 252
 253	mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
 254}
 255
 256#if IS_ENABLED(CONFIG_PPC_MPC512x)
 257static inline void buffer_swap32(u32 *buf, int len)
 258{
 259	int i;
 260
 261	for (i = 0; i < ((len + 3) / 4); i++) {
 262		*buf = swab32(*buf);
 263		buf++;
 264	}
 265}
 266
 267static void mxcmci_swap_buffers(struct mmc_data *data)
 268{
 269	struct sg_mapping_iter sgm;
 270	u32 *buf;
 271
 272	sg_miter_start(&sgm, data->sg, data->sg_len,
 273		       SG_MITER_TO_SG | SG_MITER_FROM_SG);
 274
 275	while (sg_miter_next(&sgm)) {
 276		buf = sgm.addr;
 277		buffer_swap32(buf, sgm.length);
 278	}
 279
 280	sg_miter_stop(&sgm);
 281}
 282#else
 283static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
 284#endif
 285
 286static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
 287{
 288	unsigned int nob = data->blocks;
 289	unsigned int blksz = data->blksz;
 290	unsigned int datasize = nob * blksz;
 291	struct scatterlist *sg;
 292	enum dma_transfer_direction slave_dirn;
 293	int i, nents;
 294
 295	host->data = data;
 296	data->bytes_xfered = 0;
 297
 298	mxcmci_writew(host, nob, MMC_REG_NOB);
 299	mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
 300	host->datasize = datasize;
 301
 302	if (!mxcmci_use_dma(host))
 303		return 0;
 304
 305	for_each_sg(data->sg, sg, data->sg_len, i) {
 306		if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
 307			host->do_dma = 0;
 308			return 0;
 309		}
 310	}
 311
 312	if (data->flags & MMC_DATA_READ) {
 313		host->dma_dir = DMA_FROM_DEVICE;
 314		slave_dirn = DMA_DEV_TO_MEM;
 315	} else {
 316		host->dma_dir = DMA_TO_DEVICE;
 317		slave_dirn = DMA_MEM_TO_DEV;
 318
 319		mxcmci_swap_buffers(data);
 320	}
 321
 322	nents = dma_map_sg(host->dma->device->dev, data->sg,
 323				     data->sg_len,  host->dma_dir);
 324	if (nents != data->sg_len)
 325		return -EINVAL;
 326
 327	host->desc = dmaengine_prep_slave_sg(host->dma,
 328		data->sg, data->sg_len, slave_dirn,
 329		DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 330
 331	if (!host->desc) {
 332		dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
 333				host->dma_dir);
 334		host->do_dma = 0;
 335		return 0; /* Fall back to PIO */
 336	}
 337	wmb();
 338
 339	dmaengine_submit(host->desc);
 340	dma_async_issue_pending(host->dma);
 341
 342	mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
 343
 344	return 0;
 345}
 346
 347static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
 348static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
 349
 350static void mxcmci_dma_callback(void *data)
 351{
 352	struct mxcmci_host *host = data;
 353	u32 stat;
 354
 355	timer_delete(&host->watchdog);
 356
 357	stat = mxcmci_readl(host, MMC_REG_STATUS);
 358
 359	dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
 360
 361	mxcmci_data_done(host, stat);
 362}
 363
 364static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
 365		unsigned int cmdat)
 366{
 367	u32 int_cntr = host->default_irq_mask;
 368	unsigned long flags;
 369
 370	WARN_ON(host->cmd != NULL);
 371	host->cmd = cmd;
 372
 373	switch (mmc_resp_type(cmd)) {
 374	case MMC_RSP_R1: /* short CRC, OPCODE */
 375	case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
 376		cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
 377		break;
 378	case MMC_RSP_R2: /* long 136 bit + CRC */
 379		cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
 380		break;
 381	case MMC_RSP_R3: /* short */
 382		cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
 383		break;
 384	case MMC_RSP_NONE:
 385		break;
 386	default:
 387		dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
 388				mmc_resp_type(cmd));
 389		cmd->error = -EINVAL;
 390		return -EINVAL;
 391	}
 392
 393	int_cntr = INT_END_CMD_RES_EN;
 394
 395	if (mxcmci_use_dma(host)) {
 396		if (host->dma_dir == DMA_FROM_DEVICE) {
 397			host->desc->callback = mxcmci_dma_callback;
 398			host->desc->callback_param = host;
 399		} else {
 400			int_cntr |= INT_WRITE_OP_DONE_EN;
 401		}
 402	}
 403
 404	spin_lock_irqsave(&host->lock, flags);
 405	if (host->use_sdio)
 406		int_cntr |= INT_SDIO_IRQ_EN;
 407	mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
 408	spin_unlock_irqrestore(&host->lock, flags);
 409
 410	mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
 411	mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
 412	mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
 413
 414	return 0;
 415}
 416
 417static void mxcmci_finish_request(struct mxcmci_host *host,
 418		struct mmc_request *req)
 419{
 420	u32 int_cntr = host->default_irq_mask;
 421	unsigned long flags;
 422
 423	spin_lock_irqsave(&host->lock, flags);
 424	if (host->use_sdio)
 425		int_cntr |= INT_SDIO_IRQ_EN;
 426	mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
 427	spin_unlock_irqrestore(&host->lock, flags);
 428
 429	host->req = NULL;
 430	host->cmd = NULL;
 431	host->data = NULL;
 432
 433	mmc_request_done(host->mmc, req);
 434}
 435
 436static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
 437{
 438	struct mmc_data *data = host->data;
 439	int data_error;
 440
 441	if (mxcmci_use_dma(host)) {
 442		dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
 443				host->dma_dir);
 444		mxcmci_swap_buffers(data);
 445	}
 446
 447	if (stat & STATUS_ERR_MASK) {
 448		dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
 449				stat);
 450		if (stat & STATUS_CRC_READ_ERR) {
 451			dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
 452			data->error = -EILSEQ;
 453		} else if (stat & STATUS_CRC_WRITE_ERR) {
 454			u32 err_code = (stat >> 9) & 0x3;
 455			if (err_code == 2) { /* No CRC response */
 456				dev_err(mmc_dev(host->mmc),
 457					"%s: No CRC -ETIMEDOUT\n", __func__);
 458				data->error = -ETIMEDOUT;
 459			} else {
 460				dev_err(mmc_dev(host->mmc),
 461					"%s: -EILSEQ\n", __func__);
 462				data->error = -EILSEQ;
 463			}
 464		} else if (stat & STATUS_TIME_OUT_READ) {
 465			dev_err(mmc_dev(host->mmc),
 466				"%s: read -ETIMEDOUT\n", __func__);
 467			data->error = -ETIMEDOUT;
 468		} else {
 469			dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
 470			data->error = -EIO;
 471		}
 472	} else {
 473		data->bytes_xfered = host->datasize;
 474	}
 475
 476	data_error = data->error;
 477
 478	host->data = NULL;
 479
 480	return data_error;
 481}
 482
 483static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
 484{
 485	struct mmc_command *cmd = host->cmd;
 486	int i;
 487	u32 a, b, c;
 488
 489	if (!cmd)
 490		return;
 491
 492	if (stat & STATUS_TIME_OUT_RESP) {
 493		dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
 494		cmd->error = -ETIMEDOUT;
 495	} else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
 496		dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
 497		cmd->error = -EILSEQ;
 498	}
 499
 500	if (cmd->flags & MMC_RSP_PRESENT) {
 501		if (cmd->flags & MMC_RSP_136) {
 502			for (i = 0; i < 4; i++) {
 503				a = mxcmci_readw(host, MMC_REG_RES_FIFO);
 504				b = mxcmci_readw(host, MMC_REG_RES_FIFO);
 505				cmd->resp[i] = a << 16 | b;
 506			}
 507		} else {
 508			a = mxcmci_readw(host, MMC_REG_RES_FIFO);
 509			b = mxcmci_readw(host, MMC_REG_RES_FIFO);
 510			c = mxcmci_readw(host, MMC_REG_RES_FIFO);
 511			cmd->resp[0] = a << 24 | b << 8 | c >> 8;
 512		}
 513	}
 514}
 515
 516static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
 517{
 518	u32 stat;
 519	unsigned long timeout = jiffies + HZ;
 520
 521	do {
 522		stat = mxcmci_readl(host, MMC_REG_STATUS);
 523		if (stat & STATUS_ERR_MASK)
 524			return stat;
 525		if (time_after(jiffies, timeout)) {
 526			mxcmci_softreset(host);
 527			mxcmci_set_clk_rate(host, host->clock);
 528			return STATUS_TIME_OUT_READ;
 529		}
 530		if (stat & mask)
 531			return 0;
 532		cpu_relax();
 533	} while (1);
 534}
 535
 536static int mxcmci_pull(struct mxcmci_host *host, u32 *buf, int bytes)
 537{
 538	unsigned int stat;
 539
 540	while (bytes > 3) {
 541		stat = mxcmci_poll_status(host,
 542				STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
 543		if (stat)
 544			return stat;
 545		*buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
 546		bytes -= 4;
 547	}
 548
 549	if (bytes) {
 550		u8 *b = (u8 *)buf;
 551		u32 tmp;
 552
 553		stat = mxcmci_poll_status(host,
 554				STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
 555		if (stat)
 556			return stat;
 557		tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
 558		memcpy(b, &tmp, bytes);
 559	}
 560
 561	return 0;
 562}
 563
 564static int mxcmci_push(struct mxcmci_host *host, u32 *buf, int bytes)
 565{
 566	unsigned int stat;
 567
 568	while (bytes > 3) {
 569		stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
 570		if (stat)
 571			return stat;
 572		mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
 573		bytes -= 4;
 574	}
 575
 576	if (bytes) {
 577		u8 *b = (u8 *)buf;
 578		u32 tmp;
 579
 580		stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
 581		if (stat)
 582			return stat;
 583
 584		memcpy(&tmp, b, bytes);
 585		mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
 586	}
 587
 588	return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
 589}
 590
 591static int mxcmci_transfer_data(struct mxcmci_host *host)
 592{
 593	struct mmc_data *data = host->req->data;
 594	struct sg_mapping_iter sgm;
 595	int stat;
 596	u32 *buf;
 597
 598	host->data = data;
 599	host->datasize = 0;
 600	sg_miter_start(&sgm, data->sg, data->sg_len,
 601		       (data->flags & MMC_DATA_READ) ? SG_MITER_TO_SG : SG_MITER_FROM_SG);
 602
 603	if (data->flags & MMC_DATA_READ) {
 604		while (sg_miter_next(&sgm)) {
 605			buf = sgm.addr;
 606			stat = mxcmci_pull(host, buf, sgm.length);
 607			if (stat)
 608				goto transfer_error;
 609			host->datasize += sgm.length;
 610		}
 611	} else {
 612		while (sg_miter_next(&sgm)) {
 613			buf = sgm.addr;
 614			stat = mxcmci_push(host, buf, sgm.length);
 615			if (stat)
 616				goto transfer_error;
 617			host->datasize += sgm.length;
 618		}
 619		stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
 620		if (stat)
 621			goto transfer_error;
 622	}
 623
 624transfer_error:
 625	sg_miter_stop(&sgm);
 626	return stat;
 627}
 628
 629static void mxcmci_datawork(struct work_struct *work)
 630{
 631	struct mxcmci_host *host = container_of(work, struct mxcmci_host,
 632						  datawork);
 633	int datastat = mxcmci_transfer_data(host);
 634
 635	mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
 636		MMC_REG_STATUS);
 637	mxcmci_finish_data(host, datastat);
 638
 639	if (host->req->stop) {
 640		if (mxcmci_start_cmd(host, host->req->stop, 0)) {
 641			mxcmci_finish_request(host, host->req);
 642			return;
 643		}
 644	} else {
 645		mxcmci_finish_request(host, host->req);
 646	}
 647}
 648
 649static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
 650{
 651	struct mmc_request *req;
 652	int data_error;
 653	unsigned long flags;
 654
 655	spin_lock_irqsave(&host->lock, flags);
 656
 657	if (!host->data) {
 658		spin_unlock_irqrestore(&host->lock, flags);
 659		return;
 660	}
 661
 662	if (!host->req) {
 663		spin_unlock_irqrestore(&host->lock, flags);
 664		return;
 665	}
 666
 667	req = host->req;
 668	if (!req->stop)
 669		host->req = NULL; /* we will handle finish req below */
 670
 671	data_error = mxcmci_finish_data(host, stat);
 672
 673	spin_unlock_irqrestore(&host->lock, flags);
 674
 675	if (data_error)
 676		return;
 677
 678	mxcmci_read_response(host, stat);
 679	host->cmd = NULL;
 680
 681	if (req->stop) {
 682		if (mxcmci_start_cmd(host, req->stop, 0)) {
 683			mxcmci_finish_request(host, req);
 684			return;
 685		}
 686	} else {
 687		mxcmci_finish_request(host, req);
 688	}
 689}
 690
 691static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
 692{
 693	mxcmci_read_response(host, stat);
 694	host->cmd = NULL;
 695
 696	if (!host->data && host->req) {
 697		mxcmci_finish_request(host, host->req);
 698		return;
 699	}
 700
 701	/* For the DMA case the DMA engine handles the data transfer
 702	 * automatically. For non DMA we have to do it ourselves.
 703	 * Don't do it in interrupt context though.
 704	 */
 705	if (!mxcmci_use_dma(host) && host->data)
 706		schedule_work(&host->datawork);
 707
 708}
 709
 710static irqreturn_t mxcmci_irq(int irq, void *devid)
 711{
 712	struct mxcmci_host *host = devid;
 713	bool sdio_irq;
 714	u32 stat;
 715
 716	stat = mxcmci_readl(host, MMC_REG_STATUS);
 717	mxcmci_writel(host,
 718		stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
 719			 STATUS_WRITE_OP_DONE),
 720		MMC_REG_STATUS);
 721
 722	dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
 723
 724	spin_lock(&host->lock);
 725	sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
 726	spin_unlock(&host->lock);
 727
 728	if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
 729		mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
 730
 731	if (sdio_irq) {
 732		mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
 733		mmc_signal_sdio_irq(host->mmc);
 734	}
 735
 736	if (stat & STATUS_END_CMD_RESP)
 737		mxcmci_cmd_done(host, stat);
 738
 739	if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
 740		timer_delete(&host->watchdog);
 741		mxcmci_data_done(host, stat);
 742	}
 743
 744	if (host->default_irq_mask &&
 745		  (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
 746		mmc_detect_change(host->mmc, msecs_to_jiffies(200));
 747
 748	return IRQ_HANDLED;
 749}
 750
 751static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
 752{
 753	struct mxcmci_host *host = mmc_priv(mmc);
 754	unsigned int cmdat = host->cmdat;
 755	int error;
 756
 757	WARN_ON(host->req != NULL);
 758
 759	host->req = req;
 760	host->cmdat &= ~CMD_DAT_CONT_INIT;
 761
 762	if (host->dma)
 763		host->do_dma = 1;
 764
 765	if (req->data) {
 766		error = mxcmci_setup_data(host, req->data);
 767		if (error) {
 768			req->cmd->error = error;
 769			goto out;
 770		}
 771
 772
 773		cmdat |= CMD_DAT_CONT_DATA_ENABLE;
 774
 775		if (req->data->flags & MMC_DATA_WRITE)
 776			cmdat |= CMD_DAT_CONT_WRITE;
 777	}
 778
 779	error = mxcmci_start_cmd(host, req->cmd, cmdat);
 780
 781out:
 782	if (error)
 783		mxcmci_finish_request(host, req);
 784}
 785
 786static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
 787{
 788	unsigned int divider;
 789	int prescaler = 0;
 790	unsigned int clk_in = clk_get_rate(host->clk_per);
 791
 792	while (prescaler <= 0x800) {
 793		for (divider = 1; divider <= 0xF; divider++) {
 794			int x;
 795
 796			x = (clk_in / (divider + 1));
 797
 798			if (prescaler)
 799				x /= (prescaler * 2);
 800
 801			if (x <= clk_ios)
 802				break;
 803		}
 804		if (divider < 0x10)
 805			break;
 806
 807		if (prescaler == 0)
 808			prescaler = 1;
 809		else
 810			prescaler <<= 1;
 811	}
 812
 813	mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
 814
 815	dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
 816			prescaler, divider, clk_in, clk_ios);
 817}
 818
 819static int mxcmci_setup_dma(struct mmc_host *mmc)
 820{
 821	struct mxcmci_host *host = mmc_priv(mmc);
 822	struct dma_slave_config *config = &host->dma_slave_config;
 823
 824	config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
 825	config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
 826	config->dst_addr_width = 4;
 827	config->src_addr_width = 4;
 828	config->dst_maxburst = host->burstlen;
 829	config->src_maxburst = host->burstlen;
 830	config->device_fc = false;
 831
 832	return dmaengine_slave_config(host->dma, config);
 833}
 834
 835static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 836{
 837	struct mxcmci_host *host = mmc_priv(mmc);
 838	int burstlen, ret;
 839
 840	/*
 841	 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value  0)
 842	 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
 843	 */
 844	if (ios->bus_width == MMC_BUS_WIDTH_4)
 845		burstlen = 16;
 846	else
 847		burstlen = 4;
 848
 849	if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
 850		host->burstlen = burstlen;
 851		ret = mxcmci_setup_dma(mmc);
 852		if (ret) {
 853			dev_err(mmc_dev(host->mmc),
 854				"failed to config DMA channel. Falling back to PIO\n");
 855			dma_release_channel(host->dma);
 856			host->do_dma = 0;
 857			host->dma = NULL;
 858		}
 859	}
 860
 861	if (ios->bus_width == MMC_BUS_WIDTH_4)
 862		host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
 863	else
 864		host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
 865
 866	if (host->power_mode != ios->power_mode) {
 867		host->power_mode = ios->power_mode;
 868		mxcmci_set_power(host, ios->vdd);
 869
 870		if (ios->power_mode == MMC_POWER_ON)
 871			host->cmdat |= CMD_DAT_CONT_INIT;
 872	}
 873
 874	if (ios->clock) {
 875		mxcmci_set_clk_rate(host, ios->clock);
 876		mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
 877	} else {
 878		mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
 879	}
 880
 881	host->clock = ios->clock;
 882}
 883
 884static irqreturn_t mxcmci_detect_irq(int irq, void *data)
 885{
 886	struct mmc_host *mmc = data;
 887
 888	dev_dbg(mmc_dev(mmc), "%s\n", __func__);
 889
 890	mmc_detect_change(mmc, msecs_to_jiffies(250));
 891	return IRQ_HANDLED;
 892}
 893
 894static int mxcmci_get_ro(struct mmc_host *mmc)
 895{
 896	struct mxcmci_host *host = mmc_priv(mmc);
 897
 898	if (host->pdata && host->pdata->get_ro)
 899		return !!host->pdata->get_ro(mmc_dev(mmc));
 900	/*
 901	 * If board doesn't support read only detection (no mmc_gpio
 902	 * context or gpio is invalid), then let the mmc core decide
 903	 * what to do.
 904	 */
 905	return mmc_gpio_get_ro(mmc);
 906}
 907
 908static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 909{
 910	struct mxcmci_host *host = mmc_priv(mmc);
 911	unsigned long flags;
 912	u32 int_cntr;
 913
 914	spin_lock_irqsave(&host->lock, flags);
 915	host->use_sdio = enable;
 916	int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
 917
 918	if (enable)
 919		int_cntr |= INT_SDIO_IRQ_EN;
 920	else
 921		int_cntr &= ~INT_SDIO_IRQ_EN;
 922
 923	mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
 924	spin_unlock_irqrestore(&host->lock, flags);
 925}
 926
 927static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
 928{
 929	struct mxcmci_host *mxcmci = mmc_priv(host);
 930
 931	/*
 932	 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
 933	 * multi-block transfers when connected SDIO peripheral doesn't
 934	 * drive the BUSY line as required by the specs.
 935	 * One way to prevent this is to only allow 1-bit transfers.
 936	 */
 937
 938	if (is_imx31_mmc(mxcmci) && mmc_card_sdio(card))
 939		host->caps &= ~MMC_CAP_4_BIT_DATA;
 940	else
 941		host->caps |= MMC_CAP_4_BIT_DATA;
 942}
 943
 944static bool filter(struct dma_chan *chan, void *param)
 945{
 946	struct mxcmci_host *host = param;
 947
 948	if (!imx_dma_is_general_purpose(chan))
 949		return false;
 950
 951	chan->private = &host->dma_data;
 952
 953	return true;
 954}
 955
 956static void mxcmci_watchdog(struct timer_list *t)
 957{
 958	struct mxcmci_host *host = timer_container_of(host, t, watchdog);
 959	struct mmc_request *req = host->req;
 960	unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
 961
 962	if (host->dma_dir == DMA_FROM_DEVICE) {
 963		dmaengine_terminate_all(host->dma);
 964		dev_err(mmc_dev(host->mmc),
 965			"%s: read time out (status = 0x%08x)\n",
 966			__func__, stat);
 967	} else {
 968		dev_err(mmc_dev(host->mmc),
 969			"%s: write time out (status = 0x%08x)\n",
 970			__func__, stat);
 971		mxcmci_softreset(host);
 972	}
 973
 974	/* Mark transfer as erroneus and inform the upper layers */
 975
 976	if (host->data)
 977		host->data->error = -ETIMEDOUT;
 978	host->req = NULL;
 979	host->cmd = NULL;
 980	host->data = NULL;
 981	mmc_request_done(host->mmc, req);
 982}
 983
 984static const struct mmc_host_ops mxcmci_ops = {
 985	.request		= mxcmci_request,
 986	.set_ios		= mxcmci_set_ios,
 987	.get_ro			= mxcmci_get_ro,
 988	.enable_sdio_irq	= mxcmci_enable_sdio_irq,
 989	.init_card		= mxcmci_init_card,
 990};
 991
 992static int mxcmci_probe(struct platform_device *pdev)
 993{
 994	struct mmc_host *mmc;
 995	struct mxcmci_host *host;
 996	struct resource *res;
 997	int ret = 0, irq;
 998	bool dat3_card_detect;
 999	dma_cap_mask_t mask;
1000	struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
1001
1002	pr_info("i.MX/MPC512x SDHC driver\n");
1003
1004	irq = platform_get_irq(pdev, 0);
1005	if (irq < 0)
1006		return irq;
1007
1008	mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host));
1009	if (!mmc)
1010		return -ENOMEM;
1011
1012	host = mmc_priv(mmc);
1013
1014	host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1015	if (IS_ERR(host->base))
1016		return PTR_ERR(host->base);
1017
1018	host->phys_base = res->start;
1019
1020	ret = mmc_of_parse(mmc);
1021	if (ret)
1022		return ret;
1023	mmc->ops = &mxcmci_ops;
1024
1025	/* For devicetree parsing, the bus width is read from devicetree */
1026	if (pdata)
1027		mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1028	else
1029		mmc->caps |= MMC_CAP_SDIO_IRQ;
1030
1031	/* MMC core transfer sizes tunable parameters */
1032	mmc->max_blk_size = 2048;
1033	mmc->max_blk_count = 65535;
1034	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1035	mmc->max_seg_size = mmc->max_req_size;
1036
1037	host->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);
1038
1039	/* adjust max_segs after devtype detection */
1040	if (!is_mpc512x_mmc(host))
1041		mmc->max_segs = 64;
1042
1043	host->mmc = mmc;
1044	host->pdata = pdata;
1045	spin_lock_init(&host->lock);
1046
1047	if (pdata)
1048		dat3_card_detect = pdata->dat3_card_detect;
1049	else
1050		dat3_card_detect = mmc_card_is_removable(mmc) &&
1051				   !of_property_present(pdev->dev.of_node, "cd-gpios");
1052
1053	ret = mmc_regulator_get_supply(mmc);
1054	if (ret)
1055		return ret;
1056
1057	if (!mmc->ocr_avail) {
1058		if (pdata && pdata->ocr_avail)
1059			mmc->ocr_avail = pdata->ocr_avail;
1060		else
1061			mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1062	}
1063
1064	if (dat3_card_detect)
1065		host->default_irq_mask =
1066			INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1067	else
1068		host->default_irq_mask = 0;
1069
1070	host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1071	if (IS_ERR(host->clk_ipg))
1072		return PTR_ERR(host->clk_ipg);
1073
1074	host->clk_per = devm_clk_get(&pdev->dev, "per");
1075	if (IS_ERR(host->clk_per))
1076		return PTR_ERR(host->clk_per);
1077
1078	ret = clk_prepare_enable(host->clk_per);
1079	if (ret)
1080		return ret;
1081
1082	ret = clk_prepare_enable(host->clk_ipg);
1083	if (ret)
1084		goto out_clk_per_put;
1085
1086	mxcmci_softreset(host);
1087
1088	host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1089	if (host->rev_no != 0x400) {
1090		ret = -ENODEV;
1091		dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1092			host->rev_no);
1093		goto out_clk_put;
1094	}
1095
1096	mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1097	mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1098
1099	/* recommended in data sheet */
1100	mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1101
1102	mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1103
1104	if (!host->pdata) {
1105		host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1106		if (IS_ERR(host->dma)) {
1107			if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
1108				ret = -EPROBE_DEFER;
1109				goto out_clk_put;
1110			}
1111
1112			/* Ignore errors to fall back to PIO mode */
1113			host->dma = NULL;
1114		}
1115	} else {
1116		res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1117		if (res) {
1118			host->dmareq = res->start;
1119			host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1120			host->dma_data.priority = DMA_PRIO_LOW;
1121			host->dma_data.dma_request = host->dmareq;
1122			dma_cap_zero(mask);
1123			dma_cap_set(DMA_SLAVE, mask);
1124			host->dma = dma_request_channel(mask, filter, host);
1125		}
1126	}
1127	if (host->dma)
1128		mmc->max_seg_size = dma_get_max_seg_size(
1129				host->dma->device->dev);
1130	else
1131		dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1132
1133	INIT_WORK(&host->datawork, mxcmci_datawork);
1134
1135	ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1136			       dev_name(&pdev->dev), host);
1137	if (ret)
1138		goto out_free_dma;
1139
1140	platform_set_drvdata(pdev, mmc);
1141
1142	if (host->pdata && host->pdata->init) {
1143		ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1144				host->mmc);
1145		if (ret)
1146			goto out_free_dma;
1147	}
1148
1149	timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1150
1151	ret = mmc_add_host(mmc);
1152	if (ret)
1153		goto out_free_dma;
1154
1155	return 0;
1156
1157out_free_dma:
1158	if (host->dma)
1159		dma_release_channel(host->dma);
1160
1161out_clk_put:
1162	clk_disable_unprepare(host->clk_ipg);
1163out_clk_per_put:
1164	clk_disable_unprepare(host->clk_per);
1165
1166	return ret;
1167}
1168
1169static void mxcmci_remove(struct platform_device *pdev)
1170{
1171	struct mmc_host *mmc = platform_get_drvdata(pdev);
1172	struct mxcmci_host *host = mmc_priv(mmc);
1173
1174	mmc_remove_host(mmc);
1175
1176	if (host->pdata && host->pdata->exit)
1177		host->pdata->exit(&pdev->dev, mmc);
1178
1179	if (host->dma)
1180		dma_release_channel(host->dma);
1181
1182	clk_disable_unprepare(host->clk_per);
1183	clk_disable_unprepare(host->clk_ipg);
1184}
1185
1186static int mxcmci_suspend(struct device *dev)
1187{
1188	struct mmc_host *mmc = dev_get_drvdata(dev);
1189	struct mxcmci_host *host = mmc_priv(mmc);
1190
1191	clk_disable_unprepare(host->clk_per);
1192	clk_disable_unprepare(host->clk_ipg);
1193	return 0;
1194}
1195
1196static int mxcmci_resume(struct device *dev)
1197{
1198	struct mmc_host *mmc = dev_get_drvdata(dev);
1199	struct mxcmci_host *host = mmc_priv(mmc);
1200	int ret;
1201
1202	ret = clk_prepare_enable(host->clk_per);
1203	if (ret)
1204		return ret;
1205
1206	ret = clk_prepare_enable(host->clk_ipg);
1207	if (ret)
1208		clk_disable_unprepare(host->clk_per);
1209
1210	return ret;
1211}
1212
1213static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1214
1215static struct platform_driver mxcmci_driver = {
1216	.probe		= mxcmci_probe,
1217	.remove		= mxcmci_remove,
1218	.driver		= {
1219		.name		= DRIVER_NAME,
1220		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
1221		.pm	= pm_sleep_ptr(&mxcmci_pm_ops),
1222		.of_match_table	= mxcmci_of_match,
1223	}
1224};
1225
1226module_platform_driver(mxcmci_driver);
1227
1228MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1229MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1230MODULE_LICENSE("GPL");
1231MODULE_ALIAS("platform:mxc-mmc");